DYNAMIC MOS MEMORY IN A CURRENT-LIMITED DIFFUSION-SEMICONDUCTOR STRUCTURE.

Description

TITLE DYNAMIC MEMORY.A MOS IN A CURRENT-LIMITED DIFFUSION SEMICONDUCTOR STRUCTURE. PRIORITY USA - PATENT DOM. NO. 848,000 DATED NOVEMBER 3, 1977 8 SEPTEMBER Rome, The............................... ERECTOR CMece - Tivoli 68056 / fz Register A Protocol No. 2936O £ 7θ MINISTRY OF INDUSTRY, COMMERCE AND CRAFTS Provincial Office of Industry, Commerce and Crafts of Milan COPY OF THE MINUTES OF FILING FOR A PATENT FOR INDUSTRIAL INVENTIONS In the year 1978, on the day of November 11:20 and 20 minutes, the Pitia WESTERN ELECTRIC COMPANY, INCORPORATED ÌtxStjcroax of American nationality in Hew ^ 0Γ^· (USA) rxxK3eD* K Dr.ing. G.Modiano of MODIANO & ASSOCIATI Sas di dr.ing. G. MODIANO & C. Via a me2Z0 agent (Italian Patent and Trademark Agency) and with domicile for legal purposes in Milan - Via Meravigli 16 at the agent has presented to me, the undersigned: - Stamped application for the granting of a PATENT FOR INDUSTRIAL INVENTION having as its object TITLE MAIN ooxxKixiaxwc «DYNAMIC MOS MEMORY IN A CURRENT-LIMITED DIFFUSION-SEMICONDUCTOR STRUCTURE. Inventor designates!--Priority' of patent application in: USAN 848,000 of November 3, 1977 · supplementary to patent no. filed on granted on (application no. accompanied by: - Description in duplicate of 25 pages of writing. - Drawings, plates no. 2 in duplo. - bCKStxso(ddxxxx±zx- Declaration reference to Power of Attorney. - Priority document and Italian translation (with reservation) - Authorization or deed of transfer, (with reservation) * Proof of payment on postal account no. 00668004 in the name of the Tax and Concession Registry Office of Rome of L. 122,000 issued by the Post Office of Milan 15 on 2.11.1978 no. 181 - Revenue stamp of L· 3®®*®* 2,000. The application, descriptions and drawings listed above have been signed by the applicant and countersigned by me and stamped with the office stamp THE DEPOSITOR ....... QAÀlcp. OFFICER Pietro Messineo For Copt compliant with the original pLud i rector (Federico Nappi) THE HEAD OF THE OFFICE (Dr. Renato 68056 / fa Hon.le MINI SIERO INDUSTRU C01WERCIO ED CRAFTS Central Patent Office τ. XPIa US-based company WESTERN ELECTRIC COMPANY, INCORPORATED Headquartered in New York, NY Dr.Ing.G.Mediano of (USA)____________through Nandatariq / MODIANO A ASSOCIATI Sas of Dr.Ing.C. MODIANO & C. (Italian Patent and Trademark Agency) and elected domiciled for legal purposes in Milan, Via Meravigli 16, requests for a patent. Principal subject of the invention entitled; DYNAMIC MOS MEMORY IN A CURRENT-LIMITED DIP-16 SEMICONDUCTOR STRUCTURE. Inventor designated Priority of patent application in: USA No. 84B.OOO of November 3, 1977 · 'Attached documents: a) Description in duplicate of 25 pages of writing [ . ... ί b) Drawings of n. 2 tables in duplicate copy o) LettvraTdf hymnals toc- Reference to general attorney d) Priority document with Italian translation (with reservation) ί................................................ 7 ................................................ i e) Authorization or deed of transfer (with reservation) f) » g) Certificate of payment (copies No. 00668004) of L. 122,000 issued by the Post Office of Milan 15 on h) Revenue stamp of L. 2,000. m. :-2N0V. 378 fi; • ---- - - g 'ri You 293 60A / 78 the U Rogante Branch r tPiiy there. 68056 / ζη «DYNAMIC MOS MEMORY IN A CURRENT-LIMITED DIFFUSION-SEMICONDUCTOR STRUCTURE» WESTERN ELECTRIC COMPANY, INCORPORATED», at . · ·. New York, NY (USA). ?,·.· / . · · Deposited on - at Bo. 2 9 3 60 A / / g '··^ The present invention relates to a 140¾.i memory device. n-channel of the type including a plurality of MOS devices comprise»* ··♦· * each at least one n-type region included in a semiconductor, / al e · · • * .· * · · *·' 0 · • a · p-type silicon. ····. • · « · * U.S. Patent No. 4,012,757 to Eoo describes a MOS random-access memory. The circuit structure of this type of memory is such that leakage currents cause the stored charges to decay. These charges represent data stored or memorized in capacitive memory locations. Therefore, to retain data stored in memory locations for an extended period of time, periodic read and refresh pulses are necessary. Memories subject to these periodic read and refresh pulses are called dynamic random access memories or dynamic RAM. Although the structure of the dynamic RAM device is simpler than the structure of a static RAM device and therefore more desirable, in constructing this dynamic RAM it is also desirable to minimize the decay of the stored charges. A slower decay time makes it possible to reduce the frequency of the refresh pulses. A slower decay time to or lower also reduces the possibility of losing stored data during the interval between two consecutive refresh pulses. Since the decay rate of stored data depends on the discharge current, sioae with reverse bias in the device, it becomes desirable*·ristar ··· 4 4 « re this leakage current. U.S. Patent No. 3,997,368 to Petroff et al. / Iii 4 4 4 4 4V titled Elimination of Stacking Faults in Silicon Devices: A Gettering '···. Proc ess describes a reduction of leakage currents in junctions / p·» • 4 *4 4· by suppressing the formation of crystalline defects in the vicinity of the junctions— 4* \ ni pn in a semiconductor material by a cathode ray process. 4« This gettering process involves introducing lattice distortion by forming a stressed layer on the back surface of the silicon wafer. The layer is then annealed for a period of time and temperature that induces nucleation sites with silage defects to diffuse to a region near the back surface of the wafer. Diffusion of the nucleation sites to the back surface suppresses the formation of silage defects in the device. Gettering processes similar to those described in U.S. Patent No. 3,997,368 have been used in the fabrication of typical dynamic memories. Typical hold times for these memories have been found to be between 6 and 40 milliseconds for a junction temperature of 85°C. Hold time refers to the total time range over which refresh pulses can be spaced without losing information from the memory cells. Of course, for any number of memories found, the hold times vary within a certain range. By the term typical with respect to hold time values, we mean values ​​that divide any number of devices into two groups of substantially equal defects, one group with longer hold times. ..... « · * » » · the other with shorter maintenance times. It therefore appears desirable ·.·.··· · · ·*·*· to replicate dynamic memories with typical retention times well above the* 'sopira* * · .··· .·· ···:, ; of a minimum holding time requirement. To obtain a reqa / ao·*. • · 4 4 *4 a · 4 >» In the case of manufactured memory devices, it is desirable that swtanr**, «. · · · • · · 4 4 Initially all these devices have to satisfy the requirements ρφ£έηί • aa » * relating to the maintenance time. For example, in the aforementioned U.S. Patent No. 4,012,757, it was recognized that H03 random-access memories can be constructed in a semiconductor body comprising a portion of substrate upon which an epitaxial layer has been grown in which the active memory cells are formed. However, no such memories have become commercially available. This is believed to be the case because, to date, no reasonably expected advantage of such a structure has been able to outweigh the resulting process complexity and cost of adding an epitaxial layer to the bulk silicon. The applicant has discovered that reverse-bias leakage currents in semiconductor circuits, such as dynamic random-access memories, can be suppressed when the circuits are dominated by the diffusion current at normal operating temperatures. It then becomes possible to limit the availability of the minority radios that diffuse through the material and across reverse-biased junctions without deleterious effects on the desirable characteristics of the junctions. According to the present invention, a semiconductor device. • · · * * * * «ee* with characteristics of leakage current at polari esation inverse^Van*'•-i, ·** * ee significantly low through pn junctions in a silicon body, boi-* * * • » ί 1 I · φ V · · · * · noorì stali ino. The body includes a bulk or substrate portion doped relatively strongly (e.g., more than 10 p-type dopants per cubic centimeter). An epithelial layer has been formed on the substrate portion with substantially lower dopant concentrations (e.g., more than 2 x 10 p-type dopants per cubic centimeter). The epitaxial layer has a thickness of a fraction of the diffusion length of the minority carriers in the layered structure. The layered or layered structure is typically prepared such that its minority carriers have an average diffusion length of at least 500 microns (1 micron ≈ 10**^ meters), which corresponds to an effective lifetime of these minority carriers of about 500 microns. In addition, the quality of the epitaxial layer with respect to the minority carrier generation centers is such that the number of these centers is so small that a diode formed in the epitaxial layer is substantially dominated by diffusion current within normal operating temperatures of circuit devices in the body. It has been found that a fully formed pn junction in the epitaxial layer will have an extremely high reverse leakage current. reduced. Therefore, a dynamic random-access memory cell formed in the epitaxial layer has a surprisingly long holding time, which is well worth the extra processing effort involved. In addition, if the p-n junctions of this cell are confined to a region near the surface of the layer and completely within the *ava&so ***** • 4 » ♦ · layer, then the breakdown characteristics and capacitances».&$.* ￂﾷ￢ﾙﾦ ￂﾷ. these junctions remain substantially the typical ones of oorrisjifilpjjnti 4 4 4 Ϊ· I · · to the more weakly doped layer rather than those associated with the dopants in the substrate portion of the body* •4 · · The various features and advantages of the invention are more readily understood from the following description taken in conjunction with the accompanying drawings in which: Figure 1 is a cross-section taken through a portion of a semiconductor wafer illustrating an epitaxial layer on a substrate of thickness proportional to the substrate, useful in explaining the invention; Figure 2 is an enlarged view of the epitaxial portion shown in Figure 1 and illustrating various regions doped to form p-n junctions having a leakage current base in accordance with the present invention; Figure 3 is a rough sketch of the electrical function or operation of the structure of Figure 2; Figure 4 is a diagram of preferred boron concentrations in the semiconductor material of the wafer of Figure 1; Figure 5 is an alternative and currently preferred structure «Μ ta oui the invention can be applied to obtain favorable reverse leakage current characteristics; Figure 6 is a block diagram of illustrative steps of a process for forming a semiconductor device according to a preferred embodiment of the invention. General considerations The present invention is particularly useful relative to iàptè $.ￂﾷ, * ￂﾷￂﾷ U 1 ￂﾷ 1 ￢ﾀﾢ ;. Dynamic MOS RAM. E* with reference to this type of deviceￂﾷￎﾹￎﾯ$ￎﾛￎﾐ** * . · ». 0 · • 4 · ♦ * ·· · ύ · fc fc 4 »♦·· » · e · i » · ♦ · O 1 * * t • » The * * conductor owhich the invention will be described. However, this does not mean that the invention does not have broader applicability. In general, 1 ' ijMrenz J It can be applied to various semiconductor elements which require that the leakage current through reverse-biased pn junctions remains relatively low. ​Prior art n-channel dynamic RAMs have been fabricated using conventional fabrication techniques at the surface of a p-doped silicon wafer. It is known, for example, that there is a correlation between the lifetime of minority carriers in the semiconductor material and the ultimate hold times of memory cells formed at the surface of the semiconductor wafer. For example, for a prior art memory circuit structure, the lifetime of minority carriers in the bulk silicon material of 10 to 5θ microseconds corresponds to the lifetime of typical hold times in finite memories of 2 to 1000 milliseconds. The fabrication steps for fabricating this prior art memory included gettering steps similar to those described in U.S. Pat. No. 3,997,368, the assignee has now discovered that it is possible to fabricate a semiconductor structure which provides a distinct step-like increase in d-hold times. • « • · ,· · memory cells of a dynamic RAM. However, it seems οχ?;;.... ..... • * · ·· · · this increase is achievable only when the semi-material*-·... • · · 4 · 4 4 4 4 4 » * conductor in which the memory cells are arranged has qtiàl'i4.\? ' ........ j .· * ity such as to limit any irreversible leakage current. » : ******* to what is known as the diffusive componentOaq”; e··' of the currents. ····. The desired crystalline quality or structural integrity is that with the lowest level of contaminants or harmful impurities that can be achieved with current manufacturing techniques and equipment. These harmful impurities include, for example, elements such as iron, nickel, copper, calcium, or gold. The impurities harmful for the purposes of this invention are those which have energy levels approximately intermediate between the valence and conduction bands of silicon® They therefore provide minority carrier generation centers due to their presence in the crystal lattice. They are also believed to be a cause of the formation of stacking defects and other crystalline defects which are known to cause to control reverse leakage currents when they occur in the vicinity of pn junctions. In the absence of these harmful impurities, it appears that the diffusion of minority carriers, e.g. electrons *····* in p-type materials becomes the controlling mechanism in which reverse leakage currents can occur. This environment, i.e., a semiconductor structure • ,··· ··· largely dominated by diffusion current within the operating temperature range of a device*. ···· • · * · · · formed therein constitutes a significant aspect of the present invention. ***** It is found that minority carrier diffusion currents are strongly dependent on temperature. And, in the past, a sharp increase in reverse leakage currents across diode junctions was considered indicative of a high-temperature phenomenon. It appears that the change in the temperature dependence of the reverse leakage current is the “crossover” from a leakage current dominated by source current to a leakage current dominated by diffusion current as the temperature of a given device is increased. feces (<( ;s iaV-XO / However, when a device is constructed according to the present invention, the reverse bias leakage current of its junctions advantageously highlights the temperature dependence of the diffusion current mechanism in the high-temperature portion of its intended operating temperature range. ,, · · * • · · · · · · Operating temperatures may vary from normal ambient temperatures. • · · · · · · · · · » * te up to a temperature higher than 90°C. When referred to; • ·····., : L'· at the «high or upper portion of the temperature range, aìM£a si . * · · · .· · **.*: are meant to mean temperatures normally higher than 70°C. A typical higher or elevated temperature range is from 70°C to 90°C. However, in pure crystalline structures, the reverse bias leakage current can already be dominated by diffusion currents at temperatures higher than 40°C. This diffusion-current-dominated structure requires that harmful impurities be substantially eliminated from the structure in which the device is formed. A preferred embodiment of the invention is an n-channel dynamic random-access memory device embedded in a p-type epitaxial silicon body. The body includes a substrate or bulk portion which is preferably doped with boron (boron is a p-type dopant) at a relatively high concentration, preferably 10 dopant atoms per cubic centimeter. An epitaxial layer, also of boron-doped silicon, is formed on the bulk silicon. However, in the preferred embodiment, the epitaxial layer Ί5 le is doped only to a concentration of about 2 x 10 dopant atoms per cubic centimeter* It is in this epitaxial layer that the memory cell elements are formed* The applicant found that if the structure of di sposi φίντ> o·*··. • · 4 4 4 epitaxial layer is dominated by diffusion current, then the junction characteristics, such as capacitance, threshold and breakdown voltage, of the memory cell elements are determined by the doping level in the epitaxial layer. On the other hand, the diffusion currents; ..*···· ​​• 4 4·· reverse reactions through the junctions in the elements are limited Jdàila2 *···* ..·* *.···· reduced availability of minority carriers, e.g. electronsν «1 * * 44 · a diffusion length from the junction, into the heavily doped substrate. A memory in this structure therefore has optimal capacitance, threshold and breakdown voltage characteristics and in addition characteristicsL-. ' . which have low reverse leakage which translates into advantageously prolonged retention times for each of the individual cells in the honeycomb. However, the advantageous results of the above-described structure appear when the level of harmful impurities is such that the device, e.g. the memory in the epitaxial layer, is significantly controlled in its reverse leakage current characteristics by minority carriers generated in the vicinity of the junctions. It therefore becomes important to form the memory with material having the described quality, for example a level of harmful impurities so low that it is difficult to measure even with today's techniques. However, it appears that the advantages of the structure are associated with a combination This is because the structure appears to have characteristics that tend to isolate harmful impurities in the bulk silicon, so the epitaxial material tends to have an advantageously low level of these harmful impurities. the structure of the semiconductor • · ·· ·· Figure 1 shows a portion of a semiconductor wafer. *4444 *·· » · ♦ * * 4· 4 4444 _generally indicated by the number 11. 11 wafer 11 is shown in section 'tb'a' I *t · ♦ «versal to highlight the relative thickness between the substrate or holders · · ' ·*··♦ . ί * ' • *. of bulk 12 of wafer 11 and an epitaxial layer 14 which is a format,**£d ·* . ♦ » 4 « * * , · » · , .····· correspondence of a wafer surface. 11 silicon 12 of the bulk h*ap»lo .·ζ·* * 4 4*4 r < * ** * Thickness of approximately 20 thousandths of an inch or 500 microns (500 x 10 methyl). Compared to the bulk silicon 12, the thickness of the epitaxial wafer 11 is preferably only 10 to 15 microns. Therefore, Figure 1 illustrates on a greatly enlarged scale the approximate proportions between the bulk silicon thickness and the epitaxial thickness of the wafer 11. The starting material of bulk 12 of wafer 11 is a p-type silicon material with a crystalline orientation (lOo). The p+ doping is a boron doping with a level of at least 10 atoms per cubic centimeter. It has been found that a doping level for the starting material of at least 10 atoms per cubic centimeter of boron is a threshold level for taking full advantage of the invention with respect to the doping of the epitaxial layer 14. When the bulk silicon 12 was doped to at least this level, the epitaxial layer 14 could be grown with very low, unmeasurable concentrations of harmful impurities such as iron, nickel, copper, calcium, or gold. On the other hand, as the boron doping level dropped below 18 atoms per cubic centimeter, the epitaxial layer was found to exhibit increasingly higher concentrations of harmful impurities. The higher concentrations of harmful impurities ^etqp. «•ftft* •·· # ftft * · mined effective lifetimes correspondingly shorter than minority leads. Therefore, it may be possible in a very clean process without virtually any introduction of harmful impurities into the semiconductor material to achieve the same high performance characteristics. effective lifetime even with a doping level lower than 10... a.. · ft « tomes per cubic centimeter in the substrate. ····· ····. « · ftft * ftft* In a preferred embodiment, the concentration of 15 boron in the bulk silicon 12 is consequently about 10 atoms per cubic centimeter. It is believed that at this doping level in the described process, the bulk silicon acts as a barrier or trap for harmful impurities diffusing through the wafer M. It appears that heavily doped bulk silicon exhibits a greater ability to trap any harmful impurities. No proven explanation for this increased impurity-trapping ability has been found. However, some theories have been proposed that may be of some interest. One mechanism for such a barrier may be the result of possible ionic bonds between harmful impurities and other atoms in the doped crystalline structure of the semiconductor. These bonds are believed to be at least partly responsible for retaining harmful impurities within the bulk silicon 12 as they diffuse through the structure. However, this ionic bonding by which impurities tend to be retained within the heavily doped bulk silicon structure may be only one of several mechanisms leading to the gettering of harmful impurities. / ***· • * * · * · * · Another mechanism is believed to lead to deformations *···· ​​· 4 re detected at the interface between the silicon 12 of the · · 4 4 4 4 · * ·.·...... ; · · * * · and the epitaxial layer 14. This deformation is the consequence of the different doping levels in the bulk silicon 12 and in the epitaxial layer.1^^·,; • · ·· · •e 4· 4 φ· Different doping levels result in differences in the spacing of the bulk silicon 12 and the epitaxial layer 14, which déféMina 4*44, 4 4 4 and no mismatched dislocations of lattice strains. These mismatched dislocations are believed to contribute to the "gettering" of harmful impurities from the epitaxial layer 14. Gettering resulting from mismatched dislocations introduced onto a wafer surface is known. U.S. Patent No. 3,997,368 to Petroff et al. describes means for impurity gettering. However, in the wafer structure of the present invention, the plane of the mismatched dislocations is located at the interface between the bulk silicon 12 and the epitaxial layer 14. It is believed that the proximity of the mismatched dislocations to the active p-n junctions in the The epitaxial layer 14 improves its gettering efficiency through all the heating treatment steps. This improvement is believed to be over the back surface gettering process described in U.S. Patent No. 3,997,368. It should be noted, however, that the invention is not based on any of the mecha14 / <ar / : V nitmi ou theories described here. These theories are simply presented as possible explanations of the results. With this proven increased ability to retain harmful impurities in the bulk silicon once they have penetrated the wafer, various precautions are taken to prevent harmful impurities from spreading to the wafer 11 during the manufacturing process of the devices. ·,···· · · · reducers, the epitaxial layer 14 becomes relatively free of these.iri ··* • ·. ..·;· .·* purity, therefore, the layered structure or wafer 11 exhibits char-; , ; ,.····· \ *»*'*·* lifetime ptics of the minority carriers relatively pijqlwj- ' Λ. - 4 · gata. ····; • 4 4 and Φ The epitaxial layer is grown to have a level of * doping of approximately 8 x 10 boron atoms per cubic centimeter. The doping level determines, for example, the capacitance of any junction in the material* ..·· » · 4 ι 4 4 4 Typically, at the interface between the epitaxial layer and the original substrate there will be a region of graded concentration resulting from diffusion out of boron from the substrate into the epitaxial layer during growth of the epitaxial layer itself. However, in an epitaxial layer having a thickness of about 10-15 microns, as is typical of the preferred embodiment, this effect is negligible. £1 typically finds that the layered structure formed by the bulk silicon substrate and the epitaxial layer has an electron lifetime of at least 500 microseconds. This value corresponds to a diffusion length for minority carriers, i.e., electrons, of about 500 microns. The thickness of the epitaxial layer is therefore no greater than one thirtieth of the electron diffusion length. It can therefore be noted that within the volume in which free electrons can be expected to diffuse through the rectifying junction in the form of the effective leakage current, the junction material is the abundantly and strongly ductile material. 4 · » » · * • · · » · . . · 4 * · · · · substrate layer. In this heavily doped bulk silicon, glx*e}.eb», ,.·· ··· “< f * · · free thrones are few compared to the weakly dro^afg epitaxial layer; ♦ , · · · 4 j 4 4 4 , · in which the free electrons are in much greater quantity, being.infrehs;.* .· · ·**· · 4 4 · * * · ««almost proportional to the doping level. Therefore, in a defect-free layer, the measured generation lifetimes reflect the limited diffusion current attributes of the structure. However, at this time, the junction is embedded in a finite thickness of the lightly doped material. It is this lightly doped material that determines the good breakdown characteristics and low capacitance of the KOS elements in the layer. , Device Structure Referring now to Figure 2, it shows on an enlarged scale a portion of the epitaxial layer 14 with a portion of the adjacent bulk silicon 12. In the epitaxial layer 14, regions of opposing, donor, or n-type impurities, such as phosphorus or arsenic atoms, are embedded to a relatively shallow depth (about 0.5 to 2 microns). Selective predominance of n-type impurities forms n-type regions 22, 23, and 24 at the surface of the epi16 layer. taxal 14 and determines pn junctions 25, 26 and 27» respectively. Configuration-selective oxide layers and additionally conductive configurations deposited on the dielectric oxide layers forroa·· ·. • · no active KOS devices of the n-channel dynamic EAM described here.'.'jn .·.*.*.. ···· * ··· * In particular, transistors 28 and 29 are shown. These devices are highly interconnected and can be configured as follows: :*ￂﾷￂﾷￂﾫ ￂﾷￂﾷￂﾷￂﾷￂﾻ ￂﾷ,* known treatment phases. It is important to note, however, that none of the . .ￂ�* '··!. · · of the active HOS structures including the pn junctions extends beyond*, ré*.'I ·,,· » .· • · * · « days close to the upper surface of the epi.tàs- .*·.” silicon layer. • · · · · · sial. The structure of the entire device of each merphyid cell • · · · · is arranged near the upper surface of the epitaxial layer 14· Indeed, an optimal thickness for the epitaxial layer 14 is a thickness that only slightly exceeds the depth of the pn junction d^l the upper surface of the added layer to the expected depth of the depletion region around the junction. The determination of the depth of the depletion region is well known in the art. It depends, of course, on the doping of the semiconductor material, for example that of the epitaxial layer 14, and on the maximum reverse bias voltage to be applied to the junction. This thickness of the layer 14 simultaneously allows the junction to have the characteristics of a lightly doped layer 14, while maximizing the influence of the bulk silicon with its greatly reduced number of free electrons. Transistors 28 and 29 belong to two adjacent memory cells which are generally indicated by the numbers 30 and 31 in Figure 3. Another Each element of cells 30 and 31 is a capacitor, 32 and 33 respectively. A plate 34 in capacitor 32 forms part of the epitaxial layer 14. Similarly, a plate 35 of capacitor 33 forms the epitaxial silicon adjacent to region 24. Plates 36 and 37 of the respective capacitors 32 and 33 are spaced apart from each other. Epitaxial layer 14 by thin films of silicon oxide*.er . ; • · · · · · · ····· ·., 39, The plates 36 and 37 are preferably formed from polysilicon. · * *··*., · · line with connection extensions 41 and 42 to a common voltage plane. The gates 43 and 44 of the transistors 26 and 27 are also formed, <Ja*si^·.** • e · · · e t * · ♦ · * licio polìcristallino. Le porte 43 e 44 sono anch'esse, come le armrftMfe 36 • · · · · e 37, separate dal silicio epitassiale da sottili pellicole 46 e 47 di ossi, do di silicio. The thickness of the thin films 38, 39, 46, and 47 is selected to be in the range of about 200 Angstrom units to 2000 Angstrom units. Typically, about 900 Angstrom units are currently preferred. The thicknesses of these thin oxide films are therefore only about one-tenth of the thickness of the thickest field oxide layers 48, which are preferred to be around one micron. The junction depths of the n-type diffusions are, by comparison, also about 0.8 microns below the top surface of the epitaxial layer 14. Gates 43 and 44 form integral word select lines which extend perpendicular to the cross-section of Figure 2. Extensions 41 and 42 continue away from memory cells 30 and 31 separated from epitaxial layer 14 by field oxide layers. 48. ft A second-level metallization pattern 49, preferably aluminum, is separated from the gates and capacitor plates by an interlevel dielectric layer 50. Selective openings in layer 50 allow pattern 49 to collimate with region 23. As can be seen in Figure 2, through each gate and capacitor plate 23, a dielectric layer 50 is separated from the gates and capacitor plates. - ee * ￂﾷ ￂﾷ two memory cells (30 and 31) are placed in contact. Conductors ￂﾷdehV · * · · · · a ♦ · « * · ft ft ft · · a configuration 49 form bit sense lines of the memory device. · . · The upper surface of cells 30 and 31 is passivated by a top dielectric layer 52. ft aj * -t « ft ft « ft Figure 4 illustrates a typical concentration profile in the *.·· epitaxial layer 14, bulk silicon 12, and in the interface region between the epitaxial layer and the bulk silicon. When the epitaxial layer is grown on top of the heavily doped silicon, some diffusion out of boron dopants from the bulk silicon is encountered. Boron diffuses into the epitaxial layer, but the rate of growth of the epitaxial layer exceeds that of diffusion out of boron from the bulk silicon. Therefore, the boron concentration in the epitaxial layer quickly settles to the desired value of about 2 x 10 atoms per cubic centimeter of boron. Comparing the concentration profile By comparing the dopant with an overlying portion of the vafer 11, including one of the heavily doped n-type regions for reference, it is noted that the active regions and p-n junctions are formed entirely within silicon having a uniform dopant concentration. Figure 5 refers to an alternative memory to which the present invention can preferably be applied, the above-mentioned bre19 or; U.S. Pat. No. 4,012,757 to Koo describes, for example, a drain region and a fused capacitor region. Figure 5 also illustrates an embodiment of a memory with a drain region and a fused capacitor region (34 or 35). This embodiment tends to save space in the arrangement of the memory cells.*^) and... ). It is noted that larger memories, for example 16,384 bits * · · · · · • · · « · · '·♦··*·· compared to 4,096 bits, are affected in a particularly advantageous way.·, ; from the present invention, when the physical structure of the cells coQ'éàpà**. ····.· .· · * ; reduced memory capacity, for example, causes maintenance ceilings. ^LSoi—, »' • *. · · ***· ·*'Ζ> you. The embodiment of Figure 5 represents such a memory, .l'.numèr'i'. • · · · · indicating similar functional elements have been kept the same as those in figures 2 and 3* However, the section of FIG. 5 through the two memory cells 30 and 31 differs from the section of FIG. 2 due to a deviated arrangement of the adjacent cells 30 and 31. In addition, region 23, which is an arsenic-implanted area, is made to extend perpendicular to the plane of the section to function as the bit select line 49. Gates 43 and 44 are made of polycrystalline silicon, but their common extension of a word select line 55 is now made of aluminum. The contact between the word select line 55 and gate 44 is not shown since it existed in a position deviated from the plane of the section. The respective capacitor plates 36 and 37 extend perpendicular to the cross-section through extensions 41 and 42 to the common constant voltage source. Interlevel dielectric layers 56 and 57 separate the capacitor plates 36 and 37 from the adjacent gate conductors 43 and 44, re- . · 4 » • 4 · * * * » 4 4 4 * *4 · · * 4 »* • *4*4 * · » respectively. The operation of memory structures similar to those described here is well known in the art. The increase in cell retention times appears as a distinct deviation when the structure 4 • 4 4 * of the described memory can operate in a controlled structure in the diffusion current. In this way, the leakage currents become inversely proportional to the concentration of dopants in the materials / semiconductors in which the junctions of interest are arranged. Elimination of Harmful Impurities The ability of heavily doped bulk silicon 12 to trap harmful impurities, while improved, was found to be limited compared to a less heavily doped material. It is therefore desirable to minimize the level of harmful impurities penetrating the silicon wafer 11 from the outset. During the growth process of the epitaxial layer 14, harmful impurities enter the system via contaminated gases. However, the level of harmful impurities penetrating from the contacting gas is low. Generally, the contacting gases are sufficiently pure that they can be virtually ignored as a substantial source of contaminants or harmful impurities. However, a more significant possible source of harmful impurities has been discovered. It has been discovered that as wafers 11 are heated for the deposition of epitaxial layer 14, impurities can easily migrate from a susceptor 63 (Figure 1) across an interface between wafer 11 and susceptor 63. It therefore becomes desirable to eliminate τ* to control the inward diffusion of harmful impurities from the susceptor. For example, it has been found that certain types of susceptors are better suited to containing harmful impurities than other types. Susceptors that have been found to be particularly advantageous are made of pyrolytic graphite. The levels of impurities in the susceptors are as follows: ....... of pyrolytic graphite were low enough to make the 'lira... use provided typical lifetimes in the layered structure ^pà^ioti*. i “:· '?.· of 500 microseconds, ·:*· .* * . . · · · , .····· Jl transfer of harmful impurities from the susceptor 63 to the wafer. ·' * · · · · ·····.. • ·* *· * is favored by the direct contact between the wafers 11 and the susceptor 63* Sàura» te· * · 4 φ Ja growth of the epitaxial layer 14 on each of the wafers 11, ...·· Before growing the epitaxial layer 14 with the concentrate 15 To achieve a desired boron content of 2 x 10 atoms per cubic centimeter, self-doping should advantageously be limited. Self-doping is a phenomenon according to 1 in which the epitaxial layer 14 accepts dopants from the bulk silicon through the gaseous environment of the wafers 11. The boron elements diffuse outward from the bulk silicon into the gaseous atmosphere of the reactor and are then redeposited in the crystalline structure of the epitaxial layer 14 of each of the wafers. To control the outward diffusion of boron dopants from the bulk silicon 12, a layer 66 of highly pure polycrystalline silicon is advantageously deposited on the surface of the susceptor 63 to a thickness of about 2 to 3 microns. The wafers 11 are then supported on the surface of the coated susceptor 63. The wafers 11 are then heated to a temperature of about 1100°C in a hydrogen atmosphere. At this temperature, boron tends to evaporate from the wafer surface and hydrochloric acid is then injected in gaseous form for a time interval of 5 minutes during which approximately 0.5 microns of the silicon material are chemically removed from that surface. The rate of chemical etching or etching is faster than the evaporation of boron atoms from the silicon. In situ chemical etching is carried out for perfection. The experience of the The question was that without the chemical attack or etching phase.· trill· ' ···· :. . .· · · · epitaxial layer a large number of defects occur. ·, Μ,· ,·ζ. • · · · • 4 * While the wafers remain on the susceptor in the reactor, the temperature is reduced slightly to about 1040°C for an interval of about 1 to 2 minutes. After this time period, a growth process of the epitaxial layer 14 using dichlorosilane is initiated. The primary carrier gas is hydrogen, with dopant gases being introduced in very small amounts. It is desirable to adjust the amounts to achieve precise doping levels in the epitaxial layers. Even under ideal conditions, diffusion outward from heavily doped bulk silicon 12 has some effect on the dopant level of the epitaxial layer. Further processing steps involve the formation of MQS memory cells 30 and 31 in epitaxial layer 14. In epitaxial layer 14, regions 22, 23, and 24 of opposite conductivity type are formed either by diffusion or by ion implantation techniques. Selectivity in exposing designated areas of the surface of epitaxial layer 14 to dopant of the opposite conductivity type is achieved by selective oxide masking according to known techniques. Stages include thin oxide formation and deposition and definition of polysilicon. Sublevel dielectric layers are formed, followed by aluminum deposition for the bit detection lines. These treatment steps can be performed in accordance with the well-known procedures. . · · ·. ..., * · · » · • * c » · » · * ♦ · · · During these treatment steps, harmful impurities may be introduced at various levels either through rinse water or due to treatment in the upper surface of the wafer 11. A double treatment step is performed before forming metallization patterns. ··· * . * * .* * · final open-window phosphor tering. However, removal of harmful impurities by the highly contaminated bulk silicon 14 is believed to occur throughout the various device formation stages to minimize crystalline defects in the active areas of the epitaxial layer 14 when devices are formed at its surface. In the completion of MOS memories according to the present invention, the exclusion of sources of harmful impurities during the various processing stages is of continuing importance. It should therefore be recognized that in a substantially clean environment, the exclusion of these impurities becomes of less concern. This is particularly true in view of the established impurity trapping mechanism. Therefore, various changes can be made in the process and structures described here without departing from the protected scope of ΐ the spirit and purpose of this invention.

Claims

1. CLAIM 1 '1 - n-channel MOS memory device of the type including a plurality of MOS devices each comprising at least one region of type p and n included in a p-type silicon semiconductor characterized in that the n-type regions (22, 23, 24) are included in an epi4 · * 4 · * 4 * p-type layer formed on a p-type semiconductor body, the shot .. • 44 4 4 · · · · 4 ·· · * • y · 4 · * · semiconductor (12) having a concentration of dopants notably *: *. * · · 4 4 • · 4 4 4 greater than that of the epitaxial layer (14). '*; *. *' *;. · · 2 - Device according to Claim 1, characterized by *; ·. ". . · · · · The fact that the junctions of the n-type regions with the epitaxial layer. *, **,. * ··. ** · * ·· * .... p-type are designed to support a depletion region or • S'Juo-I • 4 · "tment during operation and by the fact that the epi tassian layer has a thickness which is limited to include the depth of the junctions and to enclose substantially no more than the thickness of the separation region in the layer when the junctions are completely inversely polarized. 3 - Device according to Claims 1 or 2, characterized in that the epitaxial layer has a quality such that the diffusion length of the electrons in the layer is at least 500 microns. 4 - Device according to Claims 1, 2 or 3, characterized in that the thickness of the epitaxial layer is no more than one-thirtieth of the diffusion length of the electrons in the layer. 5 - Device according to any one of the preceding claims, characterized in that the reverse bias leakage current of the junctions during operation at temperatures higher than 50 ° C is dominated by the diffusion of minority carriers. 6 - Device according to any one of the preceding claims, characterized in that the dopant concentration of the semiconductor body is at least one hundred times greater than that of the epitaxial layer. . · ·. * 4 • 4 4 " 7 - Device according to any one of the claims, characterized in that the semiconductor body has a short-circuit; '16 · · <· traction of dopants of at least 10 dopant atoms, of type p for óóòfcintd. ; . · Τ ... • · «· · ·. • · »tro cube and by the fact that the epitaxial layer has a concentration, dihedral * '• t, * r. 14 16. . « / . 8 - Device according to any one of the claims, firstly characterized in that the epitaxial layer is grown by heating the semiconductor in a graphite susceptor (63) coated with silicon (66). in a gaseous atmosphere. p.i. WESTERN ELECTRIC COMPANY, INCORPORATED. The Agent: