Control device and control method

Abstract

To achieve zero voltage switching during intermittent operation.SOLUTION: A control device of a main circuit including an isolated inductance portion, a primary side bridge circuit, and a secondary side bridge circuit generates resonance during the idle period by intermittent operation including a first conduction period during which a first set of semiconductor devices of the primary side bridge circuit is made conductive, a second conduction period during which a second set of semiconductor devices of the primary side bridge circuit is made conductive, and an idle period during which both the first set of semiconductor devices and the second set of semiconductor devices are made cut-off for more than half the resonance period, and sets the state of the secondary side bridge circuit during the idle period to a state where the valley of the voltage due to the resonance becomes zero voltage, and switches one set of semiconductor devices of the primary side bridge circuit to a conductive state to start injecting power at the timing when the voltage applied to the semiconductor devices of the primary side bridge circuit becomes the valley of the voltage change due to resonance.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a control device and a control method for a power conversion device. [Background technology]

[0002] There is a power conversion device including a main circuit in which a plurality of semiconductor devices are configured as a bridge and a primary bridge circuit and a secondary bridge circuit are coupled via an isolation transformer. Several methods are known as methods for controlling the main circuit in such a power conversion device. For example, a control technique (SPS control) is known in which the turn-on time of each semiconductor device is kept constant and the phase of the control of the semiconductor devices in the primary bridge circuit and the control of the semiconductor devices in the secondary bridge circuit is adjusted to adjust the magnitude and direction of power transmission. In addition, a known control method that is effective for reducing power loss in semiconductor devices is a control method that switches a semiconductor device ON / OFF during any period in which the voltage applied to the semiconductor device becomes zero voltage (zero voltage switching control, ZVS control). Also, a method is known in which, during the operation of the power conversion device, a pause period is provided in which the switching of the semiconductor devices in the bridge is paused and turned off to reduce the frequency of switching and suppress the occurrence of switching losses (called "burst mode" or "intermittent operation") (see, for example, Patent Document 1, etc.). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-118234 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, according to the above-mentioned conventional technology, when the power supply is controlled by intermittent operation that switches between a pause period and an operation period, the switching when the pause period is released and the power supply is switched to operation becomes "hard switching" and does not become zero voltage switching (ZVS). In some cases, the loss caused by this hard switching exceeds the switching loss reduced by the intermittent operation.

[0005] In view of the above circumstances, an object of the present invention is to provide a control device and a control method for a power conversion device that realizes zero voltage switching during intermittent operation. [Means for solving the problem]

[0006] One aspect of the present invention is a control device for a main circuit including an isolated inductance unit, a primary-side bridge circuit including four semiconductor devices and supplying power to the inductance unit, and a secondary-side bridge circuit including four semiconductor devices and receiving power from the inductance unit, the control device comprising: a control unit that performs intermittent operation including a first conduction period in which a first set of semiconductor devices of the primary-side bridge circuit are made conductive, a second conduction period in which a second set of semiconductor devices of the primary-side bridge circuit are made conductive, and a pause period in which both of the first set of semiconductor devices and the second set of semiconductor devices are made cut-off for longer than half of a resonance period caused by resonance between a parasitic capacitance of the primary-side bridge circuit and the inductance unit, thereby generating the resonance during the pause period, and causing the state of the secondary-side bridge circuit during the pause period to be in a state where a voltage valley caused by the resonance becomes zero voltage, and switching the set of semiconductor devices of the primary-side bridge circuit to a conductive state to start the injection of power at a timing when the voltage applied to the semiconductor devices of the primary-side bridge circuit becomes the valley of the voltage change caused by the resonance.

[0007] In one aspect of the present invention, in the control device described above, the control unit controls the primary-side bridge circuit by allocating the first conduction period, the pause period, and the second conduction period in the order described below.

[0008] One aspect of the present invention is the above-mentioned control device, wherein the control unit transitions, among the semiconductor devices of the primary side bridge circuit and the secondary side bridge circuit, a semiconductor device for which a voltage applied to the semiconductor device during the idle period is expected to be lower than a desired voltage, to a conductive state at the time when the voltage is expected to be lower.

[0009] In one aspect of the present invention, in the control device described above, the control unit controls the secondary side bridge circuit to provide a period during which the output voltage of the inductance unit is lower than a desired voltage within the pause period.

[0010] In one aspect of the present invention, in the control device, the control unit determines whether or not the control method for the main circuit is to be control including the intermittent operation depending on the magnitude of the power required for power conversion.

[0011] In one aspect of the present invention, in the control device described above, the control unit determines the length of the pause period during which the intermittent operation is performed based on the magnitude of the power of the power conversion request.

[0012] One aspect of the present invention is the control device described above, wherein the control unit determines the length of the pause period to be a discrete value based on the length of the resonance period.

[0013] In one aspect of the present invention, in the control device, the control unit determines the length of the period during which the resonance state is maintained in the pause period to be a half-integer multiple of the length of the resonance period.

[0014] One aspect of the present invention is the above-mentioned control device, wherein the control unit determines, depending on the magnitude of the power of the power conversion request, a discrete value based on the length of the resonance period and a value of a phase difference between a period during which the semiconductor devices of the secondary bridge circuit are made conductive and a period during which the semiconductor devices of the secondary bridge circuit are made conductive.

[0015] One aspect of the present invention is the control device described above, wherein the control unit controls the primary side bridge circuit by allocating the first conduction period, the second conduction period, and the pause period in the order described.

[0016] A control method according to one embodiment of the present invention is a control method for controlling a main circuit including an isolated inductance unit, a primary bridge circuit including four semiconductor devices and supplying power to the inductance unit, and a secondary bridge circuit including four semiconductor devices and receiving power from the inductance unit. The control method includes a step of generating the resonance during an idle period by intermittent operation having a first conduction period during which a first set of semiconductor devices of the primary side bridge circuit are made conductive, a second conduction period during which a second set of semiconductor devices of the primary side bridge circuit are made conductive, and an idle period during which both the first set of semiconductor devices and the second set of semiconductor devices are made cut-off for longer than half of a resonance period due to resonance between the parasitic capacitance of the primary side bridge circuit and the inductance unit, and causing a state of the secondary side bridge circuit during the idle period to be in a state where a valley of voltage due to the resonance becomes zero voltage, and switching one set of semiconductor devices of the primary side bridge circuit to a conductive state to start the injection of power at a timing when the voltage applied to the semiconductor devices of the primary side bridge circuit becomes the valley of the voltage change due to the resonance. Effect of the Invention

[0017] According to the present invention, it is possible to provide a control device and a control method for a power conversion device that realizes zero voltage switching during intermittent operation. [Brief description of the drawings]

[0018] [Figure 1] 1 is a configuration diagram of a power conversion device 100 according to an embodiment. [Figure 2A] FIG. 1 is a diagram for explaining application of ZVS control to a power conversion device according to an embodiment. [Figure 2B] FIG. 13 is a diagram showing a current waveform during SPS control. [Figure 2C]FIG. 4 is a diagram showing a current waveform during intermittent control according to the embodiment. [Diagram 3] FIG. 4 is a diagram for explaining control of the embodiment. [Figure 4A] FIG. 11 is a diagram for explaining a result of application of the control according to the embodiment. [Figure 4B] FIG. 11 is a diagram for explaining a result of application of the control according to the embodiment. [Figure 5A] FIG. 13 is a diagram for explaining a comparative example of the embodiment. [Figure 5B] FIG. 13 is a diagram for explaining a comparative example of the embodiment. [Figure 6A] 2 is a diagram for explaining losses in the power conversion device 100. FIG. [Figure 6B] FIG. 13 is a diagram for explaining SPS control of a comparative example. [Figure 7] FIG. 13 is a diagram for explaining the relationship between the number of cycles n and loss. [Figure 8] FIG. 4 is a diagram for explaining control of the embodiment. [Figure 9] FIG. 11 is a diagram showing an example of parameters of components of a main circuit used in a comparative experiment. [Figure 10] FIG. 2 is a diagram for explaining switching control between SPS control and intermittent operation in an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, a voltage of zero or near zero may be referred to as a "zero voltage." The zero voltage may be a voltage within a desired voltage range near zero. For example, when a voltage waveform that oscillates with a predetermined period is positively biased and the valley of the voltage waveform becomes "zero voltage," this is equivalent to the voltage of the valley of the voltage waveform becoming a voltage within a desired voltage range near zero. In addition, the same or corresponding components in each figure are designated by the same reference numerals and their explanations are omitted as appropriate.

[0020] [First embodiment] FIG. 1 is a configuration diagram of a power conversion device 100 according to an embodiment.

[0021] The power conversion device 100 exchanges electric power in both directions between a power source 101 and a power source 104. The power conversion device 100 includes, for example, a main circuit 102 and a control device 103. The power conversion device 100 further includes voltage detectors 171 and 172 for detecting the operating state of the main circuit 102. The power conversion device 100 includes primary side DC terminals 102a and 102b and secondary side DC terminals 102c and 102d as terminals to be connected to an external bus or the like. The main circuit 102 performs power conversion (DC / DC conversion) between a primary side DC voltage E1 across primary side DC terminals 102a, 102b and a secondary side DC voltage E2 across secondary side DC terminals 102c, 102d.

[0022] The main circuit 102 is a DC / DC converter having a DAB configuration. For example, the main circuit 102 includes a primary side bridge circuit 110, a secondary side bridge circuit 120, an inductance element 130, and smoothing capacitors 150 and 160. The primary side bridge circuit 110 and the secondary side bridge circuit 120 are an example of a pair of bridge circuits.

[0023] The primary side bridge circuit 110 forms a single-phase full bridge. Specifically, the primary side bridge circuit 110 has semiconductor devices SW1 to SW4 connected between a high potential side power supply wiring PL1 and a low potential side power supply wiring NL1. Hereinafter, the semiconductor device body is simply called a "device". The power supply wiring PL1 and the power supply wiring NL1 are connected to primary side DC terminals 102a and 102b, respectively. A smoothing capacitor 150 for stabilizing the primary side DC voltage E1 is connected between the power supply wiring PL1 and the power supply wiring NL1. The semiconductor devices SW1 to SW4 have devices S1 to S4, respectively.

[0024] The devices S1 and S2 are connected in series via a node N1a to form a first leg 111 connected between the power supply line PL1 and the power supply line NL1. The node N1a is connected to an AC terminal 123a. Similarly, the devices S3 and S4 are connected between the power supply line PL1 and the power supply line NL1 via a node N1b to form a second leg 112. The node N1b is connected to an AC terminal 123b.

[0025] Similarly, the secondary bridge circuit 120 forms a single-phase full bridge. Specifically, the secondary bridge circuit 120 has semiconductor devices SW5-SW8 connected between a high-potential side power supply wiring PL2 and a low-potential side power supply wiring NL2. The semiconductor devices SW5-SW8 each have devices S5-S8. The power supply wiring PL2 and the power supply wiring NL2 are connected to secondary side DC terminals 102c and 102d, respectively. A smoothing capacitor 160 for stabilizing the secondary side DC voltage E2 is connected between the power supply wiring PL2 and the power supply wiring NL2.

[0026] The devices S5 and S6 are connected in series between the power supply wiring PL2 and the power supply wiring NL2 via a node N2a connected to the AC terminal 124a to form a third leg 121. Similarly, the devices S7 and S8 are connected in series between the power supply wiring PL2 and the power supply wiring NL2 via a node N2b connected to the AC terminal 124b to form a fourth leg 122. In the first to fourth legs 111, 112, 121, 122, the devices S1, S3, S5, and S7 form an "upper arm," and the devices S2, S4, S6, and S8 form a "lower arm." Hereinafter, the devices S1 to S8 will be collectively referred to as device S.

[0027] The device S has a self-extinguishing switching element and a diode. The switching element can be configured by any self-extinguishing element such as an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or a GCT (Gate Commutated Turn-off) thyristor. The diode is connected in anti-parallel to the switching element to configure a free wheeling diode (FWD). In the case of a MOSFET, the diode may be a body diode.

[0028] The inductance element 130 has primary side AC terminals 130a and 130b respectively connected to the AC terminals 123a and 123b of the primary side bridge circuit 110, and secondary side AC terminals 130c and 130d respectively connected to the AC terminals 124a and 124b of the secondary side bridge circuit 120. In the example of Fig. 1, the inductance element 130 is configured including a transformer 131 having a primary winding connected between the primary side AC terminals 130a and 130b and a secondary winding connected between the secondary side AC terminals 130c and 130d.

[0029] Note that the inductance element 132 may be provided in series with the winding of the transformer 131. For example, the inductance element 132 is connected in series with the primary winding of the transformer 131 as shown in FIG. 1. The inductance element 132 may be provided in a distributed manner. In this case, for example, the inductance element 132 may be divided into the primary side and the secondary side of the transformer 131, or into the positive side and the negative side of the primary side of the transformer 131. The inductance element 132 may be incorporated as a part of the inductance element 130. Note that the relationship between the voltage ratio between the primary side voltage E1 and the secondary side voltage E2 and the turns ratio of the transformer 131 can be expressed as E1=N·E2.

[0030] The voltage detector 171 detects the voltage across the terminals of the smoothing capacitor 150, i.e., the primary side DC voltage E1, and outputs a signal indicating the detected value to the control device 103. The voltage detector 172 detects the voltage across the terminals of the smoothing capacitor 160, i.e., the secondary side DC voltage E2, and outputs a signal indicating the detected value to the control device 103.

[0031] The control device 103 is a computer including a CPU capable of executing a program, a semiconductor memory, and the like. For example, the control device 103 includes a control unit 1031, an interface unit, and a storage unit 1032. The control device 103 executes the main processing of the control device 103 by causing the control unit 1031 (CPU) to execute a program, and causes the storage unit 1032 to store the results of the processing. The interface unit is connected to the main circuit 102, etc. The control unit 1031 controls the main circuit 102 through its processing. In the following description, the processing by the control unit 1031 may be described as the processing of the control device 103.

[0032] The above-described power conversion device 100 is an example of a DAB converter.

[0033] Application of ZVS control to the power conversion device of the embodiment will be described with reference to FIGS. 2A to 2C. Fig. 2A is a diagram for explaining application of ZVS control to the power conversion device of the embodiment. Fig. 2B is a diagram showing a current waveform during SPS control. Fig. 2C is a diagram showing a current waveform during intermittent control of the embodiment. Note that the current waveforms shown in Figs. 2B and 2C are modeled examples.

[0034] The right-hand range in Fig. 2A is the range in which ZVS control can be applied, and is called the ZVS operating range. The left-hand range in Fig. 2A (hatched range) is the range in which application of ZVS control is restricted, and is called the restricted range.

[0035] If the SPS control is performed within the ZVS operating range, the semiconductor device can be subjected to ZVS control, thereby reducing the loss of the semiconductor device. However, in the comparative example using SPS control, there were regions where the semiconductor device could not be ZVS controlled, and in such a comparative example, the effect of reducing losses due to ZVS control could not be obtained.

[0036] For example, the ZVS operating range and limit range are distinguished by the magnitude of the peak value ip of the inductor current. The parasitic output capacitance of the semiconductor device differs depending on the type of semiconductor device. When the peak value ip becomes smaller than a predetermined value, sufficient current cannot flow even when the semiconductor device is turned on. In such a situation, it may be impossible to complete charging and discharging the parasitic output capacitance of the semiconductor device within a desired time. When the limit range is reached, the charge accumulated in the parasitic output capacitance of the semiconductor device cannot be discharged completely, and the voltage applied to the semiconductor device does not become zero. As a result, the power conversion device of the comparative example cannot perform ZVS operation, and switching loss may increase.

[0037] Therefore, in this embodiment, an example for enabling ZVS operation by avoiding a situation that may fall within the limiting range will be described.

[0038] The control of the embodiment will be described with reference to FIG. FIG. 3 is a diagram for explaining the control according to the embodiment. The timing chart in Figure 3 shows the switching patterns of each device and the relationship between the voltage and current of each part.

[0039] The signals assigned from (a) to (f) on the upper side of Figure 3 are shown in order. (a) shows the state of the primary side devices S1-S4 (called primary side devices), (b) to (e) show the state of the secondary side devices S5-S8 (called secondary side devices), (f) shows the transformer primary side voltage e1, (g) shows the transformer secondary side voltage e2, (h) shows the voltage (drain-source voltage) vs1 of device S1, and (i) shows the inductor current iL. The states of the devices assigned from (a) to (e) are shown as two values, on (ON) and off (OFF). Devices listed here are shown to be on (ON), and devices not listed are shown to be off (OFF).

[0040] The control within the period shown in FIG. 3 will be explained below according to the procedure. Time t1 is the starting point of one control cycle. At time t1, the control unit 1031 turns on devices S1 and S4 among the primary side devices S1-S4 (referred to as primary side devices). As described above, devices S2 and S3, which are not shown, remain in the off state.

[0041] At time t1, due to the control result of the previous control cycle, among the secondary side devices S5-S8 (referred to as secondary side devices), devices S6 and S8 remain on. By keeping devices S6 and S8 on, the transformer secondary side voltage e2 becomes zero.

[0042] As a result, the transformer primary voltage e1 becomes voltage E1, the transformer secondary voltage e2 and the voltage vs1 of the device S1 become zero, and the inductor current iL gradually increases.

[0043] The period from time t1 to t2 is designated as Tinc. The time Tpri during which the primary side device is turned on is related to the magnetic flux density of the core of the transformer 131. It is preferable to set the product of voltage and time during this period to be constant. The method of keeping the product of voltage and time during this period constant may be the same as that used in the case of using SPS control in the first comparative example described later.

[0044] The control unit 1031 turns off the device S6 at time t2. This causes the transformer secondary voltage e2 to become voltage E2, and the inductor current iL stops increasing. If the voltage ratio between the primary voltage e1 and the secondary voltage e2 matches the turns ratio of the transformer, the inductor current iL becomes approximately constant.

[0045] The control unit 1031 turns on the device S5 at time t3 after time t2. At this stage, the voltage e2 on the secondary side of the transformer (the potential of the secondary side AC terminal 130c) becomes equal to the potential E2 of the power supply 104.

[0046] The control unit 1031 turns off devices S1, S4, and S8, for example, at a point (time t4) when a predetermined time (period Tpri) has elapsed from time t1. As a result, current does not flow through devices S1 and S4, and current flows through the reverse-connected diodes of devices S2 and S3. In the process, the parasitic capacitances of devices S1 and S4 are charged, and the parasitic capacitances of devices S2 and S3 are discharged. As a result, the primary side voltage e1 changes from E1 to -E1, and the device voltage vs1 of device S1 rises to E1. Device S8 is off, but the reverse-connected diodes are conductive.

[0047] After time t4, there is a period during which both devices S1, S4 and devices S2, S3 are off, and this off period is set to be relatively long. In this way, the difference from the comparative example is that a period in which both devices S1, S4 and S2, S3 are off is provided between the period Tpri in which devices S1, S4 are on and the period in which devices S2, S3 (described later) are on. The period in which both devices S1, S4 and S2, S3 are off is called a quiescent period. The period from time t4 to time t11 is an example of a quiescent period.

[0048] The above description of the operation during the idle period in which both devices S1 and S4 and devices S2 and S3 are turned off will be continued. As noted above, by time t5, device S8 has been turned off.

[0049] For example, at time t5, the current changes from positive to negative, and the reverse conducting diode of device S8 (which is already off) becomes reverse biased. As a result, the parasitic capacitance of device S8 is charged and the parasitic capacitance of device S7 is discharged. After that, when the parasitic capacitance of device S7 is completely discharged, the reverse conducting diode of device S7 becomes forward biased and conducts. After this, the reverse conducting diodes of devices S5 and S7 conduct, causing voltage e2 to become zero (or a voltage close to zero that can be considered to be zero). As described above, after the reverse conducting diode of device S7 becomes forward biased and starts conducting, control unit 1031 may turn on device S7, which causes device S7 to also become ZVS. In the primary side devices, after time t5, the reverse-connected diodes of devices S2 and S3 become reverse-biased and the reverse-connected diodes of S1 and S4 become conductive. In the process, the parasitic capacitances of devices S2 and S3 are charged, and the parasitic capacitances of devices S1 and S4 are discharged. After charging and discharging of both the primary side devices and the secondary side devices are completed, current flows through the reverse-connected diodes of devices S1 and S4 and devices S5 and S7, but at time t7, current iL reaches zero again. After time t7, resonance occurs between the parasitic capacitance of the primary side device and the transformer 131 and continues. The period during which such resonance occurs is called a resonance period Tosc. For example, the control unit 1031 sets the voltage e2 to zero within this resonance period Tosc, and then switches on the device S7 at some timing within the period until the current iL becomes zero again. Time t7 in Fig. 3 indicates the latest timing within the above period. The control unit 1031 may switch on the device S7 at time t7, for example, to turn on the devices S5 and S7.

[0050] The switching pattern of turning on the above-mentioned devices S5 and S7 creates a state in which the impedance on the secondary side of the transformer 131 is lowered. In this way, the valley of the resonant voltage generated in the primary side device during the resonant period Tosc can be set to zero or a value close to zero.

[0051] The state of the resonance period Tosc will be explained by dividing it into the first half and the second half. The first half is a predetermined period T1, and the second half is a period determined by the resonance period T2. For example, the resonance period T2 is from time t7 to time t8. The resonance in the latter half is assumed to be a simple LC resonance. The number (number of cycles) indicating the magnification of the resonance period T2 is denoted by n. To achieve ZVS control, the value of the number of cycles n is set to an odd multiple of 0.5. It is advisable to control the duration of the latter half of the resonance period Tosc according to the value of this number of cycles n. In this case, the duration of the latter half of the resonance period Tosc is nT2, and a discrete value can be set according to the value of the number of cycles n.

[0052] The control unit 1031 adjusts the length of the latter half of the resonance period Tosc so as to satisfy this, thereby making the device voltage vs1 of the device S1 zero at the end of the resonance period Tosc. At time t11, the control unit 1031 turns on the devices S2 and S4 to realize the ZVS operation. This ends the pause period.

[0053] The above explanation corresponds to the first half of the control cycle TSW. The second half of the control cycle TSW, from time t11 to time t21, corresponds to the first half of the control cycle TSW, from time t1 to time t11. The control unit 1031 switches the control targets from the set of devices S1 and S4 to the set of devices S2 and S3, and from the set of devices S6 and S8 to the set of devices S5 and S7. By utilizing such symmetrical characteristics, the control pattern of the first half can be reused.

[0054] By controlling each device in this way, ZVS can be achieved for all switching operations, including the primary and secondary sides, unlike the commonly used intermittent operation.

[0055] The result of applying the control of the embodiment will be described with reference to FIGS. 4A to 6B. Fig. 4A and Fig. 4B are diagrams for explaining the application results of the control of the embodiment, and Fig. 9 is a diagram showing an example of parameters of components of the main circuit used in the comparative experiment.

[0056] The configuration used in this comparative experiment is an example of a power conversion device 100 with a rated capacity of 3.3 kW for power conversion using a SiC type MOSFET (3.3 kV, 23 A) on the high voltage side (primary side). Parameters of the main circuit 102 are shown in Fig. 4C. The illustrated power conversion device 100 aims to reduce the conduction loss of the device, and uses a device with a relatively large rated current and output capacity compared to the current used. In addition, a relatively high switching frequency was selected for the purpose of miniaturizing the transformer 131. Such a combination of conditions tends to be easily affected by the output capacitance of each device.

[0057] 4A and 4B show experimental results when the number of cycles n of the resonance period is a half integer, more specifically, the number of cycles n is set to 2.5 and the conversion power is set to 1200 (W). FIG. 4A shows the relationship between the primary voltage e1, secondary voltage e2, and current iL of the transformer 131, and FIG. 4B shows the relationship between the current iL and device voltage vs1. As shown in Figure 4B, for example, it can be confirmed that the device S1 is turned on at the valley of the amplitude of the device voltage vs1 applied to the device S1. Although the resonant voltage included in the device voltage vs1 may be attenuated to some extent by the resistance components of the circuit, the device voltage vs1 is close to zero. For this reason, it is considered that the switching loss that occurs is very small.

[0058] On the other hand, in general intermittent operation, it is not known at what point in the resonating device voltage the device will be turned on. In order to simulate this and compare it with the operation of the proposed method, we deliberately set the number of cycles n to 2 so that switching (hard switching) occurs at the peak of the resonant voltage. 5A and 5B are diagrams for explaining a comparative example of the embodiment. Fig. 5A and Fig. 5B show experimental results when the value of the number of cycles n is an integer, more specifically, the value of the number of cycles n is set to 2 (n = 2), and the conversion power is set to 1200 (W). FIG. 5A shows the relationship between the primary voltage e1, secondary voltage e2, and current iL of transformer 131 of the comparative example, and FIG. 5B shows the relationship between the current iL and device voltage vs1 of the comparative example.

[0059] Figure 5B shows the waveform of a part of the period in Figure 5A with the time axis expanded. As shown here, the inductor current iL fluctuates between positive and negative periodically due to resonance. When the inductor current iL becomes zero and the voltage vs1 applied to the device S1 reaches the peak value of the resonant voltage, the device S1 is turned on. If the device S1 is switched at such a timing, ZVS will not be achieved and a relatively large switching loss will occur in the device S1.

[0060] Losses in the power conversion device 100 that are affected by the control method will be described with reference to Figures 6A and 6B. Figure 6A is a diagram for explaining losses in the power conversion device 100. Figure 6B is a diagram for explaining SPS control of a comparative example. First, the SPS control of the comparative example shown in FIG. 6B will be described. The SPS control shown here is an example of a method of adjusting the direction and magnitude of power conversion by, for example, keeping the turn-on time of each semiconductor device constant and adjusting the phase of the control of the semiconductor devices in the primary bridge circuit and the control of the semiconductor devices in the secondary bridge circuit.

[0061] For example, the SPS control during the period shown in FIG. 6B will be described according to the procedure. The period from time t30 to time t50 is defined as one period of SPS control. At time t31, the control unit 1031 turns on devices S1 and S4 among the primary side devices S1-S4 (referred to as primary side devices). As described above, devices S2 and S3, which are not shown, remain in the OFF state. Time t30 arrives after time t31.

[0062] At time t31, due to the control result of the previous control cycle, among the secondary side devices S5-S8 (referred to as secondary side devices), devices S6 and S7 remain on. By keeping devices S6 and S7 on, the transformer secondary side voltage e2 becomes -E2.

[0063] With devices S1 and S4 turned on, the transformer primary voltage e1 becomes voltage E1. The inductor current iL gradually increases due to the voltages e1 and e2 applied to the transformer.

[0064] At time t32, among the secondary side devices, devices S6 and S7 are turned off. Then, at time t33, among the secondary side devices, devices S5 and S8 are turned on. By turning on devices S5 and S8, the transformer secondary side voltage e2 becomes E2, and the inductor current iL stops increasing. The on-period of devices S1 and S4 and the on-period of devices S2 and S3 are denoted as Tpri. For example, the on-period (Tpri) of devices S1 and S4 is from time t31 to time t34. The period Tpri of the primary side devices is related to the magnetic flux density of the core of transformer 131. It is advisable to set the product of voltage and time during this period to be constant.

[0065] At time t34, the control unit 1031 turns off the devices S1 and S4, causing the transformer primary voltage e1 to become the voltage −E1, and the inductor current iL starts to decrease. At time t41 after time t34, the control unit 1031 turns on devices S2 and S3 among the primary side devices.

[0066] At time t42, the control unit 1031 turns off devices S5 and S8 among the secondary side devices. Then, at time t43, the control unit 1031 turns on devices S6 and S7 among the secondary side devices. By turning off devices S5 and S8, the transformer secondary side voltage e2 becomes −E2, and the decrease in inductor current iL stops.

[0067] The above description corresponds to the first half of the control cycle TSW of SPS control. The period from time t41 to time t51 corresponds to the first half period from time t31 to time t41 described above. The control unit 1031 switches the control targets from the set of devices S1 and S4 to the set of devices S2 and S3, and from the set of devices S5 and S8 to the set of devices S6 and S7. By utilizing such symmetrical characteristics, the control pattern of the first half can be reused. After time t51, the same control as after time t31 is repeated. After time t51 comes time t50, which is the start of the next cycle of SPS control. Neither time t30 nor time t50 is the timing for switching the state of each device. Here, the timing at which the inductor current iL passes zero and changes direction is used as the timing for dividing the cycle.

[0068] FIG. 6A shows measured loss values ​​of the power conversion device 100 when controlled under different control conditions. The control conditions shown here include the intermittent control of this embodiment, SPS control as a first comparative example, and intermittent control as a second comparative example (FIGS. 5A and 5B).

[0069] In the SPS control of the comparative example shown in Figure 6B, the direction and magnitude of power conversion are adjusted by adjusting the phase of two square waves with a duty ratio of approximately 0.5. However, a phenomenon may occur in which the switching loss of the device increases even when the load is reduced and the load current is small. In the example shown here, the switching loss increases when the load falls below 2500W. It is presumed that this phenomenon occurs because, as the load current decreases, the effect of the parasitic output capacitance cannot be ignored, resulting in a situation in which ZVS cannot be achieved and an increase in switching losses.

[0070] Therefore, similarly to the results of the SPS control of the comparative example, the results of applying this embodiment are plotted in the graph of FIG. 6A. By setting the number of cycles n to a half integer, it is possible to set it in ascending order, for example, 0.5, 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, 7.5, 8.5, 9.5, etc. The graph in Fig. 6A shows the evaluation results when the number of cycles n is set to five values: 0.5, 1.5, 2.5, 5.5, 9.5, and 15.5. Note that there is no restriction on increasing the value of the number of cycles n by 1, and it is also possible to omit it as appropriate and make the difference value discontinuous.

[0071] As shown in FIG. 6A, the control of this embodiment shows a tendency for relatively low losses at light loads. It is also applicable even in situations where the comparative example falls within the limit range. It can be confirmed that when operating under these conditions, losses are significantly reduced compared to those expected when applying SPS control. The control of this embodiment shows that losses are reduced even at light loads where losses increase when applying SPS control, confirming the effectiveness of the proposed control.

[0072] Furthermore, the effectiveness of this embodiment was verified by changing the value of the number of cycles n of the resonance period. The result is shown below, where the value of the number of cycles n of the resonance period is changed from 2.5 to 2, with the conversion required power being 1200 (W). It was confirmed that the loss increased significantly when the value of the number of cycles n was changed from 2.5 to 2. This is presumably because the switching at the end of the pause period becomes hard switching due to the number of cycles n being an integer. In actual operation, when the number of cycles n is set to 2, large switching losses occur, so this is not a recommended operating method. The case where the number of cycles n is set to an integer (comparative example) was implemented to verify the effectiveness of the loss reduction with and without the ZVS operation of this embodiment.

[0073] With reference to FIG. 7, the difference in loss when the number of cycles n is set to an integer and a half integer will be described. FIG. 7 is a diagram for explaining the relationship between the number of cycles n and the loss. The graph in FIG. 7 shows the measurement results of loss and the analysis results of loss when the number of cycles n is set to an integer (n = 2) and a half integer (n = 2.5). The loss measurement results show the power loss (total loss) calculated by inserting a power meter into the input and output and taking the difference between the values. The analysis results of the losses are estimated by summing the results of three separate calculations: Eoss, Eqoss, and the conduction loss of the MOSFET. Here, Eoss is the power loss corresponding to the dissipation of energy stored in the output capacitance of the device. Also, Eqoss is the power loss corresponding to the energy dissipated in the device that is turned on when the device is turned on, which charges the opposing device. These losses due to the output capacitance can be calculated from the measured parasitic capacitance of the device.

[0074] As shown in Figure 7, the reduction in Eoss and Eqoss obtained from the analysis results when the number of cycles n is changed from an integer (n = 2) to a half integer (n = 2.5) roughly matches the reduction in total loss obtained from the measurement results. As mentioned above, intermittent operation with the number of cycles n being an integer (n = 2) is an example of an intentionally set inappropriate case, so in actual general intermittent operation, it is possible that switching losses will be lower even if hard switching is performed. However, the results confirmed that whether or not ZVS is achieved has a strong impact on power conversion efficiency.

[0075] According to the above embodiment, the control device 103 is a control device for a main circuit including an insulating transformer 131 (inductance unit), a primary bridge circuit including four semiconductor devices and supplying power to the inductance unit, and a secondary bridge circuit including four semiconductor devices and receiving power from the inductance unit. The control unit 1031 of the control device 103 performs intermittent operation including a first conduction period in which a first set of semiconductor devices of the primary bridge circuit are made conductive, a second conduction period in which a second set of semiconductor devices of the primary bridge circuit are made conductive, and a pause period in which both the first set of semiconductor devices and the second set of semiconductor devices are made cut off for more than half the resonance period caused by resonance between the parasitic capacitance of the primary bridge circuit and the inductance unit, thereby generating resonance of the inductance unit during the pause period, making the state of the secondary bridge circuit during the pause period a state in which the valley of the voltage caused by the resonance becomes zero voltage, and switching one set of semiconductor devices of the primary bridge circuit to a conductive state and starting power injection at the timing when the voltage applied to the semiconductor devices of the primary bridge circuit becomes the valley of the voltage change caused by the resonance. In this way, the control device 103 can realize zero voltage switching during intermittent operation.

[0076] The control unit 1031 of the control device 103 may control the primary side bridge circuit by allocating the first conduction period, the pause period, and the second conduction period in the order described above.

[0077] The control unit 1031 of the control device 103 may transition, among the semiconductor devices of the primary side bridge circuit and the secondary side bridge circuit, those semiconductor devices for which the voltage applied to the semiconductor devices during the idle period is expected to be lower than the desired voltage, to a conductive state at the time when the voltage is expected to be lower.

[0078] The control unit 1031 of the control device 103 controls the secondary bridge circuit to provide a period during which the output voltage of the transformer 131 is lower than a desired voltage within the pause period, thereby enabling ZVS.

[0079] Furthermore, according to the embodiment, zero voltage switching can be realized even with intermittent control, thereby improving the efficiency of power conversion, especially during light loads where hard switching occurs with conventional control methods. The reduction in switching loss of the device allows the selection of a smaller device, which in turn allows the switching frequency of the device to be increased, thereby enabling the transformer 131 to be made smaller. Furthermore, according to the embodiment, since an increase in loss is suppressed even if the parasitic capacitance of the semiconductor device is large, a semiconductor device with a large chip area can be adopted, thereby making it possible to reduce the conduction loss of the semiconductor device.

[0080] In the control of the above embodiment, it is preferable to adjust the control so as to satisfy the following requirements. (1) It is advisable to switch the pair of devices S1 and S4 and the pair of devices S2 and S3 together. (2) During the period Tdec, devices S2 and S3, or devices S1 and S4 may be turned on. Note that a dead time is required to charge and discharge the parasitic capacitance. In addition, devices S2 and S3 may be turned on during the period Tdec after the period in which the pair of devices S1 and S4 are on, and devices S1 and S4 may be turned on during the period Tdec after the period in which the pair of devices S2 and S3 are on. (3) Devices S1 and S4 are connected to a device voltage v s1 ZVS is achieved by turning on the devices S2 and S3 at the timing when the device voltage v s3 ZVS is achieved by turning it on when the current becomes zero. (4) Although the device S8 may be kept on after the period Tdec has begun, the device S8 must be turned off before entering T1. When T1 begins, the device S8 is charged, generating a device voltage vs8. (5) After vs8 is charged and vs7 is discharged, device S7 is turned on to achieve ZVS. Note that device S7 must be turned on within the period T1. After this period, the period (nT2) during which resonance occurs will begin, but the resonance will become such that the valley of the resonance becomes high, making it difficult to achieve ZVS. (6) Devices S5 and S6 can be controlled in the same way as SPS control, that is, devices S5 and S6 can be switched after the parasitic capacitances are charged and discharged. (7) The roles of devices S5 and S6 may be exchanged with the roles of devices S8 and S7. For example, the control of devices S5 and S8 may be exchanged, and the control of devices S6 and S7 may be exchanged. (8) The sequence shown in FIG. 3 is an embodiment in which an OFF period is inserted every half cycle. In this case, the switch to be controlled during the resonance period is determined depending on whether the half cycle of the current iL before the resonance period is positive or negative. (9) If the operation method involves a rest period every half cycle, it is advisable to set the on-time of all devices on the primary side to the same time. (10) The turn-off time difference (phase difference) between devices S1 and S4 and devices S6 and S7 may be adjusted based on the required conversion power.

[0081] [Second embodiment] A second embodiment will be described with reference to FIG. In the first embodiment described above, a case where the ZVS control is enabled by applying the intermittent control to a situation that is not subject to the ZVS control is described. In addition to this, in this embodiment, an application example in which the SPS control is transitioned to the intermittent control in the ZVS operation range is described.

[0082] FIG. 8 is a diagram for explaining the control according to the embodiment. The types of signals shown in the timing chart of Fig. 8 correspond to the types of signals shown in the timing chart of Fig. 3. The following mainly describes the differences from Fig. 3.

[0083] The period from time t1 to time t15 shown in FIG. 8 includes the period during which the SPS control shown in the previous figures is applied.

[0084] For example, it is assumed that the period before time t1 is the above-mentioned idle period. In this case, time t1 is the starting point of one control cycle, and a first conduction period, a second conduction period, and a pause period are allocated to this one cycle in the order listed. At time t1, the control unit 1031 turns on devices S1 and S4 among the primary side devices S1-S4 (referred to as primary side devices). As described above, devices S2 and S3, which are not shown, remain in the off state.

[0085] At time t1, the previous control cycle is in a pause period, and among the secondary side devices, devices S6 and S8 remain on. By turning on devices S6 and S8, the transformer secondary side voltage e2 becomes zero.

[0086] As a result, the transformer primary voltage e1 becomes voltage E1, the transformer secondary voltage e2 and the voltage vs1 of the device S1 become zero, and the inductor current iL gradually increases.

[0087] The period from time t1 to time t2 is the turn-on time Tinc of devices S1 and S4. The control unit 1031 turns off the device S6 at time t2. This causes the transformer secondary voltage e2 to become voltage E2, and the inductor current iL stops increasing. If the voltage ratio between the primary voltage e1 and the secondary voltage e2 matches the turns ratio of the transformer, the inductor current iL becomes approximately constant.

[0088] Here, the control unit 1031 switches to a control in which the first conduction period and the second conduction period are consecutively performed, as in the SPS control. For example, the control unit 1031 turns on the device S5 at time t33 after time t2. At this stage, the voltage e2 on the secondary side of the transformer becomes equipotential with the potential E2 of the power source 104.

[0089] From this point onwards, up to time t43, refer to the description of the SPS control in FIG. 6B. At time t43, the control unit 1031 turns on devices S6 and S8 among the devices on the secondary side. By turning on devices S6 and S8, the transformer secondary voltage e2 becomes −E2, and the decrease in the inductor current iL stops. The above explanation corresponds to the first half of the control period TSW, which includes the SPS control. At time t15, which is a predetermined time after time t43, the control unit 1031 switches to intermittent control. In this manner, the period from time t33 to time t15 corresponds to SPS control. Note that the period from time t15 to time t21 is a pause period of intermittent control. After time t21, the same control as that after time t1 is repeated.

[0090] In this way, the control unit 1031 interrupts the continuous SPS control and inserts a pause period after time t15. For example, the control unit 1031 turns off all of the devices S1 to S4 at time t15 to start an idle period. Resonance occurs during this idle period, and the device voltage vs1 becomes zero at time t21. The control unit 1031 turns on the devices S1 and S4 at this timing, thereby reducing losses due to switching of the devices S1 and S4.

[0091] The above description illustrates ZVS control of the device S1, but the same applies to the other devices. In addition, the sequence shown in Fig. 8 includes one pause period in which the value of the number of cycles n is set to 1.5. In this way, by providing a pause period during SPS control, the average power can be reduced.

[0092] With reference to FIG. 10, an operation for switching between SPS control and intermittent operation according to the embodiment will be described. Fig. 10 is a diagram for explaining the switching control between the SPS control and the intermittent operation in the embodiment. The characteristics shown in Fig. 10 correspond to the characteristics shown in Fig. 2 described above.

[0093] 10 shows the region where SPS control is applied and the region where SPS control cannot be applied and intermittent control is applied. More specifically, in the region where intermittent control is applied, the value of the number of cycles n of resonance during the pause period is specified.

[0094] For example, a case will be described in which the magnitude of the required power gradually decreases. In the first stage, the control unit 1031 applies the SPS control. When the magnitude of the required power decreases and the peak current ip falls to the threshold ip.ZVS, the control unit 1031 switches from SPS control to intermittent control. At this time, the control unit 1031 refers to the conversion table stored in the storage unit 1032 to obtain the value of the number of cycles n of resonance during the pause period for the magnitude of the required power. In this figure, the value of the number of cycles n is 0.5.

[0095] Similarly, when the required power is further reduced and the peak current ip falls to the threshold ip.ZVS, the control unit 1031 refers to the conversion table stored in the storage unit 1032 and updates the value of the number of cycles n. In this figure, the value of the number of cycles n is 1.5. The control unit 1031 obtains a longer pause period by repeatedly referring to the conversion table and updating the value of the number of cycles n in the same manner as described above. This makes it possible to apply the method to areas with low required power.

[0096] According to the above embodiment, a pause period (pause mode) can be inserted at any time when the current iL becomes zero in the SPS control. The period from when device S5 is turned on to when device S7 is turned off shown in FIG. 8 follows the same sequence as in SPS control. When a pause period is provided, the control unit 1031 turns off the device S7 before the current iL becomes zero, for example. As a result, after the current iL becomes zero, the control unit 1031 turns on the device S8 within the period T1 of the resonance period Tosc. This makes it possible to continue the resonance for a length of nT2. Depending on whether the half cycle of the current iL in the period T1 is positive or negative, the control unit 1031 determines and operates the device to be controlled.

[0097] By using SPS control, highly efficient operation is possible through ZVS operation when the load is relatively high.

[0098] According to the above embodiment, the control unit 1031 of the control device 103 can determine whether the control method for the main circuit 102 is to include intermittent operation, depending on the magnitude of the power required for power conversion.

[0099] In the above-described manner, the control unit 1031 may determine the length of the suspension period during which the intermittent operation is performed depending on the magnitude of the power of the power conversion request.

[0100] The control unit 1031 determines the length of the pause period to be a discrete value based on the length of the resonance period.

[0101] The control unit 1031 may determine the length of the period during which the resonance state is maintained in the pause period to be a half-integer multiple of the length of the resonance period.

[0102] The control unit 1031 may determine the magnitude of the power of the power conversion request based on a discrete value based on the length of the resonance period and the value of the phase difference between the period during which the semiconductor devices of the secondary bridge circuit are made conductive and the period during which the semiconductor devices of the secondary bridge circuit are made conductive.

[0103] According to at least any of the above-described embodiments, the control device for a main circuit includes an isolated inductance section, a primary bridge circuit including four semiconductor devices and supplying power to the inductance section, and a secondary bridge circuit including four semiconductor devices and receiving power from the inductance section. The control device performs intermittent operation including a first conduction period during which a first set of semiconductor devices of the primary side bridge circuit are made conductive, a second conduction period during which a second set of semiconductor devices of the primary side bridge circuit are made conductive, and a pause period during which both the first set of semiconductor devices and the second set of semiconductor devices are made cut-off for exceeding half of a resonance period due to resonance between the parasitic capacitance of the primary side bridge circuit and the inductance section, thereby generating resonance of the inductance section during the pause period, and bringing the state of the secondary side bridge circuit during the pause period into a state where the valley of voltage due to the resonance becomes zero voltage, and is configured to switch the set of semiconductor devices of the primary side bridge circuit into a conductive state to start the injection of power at a timing when the voltage applied to the semiconductor devices of the primary side bridge circuit becomes the valley of the voltage change due to the resonance. This allows for zero voltage switching during intermittent operation.

[0104] Although the preferred embodiment of the present invention has been described in detail above, the present invention is not limited to the specific embodiment, and various modifications and changes are possible within the scope of the gist of the present invention described in the claims.

[0105] The present invention can be used in the following applications: For example, the above-mentioned power conversion device 100 can be used in power conversion devices including main circuits that require insulation, further, among these power conversion devices, power conversion devices (equipment) that exchange power in both directions, solid-state transformers (SSTs) that are expected to replace power transformers, and on-board chargers for electric vehicles that have the ability to supply power to a power grid. [Explanation of symbols]

[0106] 100...Power conversion device 101, 104…Power supply (DC power supply) 102…Main circuit 103...Control device 110...Primary bridge circuit 120...Secondary bridge circuit 130...Inductance element 131...Transformer 1031...Control unit 1032...Storage section

Claims

1. An insulated inductance section; a primary bridge circuit including four semiconductor devices and supplying power to the inductance unit; a secondary bridge circuit including four semiconductor devices and receiving power from the inductance unit; A control device for a main circuit comprising: an intermittent operation including a first conduction period during which a first set of semiconductor devices of the primary bridge circuit are made conductive, a second conduction period during which a second set of semiconductor devices of the primary bridge circuit are made conductive, and a pause period during which both the first set of semiconductor devices and the second set of semiconductor devices are made cut off for more than half a resonance period caused by resonance between a parasitic capacitance of the primary bridge circuit and the inductance unit, thereby generating the resonance in the pause period; a control unit that sets the state of the secondary bridge circuit during the pause period to a state in which the valley of the voltage due to the resonance becomes zero voltage, and switches a pair of semiconductor devices of the primary bridge circuit to a conductive state at a timing when the voltage applied to the semiconductor devices of the primary bridge circuit becomes the valley of the voltage change due to the resonance, thereby starting the injection of the power. A control device comprising:

2. The control unit is The first conduction period, the pause period, and the second conduction period are assigned in the order described above to control the primary bridge circuit. The control device according to claim 1 .

3. The control unit is among the semiconductor devices of the primary side bridge circuit and the secondary side bridge circuit, a semiconductor device in which a voltage applied to the semiconductor device is expected to be lower than a desired voltage during the idle period is transitioned to a conductive state at a timing when the voltage is expected to be lower. The control device according to claim 1 .

4. The control unit controls the secondary bridge circuit, A period during which the output voltage of the inductance unit is lower than a desired voltage is provided within the pause period. The control device according to claim 1 .

5. The control unit is determining whether or not the control method of the main circuit is to be the control including the intermittent operation depending on the magnitude of the power required for power conversion; The control device according to claim 1 .

6. The control unit is determining a length of the pause period during which the intermittent operation is performed based on the magnitude of the power of the power conversion request; The control device according to claim 5.

7. The control unit is determining a length of the pause period to a discrete value based on a length of the resonance period; The control device according to claim 6.

8. The control unit is The length of the period during which the resonance state is maintained in the pause period is determined to be a half-integer multiple of the length of the resonance period. The control device according to claim 6.

9. The control unit is determining, depending on the magnitude of the power of the power conversion request, a discrete value based on the length of the resonance period and a value of a phase difference between a period during which the semiconductor devices of the secondary bridge circuit are in a conductive state and a period during which the semiconductor devices of the secondary bridge circuit are in a conductive state; The control device according to claim 6.

10. The control unit is The first conduction period, the second conduction period, and the pause period are assigned in the order described above to control the primary bridge circuit. The control device according to claim 1 .

11. An insulated inductance section; a primary bridge circuit including four semiconductor devices and supplying power to the inductance unit; a secondary bridge circuit including four semiconductor devices and receiving power from the inductance unit; A method for controlling a main circuit, comprising: an intermittent operation is performed including a first conduction period during which a first set of semiconductor devices of the primary bridge circuit are made conductive, a second conduction period during which a second set of semiconductor devices of the primary bridge circuit are made conductive, and a pause period during which both the first set of semiconductor devices and the second set of semiconductor devices are made cut off for more than half of a resonance period caused by resonance between a parasitic capacitance of the primary bridge circuit and the inductance unit, thereby generating the resonance in the pause period; a step of setting the state of the secondary bridge circuit during the pause period to a state in which the valley of the voltage due to the resonance becomes zero voltage, and switching one set of semiconductor devices of the primary bridge circuit to a conductive state at a timing when the voltage applied to the semiconductor devices of the primary bridge circuit becomes the valley of the voltage change due to the resonance, thereby starting the injection of the power. A control method comprising:

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