Semiconductor device having superjunction structure and schottky barrier diode and manufacturing method thereof

Abstract

To provide a semiconductor device including a Schottky barrier diode having a superjunction structure capable of obtaining stable performance, and a method for manufacturing the same.SOLUTION: A semiconductor device includes a drain layer formed of a first conductivity type semiconductor, a drift layer formed of a first conductivity type semiconductor on one surface of the drain layer, a column structure in which a plurality of first conductivity type columns and a plurality of second conductivity type columns are alternately arranged in the drift layer, a Schottky barrier diode formed on an upper portion of the second conductivity type column, and a second conductivity type body layer formed on the Schottky barrier diode, and the second conductivity type column has a superjunction structure having a multi-stage sawtooth outer portion in a cross-sectional view.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device having a superjunction structure and a Schottky barrier diode, and a manufacturing method thereof. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device having a superjunction structure. In this semiconductor device, a groove is formed in a first conductivity type semiconductor by etching. A second conductivity type layer is formed in the groove by epitaxial growth. As a result, a superjunction structure is obtained. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2013-102087 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the semiconductor device described in Patent Document 1, when a second conductivity type layer is formed in the groove by epitaxial growth, the opening of the groove is likely to be blocked, which causes voids to remain inside the groove, making it impossible to obtain stable performance of the Schottky barrier diode having a superjunction structure.

[0005] The present disclosure has been made to solve the above-mentioned problems. An object of the present disclosure is to provide a semiconductor device including a Schottky barrier diode having a superjunction structure capable of obtaining stable performance, and a manufacturing method thereof. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure includes: A drain layer formed of a first conductivity type semiconductor; a drift layer formed of a first conductivity type semiconductor on one surface of the drain layer; a column structure in which a plurality of first conductivity type columns and a plurality of second conductivity type columns are alternately arranged in the drift layer; a Schottky barrier diode formed on an upper portion of the second conductivity type column; a second conductive type body layer formed on the Schottky barrier diode; Equipped with The semiconductor device has a superjunction structure in which the second conductive type column has an outer portion that is sawtooth-shaped with multiple steps in a cross-sectional view.

[0007] The second conductivity type column is a second conductivity type impurity layer; A filling layer formed inside the impurity layer; It is an aspect of the present disclosure that the present invention is provided with the above.

[0008] In one aspect of the present disclosure, the filling layer is made of an insulator or a semiconductor.

[0009] The impurity concentration of the impurity layer is 1.0×10 17 cm -3 Above 1.0×10 20 cm -3 The following is one aspect of the present disclosure.

[0010] the first conductivity type column is formed of first conductivity type silicon carbide; According to one aspect of the present invention, the impurity layer is made of second conductivity type silicon carbide.

[0011] A method for manufacturing a semiconductor device according to the present disclosure includes: a first drift layer formation step of forming a drift layer of the first conductivity type by epitaxial growth on a drain layer formed of a semiconductor of the first conductivity type; a second step of forming a channel region in the drift layer; a third step of forming a region in which a Schottky barrier diode is to be formed; A fourth step of forming a region in which a superjunction structure is to be formed; Including, the third step is a step of forming a recess, the step including a step of implanting ions using a mask having holes formed only inside a region in which the channel region is to be formed, and a step of etching a part of the region into which the ions have been implanted using the mask as is; The fourth step includes a step of implanting ions using the mask as is, and a step of etching a portion of the ion-implanted region, and the ion implanting step and the etching step are repeated at least two times to form a recess, thereby forming a semiconductor device.

[0012] In one aspect of the present disclosure, the step of implanting ions in the second step includes a step of oblique through ion implantation.

[0013] One embodiment of the present disclosure is that in the ion implantation process in the second, third or fourth process, the area of ​​the region in which the ion-implanted impurities exist is larger than the area of ​​the hole in the mask when viewed from above.

[0014] One embodiment of the present disclosure includes a step of filling the recesses formed by the fourth step with a semiconductor material or an insulating material, and a step of filling the recesses formed by the second step and the third step with a metal material. Effect of the Invention

[0015] According to the present disclosure, it is possible to obtain stable performance of a Schottky barrier diode having a superjunction structure. [Brief description of the drawings]

[0016] [Figure 1] 1 is a cross-sectional view of a semiconductor device in a first embodiment. [Diagram 2]1 is a cross-sectional view illustrating a manufacturing method of the semiconductor device in the first embodiment. [Diagram 3] 1 is a cross-sectional view illustrating a manufacturing method of the semiconductor device in the first embodiment. [Figure 4] 1 is a cross-sectional view illustrating a manufacturing method of the semiconductor device in the first embodiment. [Diagram 5] 5A to 5C are views for explaining a method of forming an impurity layer of a second conductivity type of the semiconductor device in the first embodiment. [Figure 6] FIG. 11 is a cross-sectional view of a semiconductor device in a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] The embodiments will be described with reference to the accompanying drawings. In each drawing, the same or corresponding parts are denoted by the same reference numerals. Duplicate descriptions of the parts will be appropriately simplified or omitted.

[0018] Embodiment 1 FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment.

[0019] 1, the semiconductor device 1 is a silicon carbide planar type MOSFET including a Schottky barrier diode having a superjunction structure. The semiconductor device 1 includes a drain layer 2, a drift layer 3, a plurality of body layers 4, a plurality of source layers 5, a plurality of body contact layers 6, a plurality of gate insulating layers 7, a plurality of gate electrode layers 8, a plurality of interlayer insulating layers 9, a plurality of source electrode layers 10, a wiring electrode layer 11, a drain electrode layer 12, a plurality of impurity layers 13, a plurality of filling layers 14, a Schottky barrier diode 18, and a Schottky electrode 19.

[0020] The drain layer 2 is made of silicon carbide of a first conductivity type. For example, the drain layer 2 is made of n +For example, the drain layer 2 is formed with nitrogen as an impurity. The drift layer 3 is formed on a first surface (upper surface in FIG. 1 ) of the drain layer 2. The drift layer 3 is formed of silicon carbide of a first conductivity type having a lower impurity concentration than the drain layer 2. For example, the drift layer 3 is formed of n - For example, the drift layer 3 is formed on the drain layer 2 by epitaxial growth.

[0021] The body layers 4 are formed on the drift layer 3. The body layers 4 are made of silicon carbide of a second conductivity type. For example, the body layers 4 are made of p - For example, the body layers 4 are formed by ion implantation using aluminum as an impurity.

[0022] The source layers 5 are formed on the body layers 4, respectively. The source layers 5 are made of silicon carbide of the first conductivity type having a higher impurity concentration than the drift layer 3. For example, the source layers 5 are made of n + For example, the source layers 5 are formed by ion implantation using nitrogen as an impurity.

[0023] The body contact layers 6 are formed on each of the body layers 4. In each of the body layers 4, the body contact layer 6 is surrounded by a source layer 5. The body contact layers 6 are formed of silicon carbide of the second conductivity type having a higher impurity concentration than the body layers 4. For example, the body contact layers 6 are formed of p + For example, the body contact layers 6 are formed by ion implantation using aluminum as an impurity.

[0024] The multiple gate insulating layers 7 are formed so as to be in contact with the respective source layers 5 of the adjacent body layers 4. Specifically, the multiple gate insulating layers 7 are formed so as to span the body layer 4 adjacent to the drift layer 3 and the respective source layers 5 present inside the body layer 4. For example, the multiple gate insulating layers 7 are formed by thermal oxidation.

[0025] The gate electrode layers 8 are respectively formed on the gate insulating layers 7. For example, the gate electrode layers 8 are formed of polysilicon by a CVD method.

[0026] The plurality of interlayer insulating layers 9 are formed so as to cover the respective gate electrode layers 8. For example, the plurality of interlayer insulating layers 9 are formed by a CVD method.

[0027] The multiple source electrode layers 10 are formed corresponding to the multiple body layers 4, respectively. The source electrode layers 10 are formed so as to be in contact with the source layers 5. The source electrode layers 10 may be formed so as to span the body contact layers 6. For example, the multiple source electrode layers 10 are formed by depositing Ni, Ti, or the like by a sputtering method and subjecting the film to a heat treatment.

[0028] The wiring electrode layer 11 is formed so as to cover the multiple source electrode layers 10. For example, the wiring electrode layer 11 is formed of an aluminum alloy or the like by a sputtering method.

[0029] The drain electrode layer 12 is formed on the second surface (the lower surface in FIG. 1) of the drain layer 2. For example, the drain electrode layer 12 is formed by depositing Ni or the like by sputtering and subjecting it to heat treatment.

[0030] The Schottky electrode 19 is formed in a recess formed to penetrate the body contact layer 6 and the source electrode layer 10 and reach the drift layer 3. A Schottky barrier diode 18 is formed on the surface where the Schottky electrode 19 and the drift layer 3 are in contact. For example, the Schottky barrier diode 18 and the Schottky electrode 19 are formed of an aluminum alloy or the like by a sputtering method.

[0031] In this embodiment, a column structure C is formed in the drift layer 3. In the column structure C, a plurality of first conductivity type columns C1 and a plurality of second conductivity type columns C2 are alternately arranged. This forms a superjunction structure. The plurality of first conductivity type columns C1 are part of a layer formed as the drift layer 3. The plurality of second conductivity type columns C2 are formed separately from the layer formed as the drift layer 3.

[0032] Each of the plurality of second-conductivity type columns C2 is formed below the Schottky barrier diode 18. In each of the plurality of second-conductivity type columns C2, the upper portion is surrounded by the body layer 4, the source layer 5, and the body contact layer 6. Each of the plurality of second-conductivity type columns C2 has a multi-stage sawtooth-shaped outer portion in a cross-sectional view. Specifically, in each of the plurality of second-conductivity type columns C2, a plurality of first inclined portions A1 and a plurality of second inclined portions A2 are alternately arranged in the thickness direction of the drift layer 3. The first inclined portion A1 is formed so as to widen in the lateral direction from one surface (upper surface in FIG. 1) of the drain layer 2 to the other surface (lower surface in FIG. 1). The second inclined portion A2 is formed so as to narrow in the lateral direction from one surface of the drain layer 2 to the other surface. In this case, the second inclined portion A2 is formed so as to narrow more rapidly than the first inclined portion A1 widens.

[0033] More specifically, each of the multiple columns C2 of the second conductivity type includes an impurity layer 13 and a filling layer 14. The impurity layer 13 forms an outer portion of the column C2 of the second conductivity type. The impurity layer 13 is made of silicon carbide of the second conductivity type. The impurity layer 13 is a p-type layer. For example, the impurity layer 13 is formed by ion implantation using aluminum as an impurity. The impurity concentration of the impurity layer 13 is 1.0×10 17 cm -3 Above 1.0×10 20 cm -3 The filling layer 14 is formed inside the impurity layer 13. The filling layer 14 is made of an insulator or a semiconductor. For example, the filling layer 14 is made of silicon dioxide.

[0034] Thus, in this embodiment, a vertical groove structure is formed in the drift layer 3 by alternating a plurality of first conductivity type columns C1 and a plurality of second conductivity type columns C2. In this case, when a voltage is applied, the depletion layer spreads laterally. As a result, a depletion layer is formed to the depth of the groove. At this time, the depletion layer spreads only half the distance between the grooves, and a depletion layer with a thickness equal to the depth of the groove is formed. In this way, the spread of the depletion layer can be small, and the impurity concentration of the drift layer 3 can be increased to about five times that of a non-superjunction structure. This reduces the ON resistance.

[0035] In this principle, it is preferable to make the grooves and the intervals between the grooves as narrow and deep as possible. In this principle, the breakdown voltage is ensured by a mechanism different from that of conventional MOSFETs. This allows performance to be achieved that exceeds the so-called silicon limit and silicon carbide limit.

[0036] Next, a method for manufacturing the semiconductor device 1 will be described.

[0037] First, three types of ion implantation steps are performed on the drift layer 3 epitaxially formed on the drain layer. In each of the three types of ion implantation, a resist pattern is first formed. Then, the ion implantation is performed. Then, the resist pattern is removed. As a result, p - Ion implantation part of the n + Type ion implantation area and p + The ion implantation part of the mold is formed. - The ion-implanted portion of the mold becomes the body layer 4. + The ion-implanted portion of the p-type layer becomes the source layer 5. + The ion-implanted portion of the mold becomes the body contact layer 6.

[0038] Next, a method for manufacturing the Schottky barrier diode 18 having a superjunction structure included in the semiconductor device 1 will be described with reference to Figures 2 to 4. Figures 2 to 4 are cross-sectional views for explaining the method for manufacturing the semiconductor device 1 in the first embodiment. Note that the body layer 4, source layer 5, body contact layer 6, etc. are omitted in Figures 2 to 4.

[0039] As shown in FIG. 2(a), a mask pattern forming process is performed. In the mask pattern forming process, a silicon dioxide layer 15 is first formed on the entire surface. Next, a resist pattern is formed, and then dry etching is performed. After that, the resist pattern is removed. As a result, a mask pattern of the silicon dioxide layer 15 is formed.

[0040] 2(b), a shallow and wide second conductivity type impurity layer 13 is formed by oblique through ion implantation DI. In the ion implantation step, impurities such as aluminum are ion-implanted into the silicon dioxide layer 15 at positions corresponding to the openings. At this time, the ion implantation is performed so that a part of the region where the impurities exist extends outward beyond the openings of the mask pattern when viewed from above.

[0041] 2(c), a second conductive type impurity layer 13 narrower than that of the oblique through ion implantation DI is formed by the vertical ion implantation VI. At this time, the vertical ion implantation VI is also performed so that a part of the region where the impurity exists extends outside the opening of the mask pattern when viewed from above. Note that the vertical ion implantation VI here also includes ion implantation performed at an angle of 8 degrees or less from the vertical to prevent channeling.

[0042] 2(d), a part of the impurity layer 13 is etched without removing the mask pattern of the silicon dioxide layer 15. In the etching process, a part of the impurity layer 13 is etched at a position corresponding to the opening of the silicon dioxide layer 15. At this time, the silicon dioxide layer 15 is also reduced in thickness.

[0043] 2(e), a second conductivity type impurity layer 13 is formed by vertical ion implantation VI. At this time, in the ion implantation step, impurities such as aluminum are further ion-implanted at positions corresponding to the openings of the silicon dioxide layer 15. At this time, the ion implantation is performed so that a part of the region where the impurity is present extends outward beyond the openings of the mask pattern in top view. As a result, the impurity layer 13 is further formed.

[0044] Next, as shown in Fig. 3(f), a part of the impurity layer 13 is etched without removing the mask pattern of the silicon dioxide layer 15. In the etching process, a part of the impurity layer 13 is etched at a position corresponding to the opening of the silicon dioxide layer 15. At this time, the silicon dioxide layer 15 is also reduced. Both the processes of Fig. 2(e) and Fig. 3(f) may be repeated.

[0045] 3(g), a part of the impurity layer 13 and a part of the drift layer 3 are etched without removing the mask pattern of the silicon dioxide layer 15. In this etching process, a recess is formed as a region where the Schottky barrier diode 18 is to be formed. At this time, the silicon dioxide layer 15 is also reduced in thickness.

[0046] Next, as shown in Fig. 3(h), a second conductivity type impurity layer 13 is formed by vertical ion implantation VI. At this time, in the ion implantation step, impurities such as aluminum are further ion-implanted at positions corresponding to the openings of the silicon dioxide layer 15. At this time, the ion implantation is performed so that a part of the region where the impurity is present extends outward beyond the openings of the mask pattern in top view. As a result, the impurity layer 13 is further formed.

[0047] 3(i), a part of the impurity layer 13 is etched without removing the mask pattern of the silicon dioxide layer 15. In the etching process, a part of the impurity layer 13 is etched at a position corresponding to the opening of the silicon dioxide layer 15. At this time, the silicon dioxide layer 15 is also reduced in thickness.

[0048] 3(j), a second conductivity type impurity layer 13 is formed by vertical ion implantation VI. At this time, in the ion implantation step, impurities such as aluminum are further ion-implanted at positions corresponding to the openings of the silicon dioxide layer 15. At this time, the ion implantation is performed so that a part of the region where the impurity is present extends outward beyond the openings of the mask pattern in top view. As a result, the impurity layer 13 is further formed.

[0049] 4(k), a part of the impurity layer 13 is etched without removing the mask pattern of the silicon dioxide layer 15. In the etching process, a part of the impurity layer 13 is etched at a position corresponding to the opening of the silicon dioxide layer 15. At this time, the silicon dioxide layer 15 is also reduced in thickness.

[0050] Next, as shown in FIG. 4(l), the process described in FIG. 3(j) and the process described in FIG. 4(k) are repeated. Through these processes, the impurity layer 13 constituting the superjunction structure is formed. This repeating process can be repeated a necessary number of times to obtain a column length required to obtain the desired characteristics of the superjunction structure. In other words, as the second conductivity type column forming process, an ion implantation process and an etching process are alternately performed multiple times. As a result, a multi-stage sawtooth-shaped impurity layer 13 is formed.

[0051] Next, as shown in Fig. 4(m), a mask pattern removing step is performed in which the silicon dioxide layer 15 is removed.

[0052] TIFF2025018394000002.tif43 Next, a heat treatment process is performed to activate the impurity layer 13 formed by the ion implantation process up to FIG. 4(m). The activation of the impurity layer 13 is performed, for example, by heat treatment at 1400 degrees Celsius to 1600 degrees Celsius. Alternatively, for example, a protective film such as a carbon coating may be used.

[0053] Thereafter, a gate insulating layer forming process is performed. In the gate insulating layer forming process, after necessary pre-treatment, the surface of the silicon carbide is thermally oxidized to convert it into a silicon dioxide film, and further necessary post-treatment is performed. The gate insulating layer forming process is performed, for example, in an environment of 1000 degrees Celsius to 1200 degrees Celsius. Then, a resist pattern is formed. Then, the gate insulating film is etched. Then, the resist pattern is removed. As a result, the gate insulating layer 7 is formed.

[0054] Next, as shown in Fig. 4(n), a filling step is performed in which a silicon dioxide layer 14 is formed. The silicon dioxide layer 14 also fills the grooves formed by the etching step.

[0055] Next, as shown in Fig. 4(o), an etch-back process is performed in which the silicon dioxide layer 14 on the region where the Schottky barrier diode 18 is to be formed is removed, resulting in the formation of the fill layer 14.

[0056] 4(p), a metal filling step is performed. In this step, for example, aluminum can be filled. As a result, a Schottky barrier diode 18 and a Schottky electrode 19 are formed.

[0057] Thereafter, a gate electrode layer forming step is performed. In the gate electrode layer forming step, a polysilicon film is formed. Then, a resist pattern is formed. Then, the polysilicon film is etched. Then, the resist pattern is removed. As a result, the gate electrode layer 8 is formed. Then, a source electrode layer forming step is performed. In the source electrode layer forming step, a metal film is formed. Then, a resist pattern is formed. Then, the metal film is etched. Then, the resist pattern is removed. Then, metal sintering is performed. As a result, the source electrode layer 10 is formed. Note that after the source electrode layer 10 is formed, the above-mentioned Schottky electrode 19 may be formed.

[0058] Then, an interlayer insulating layer forming process is performed. In the interlayer insulating layer forming process, an interlayer insulating layer 9 is formed. Then, a wiring electrode layer forming process is performed. In the wiring electrode layer forming process, a wiring electrode layer 11 is formed. Then, a drain electrode layer forming process is performed. In the drain electrode layer forming process, a metal film is formed. Then, laser annealing is performed. As a result, a drain electrode layer 12 is formed.

[0059] Next, a method for forming the second conductivity type impurity layer 13 will be described with reference to FIG. FIG. 5 is a diagram for illustrating a method of forming an impurity layer of a second conductivity type in the semiconductor device according to the first embodiment.

[0060] 5 shows a profile when aluminum is used as an impurity and ion-implanted into the drift layer 3 of silicon carbide. As shown in FIG. 5, in each ion-implantation step, the impurity spreads radially. The depth of the ion implantation at this time is, for example, about 0.7 μm. The lateral spread of the ion implantation is, for example, about 0.2 μm. Although not shown in FIG. 5, such ion implantation is repeated with changing depths, so that in each of the multiple second conductivity type columns C2, the outer portion is formed such that multiple first inclined portions A1 and multiple second inclined portions A2 are alternately arranged in the thickness direction of the drift layer 3.

[0061] According to the first embodiment described above, the plurality of second conductivity type columns C2 have a multi-stage sawtooth-shaped outer portion in a cross-sectional view. Specifically, the second conductivity type columns C2 are formed of the impurity layer 13 and the filling layer 14. For this reason, no voids are generated. As a result, it is possible to provide a semiconductor device 1 including a Schottky barrier diode having a superjunction structure capable of obtaining stable performance. In addition, it is possible to easily manufacture a semiconductor device 1 including a Schottky barrier diode having a superjunction structure capable of obtaining stable performance.

[0062] In a cross-sectional view of the multiple columns C2 of the second conductivity type, the impurity layer 13 above the body layer 4 may be omitted. In this case, the semiconductor device 1 with stable performance can be manufactured at lower cost.

[0063] Furthermore, the filling layer 14 is made of an insulator or a semiconductor, which makes it easier to manufacture the semiconductor device 1 with stable performance.

[0064] The impurity concentration of the impurity layer 13 is 1.0×10 17 cm -3 Above 1.0×10 20 cm -3 As a result, stable performance can be obtained more reliably.

[0065] The first conductivity type column C1 is made of silicon carbide of the first conductivity type. The impurity layer 13 is made of silicon carbide of the second conductivity type. This makes it possible to obtain stable performance in the silicon carbide semiconductor device 1.

[0066] Furthermore, in the drift layer 3, a plurality of second conductivity type columns C2 are formed so as to form an outer portion of a multi-stage sawtooth shape in cross section. This makes it possible to easily manufacture the semiconductor device 1 including a Schottky barrier diode having a superjunction structure capable of obtaining stable performance.

[0067] In addition, by repeating the ion implantation process and the etching process, a plurality of columns C2 of the second conductivity type are formed so that the outer portion has a multi-stage sawtooth shape in cross section. At this time, in the ion implantation process, the impurities are implanted at positions corresponding to the openings of the mask pattern. In the etching process, the mask pattern is used as is. Therefore, photolithography is not required for each stage, and mask alignment is also not required. Furthermore, since a heat-resistant silicon dioxide layer mask is used, high-temperature ion implantation at about 500 degrees Celsius can be performed without the problem of ion implantation in deep regions with a high aspect ratio. Therefore, the process is greatly simplified. As a result, it is possible to easily manufacture the semiconductor device 1 including the Schottky barrier diode having a superjunction structure that can obtain stable performance.

[0068] For example, in silicon carbide etching by ICP-RIE in an SF6-02-Ar atmosphere, the selectivity can be 8. In this case, even if the silicon dioxide layer 15 is reduced in thickness during the etching process, the ion implantation process and the etching process can be repeated multiple times without changing the mask pattern. For example, when the silicon dioxide layer 15 has a thickness of 3 μm, if the silicon dioxide layer functioning as a mask for ion implantation has a thickness of 1 μm, a reduction of up to 2 μm is permitted, and the silicon carbide layer can be etched to a thickness of 16 μm. This means that etching can be performed deeper than the thickness (approximately 10 μm) of the drift layer 3 of a silicon carbide semiconductor device having a breakdown voltage of about 1000 V without a superjunction structure. In addition, when the superjunction structure is present, the drift layer 3 can be made thinner than when the superjunction structure is not present. Therefore, the silicon dioxide layer 15 can be made thinner than 3 μm, and a semiconductor device 1 with stable performance can be manufactured more easily.

[0069] In addition, in the ion implantation process, the ions are implanted so that a part of the region where the impurities are present extends outside the opening of the mask pattern when viewed from above. This makes it possible to easily manufacture the semiconductor device 1 with stable performance.

[0070] In addition, after the ion implantation process and the etching process are repeated, the grooves formed by the etching process are filled with an insulator or a semiconductor. Therefore, no voids are generated. As a result, the semiconductor device 1 with stable performance can be easily manufactured.

[0071] Embodiment 2 6 is a cross-sectional view of a semiconductor device in accordance with embodiment 2. Note that the same or corresponding parts as those in embodiment 1 are denoted by the same reference numerals, and a description of these parts will be omitted.

[0072] 6, the semiconductor device 1 is a trench MOSFET. A plurality of impurity layers 13 and a plurality of filling layers 14 are also added to the semiconductor device 1.

[0073] According to the above-described second embodiment, the plurality of second conductivity type columns C2 have a multi-stage sawtooth outer portion in a cross-sectional view in the trench type semiconductor device 1. Therefore, even in the trench type semiconductor device 1, it is possible to obtain a semiconductor device 1 including a Schottky barrier diode having a superjunction structure that can obtain stable performance.

[0074] In the first or second embodiment, the first conductivity type may be p-type and the second conductivity type may be n-type, with stable performance being obtained in this case as well.

[0075] Moreover, the first or second embodiment may be applied to a semiconductor device 1 whose main component is silicon. In this case as well, stable performance can be obtained.

[0076] Having described several aspects of at least one embodiment, it should be understood that various alterations, modifications, and improvements will readily occur to those skilled in the art and are intended to be part of this disclosure, and are intended to be within the scope of this disclosure.

[0077] It is to be understood that the embodiments of the method and apparatus described herein are not limited in their application to the details of construction and the arrangement of components set forth in the above description or illustrated in the accompanying drawings, and the method and apparatus can be implemented in other embodiments and practiced or carried out in various ways.

[0078] The specific implementations are provided herein for illustrative purposes only and are not intended to be limiting.

[0079] The phraseology and terminology used in this disclosure are for the purpose of description and should not be regarded as limiting. The use of "including," "comprising," "having," "including" and variations thereof herein means the inclusion of the items listed thereafter and equivalents thereof as well as additional items.

[0080] References to "or" may be construed as meaning that any term described using "or" refers to one, more than one, and all of those described terms.

[0081] All references to front, back, left, right, top, bottom, up, down, horizontal, vertical, front and back are intended for convenience of description. Such references are not intended to limit the components of this disclosure to any one positional or spatial orientation. Accordingly, the foregoing description and drawings are by way of example only. [Explanation of symbols]

[0082] 1 semiconductor device, 2 drain layer, 3 drift layer, 4 body layer 5 source layer, 6 body contact layer, 7 gate insulating layer 8 gate electrode layer, 9 interlayer insulating layer, 10 source electrode layer 11 wiring electrode layer, 12 drain electrode layer, 13 impurity layer 14 filling layer (silicon dioxide layer), 15 silicon dioxide layer

Claims

1. A drain layer formed of a first conductivity type semiconductor; a drift layer formed on one surface of the drain layer and made of a semiconductor of a first conductivity type; a column structure in which a plurality of first conductivity type columns and a plurality of second conductivity type columns are alternately arranged in the drift layer; a Schottky barrier diode formed on an upper portion of the second conductivity type column; a second conductive type body layer formed on the Schottky barrier diode; Equipped with The semiconductor device has a superjunction structure in which the second conductivity type column has an outer portion that is sawtooth-shaped with multiple steps in a cross-sectional view.

2. The second conductivity type column is an impurity layer of a second conductivity type; A filling layer formed inside the impurity layer; The semiconductor device according to claim 1 ,

3. The semiconductor device according to claim 2 , wherein the filling layer is made of an insulator or a semiconductor.

4. 4. The semiconductor device according to claim 2, wherein the impurity concentration of the impurity layer is not less than 1.0×10 17 cm −3 and not more than 1.0×10 20 cm −3 .

5. the first conductivity type column is formed of first conductivity type silicon carbide; 4. The semiconductor device according to claim 2, wherein the impurity layer is made of silicon carbide of the second conductivity type.

6. a first drift layer formation step of forming a drift layer of the first conductivity type by epitaxial growth on a drain layer formed of a semiconductor of the first conductivity type; a second step of forming a channel region in the drift layer; a third step of forming a region in which a Schottky barrier diode is to be formed; A fourth step of forming a region in which a superjunction structure is to be formed; Including, the third step is a step of forming a recess, the step including a step of implanting ions using a mask having holes formed only inside a region in which the channel region is to be formed, and a step of etching a part of the region into which the ions have been implanted using the mask as is; The fourth step includes a step of implanting ions using the mask as is and a step of etching a portion of the ion-implanted region, and the ion implanting step and the etching step are repeated at least two times to form a recess.

7. 11. The method for manufacturing a semiconductor device according to claim 10, wherein the step of implanting ions in the second step includes a step of oblique through-ion implantation.

8. 11. The method for manufacturing a semiconductor device according to claim 10, wherein in the ion implantation step in the second step, the third step or the fourth step, an area of ​​a region in which the ion-implanted impurities exist is larger than an area of ​​the hole in the mask when viewed from above.

9. 11. The method for manufacturing a semiconductor device according to claim 10, further comprising the steps of filling the recesses formed by the fourth step with a semiconductor material or an insulating material, and filling the recesses formed by the second step and the third step with a metal material.

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