HIGH RESISTIVITY POLYCRYSTALLINE SILICON CARBIDE (SiC) SUBSTRATE AND MANUFACTURING METHOD OF THE SAME

Abstract

To provide a high resistivity polycrystalline substrate, and a method for manufacturing the high resistivity polycrystalline substrate.SOLUTION: A method contains steps of: forming a polycrystalline substrate having a high resistibility (e.g., 1×10^5 or 1E+5 ohmic centimeter or more); forming a single crystal substrate by fusing a semiconductor grade silicon with a high grade, and thereafter, using a seed crystal, and starting a formation of the single crystal; bonding a second surface of the polycrystalline substrate when the polycrystalline substrate and the single crystal substrate are formed to a third surface of the single crystal substrate by using a surface active bonding (SAB) technique; and removing one part of the single crystal substrate.SELECTED DRAWING: Figure 4A

Description

[Technical field]

[0001] The present disclosure is directed to high resistivity polycrystalline substrates and methods of making high resistivity polycrystalline substrates. [Background technology]

[0002] The semiconductor industry has shown great interest in silicon carbide (SiC), particularly for the manufacture of devices or components such as radar, diodes, transistors, or other similar or similar applications.

[0003] The development and manufacture of silicon carbide-based electronic devices is limited by factors such as the electrical and mechanical properties of the silicon carbide wafers that are formed. Many of the silicon carbide wafers manufactured have low resistivity, which is beneficial for the final product. Another issue is the amount of warpage that results from the manufacture of the wafers. Lower resistivity allows electrical signals to pass through the silicon carbide wafer more easily, but in return limits the use of silicon carbide wafers in high power applications (e.g., radar) where high resistivity is desired. Increased amounts of warpage also result in defects from polishing processes, etc., in the manufacture of the final electronic device, or lead to an increased number of cracked or broken wafers or substrates during processing and manufacture.

[0004] Such polycrystalline SiC wafers can be manufactured by a method of bonding a single crystal (i.e., monocrystalline) wafer onto a polycrystalline SiC wafer. For example, there is a wafer manufacturing method in which a polycrystalline SiC wafer and a single crystal (i.e., monocrystalline) SiC wafer are bonded and integrated by direct bonding. In power devices, such crystal defects, low resistivity, and high warpage can be problematic in high power applications because these factors limit the functionality of the power devices such that they function outside of selected tolerances. In such situations, these devices may be discarded (e.g., scrapped), which increases manufacturing costs due to reduced yields. Summary of the Invention

[0005] A polycrystalline SiC wafer or substrate with high resistivity is beneficial to the function of the high power electronic device or system in which the polycrystalline SiC wafer or substrate exists or is utilized in the manufacture of the high power electronic device or system. The present disclosure is directed to providing at least one embodiment of a wafer including a polycrystalline SiC wafer or substrate with high resistivity (e.g., 1×10^5 or 1E+5 ohm-cm or greater) and low warpage. Electronic devices or components manufactured using or from a wafer including a high resistivity polycrystalline SiC wafer or substrate are further optimized in use and have low or no crystal defects. Wafers formed according to embodiments of the present disclosure have high or very high resistivity compared to existing polycrystalline SiC wafers or substrates.

[0006] At least one embodiment of the present disclosure is summarized as comprising a polycrystalline silicon carbide (SiC) base substrate including a first surface, a second surface opposite the first surface, a resistivity of 1×10^5 or 1E+5 ohm-centimeters or greater, and a grain size of 0.5 millimeters (mm) or greater.

[0007] In some embodiments, a single crystal silicon carbide (SiC) substrate is bonded to a first surface of a polycrystalline silicon carbide (SiC) base substrate. The single crystal silicon carbide (SiC) may have a resistivity similar to or equal to the resistivity of the polycrystalline silicon carbide substrate. [Brief description of the drawings]

[0008] For a better understanding of the embodiments, reference will now be made, by way of example, to the accompanying drawings, in which identical reference numbers identify the same or similar elements or acts, unless the context dictates otherwise. Sizes and relative proportions of elements in the drawings are not necessarily drawn to scale. For example, some of these elements may be enlarged and positioned to improve the legibility of the drawings. [Figure 1] 1 is a perspective side view of an embodiment of a wafer of the present disclosure; [Diagram 2] 1 is a perspective view of an alternative embodiment of a wafer of the present disclosure; [Figure 3A] 1 is directed to a plan view of another alternative embodiment of a wafer of the present disclosure. [Figure 3B] 3B is directed to a perspective side view of another alternative embodiment of the wafer shown in FIG. 3A of the present disclosure. [Figure 3C] 3C of another embodiment of a wafer of the present disclosure. [Figure 4A] 3 is a flow chart of a method for manufacturing the embodiment of the wafer of the present disclosure shown in FIGS. 1 and 2. [Figure 4B] 4 is a flow chart of a method for manufacturing another embodiment of the wafer shown in FIGS. 3A-3C of the present disclosure. [Figure 4C] 4 is a flow chart of an alternative method for manufacturing another embodiment of the wafer shown in FIGS. 3A-3C of the present disclosure. [Figure 5A] 4B is a side view of at least some steps of the embodiment of the manufacturing method shown in FIG. 4A for producing the embodiment of the wafer shown in FIGS. 1 and 2 of the present disclosure. [Figure 5B] 4B is a side view of at least some steps of the embodiment of the manufacturing method shown in FIG. 4A for producing the embodiment of the wafer shown in FIGS. 1 and 2 of the present disclosure. [Figure 5C] 4B is a side view of at least some steps of the embodiment of the manufacturing method shown in FIG. 4A for producing the embodiment of the wafer shown in FIGS. 1 and 2 of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] In the following description, specific details are set forth to provide a thorough understanding of various embodiments of devices, methods, and articles. However, one of ordinary skill in the art will understand that other embodiments may be practiced without these details. In other instances, well-known structures and methods related to, for example, silicon carbide substrates or layers (e.g., polycrystalline silicon carbide, single crystal silicon carbide, etc.), semiconductor manufacturing processes, etc., have not been shown or described in detail in some figures to avoid unnecessarily obscuring the description of the embodiments.

[0010] Unless the context otherwise requires, throughout the following specification and claims, the word "comprise" and variations thereof, such as "comprising" and "comprises," are to be interpreted in their open and inclusive sense, i.e., "including, but not limited to."

[0011] References throughout this specification to "one embodiment" or "one embodiment" mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in one embodiment" in various places throughout this specification do not necessarily refer to the same embodiment or all embodiments. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments to yield further embodiments.

[0012] Headings are provided for convenience only and do not interpret the scope or meaning of the disclosure or claims.

[0013] The sizes and relative positions of elements in the figures are not necessarily drawn to scale, for example, the shapes and angles of various elements may not be drawn to scale, and some of these elements may be enlarged and positioned to improve the legibility of the figures.

[0014] The use of "lateral" means that a surface, sidewall, or similar or analogous structure or feature is at an angle relative to another respective surface, sidewall, or similar or analogous respective structure or feature. For example, if a first surface is transverse to a first sidewall, the first surface can be at an angle equal to 25 degrees, 35 degrees, 45 degrees, 75 degrees, 90 degrees, 120 degrees, etc.

[0015] Generally, polycrystalline silicon carbide (SiC) substrates, wafers, or layers have been utilized within various electronic devices and components (e.g., semiconductor dies, semiconductor packages, semiconductor transistors, etc.). Such polycrystalline SiC substrates, wafers, or layers have a resistivity that results in a resistance being present along an electrical path passing through or along the polycrystalline SiC substrate, wafer, or layer. This resistance opposes an electrical signal as it passes through or along the electrical path, and is referred to as the on-resistance (R on ) is generally known as the on-resistance (R on ) is high when used in high power and high frequency applications (e.g., radar or other similar or similar types of radio frequency applications or devices at relatively high gigahertz (GHz) frequencies compared to other situations). For example, the on-resistance (R on ), a highly resistive and stable polycrystalline SiC substrate provides good electrical performance and reduces insertion loss such that the polycrystalline SiC substrate is optimized for use in high power and high frequency applications. While the industry has produced high resistivity single crystal SiC substrates for such high frequency and high power applications, the production of single crystal SiC substrates is significantly more expensive and costly than the production of polycrystalline SiC substrates. In light of this, the present disclosure is directed to one or more embodiments of a high resistivity polycrystalline SiC substrate optimized for use in high power and high frequency applications, as well as a method for producing a high resistivity polycrystalline SiC substrate.

[0016] A polycrystalline SiC substrate or wafer with high resistivity in a high power and high frequency electronic device in which the polycrystalline SiC substrate or wafer is present. The present disclosure is directed to providing at least one embodiment of a wafer or substrate including a polycrystalline SiC substrate or wafer with high resistivity and low warpage. An electronic device or component manufactured from or including a polycrystalline SiC substrate or wafer with high resistivity and low warpage functions stably even at high power and high frequency. Such embodiments of the polycrystalline SiC substrate or wafer of the present disclosure have fewer crystal defects, so that the polycrystalline SiC substrate or wafer of the present disclosure is further optimized. The polycrystalline SiC substrate or wafer has high or very high resistivity compared to existing polycrystalline SiC substrates or wafers that are generally manufactured to have resistivities much lower than 1×10^5 or 1E+5 ohm-centimeters. Additionally, the low amount of warpage in the polycrystalline SiC substrate or wafer embodiments of the present disclosure prevents or reduces the likelihood of defects occurring from processes such as polishing during the manufacture of final electronic devices, or reduces the number of polycrystalline SiC wafers or substrates that crack or break during processing and manufacturing.

[0017] 1 is a side view of one embodiment of a wafer 100 of the present disclosure. The wafer 100 includes a first side 102 and a second side 104 opposite the first side 102. The wafer 100 further includes a polycrystalline silicon carbide (SiC) layer 106, a bond region 108, and a single crystal silicon carbide (SiC) layer 110 bonded to the polycrystalline silicon carbide layer 106 at the bond region 108. The polycrystalline silicon carbide layer 106 may be referred to as a polycrystalline silicon carbide substrate, a polycrystalline silicon carbide wafer, a polycrystalline silicon carbide layer, or in some other suitable manner. The single crystal silicon carbide (SiC) layer 110 may be referred to as a single crystal silicon carbide substrate, a single crystal silicon carbide wafer, a single crystal silicon carbide layer, or in some other suitable manner. The polycrystalline silicon carbide (SiC) layer 106 may be referred to hereinafter in this disclosure as polycrystalline layer 106, and the single crystal silicon carbide (SiC) layer 110 may be referred to hereinafter in this disclosure as single crystal layer 110.

[0018] The polycrystalline layer 106 has a high resistivity, e.g., a resistivity of 1×10^5, or 1E+5 ohm-centimeters or greater. This high resistivity of the polycrystalline layer 106 allows high power and high frequency (e.g., gigahertz (GHz) level frequencies) electrical signals (e.g., electrons) to stably pass through the polycrystalline layer 106 such that the electrical signals can stably travel through the polycrystalline layer 106 and reach their targets with more accurate and consistent strength and precision compared to when the polycrystalline layer 106 has a lower resistivity instead. That is, the on-resistance (R on ) is high (i.e., high resistivity), a high power, high frequency electrical signal passes more easily and reliably through the polycrystalline layer 106 without the imprecision that occurs when the high power, high frequency electrical signal passes through the polycrystalline layer 106 as it travels to its target within the high power, high frequency electronic device (e.g., a radar, a semiconductor package, a semiconductor die, or any other similar or analogous high power, high frequency electronic device in which the polycrystalline layer 106 may be present).

[0019] The polycrystalline layer 106 includes a first surface 112 and a second surface 114 opposite the first surface 112. The first surface 112 of the polycrystalline layer 106 is on the second side 104 of the wafer 100. The monocrystalline layer 110 includes a third surface 116 and a fourth surface 118 opposite the third surface 116. The fourth surface 118 of the monocrystalline layer 110 is on the first side 102 of the wafer 100.

[0020] The polycrystalline layer 106 has a first thickness T1, which may be referred to as a first dimension. The first thickness T1 extends from a first surface 112 of the polycrystalline layer 106 to a second surface 114 of the polycrystalline layer 106. In some embodiments, the first thickness T1 may be in a range of 150 to 1000 micrometers (μm), or may be equal to the upper and lower ends of this range (e.g., the first thickness T1 may be equal to 150 micrometers (μm) or may be equal to 1000 micrometers (μm)). In some embodiments, the first thickness T1 may be equal to 1 millimeter (mm) or less.

[0021] The monocrystalline layer 110 has a second thickness T2, which may be referred to as a second dimension. The second thickness T2 extends from the third surface 116 of the monocrystalline layer 110 to the fourth surface 118 of the monocrystalline layer 110. The second thickness T2 of the monocrystalline layer 110 may be less than the first thickness T1 of the polycrystalline layer 106. The second thickness T2 of the monocrystalline layer 110 may be in the range of 0.3 to 2 micrometers (μm) or equal to the upper and lower ends of this range (e.g., the second thickness T2 may be equal to 0.3 micrometers (μm) or equal to 2 micrometers (μm)). In some embodiments, the second thickness may be in the range of 0.3 to 1 micrometers (μm) or equal to the upper and lower ends of this range (e.g., the second thickness T2 may be equal to 0.3 micrometers (μm) or equal to 1 micrometer (μm)). In some embodiments, the second thickness T2 of the single crystal layer 110 can be equal to 0.5 micrometers (μm). In some embodiments, the second thickness T2 can be equal to or less than 20-200 micrometers (μm), or equal to the upper and lower ends of this range (e.g., the second thickness T2 can be equal to 20 micrometers (μm) or equal to 200 micrometers (μm)). In some embodiments, the second thickness T2 can be equal to 120 micrometers (μm).

[0022] Single crystal layer 110 may have a resistivity of 1E5 (1×10^5) to 1E12 (1×10^12) ohm-cm, or a resistivity equal to the upper and lower ends of this range.

[0023] 1, a bond region 108 exists between the first surface 112 of the polycrystalline layer 106 and the second surface 114 of the monocrystalline layer 110, and the bond region 108 is where the second surface 114 of the polycrystalline layer 106 is directly bonded to the monocrystalline layer 110. In some embodiments, the monocrystalline layer 110 is directly bonded to the polycrystalline layer 106 by utilizing a surface activated bonding (SAB) technique, i.e., no material (e.g., adhesive) exists between the monocrystalline layer 110 and the polycrystalline layer 106. For example, in a surface activated bonding technique, the second surface 114 of the polycrystalline layer 106 and the third surface 116 of the monocrystalline layer 110 may be bombarded with argon (Ar) ions or neutral atoms (e.g., a particle beam, which may be argon (Ar), neutral atoms, or any other similar or comparable type of particles or atoms, which may be suitable) in an ultra-high vacuum to clean and activate the second surface 114 of the polycrystalline layer 106 and the third surface 116 of the monocrystalline layer 110. After the second surface 114 of the polycrystalline layer 106 and the third surface 116 of the monocrystalline layer 110 are cleaned and activated, the second surface 114 of the polycrystalline layer 106 and the third surface 116 of the monocrystalline layer 110 are spontaneously bonded by contacting the second surface 114 of the polycrystalline layer 106 with the third surface 116 of the monocrystalline layer 110. This contacting of the second surface 114 of the polycrystalline layer 106 with the third surface 116 of the monocrystalline layer 110 may occur without a heat treatment.

[0024] The wafer 100 further includes at least one sidewall 120 (e.g., circular in the embodiment shown in FIG. 1 ) where the at least one first sidewall 120a of the polycrystalline layer 106 and the at least one second sidewall 120b of the monocrystalline layer 110 are respectively coplanar and flush with one another. That is, the at least one sidewall 120 includes and is defined by the respective sidewalls of the polycrystalline layer 106, the bonding layer 202, and the monocrystalline layer 110. The bonding layer 202 includes a sidewall 120c that is coplanar with the sidewall 120a of the polycrystalline layer 106 and the sidewall 120b of the monocrystalline layer 110.

[0025] As previously described herein, the polycrystalline layer 106 has a high resistivity, for example, a resistivity of 1×10^5 or 1E+5 ohm-cm or greater. In some alternative embodiments, the polycrystalline layer 106 has a high resistivity in the range of 1×10^5 (1E+5) to 1×10^12 (1E+12) ohm-cm, or equal to the upper and lower ends of this range. In some alternative embodiments, the polycrystalline layer 106 has a high resistivity in the range of 1×10^5 to 1×10^9 ohm-cm, or equal to the upper and lower ends of this range. In some alternative embodiments, the polycrystalline layer 106 has a high resistivity in the range of 1×10^9 (1E9) to 1×10^12 (1E+12) ohm-cm, or equal to the upper and lower ends of this range. This high resistivity of the polycrystalline layer 106 allows electrical signals (e.g., electrons) to pass through the polycrystalline layer 106 reliably without inaccuracies as they pass through the polycrystalline layer 106, so that high power and high frequency electrical signals can travel through the polycrystalline layer 106 and reach their destination with a higher level of precision than if the polycrystalline layer 106 instead had a lower resistivity (e.g., less than 1×10^5, or 1E+5 ohm-centimeters). That is, the on-resistance (R on ) is high (i.e., high resistivity), an electrical signal passes through the polycrystalline layer 106 more stably and accurately without imprecision as it travels through the polycrystalline layer 106 to its target within an electronic device (e.g., a semiconductor package, a semiconductor die, or any other similar or analogous electronic device in which the polycrystalline layer 106 may be present).

[0026] Although not shown in FIG. 1, in some alternative embodiments of wafer 100, a silicon oxide (e.g., SiO2) layer may be present in bond region 108 such that the silicon oxide layer is between polycrystalline layer 106 and monocrystalline layer 110.

[0027] Wafer 100 has a diameter D1 extending from opposite points along the peripheral edge of wafer 100. Diameter D1 may be in the range of 150 to 300 millimeters (mm) and may be equal at the upper and lower ends of this range.

[0028] An embodiment of the wafer 100 may have some degree of bowing, which may be some bending or warping within the embodiment of the wafer 100, causing the second surface 114 of the polycrystalline layer 106 to be slightly curved or have a slight curvature. However, while some degree of bowing may be present in the wafer 100, the bowing of the wafer 100 may be 75 micrometers (μm) or less, or 45 micrometers (μm) or less. Bowing may be measured as the distance from a center point of the wafer to a point at or near the edge of the wafer in a direction transverse to the second surface 114 of the wafer.

[0029] The second surface 114 of the polycrystalline layer 106 may have a roughness of 20 angstroms (Å) or less. In some embodiments, the second surface 114 of the polycrystalline layer 106 may have a roughness in the range of 1 to 5 angstroms (Å), equal to the lower and upper ends of this range (e.g., the roughness may be equal to 1 angstrom (Å) or equal to 5 angstroms (Å)). This roughness of the second surface 114 may be obtained by polishing the second surface 114.

[0030] The third surface 116 of the monocrystalline layer 110 may have a roughness of 20 angstroms (Å) or less. In some embodiments, the third surface 116 of the monocrystalline layer 110 may have a roughness in the range of 1 to 5 angstroms (Å), equal to the lower and upper ends of this range (e.g., the roughness may be equal to 1 angstrom (Å) or equal to 5 angstroms (Å)). This roughness of the third surface 116 may be obtained by polishing the third surface 116.

[0031] The fourth surface 118 of the monocrystalline layer 110 may have a roughness of 20 angstroms (Å) or less. In some embodiments, the fourth surface 118 of the monocrystalline layer 110 may have a roughness in the range of 1 to 5 angstroms (Å), equal to the lower and upper ends of this range (e.g., the roughness may be equal to 1 angstrom (Å) or equal to 5 angstroms (Å)). This roughness of the fourth surface 118 may be obtained by polishing or planarizing the fourth surface 116. In some embodiments, the roughness of the first surface 112 of the polycrystalline layer 106 may be equal to or greater than the roughness of the second surface 114 of the polycrystalline layer 106. This roughness of the first surface 112 may be obtained by polishing or planarizing the first surface 112.

[0032] FIG 2 is directed to a perspective side view of an alternative embodiment of wafer 200, which has some of the same or similar features as the embodiment of wafer 100 shown in FIG 1. The same or similar features of wafer 200 relative to wafer 100 have the same or similar reference numerals. Thus, the following discussion of the alternative embodiment of wafer 200 shown in FIG 2 focuses on different or additional features or details as compared to the embodiment of wafer 100 shown in FIG 1.

[0033] Unlike the embodiment of wafer 100 shown in FIG. 1, in which second surface 114 of polycrystalline layer 106 is directly bonded to third surface 116 of monocrystalline layer 110, in the embodiment of wafer 200 shown in FIG. 2, a bonding layer 202 is present in bonding region 108 to bond polycrystalline layer 106 to monocrystalline layer 110. For example, prior to performing the surface activated bonding (SAB) technique previously discussed herein, a first conductive layer may be formed on second surface 114 of polycrystalline layer 106 and a second conductive layer may be formed on third surface 116 of monocrystalline layer 110. The first conductive layer and second conductive layer may be fabricated of the same or different conductive materials that are suitable to be bonded utilizing SAB techniques. In some embodiments, the first conductive layer and the second conductive layer may be formed on the second surface 114 of the polycrystalline layer 106 and the third surface 116 of the single crystal layer 110, respectively, by a sputtering technique or by any other technique suitable for forming a first conductive layer and a second conductive layer on the second surface of the polycrystalline layer 106 and the third surface 116 of the single crystal layer 110, respectively.

[0034] After the first conductive layer and the second conductive layer are formed on the second surface 114 of the polycrystalline layer 106 and the third surface 116 of the monocrystalline layer 110, respectively, a surface activated bonding technique is performed, whereby the first conductive layer and the second conductive layer are bombarded with argon (Ar) ions or neutral atoms (e.g., a particle beam, which may be argon (Ar), may be neutral atoms, or any other similar or comparable type of particles or atoms that may be suitable) in an ultra-high vacuum to clean and activate the first conductive layer and the second conductive layer on the second surface 114 of the polycrystalline layer 106 and the third surface 116 of the monocrystalline layer 110, respectively. After the first and second conductive layers are cleaned and activated, the first conductive layer on the second surface 114 of the polycrystalline layer 106 and the second conductive layer on the third surface 116 of the monocrystalline layer 110 are spontaneously bonded by contacting the first conductive layer on the second surface 114 of the polycrystalline layer 106 with the second conductive layer on the third surface 116 of the monocrystalline layer 110. This contact between the first conductive layer on the second surface 114 of the polycrystalline layer 106 and the second conductive layer on the third surface 116 of the monocrystalline layer 110 can be made without a heat treatment. When the first conductive layer on the second surface 114 of the polycrystalline layer 106 is bonded to the second conductive layer on the third surface 116 of the monocrystalline layer 110, a bonding layer 202 is formed between the polycrystalline layer 106 and the monocrystalline layer 110.

[0035] In some alternative embodiments, instead of forming both the first and second conductive layers as previously discussed, only one of the first conductive layer or the second conductive layer may be formed only on one of the second surface 114 of the polycrystalline layer 106 or the third surface 116 of the monocrystalline layer 110. After only one of the first conductive layer or the second conductive layer is formed, the SAB technique is performed in the same or similar manner as previously discussed herein with respect to either Figure 1 or Figure 2, except that at least one of the second surface 114 of the polycrystalline layer 106 or the third surface 116 of the monocrystalline layer 110 is still uncovered and exposed to an argon or neutral atom beam.

[0036] If the first material of the polycrystalline layer 106 is not compatible with directly bonding to the second material of the single crystal layer 110, then either both the first conductive layer and / or the second conductive layer may be formed. That is, if the first material of the polycrystalline layer 106 is not compatible with the second material of the single crystal layer 110, then either both the first conductive layer and / or the second conductive layer may be formed to facilitate bonding of the polycrystalline layer 106 to the single crystal layer 110.

[0037] When the bonding layer 202 is between the second surface 114 of the polycrystalline layer 106 and the third surface of the monocrystalline layer 110, the bonding layer 202 has a third thickness T3, which may be referred to as a third dimension. The third thickness T3 extends from the second surface 114 of the polycrystalline layer 106 to the third surface 116 of the monocrystalline layer 110. The third thickness T3 may be less than the first thickness T1. The third thickness T3 of the bonding layer 202 may be in the range of 0.2 to 5 micrometers (μm) and may be equal to the upper and lower ends of this range (e.g., the third thickness T3 may be equal to 0.2 micrometers (μm) or may be equal to 5 micrometers (μm)). In some embodiments, the third thickness may be equal to 0.5 micrometers (μm).

[0038] Alternate embodiments of wafer 200 may have some degree of bowing, which may be some bending or warping in alternate embodiments of wafer 200, causing second surface 114 of polycrystalline layer 106 to be slightly curved or have a slight curvature. However, while alternate embodiments of wafer 200 may have some degree of bowing, the bowing in alternate embodiments of wafer 200 may be 75 micrometers (μm) or less, or 45 micrometers (μm) or less.

[0039] The second surface 114 of the polycrystalline layer 106 may have a roughness of 20 angstroms (Å) or less. In some embodiments, the second surface 114 of the polycrystalline layer 106 may have a roughness in the range of 1 to 5 angstroms (Å), equal to the lower and upper ends of this range (e.g., the roughness may be equal to 1 angstrom (Å) or equal to 5 angstroms (Å)). This roughness of the second surface 114 may be obtained by polishing the second surface 114.

[0040] The third surface 116 of the monocrystalline layer 110 may have a roughness of 20 angstroms (Å) or less. In some embodiments, the third surface 116 of the polycrystalline layer 106 may have a roughness in the range of 1 to 5 angstroms (Å), equal to the lower and upper ends of this range (e.g., the roughness may be equal to 1 angstrom (Å) or equal to 5 angstroms (Å)). This roughness of the third surface 116 may be obtained by polishing the third surface 116.

[0041] The fourth surface 118 of the monocrystalline layer 110 may have a roughness of 20 angstroms (Å) or less. In some embodiments, the fourth surface 118 of the monocrystalline layer 110 may have a roughness in the range of 1 to 5 angstroms (Å), equal to the lower and upper ends of this range (e.g., the roughness may be equal to 1 angstrom (Å) or equal to 5 angstroms (Å)). This roughness of the fourth surface 118 may be obtained by polishing or planarizing the fourth surface 116.

[0042] In some embodiments, the roughness at the first surface 112 of the polycrystalline layer 106 can be equal to or greater than the roughness of the second surface 114 of the polycrystalline layer 106. This roughness of the first surface 112 can be obtained by polishing or planarizing the first surface 112.

[0043] FIG. 3A is a plan view of one embodiment of a polycrystalline substrate 300. As shown in FIG. 3A, the grains 301 of the polycrystalline substrate 300 are readily visible on the first surface 302 and the opposing second surface 304 (see FIG. 3B of this disclosure for the first surface 302 and the second surface 304). The grains 301 have an average grain size greater than 0.5 millimeters (mm). In some embodiments, the average grain size is greater than 1 millimeter (mm). In some embodiments, the grain size is in the range of 0.5 to 2 millimeters (mm), or the average grain size is equal to the upper and lower ends of this range. In some embodiments, the grain size is in the range of 1 to 2 millimeters (mm), or the average grain size is equal to the upper and lower ends of this range.

[0044] The average grain size can be determined using a line segment technique or model. In this technique, a random line is drawn on a micrograph image of a selected area of ​​the substrate. Once a random line is selected, the number of grain boundaries that intersect with the random line are counted. Once the number of grain boundaries that intersect with the random line is determined, the length of the random line is divided by the number of grain boundaries that it intersects divided by the length of the random line. Alternatively, this process can be completed for multiple random lines, where the number of intersections with grain boundaries for the multiple random lines are counted, and then the sum of the lengths of the lines is divided by the total number of intersecting grain boundaries to obtain the average grain size of the substrate.

[0045] 3B is a perspective side view of an embodiment of a polycrystalline substrate 300, which may be a monocrystalline substrate or a polycrystalline wafer before a wafer (e.g., monocrystalline layer 110) is bonded or joined to the polycrystalline substrate 300. The polycrystalline substrate 300 has a diameter D1. The polycrystalline substrate 300 may be utilized in forming the polycrystalline layer 106 in the embodiment of the wafer 100 and in the alternative embodiment of the wafer 200. The polycrystalline substrate 300 includes a first surface 302, a second surface 304 opposite the first surface 302, and a sidewall 306 extending from the first surface 302 to the second surface 304 and lateral to the first surface 302 and the second surface 304. The second surface 304 of the polycrystalline substrate 300 may correspond to the second surface 114 of the polycrystalline layer 106, as in the embodiment of the wafer 100 and in the alternative embodiment of the wafer 200. Sidewall 306 of polycrystalline substrate 300 may correspond to at least one first sidewall 120 a of polycrystalline layer 106 , as in the embodiment of wafer 100 and the alternative embodiment of wafer 200 .

[0046] The fourth thickness T4 of polycrystalline substrate 300 extends from first surface 302 to second surface 304 of polycrystalline substrate 300. The fourth thickness T4 can be equal to or greater than the third thickness T3 of polycrystalline layer 106, as in the embodiment of wafer 100 and the alternative embodiment of wafer 200. The fourth thickness T4 can be in the range of 150 micrometers (μm) to 1000 micrometers (μm), or equal to the lower and upper ends of this range.

[0047] The polycrystalline substrate 300 has a high resistivity, for example, a resistivity of 1×10^5, or 1E+5 ohm-centimeters or greater.

[0048] An embodiment of polycrystalline substrate 300 may have some degree of warping, which may be some bending or warping within an embodiment of polycrystalline substrate 300, causing second surface 304 of polycrystalline layer 106 to be slightly curved or have a slight curvature. However, while some degree of warping may be present in polycrystalline substrate 300, the warping in polycrystalline substrate 300 may be 75 micrometers (μm) or less, or 45 micrometers (μm) or less.

[0049] The second surface 304 of the polycrystalline substrate 300 may have a roughness of 20 angstroms (Å) or less. In some embodiments, the second surface 304 of the polycrystalline substrate 300 may have a roughness in the range of 1 to 5 angstroms (Å), equal to the lower and upper ends of this range (e.g., the roughness may be equal to 1 angstrom (Å) or equal to 5 angstroms (Å)). This roughness of the second surface 304 may be obtained by polishing the second surface 304.

[0050] In at least one embodiment, the size of the grains 301 at the first surface 302 is the same as or similar to the size of the grains 301 at the second surface 304. In at least one embodiment, the average size of the grains 301 at the first surface 302 is the same (i.e., equal) or similar to the average size of the grains 301 at the second surface 304.

[0051] In at least one embodiment, the average grain size of the grains 301 taken along various locations (i.e., slices) of the thickness T4 of the polycrystalline substrate 300 remains the same (i.e., equal) or similar to one another. For example, if the polycrystalline substrate 301 is cut proximate the first surface 302 and the average grain size is measured, the average grain size in this slice proximate the first surface 302 will be the same or similar to the average grain size at the second surface 304, or the same or similar to the average grain size measured in a slice taken anywhere else along the thickness T4 of the polycrystalline substrate 300. That is, the average grain size taken along any slice at the first surface 302 and the second surface 304, or at any location therebetween, will be the same (i.e., equal) or similar to the average grain size in any other slice at the first surface 302 and the second surface 304, or at any other location therebetween, such that the average grain size is uniform along the entire thickness T4 of the polycrystalline substrate 300.

[0052] FIG. 3C is an exaggerated close-up of cross section 3C-3C shown in FIG. 3A of the embodiment of polycrystalline substrate 300 shown in FIG. 3A. Polycrystalline substrate 300 includes grains 402 of silicon carbide (e.g., SiC, SiC2, etc.) that may be bonded together (see FIG. 4A of this disclosure). The grains 402 shown in FIG. 3C are the same as grains 301 shown in FIG. 3A. As shown in FIG. 3C, this exaggerated close-up may represent the grain structure of polycrystalline substrate 300 (see FIG. 3A and FIG. 3B of this disclosure) or the grain structure of polycrystalline layer 106 of wafer 100, 200 (see FIG. 1 and FIG. 2 of this disclosure). Polycrystalline substrate 300 is a non-columnar type polycrystalline such that polycrystalline substrate 300 has randomly oriented or amorphously oriented grains and does not have a columnar type structure. These random, amorphous, oriented grains and non-columnar structure of the polycrystalline layer 300 may be referred to as a non-oriented grain structure. This non-oriented grain structure may help increase the overall resistivity of the polycrystalline substrate 300. The polycrystalline substrate 300 may include pores 404 that may be present along grain boundaries 406 that exist between the grains 402. The grain boundaries 406 exist between adjacent pairs of each of the grains 402. Carbon may be present at the grain boundaries 406 to bond the grains 402 to one another within the polycrystalline layer 106. The grains 402 may have a size of 1 millimeter (mm) or less.

[0053] As previously discussed herein, the polycrystalline layer 106 has a high resistivity, which may be formed utilizing a similarly highly resistive polycrystalline substrate 300. The polycrystalline substrate 300 may have a high resistivity by either reducing or limiting the number of pores 404 between the grains 402 along the grain boundaries 406, such that the polycrystalline substrate 300 has a resistivity of 1×10^5 ohm-cm or greater. In some embodiments, the polycrystalline substrate 300 may have a small amount of nitrogen (N) doped into the polycrystalline substrate 300 to reduce or counteract the effect of the presence of pores 404 in the polycrystalline layer 106. For example, in some embodiments, the polycrystalline layer 106 may have a concentration of nitrogen (N) in the polycrystalline substrate 300 of 1E+16 atoms / cm. 3 (i.e. 1×10 16 atoms / cm3 ) or less. Polycrystalline substrate 300 can be fabricated to have such low concentrations of nitrogen by utilizing source gases with a purity of 99.9% or greater, or alternatively, by using high purity solid source material to reduce the concentration of nitrogen (N) present in polycrystalline substrate 300 once formed.

[0054] In at least one embodiment, the polycrystalline substrate 300 is 1×10 7 In at least one embodiment, the polycrystalline substrate 300 has a resistivity of 1×10 8 It has a resistivity of ohm-centimeters or greater.

[0055] In view of the above discussion, the resistivity of the polycrystalline substrate 300 is increased by reducing the effect of or preventing the formation of the pores 404 in the polycrystalline substrate 300, as well as by providing relatively large grains 402 (i.e., see the discussion earlier herein regarding the grain size of the grains 402) and large grain boundaries 406. In at least some embodiments, the porosity of the polycrystalline substrate 300 is in the range of 0-2%, or equal to the upper and lower ends of this range. In at least some embodiments, the porosity of the polycrystalline substrate 300 is 2% or less. In at least some embodiments, the porosity of the polycrystalline substrate 300 is 1% or less. That is, in an ideal world, the polycrystalline substrate 300 would not have the pores 404, and it is desirable to avoid the presence of the pores 404 in the polycrystalline substrate 300 so that the polycrystalline substrate 300 is not porous.

[0056] In at least some embodiments, the polycrystalline substrate 300 has a silicon carbide (SiC) purity of 98% or greater. In at least some embodiments, the polycrystalline substrate has a silicon carbide (SiC) purity in the range of 99% to 100% or equal to the upper and lower ends of this range. In at least one embodiment of the polycrystalline substrate 300, the polycrystalline substrate 300 does not contain any metal or additive materials and is composed only of silicon carbide (SiC). That is, in light of these ranges of purity and purity considerations for the polycrystalline substrate 300, in an ideal world, the polycrystalline substrate 300 would be 100% pure silicon carbide (SiC) and would not contain additives (i.e., metal particles).

[0057] The polycrystalline substrate 300 has a density 98% greater than a high resistivity monocrystalline SiC layer or substrate. Compared to a monocrystalline layer or substrate having a similar high resistivity, the much denser polycrystalline substrate 300 further prevents low resistance spots and allows conduction with less resistance between the grains 402. In at least one embodiment, the polycrystalline substrate 300 has a density in the range of 3.14 g / cm^3 (i.e., grams per cubic centimeter) to 3.21 g / cm^3, or a density equal to the upper and lower ends of this range. In at least some embodiments, the polycrystalline substrate 300 has a density of 3.19 g / cm^3 or greater.

[0058] In at least one embodiment, the polycrystalline substrate 300 has a thermal conductivity in the range of 250 W / (m×K) (i.e., watts per meter Kelvin) to 350 W / (m×K), or equal to the upper and lower ends of this range. In at least one embodiment, the polycrystalline substrate 300 has a thermal conductivity of 300 W / (m×K) or greater. That is, since the polycrystalline substrate 300 has a relatively high thermal conductivity, the polycrystalline substrate 300 can dissipate thermal energy, or heat, more effectively than a respective polycrystalline substrate having a lower thermal conductivity. Since the polycrystalline substrate 300 has a high resistivity due to the relatively large crystal grains 301, 402, the relatively large grain boundaries 406, and the few or no pores 404, and has a high thermal conductivity, the polycrystalline substrate 300 is effective and can be utilized in high power and high frequency applications.

[0059] In at least one embodiment, the polycrystalline substrate 300 has a transparency in the range of 97.5% to 99.5%, or equal to the upper and lower ends of this range, In at least one embodiment, the polycrystalline substrate has a transparency of 98% or greater.

[0060] In at least one embodiment, polycrystalline substrate 300 has a 111 crystal orientation. In at least one embodiment, polycrystalline substrate 300 has 111 crystal orientation in between 60% and 90% of the grains, or between the upper and lower ends of this range.

[0061] Figure 4A is directed to a flowchart 500 of an embodiment of a method for manufacturing an embodiment of a wafer 100 of the present disclosure shown in Figure 1. Figures 5A-5C are directed to side views of respective steps 502, 504, 506, and 508 of the flowchart 500 of an embodiment of a method for manufacturing an embodiment of a wafer 100 of the present disclosure.

[0062] In a polycrystalline substrate formation step 502, a polycrystalline substrate 300 having high resistivity is formed. In a single crystal substrate formation step 504, a single crystal substrate 600 is formed. The polycrystalline substrate formation step 502, in which the polycrystalline substrate 300 is formed, and the single crystal substrate formation step 504, in which the single crystal substrate 600 is formed, may occur simultaneously within a semiconductor manufacturing plant (FAB) or may occur at different times within the FAB.

[0063] The polycrystalline substrate formation step 502 for forming the highly resistive polycrystalline substrate 300 may be performed utilizing at least one of the embodiments of the method for forming the polycrystalline substrate 300 illustrated in the chemical vapor deposition (CVD) flow chart 502a shown in FIG. 4B or the high temperature chemical vapor deposition (HTCVD) flow chart 502b shown in FIG. 4C.

[0064] When the polycrystalline substrate 300 is formed using the method of the CVD flow chart 502a shown in FIG. 4B, in a first step 510, a carrier (e.g., a graphite disk, a dummy silicon substrate, or any other suitable type of carrier or temporary carrier on which polycrystalline silicon carbide (SiC) can be formed) is inserted or introduced into a chamber of a CVD tool configured to carry out or perform a CVD process to form the polycrystalline substrate 300. The carrier may be a plate, a carrier substrate, or any other suitable type of carrier on which the polycrystalline substrate is formed. The carrier may be a polycrystalline carrier substrate or plate, a graphite carrier substrate or plate, or any other suitable type of carrier substrate or plate on which the polycrystalline substrate 300 is formed.

[0065] After a first step 510 in which a carrier is inserted or introduced into the CVD tool chamber, in a second step 512, the chamber is sealed and a carrier gas is introduced into the CVD tool chamber. The carrier gas can be hydrogen gas. In some embodiments, the carrier gas can be some other type of noble gas (e.g., argon, helium, etc.). The carrier gas is introduced at a flow rate of 100 liters per minute (l / min). The carrier gas is configured or selected to promote a chemical reaction in the CVD tool furnace chamber to grow polycrystalline silicon carbide (SiC) on the carrier in the CVD tool furnace chamber. In some embodiments, during the second step 512, the CVD tool furnace chamber can be heated within a range of 1250 to 1350 degrees Celsius (°C) or to a temperature equal to the upper and lower ends of this range (e.g., a temperature equal to 1250 degrees Celsius (°C) or a temperature equal to 1350 degrees Celsius (°C)). In some alternative embodiments, during the second step 512, the furnace chamber of the CVD tool may be heated to a temperature equal to 1320 degrees Celsius (° C.).

[0066] After a second step 512 in which a carrier gas is introduced into the furnace chamber of the CVD tool and the furnace chamber of the CVD tool is heated or the heating is started, a source gas is introduced into the furnace chamber of the CVD tool in a third step 514. The source gas includes a carbon or carbon-based gas (e.g., ethene) and a silicon-containing or silicon-based gas (e.g., silane, trichlorosilane (TCS), or any other similar silicon-containing or silicon-based gas). When the source gas includes ethene gas and silane gas, the ethene gas is introduced at a flow rate of 60 milliliters per minute (ml / min) and the silane gas is introduced at a flow rate of 80 milliliters per minute (ml / min). For example, the carbon gas or carbon-based gas, in this case ethene gas, can be introduced into the CVD tool furnace chamber by introducing a solid source of ethene into the CVD tool furnace chamber, and the silicon-containing gas or silicon-based gas, in this case silane gas, can be introduced into the CVD tool furnace chamber by introducing a solid source of silane into the CVD tool furnace chamber. Alternatively, the respective fluid passages in fluid communication with the CVD tool furnace chamber can be opened to introduce the carbon gas or carbon-based gas (i.e., ethene gas) and the silicon-containing gas or silicon-based gas (i.e., silane gas). At this stage, when these respective gases are introduced into the CVD tool chamber, these respective gases chemically react with each other to form polycrystalline silicon carbide (SiC) which is deposited on the carrier, and the polycrystalline silicon carbide is formed on the carrier surface of the carrier. If the carrier is a polycrystalline silicon carbide carrier substrate or plate, the polycrystalline silicon carbide formed by the reaction in the CVD tool chamber is deposited on the polycrystalline silicon carbide carrier substrate or plate. When the carrier is a graphite carrier substrate or plate, the polycrystalline silicon carbide formed by the reaction in the chamber of the CVD tool is deposited on the graphite carrier substrate or plate, and the carrier has a polycrystalline structure such that a polycrystalline substrate 300 can be formed on each surface of the carrier.Each surface of the carrier has a roughness of 5 nm (i.e., nanometers) or less. Each surface of the carrier has the same or similar structure as the polycrystalline substrate 300 that is formed and grown on the carrier. In some situations, each surface of the carrier is treated with a surface treatment process prior to forming or growing the polycrystalline substrate 300 on the carrier. When the polycrystalline silicon carbide is formed in the chamber of the CVD tool, a polycrystalline silicon carbide substrate is formed. In some embodiments, the polycrystalline silicon carbide is doped with a small amount of nitrogen (e.g., 1×10. 16 atoms / cm 3 The nitride may be doped with nitrogen at a concentration of 1000 to 2000 nm.

[0067] A third step 514 in the process is performed for 1-4 hours, 1 hour, or 4 hours to form a selected thickness of polycrystalline silicon carbide formed on the carrier. Performing the third step 514 for 1-4 hours, 1 hour, or 4 hours forms polycrystalline silicon carbide having a thickness of 350-500 micrometers (μm), or a thickness equal to the upper and lower ends of this range.

[0068] After a third step 514 in which carbon gas or a carbon-based gas (i.e., ethene gas) and a silicon-containing gas or a silicon-based gas (i.e., silane gas) are introduced into the furnace chamber of the CVD tool while being heated to form polycrystalline silicon carbide on the carrier, in a fourth step 516, the chamber of the CVD tool and the polycrystalline substrate 300 formed on the carrier are cooled to room temperature. As the polycrystalline substrate 300 cools on the carrier, some warping of the polycrystalline substrate 300 may occur due to the difference in thermal conductivity between the polycrystalline substrate 300 and the carrier. However, this warping of the polycrystalline substrate 300 may be 75 micrometers (μm) or less, or 45 micrometers (μm) or less. Once cooled to room temperature, the polycrystalline substrate 300 bonded to the carrier and the carrier are removed from the chamber of the CVD tool. After the polycrystalline substrate 300 and carrier are removed from the chamber, the polycrystalline substrate 300 may then be further processed (e.g., polishing techniques, planarizing techniques, etc.) after being removed from the carrier, a portion of the polycrystalline substrate 300 may be sliced ​​from the polycrystalline substrate 300 either while bonded to the carrier or after being removed from the carrier, or before or after further processing, to form the polycrystalline layer 106, or the polycrystalline substrate may undergo other suitable types of processing techniques to further purify or process the polycrystalline substrate 300 to form various electronic devices or components.

[0069] After polycrystalline substrate 300 is formed, polycrystalline substrate 300 may be utilized to form an embodiment of wafer 100 as shown in FIG. 1, or an alternative embodiment of wafer 200 as shown in FIG. 2. For example, in at least one situation, second surface 304 of polycrystalline substrate 300 is polished or planarized such that second surface 304 of polycrystalline substrate 300 has a roughness of 20 angstroms (Å) or less. In some embodiments, second surface 304 of polycrystalline substrate 300 has a roughness in the range of 1 to 5 angstroms (Å), or equal to the lower or upper ends of this range (e.g., the roughness can be equal to 1 angstrom (Å) or equal to 5 angstroms (Å)). After the second surface 304 of the polycrystalline substrate 300 has been polished or planarized, the polycrystalline substrate 300 may then be utilized to form the embodiment of the wafer 100 shown in FIG. 1 or the alternative embodiment of the wafer 200 shown in FIG. 2.

[0070] When the CVD tool method illustrated in flow chart 502a is utilized to form polycrystalline substrate 300, polycrystalline substrate 300 is comprised of a polycrystalline structure that is predominantly of the 3C-SiC polytype. For example, in some embodiments, the crystalline structure of polycrystalline substrate 300 is comprised of 80% of the 3C-SiC polytype. In some embodiments, the crystalline structure of polycrystalline substrate 300 may be comprised of 50%-100% of the 3C-SiC polytype, or equal to the upper and lower ends of this range (e.g., equal to 50% or equal to 100%). Polycrystalline substrate 300 has a high resistivity, greater than 1x10^5, or 1E+5 ohm-centimeters.

[0071] When the polycrystalline substrate 300 is formed using the method of the HTCVD flow chart 502b shown in FIG. 4C, in a first step 518, a carrier (e.g., a graphite disk, a dummy silicon substrate, or any other suitable type of carrier or temporary carrier on which polycrystalline silicon carbide (SiC) can be formed) is inserted or introduced into a chamber of an HTCVD tool configured to perform or implement the HTCVD process for forming the polycrystalline substrate 300. The carrier can be a plate, a carrier substrate, or any other suitable type of carrier on which the polycrystalline substrate is formed. The carrier can be a polycrystalline carrier substrate or plate, a graphite carrier substrate or plate, or any other suitable type of carrier substrate or plate on which the polycrystalline substrate is formed. The carrier has a polycrystalline structure such that the polycrystalline substrate 300 can be formed on each surface of the carrier. Each surface of the carrier has a roughness of 5 nm (i.e., nanometers) or less. Each surface of the carrier has the same or similar structure as the polycrystalline substrate 300 that is formed and grown on the carrier. In some circumstances, each surface of the carrier is treated with a surface treatment process prior to forming or growing the polycrystalline substrate 300 on the carrier.

[0072] After a first step 518 in which the carrier is inserted or introduced into the chamber of the HTCVD tool, in a second step 520, the chamber is sealed and a carrier gas is introduced into the chamber of the HTCVD tool. The carrier gas can be argon gas, helium gas, or hydrogen gas. In some embodiments, the carrier gas can be some other type of noble gas. The carrier gas is introduced at a flow rate of 100 liters per minute (l / min). The carrier gas is configured or selected to promote a chemical reaction in the furnace chamber of the HTCVD tool to grow polycrystalline silicon carbide (SiC) on the carrier in the furnace chamber of the HTCVD tool. In some embodiments, during the second step 520, the furnace chamber of the HTCVD tool can be heated within a range of 2000 to 2500 degrees Celsius (°C) or can be heated to a temperature equal to the upper and lower ends of this range (e.g., a temperature equal to 2000 degrees Celsius (°C) or a temperature equal to 2500 degrees Celsius (°C)). In some alternative embodiments, during the second step 520, the furnace chamber of the HTCVD tool may be heated to a temperature equal to 2250 degrees Celsius (° C.).

[0073] After a second step 520 in which a carrier gas is introduced into the furnace chamber of the HTCVD tool and the furnace chamber of the HTCVD tool is heated or heating is started, in a third step 522, a source gas is introduced into the furnace chamber of the CVD tool. The source gas includes a carbon or carbon-based gas (e.g., ethene) and a silicon-containing or silicon-based gas (e.g., silane, trichlorosilane (TCS), or any other similar silicon-containing or silicon-based gas. When the source gas includes ethene gas and silane gas, the ethene gas is introduced at a flow rate of 46.7 milliliters per minute (ml / min) and the silane gas is introduced at a flow rate of 350 milliliters per minute (ml / min). For example, the carbon or carbon-based gas, in this case ethene gas, may be introduced into the furnace chamber of the HTCVD tool by introducing a solid source of ethene into the furnace chamber of the HTCVD tool, and the silicon-containing or silicon-based gas, in this case silane gas, may be introduced into the furnace chamber of the HTCVD tool by introducing a solid source of silane into the furnace chamber of the HTCVD tool. Alternatively, the carbon or carbon-based gas (i.e., ethene gas) and the silicon-containing or silicon-based gas (i.e., silane gas) may be introduced into the furnace chamber of the HTCVD tool by introducing a solid source of silane into the furnace chamber of the HTCVD tool. The respective fluid passages in fluid communication with the furnace chamber of the HTCVD tool can be opened to introduce the respective gases. At this stage, when these respective gases are introduced into the chamber of the HTCVD tool, these respective gases chemically react with each other to form polycrystalline silicon carbide (SiC) which deposits on the carrier, with the polycrystalline silicon carbide being formed on the carrier surface of the carrier. If the carrier is a polycrystalline silicon carbide carrier substrate or plate, the polycrystalline silicon carbide formed by the reaction in the chamber of the HTCVD tool is deposited on the polycrystalline silicon carbide carrier substrate or plate. If the carrier is a graphite carrier substrate or plate, the polycrystalline silicon carbide formed by the reaction in the chamber of the HTCVD tool is deposited on the graphite carrier substrate or plate. When the polycrystalline silicon carbide is formed in the chamber of the HTCVD tool, a polycrystalline silicon carbide substrate is formed.In some embodiments, the polycrystalline silicon carbide is 1×10. 16 atoms / cm 3 It may be doped with small amounts of nitrogen.

[0074] A third step 522 in the process is carried out for 1-4 hours, 1 hour, or 4 hours to form a selected thickness of polycrystalline silicon carbide formed on the carrier. Carrying out the third step 522 for 1-4 hours, 1 hour, or 4 hours results in polycrystalline silicon carbide having a thickness of 350-500 micrometers (μm), or the thickness may be equal to the upper and lower ends of this range.

[0075] After a third step 522 in which carbon or carbon-based gas (i.e., ethene gas) and silicon-containing or silicon-based gas (i.e., silane gas) are introduced into the furnace chamber of the HTCVD tool while being heated to form polycrystalline silicon carbide on the carrier, in a fourth step 524, the chamber of the HTCVD tool and the polycrystalline substrate 300 formed on the carrier are cooled to room temperature. As the polycrystalline substrate 300 cools on the carrier, the difference in thermal conductivity between the polycrystalline substrate 300 and the carrier may cause some warping of the polycrystalline substrate 300. However, this warping of the polycrystalline substrate 300 may be 75 micrometers (μm) or less, or 45 micrometers (μm) or less. Once cooled to room temperature, the polycrystalline substrate 300 bonded to the carrier and the carrier are removed from the chamber of the HTCVD tool. After the polycrystalline substrate 300 and carrier are removed from the chamber, the polycrystalline substrate 300 may be removed from the carrier and then further processed (e.g., polishing techniques, planarizing techniques, etc.), a portion of the polycrystalline substrate 300 may be sliced ​​from the polycrystalline substrate 300 either while bonded to the carrier or after being removed from the carrier, or before or after further processing, to form the polycrystalline layer 106, or the polycrystalline substrate may undergo other suitable types of processing techniques to further purify or process the polycrystalline substrate 300 to form various electronic devices or components.

[0076] After polycrystalline substrate 300 is formed, polycrystalline substrate 300 may be utilized to form an embodiment of wafer 100 as shown in FIG. 1, or an alternative embodiment of wafer 200 as shown in FIG. 2. For example, in at least one situation, second surface 304 of polycrystalline substrate 300 is polished or planarized such that second surface 304 of polycrystalline substrate 300 has a roughness of 20 angstroms (Å) or less. In some embodiments, second surface 304 of polycrystalline substrate 300 has a roughness in the range of 1 to 5 angstroms (Å), or equal to the lower or upper ends of this range (e.g., the roughness can be equal to 1 angstrom (Å) or equal to 5 angstroms (Å)). After the second surface 304 of the polycrystalline substrate 300 has been polished or planarized, the polycrystalline substrate 300 may then be utilized to form the embodiment of the wafer 100 shown in FIG. 1 or the alternative embodiment of the wafer 200 shown in FIG. 2.

[0077] In the single crystal substrate formation step 504, a single crystal substrate 600 (see FIG. 5B) may be formed utilizing known methods in the semiconductor industry. For example, the single crystal substrate 600 may be formed by melting high purity semiconductor grade silicon and then utilizing a seed crystal to initiate the formation of the single crystal substrate.

[0078] Once polycrystalline substrate 300 and monocrystalline substrate 600 are formed, in a bonding or joining step 506 of flowchart 500 for forming an embodiment of wafer 100, second surface 304 of polycrystalline substrate 300 is bonded to third surface 602 of monocrystalline substrate 600 utilizing a surface activated bonding (SAB) technique. Third surface 602 of monocrystalline substrate 600 may correspond to third surface 116 of monocrystalline layer 110 of wafer 100.

[0079] When the SAB technique is utilized, the second surface 304 of the polycrystalline substrate 300 is exposed to a beam of neutral atoms or argon (Ar) atoms to activate and clean the second surface 304 of the polycrystalline substrate 300, as represented by arrow 603 in FIG. 5A. The second surface 304 of the polycrystalline substrate 300 may be planarized to be substantially flat and level, and polished to have a roughness of 20 angstroms (Å) or less. In some embodiments, the second surface 304 of the polycrystalline substrate 300 may have a roughness in the range of 1 to 5 angstroms (Å), or equal to the lower and upper ends of this range, prior to exposure to the beam of neutral atoms or argon (Ar) atoms (e.g., the roughness may be equal to 1 angstrom (Å) or equal to 5 angstroms (Å)).

[0080] When the SAB technique is utilized, the third surface 602 of the single crystal substrate 600 is exposed to a beam of neutral atoms or argon (Ar) atoms (not shown) to activate and clean the third surface 602 of the single crystal substrate 600. The third surface 602 of the single crystal substrate 600 may be planarized to be substantially flat and level, and polished to have a roughness of 20 angstroms (Å) or less. In some embodiments, the third surface 602 of the single crystal substrate 600 may have a roughness in the range of 1 to 5 angstroms (Å), or equal to the lower and upper ends of this range, prior to exposure to the beam of neutral atoms or argon (Ar) atoms (e.g., the roughness may be equal to 1 angstrom (Å) or equal to 5 angstroms (Å)).

[0081] The fourth surface 610 of the second portion 600b of the single crystal substrate 600 may have a roughness of 20 angstroms (Å) or less. In some embodiments, the fourth surface 610 of the second portion 600b of the single crystal substrate 600 may have a roughness in the range of 1 to 5 angstroms (Å), or equal to the lower and upper ends of this range (e.g., the roughness may be equal to 1 angstrom (Å) or equal to 5 angstroms (Å)). This roughness of the fourth surface 610 may be obtained by polishing or planarizing the fourth surface 610.

[0082] In some embodiments, the roughness at the first surface 302 of the polycrystalline substrate 300 may be equal to or greater than the roughness of the second surface 304 of the polycrystalline substrate 300. This roughness of the first surface 302 may be obtained by polishing or planarizing the first surface 302.

[0083] After the second surface 304 of the polycrystalline substrate 300 and the third surface 602 of the single crystal substrate 600 are cleaned and activated, the single crystal substrate 600 is flipped over and the cleaned and activated third surface 602 of the single crystal substrate 600 contacts the cleaned and activated second surface 304 of the polycrystalline substrate 300, such that the cleaned and activated second surface 304 spontaneously bonds with the cleaned and activated third surface 602, and the single crystal substrate 600 is bonded to the polycrystalline substrate 300 at the bonding region 604. When the single crystal substrate 600 is bonded to the polycrystalline substrate 300, the sidewall 606 of the single crystal substrate 600 is flush with the sidewall 306 of the polycrystalline substrate 300. The single crystal substrate 600 has a fifth thickness T5 that extends from a third surface 602 of the single crystal substrate 600 to a fourth surface 608 of the single crystal substrate 600 opposite the third surface 602 of the single crystal substrate 600.

[0084] After a bonding step 506 in which the single crystal substrate 600 is bonded to the polycrystalline substrate 300, a first portion 600a of the single crystal substrate 600 is removed from the second portion 600b in a removing step 508. The first portion 600a may be removed from the second portion 600b by slicing the single crystal substrate 600 forming the first portion 600a and the second portion 600b. After the second portion 600b is removed from the first portion 600a, the second portion 600b of the single crystal substrate 600 may be reused to form another wafer that is the same or similar to the wafer 100, for example, by performing the bonding step 506 and the removing step 508 of the manufacturing method in the flowchart 500. By removing the first portion 600a from the second portion 600b, the sidewall 606 is divided into a first sidewall 606a of the first portion 600a and a second sidewall 606b of the second portion 600b. After the first portion 600a is removed, the second sidewall 606b of the second portion 600b remains coplanar and flush with the sidewall 306 of the polycrystalline substrate 300. After the first portion 600a is removed, the second portion 600b remains bonded to the polycrystalline substrate 300 at the bond region 604. After the first portion 600a is removed from the second portion 600b, the second portion 600b has a second thickness T2 extending between a third surface 602 of the second portion 600b and a fourth surface 610 of the second portion 600b formed by removing the first portion 600a from the second portion 600b. After the first portion 600a is removed from the second portion 600b, the first portion has a sixth thickness T6 extending from the fourth surface 608 of the first portion 600a to a fifth surface 612 of the first portion 600a opposite the fourth surface of the first portion 600a. The sixth thickness T6 is less than the fifth thickness T5.

[0085] The second portion 600b of the monocrystalline substrate 600 may correspond to the monocrystalline layer 110 of the wafer 100, the polycrystalline substrate 300 may correspond to the polycrystalline layer 106 of the wafer 100, and the bonded region 604 may correspond to the bonded region 108 of the wafer 100. That is, in some embodiments, the wafer 100 is fabricated after the first portion 600a is removed from the second portion 600b. In some alternative embodiments, some further processing steps may be performed to complete the fabrication of the wafer 100, such as grinding the first surface 302 of the polycrystalline substrate 300.

[0086] Generally, the single crystal substrate 600 is more expensive to manufacture than the polycrystalline substrate 300, so by bonding the single crystal substrate 600 to the high resistivity polycrystalline substrate 300 as a support and removing the first portion 600a from the second portion 600b, the single crystal substrate 600 can be used to form multiple substrates of the wafer 100, thereby reducing the manufacturing cost. In other words, the cost of manufacturing the single crystal substrate 600 may be expensive, but the cost of manufacturing the single crystal substrate 600 can be distributed across multiple substrates of the wafer 100 manufactured using a manufacturing method such as that in the flowchart 500.

[0087] In an alternative embodiment of the manufacturing method of flowchart 500, the first portion 600a of the single crystal substrate 600 may be removed from the second portion 600b of the single crystal substrate 600 prior to bonding the single crystal substrate 600 to the polycrystalline substrate 300. After the first portion 600a is removed from the second portion 600b, the third surface 602 of the second portion 600b of the single crystal substrate 600 is bonded to the second surface 304 of the polycrystalline substrate 300. In other words, the removing step 508 occurs before the bonding step 506 in this alternative embodiment of the method of manufacturing the wafer 100.

[0088] While the method discussed in detail with respect to the flowchart of FIG. 5A describes forming the wafer 100, the method discussed in detail with respect to the flowchart 500 of FIG. 5A may be modified by forming a first conductive layer on the second surface 304 of the polycrystalline substrate 300 by sputtering techniques, forming a second conductive layer on the third surface 602 of the monocrystalline substrate 600, or forming only one of the first and second conductive layers and then bonding the polycrystalline substrate 300 to the monocrystalline substrate 600 using both the first and second conductive layers or only one of the first or second conductive layers. This sputtering step may be performed or carried out between the first step 502 and the second step 504 of the method, as discussed in detail with respect to the flowchart 500 of FIG. 5A. When this sputtering step is performed or carried out, a bonding layer 202 as shown in FIG. 2 is formed, resulting in the production of an alternative embodiment of the wafer 200.

[0089] Although not shown, the wafer 100 as shown in FIG. 5C may be further processed and refined (e.g., additional layers (e.g., conductive and non-conductive) formed on the monocrystalline layer 110, singulating the wafer 100, backgrinding the wafer 100, etc.) and utilized in forming electronic devices, such as semiconductor packages or semiconductor devices, and components. For example, a first electrode may be formed on a first side 102 of the wafer 100 and a second electrode may be formed on a second side 104 of the wafer 100 such that an electrical current may be passed through the wafer 100, with the highly resistive wafer 100 allowing the wafer 100 to be utilized in high power and high frequency applications.

[0090] At least one embodiment of a device of the present disclosure may be summarized as comprising a polycrystalline silicon carbide (SiC) base substrate including a first surface, a second surface opposite the first surface, a resistivity of 1×10 ohm-cm or greater, and a grain size of 0.5 millimeters (mm) or greater, and a single crystal silicon carbide (SiC) substrate directly bonded to the first surface of the polycrystalline silicon carbide (SiC) base substrate.

[0091] The single crystal silicon carbide (SiC) substrate can have a thickness of at least one of less than and equal to 1 micrometer (μm).

[0092] The polycrystalline silicon carbide (SiC) based substrate can have a thickness of 300 micrometers (μm) or greater.

[0093] The polycrystalline silicon carbide (SiC) base substrate may have a thickness of at least one of 300 to 500 micrometers (μm), equal to 300 micrometers (μm), and equal to 500 micrometers (μm).

[0094] The resistivity of the polycrystalline silicon carbide (SiC) based substrate 0 can be at least one of 1×10^5 ohm-cm to 1×10^12 ohm-cm, equal to 1×10^5 ohm-cm, and equal to 1×10^12 ohm-cm.

[0095] The resistivity of the polycrystalline silicon carbide (SiC) based substrate can be at least one of 1×10^5 ohm-cm to 1×10^9 ohm-cm, equal to 1×10^5 ohm-cm, and equal to 1×10^8 ohm-cm.

[0096] The first surface may have a roughness of 5 Angstroms (Å) or less.

[0097] The particle size may be 5 millimeters (mm) or less.

[0098] At least one embodiment of a device of the present disclosure can be summarized as comprising a polycrystalline silicon carbide (SiC) substrate including a first surface, a second surface opposite the first surface, a resistivity of 1×10^5 ohm-cm or greater, and a grain size of 0.5 millimeters (mm) or greater.

[0099] The polycrystalline silicon carbide (SiC) substrate can have a thickness of 300 micrometers (μm) or greater.

[0100] The polycrystalline silicon carbide (SiC) substrate can have a thickness of at least one of 300 to 500 micrometers (μm), equal to 300 micrometers (μm), and equal to 500 micrometers (μm).

[0101] The resistivity of the polycrystalline silicon carbide (SiC) substrate can be at least one of 1×10^5 ohm-cm to 1×10^12 ohm-cm, equal to 1×10^5 ohm-cm, and equal to 1×10^12 ohm-cm.

[0102] The resistivity of the polycrystalline silicon carbide (SiC) substrate can be at least one of 1×10^5 ohm-cm to 1×10^9 ohm-cm, equal to 1×10^5 ohm-cm, and equal to 1×10^8 ohm-cm.

[0103] The first surface may have a roughness of 5 Angstroms (Å) or less.

[0104] A large portion of a polycrystalline silicon carbide (SiC) substrate may be composed of the 4H-SiC crystal structure.

[0105] Eighty percent (80%) of a polycrystalline silicon carbide (SiC) substrate may be composed of the 4H—SiC crystal structure.

[0106] The particle size may be 5 millimeters (mm) or less.

[0107] At least one embodiment of the method of the present disclosure is summarized as including forming a polycrystalline silicon carbide (SiC) base substrate on a support substrate, the polycrystalline silicon carbide (SiC) base substrate having a resistivity greater than 1×10 ohm-cm and a grain size equal to or greater than 0.5 millimeters (mm), and removing the polycrystalline silicon carbide (SiC) base substrate from the support substrate.

[0108] Forming the polycrystalline silicon carbide (SiC) base substrate may include raising a temperature in a chamber of a HTCVD (high temperature chemical vapor deposition) furnace in which the support substrate is housed to at least one of 2000-2500 degrees Celsius (°C), equal to 2000 degrees Celsius (°C), and 2500 degrees Celsius (°C), and introducing a silane source gas and an ethene source gas into the chamber to grow the polycrystalline silicon carbide (SiC) base substrate on the support substrate.

[0109] Forming the polycrystalline silicon carbide (SiC) base substrate may include raising a temperature in a CVD (chemical vapor deposition) furnace chamber in which the support substrate is stored to at least one of 1250 to 1350 degrees Celsius (°C), equal to 1250 degrees Celsius (°C), and 1350 degrees Celsius (°C), and introducing a silane precursor gas and an ethene precursor gas into the chamber to grow the polycrystalline silicon carbide (SiC) base substrate on the support substrate.

[0110] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary, to employ concepts from various patents, applications, and publications to provide further embodiments.

[0111] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but rather to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. A device, comprising: A polycrystalline silicon carbide (SiC) based substrate, A first surface, a second surface opposite the first surface; A resistivity of 1×10^5 ohm-cm or greater; and a polycrystalline silicon carbide (SiC) base substrate including a grain size of 0.5 millimeters (mm) or greater; a single crystal silicon carbide (SiC) substrate bonded directly to the first surface of the polycrystalline silicon carbide (SiC) base substrate; A device comprising:

2. 10. The device of claim 1, wherein the single crystal silicon carbide (SiC) substrate has at least one of a thickness less than 1 micrometer (μm) and a thickness equal to 1 micrometer (μm).

3. The device of claim 2 , wherein the polycrystalline silicon carbide (SiC) base substrate has a thickness of 300 micrometers (μm) or greater.

4. 4. The device of claim 3, wherein the polycrystalline silicon carbide (SiC) base substrate has at least one of a thickness between 300 and 500 micrometers (μm), a thickness equal to 300 micrometers (μm), and a thickness equal to 500 micrometers (μm).

5. 2. The device of claim 1, wherein the resistivity of the polycrystalline silicon carbide (SiC) base substrate is at least one of a resistivity between 1×10^5 ohm-cm and 1×10^12 ohm-cm, a resistivity equal to 1×10^5 ohm-cm, and a resistivity equal to 1×10^12 ohm-cm.

6. 2. The device of claim 1, wherein the resistivity of the polycrystalline silicon carbide (SiC) base substrate is at least one of a resistivity between 1×10^5 ohm-cm and 1×10^9 ohm-cm, a resistivity equal to 1×10^5 ohm-cm, and a resistivity equal to 1×10^8 ohm-cm.

7. The device of claim 1 , wherein the first surface has a roughness of 5 Angstroms (Å) or less.

8. The device of claim 1 , wherein the particle size is 5 millimeters (mm) or less.

9. A polycrystalline silicon carbide (SiC) substrate, A first surface, a second surface opposite the first surface; A resistivity of 1×10^5 ohm-cm or greater; and 1. A device comprising a polycrystalline silicon carbide (SiC) substrate comprising a grain size of 0.5 millimeters (mm) or greater.

10. 10. The device of claim 9, wherein the polycrystalline silicon carbide (SiC) substrate has a thickness of 300 micrometers (μm) or greater.

11. 11. The device of claim 10, wherein the polycrystalline silicon carbide (SiC) substrate has at least one of a thickness between 300 and 500 micrometers (μm), a thickness equal to 300 micrometers (μm), and a thickness equal to 500 micrometers (μm).

12. 10. The device of claim 9, wherein the resistivity of the polycrystalline silicon carbide (SiC) substrate is at least one of a resistivity between 1×10^5 ohm-cm and 1×10^12 ohm-cm, a resistivity equal to 1×10^5 ohm-cm, and a resistivity equal to 1×10^12 ohm-cm.

13. 10. The device of claim 9, wherein the resistivity of the polycrystalline silicon carbide (SiC) substrate is at least one of a resistivity between 1×10^5 ohm-cm and 1×10^9 ohm-cm, a resistivity equal to 1×10^5 ohm-cm, and a resistivity equal to 1×10^8 ohm-cm.

14. The device of claim 9 , wherein the first surface has a roughness of 5 Angstroms (Å) or less.

15. 10. The device of claim 9, wherein the polycrystalline silicon carbide (SiC) substrate is predominantly composed of a 4H-SiC crystal structure.

16. 16. The device of claim 15, wherein 80% of the polycrystalline silicon carbide (SiC) substrate is composed of 4H-SiC crystal structure.

17. 10. The device of claim 9, wherein the particle size is 5 millimeters (mm) or less.

18. forming a polycrystalline silicon carbide (SiC) base substrate on a surface of a support substrate, the SiC base substrate having a resistivity greater than 1×10 ohm-cm and a grain size of 0.5 millimeters (mm) or greater, the support substrate being a polycrystalline material and having a roughness of 5 nanometers (nm) or less; and removing the polycrystalline silicon carbide (SiC) base substrate from the support substrate.

19. forming the polycrystalline silicon carbide (SiC) base substrate; Raising the temperature in a chamber of a HTCVD (High Temperature Chemical Vapor Deposition) furnace in which the support substrate is stored to at least one of a temperature between 2000 and 2500 degrees Celsius (°C), a temperature equal to 2000 degrees Celsius (°C), and a temperature of 2500 degrees Celsius (°C); 20. The method of claim 18, comprising: introducing a silane source gas and an ethene source gas into a chamber for growing the polycrystalline silicon carbide (SiC) base substrate on the support substrate.

20. forming the polycrystalline silicon carbide (SiC) base substrate; Raising the temperature in a chamber of a CVD (Chemical Vapor Deposition) furnace in which the support substrate is stored to at least one of a temperature between 1250 and 1350 degrees Celsius (°C), a temperature equal to 1250 degrees Celsius (°C), and a temperature equal to 1350 degrees Celsius (°C); 20. The method of claim 18, comprising: introducing a silane source gas and an ethene source gas into a chamber for growing the polycrystalline silicon carbide (SiC) base substrate on the support substrate.

21. The device of claim 1 , wherein the polycrystalline silicon carbide (SiC) base substrate has a resistivity of 1×10^7 ohm-cm or greater.

22. The device of claim 1 , wherein the polycrystalline silicon carbide (SiC) base substrate has a resistivity of 1×10^8 ohm-cm or greater.

23. The device of claim 1 , wherein the polycrystalline silicon carbide (SiC) base substrate has a purity of 98% or greater.

24. 10. The device of claim 1, wherein the polycrystalline silicon carbide (SiC) base substrate has a density in the range of 3.14 grams per cm^3 (g / cm^3) to 3.21 grams per cm^3 (g / cm^3), or equal to the upper and lower ends of this range.

25. 10. The device of claim 1, wherein the polycrystalline silicon carbide (SiC) base substrate has a density of 3.19 grams / cm^3 (g / cm^3) or greater.

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