Semiconductor device and manufacturing method thereof

Abstract

To make an insulating film thickness on a conductor in a coarse and dense region uniform without making a conductor pattern disappearing after CMP processing even when the conductor pattern is arranged in a dense region with a narrow line width that is isolated from the surrounding area.SOLUTION: A semiconductor device includes, on a substrate, a dense region in which elements and a plurality of first conductors formed with a first inter-conductor spacing are formed, a coarse region in which isolated second conductors are formed or at least one second conductor formed with a second inter-conductor spacing wider than the first inter-conductor spacing is formed, and an insulating film covering the dense region and the coarse region. A method for manufacturing the semiconductor device includes the steps of: etching a part of the insulating film on the dense region to form a first convex portion of the insulating film on the dense region and form a second convex portion of the insulating film on the coarse region; and planarizing a plane of the insulating film including the first convex portion and the second convex portion.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] For example, CMP (Chemical Mechanical Polishing) is commonly used as a method for planarizing an insulating film formed on metal wiring in semiconductor devices such as solid-state imaging devices equipped with image sensors, which are photoelectric conversion elements. In CMP, a slurry (abrasive) is applied to a polishing pad, and the insulating film is polished by pressing the wafer surface against the polishing pad and rotating it.

[0003] Fig. 23 is a schematic cross-sectional view showing an example of pattern shape dependence in a semiconductor device according to a conventional example before CMP processing, and Fig. 24 is a schematic cross-sectional view showing an example of pattern shape dependence in the semiconductor device of Fig. 23 after CMP processing. Also, Fig. 25 is a schematic cross-sectional view showing an example of the mechanism by which pattern shape dependence occurs in the semiconductor device of Fig. 23.

[0004] In FIG. 23, a photoelectric conversion element 11 is formed on a semiconductor substrate 10, e.g., a Si substrate, and then wiring conductors 13 and 14 are formed. After that, an insulating film 12 is formed. Then, as shown in FIG. 25, the surface of the formed semiconductor device is polished while being pressed against a polishing pad 15 with a stress F. Here, recesses 51 and 52 are formed in the insulating film 12 along the patterns of the conductors 13 and 14. Because the polishing pad 15 is somewhat soft, the convex portions of the patterns strongly contact the polishing pad 15. As a result, the convex portions of the patterns are preferentially polished, and planarization progresses. Therefore, in a manufacturing method using the CMP method, the thickness of the film varies depending on the pattern shape. Depending on the density of the metal wiring pattern, differences in film thickness occur between flat portions 53 and 54 within the semiconductor chip. Note that in FIGS. 23 to 25, 1 denotes a dense region where the conductors 13 are densely packed and the spacing between the conductors 13 is narrower than a predetermined value. 2 denotes a sparse region where the conductors 14 are not densely packed but isolated and the spacing between the conductors 14 is wider than a predetermined value. That is, the spacing between the conductors 13 is narrower than the spacing between the conductors 14.

[0005] Here, if the insulating film 12 becomes too thin and the conductors 13 and 14 are exposed, there is a risk that the conductors 13 and 14 will be lost due to chemicals in the cleaning process after the CMP process, so the insulating film 12 needs to have a certain thickness. On the other hand, if the insulating film 12 becomes too thick, it will be difficult to etch the through-holes in the contact formation process after the CMP process.

[0006] For example, Figure 4 of Patent Document 1 discloses an example of a typical dummy metal arrangement, and Figure 1 of Patent Document 1 discloses an example of a dummy metal arrangement when a photoelectric conversion element is present in a coarse region. Conventionally, as a method for uniforming the insulating film thickness on the conductor of metal wiring, dummy metal is arranged in the coarse region of the conductor pattern to reduce the difference in density. However, when a photoelectric conversion element such as a light receiving element is present in the coarse region, the insulating film thickness on the metal wiring is uniformed by arranging dummy metal on the insulating film and then covering it with an insulating film.

[0007] 1 and 2 of Patent Document 2 disclose an example in which dummy metal is not arranged. In this example, for a structure in which an optical black (light-shielding pattern) region exists in a peripheral circuit region outside the imaging region where photoelectric conversion elements exist, a resist is used to prevent etching of the pattern on the imaging region and to etch part of the insulating film on the optical black, and then the insulating film is planarized by CMP processing. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Patent No. 4961232 [Patent Document 2] Patent No. 5704811 Summary of the Invention [Problem to be solved by the invention]

[0009] The method of placing dummy metal on the insulating film covering the photoelectric conversion element portion as described above and planarizing the insulating film covering the metal pattern can avoid the problem of large differences in insulating film thickness between sparse and dense regions, but it requires an additional process step of selectively removing the dummy metal and the insulating film above the photoelectric conversion element portion, resulting in an increase in manufacturing costs.

[0010] In addition, in a method in which dummy metal is not placed, but resist is used on a dense region where peripheral circuits exist outside a sparse region where photoelectric conversion elements exist, so that the pattern on the sparse region is not etched and part of the insulating film on the dense region is etched, and then the insulating film is planarized by CMP processing, there is a problem that the line width of the metal wiring in the dense region is narrow, and the insulating film on the pattern isolated from the periphery does not have resist because it is a dense region, so it is etched in the etching process, and in the subsequent process of planarizing the insulating film by CMP processing, the metal wiring of the pattern isolated from the periphery because of its narrow line width disappears.

[0011] The object of the present invention is to solve the above problems and to provide a method for manufacturing a semiconductor device that can make the insulating film thickness on the conductor wiring in the sparsely-dense region uniform, even when the line width in the dense region is narrow and the conductor pattern is isolated from the surrounding area, without disappearing after CMP processing, and to provide the semiconductor device. [Means for solving the problem]

[0012] A method for manufacturing a semiconductor device according to one aspect of the present invention includes: a dense region on a substrate in which elements and a plurality of first conductors are formed at first inter-conductor intervals; a rough region on the substrate in which isolated second conductors are formed or in which at least one second conductor is formed with a second conductor spacing wider than the first conductor spacing; a method for manufacturing a semiconductor device having an insulating film covering the dense region and the sparse region, the method comprising: forming a first convex portion of the insulating film on the dense region by etching a part of the insulating film on the dense region and forming a second convex portion of the insulating film on the sparse region; Next, a step of planarizing the surface of the insulating film including the first convex portion and the second convex portion; Includes. [Effects of the Invention]

[0013] Therefore, in the method for manufacturing a semiconductor device according to the present invention, a first convex portion of the insulating film is formed on the dense region by etching a part of the insulating film on the dense region, a second convex portion of the insulating film is formed on the sparse region, and then the plane of the insulating film including the first convex portion and the second convex portion is planarized. As a result, the insulating film is not etched in the etching process, the conductor is not lost when the insulating film is planarized in the subsequent CMP process, and the insulating film thickness on the conductor wiring in the sparse region can be made uniform. [Brief explanation of the drawings]

[0014] [Figure 1] 1A is a plan view showing a first step in an example of a manufacturing process for a semiconductor device according to embodiment 1, and FIG. 1B is a schematic cross-sectional view taken along line AA' in FIG. 1A. [Figure 2] 2 is a schematic cross-sectional view showing a second step of the semiconductor device of FIG. 1. FIG. [Figure 3] 1. FIG. 4 is a schematic cross-sectional view showing a third step of the semiconductor device of FIG. [Figure 4] 1. FIG. 4 is a schematic cross-sectional view showing a fourth step of the semiconductor device of FIG. [Figure 5] 1. FIG. 4 is a schematic cross-sectional view showing a fifth step of the semiconductor device of FIG. [Figure 6] 1. FIG. 4 is a schematic cross-sectional view showing a sixth step of the semiconductor device of FIG. [Figure 7] 1. FIG. 4 is a schematic cross-sectional view showing a seventh step of the semiconductor device of FIG. [Figure 8] 10A and 10B are schematic cross-sectional views showing an example of a manufacturing process for a semiconductor device according to Modification 1, illustrating a step before a CMP process. [Figure 9] 9 is a schematic cross-sectional view showing a step after the CMP process of the semiconductor device of FIG. 8. [Figure 10] 10 is a schematic cross-sectional view showing an example of a manufacturing process for a semiconductor device according to Modification 2, illustrating a step before a CMP process. [Figure 11] 11 is a schematic cross-sectional view showing a step after the CMP process of the semiconductor device of FIG. 10. [Figure 12] 10A to 10C are schematic cross-sectional views showing an example of a manufacturing process for a semiconductor device according to Modification 3. [Figure 13] 10A is a plan view showing a first step in an example of a manufacturing process for a semiconductor device according to embodiment 2, and FIG. 10B is a schematic cross-sectional view taken along line BB' in FIG. 10A. [Figure 14] 10A is a plan view showing a first step in an example of a manufacturing process for a semiconductor device according to embodiment 3, and FIG. 10B is a schematic cross-sectional view taken along line CC' in FIG. [Figure 15] 10A is a plan view showing a first step of an example of a manufacturing process for a semiconductor device according to Modification 4, and FIG. 10B is a schematic cross-sectional view taken along line DD′ of FIG. 10A. [Figure 16] 10(A) is an example of a manufacturing process for a semiconductor device according to Modification 5, and is a plan view showing a first step, and FIG. 10(B) is a schematic cross-sectional view taken along line EE' of FIG. 10(A). [Figure 17] 10(A) is an example of a manufacturing process for a semiconductor device according to Modification 6, and is a plan view showing a first step, and FIG. 10(B) is a schematic cross-sectional view taken along line FF' in FIG. [Figure 18] 10(A) is an example of a manufacturing process for a semiconductor device according to Modification 7, and is a plan view showing a first step, and FIG. 10(B) is a schematic cross-sectional view taken along line GG' in FIG. [Figure 19] 13A is a plan view showing a first step of an example of a manufacturing process for a semiconductor device according to Modification 8, and FIG. 13B is a schematic cross-sectional view taken along line HH′ in FIG. 13A. [Figure 20]13A is a plan view showing a first step of an example of a manufacturing process for a semiconductor device according to Modification 9, and FIG. 13B is a schematic cross-sectional view taken along line II' of FIG. 13A. [Figure 21] 20(A) is a plan view showing a modified example of the manufacturing process for the semiconductor device of FIG. 20(A), and FIG. 20(B) is a schematic cross-sectional view taken along line II' of FIG. 20(A). [Figure 22] 13A is a plan view showing a first step of an example of a manufacturing process for a semiconductor device according to Modification 10, and FIG. 13B is a schematic cross-sectional view taken along line JJ′ in FIG. [Figure 23] FIG. 10 is a schematic cross-sectional view showing an example of pattern shape dependency in a semiconductor device according to a conventional example before CMP processing. [Figure 24] 24 is a schematic cross-sectional view showing an example of pattern shape dependency in the semiconductor device of FIG. 23 after CMP processing. [Figure 25] 24 is a schematic cross-sectional view showing an example of a mechanism by which pattern shape dependency occurs in the semiconductor device of FIG. 23. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments and modifications of the present invention will be described with reference to the drawings. The same or similar components are denoted by the same reference numerals. In the following embodiments and modifications, a semiconductor device that is a solid-state imaging device including an imaging element such as a photoelectric conversion element will be described. However, the present invention is not limited to this and can be widely applied to semiconductor devices including semiconductor elements and conductors.

[0016] (Embodiment 1) Fig. 1(A) is a plan view showing a first step of an example of a manufacturing process for a semiconductor device according to embodiment 1, and Fig. 1(B) is a schematic cross-sectional view taken along line A-A' in (A). Figs. 2 to 7 are schematic cross-sectional views showing second to seventh steps of the semiconductor device of Fig. 1. For ease of illustration, in the schematic cross-sectional views of the present application, lines of components that would normally be visible when looking to the other side along the cross-sectional line have been omitted (particularly in the conductor pattern reversal mask 20).

[0017] 1A and 1B, photoelectric conversion elements 11 are formed on a semiconductor substrate 10, such as a Si substrate. Wiring conductors 13 and 14 are then formed using a conductor mask pattern (not shown). Then, an insulating film 12, such as SiO2, is formed to cover the photoelectric conversion elements 11 and a circuit portion formed by wiring conductors 13 and 14 made of metal, such as Cu or Al. As described above, recesses 22 are formed in dense regions 1 where the conductors 13 are densely packed, and recesses 21 are formed in sparse regions 2 where the conductors 14 are not densely packed and are isolated. That is, the photoelectric conversion elements 11 are disposed in regions where the metal wiring of the conductors 14 is sparse, and the insulating film 12 on the photoelectric conversion elements 11 has a recess 21 that is thinner than the surrounding area. Meanwhile, a conductor pattern in which the metal wiring of the conductors 13 is isolated is disposed in the dense region 1, and the insulating film 12 on the isolated conductor pattern has a recess 22 that is thinner than the surrounding area.

[0018] 2, a pattern of resist 16 is formed on each of the insulating film 12 in the dense region 1 and the sparse region 2, and then, as shown in FIG. 3, exposure 60 is performed from the upper surface of the device using a conductor pattern inversion mask 20 having mask holes 20h by photolithography, thereby forming resist patterns that will serve as masks for subsequent etching in the dense region 1 and the sparse region 2. As a result, the resist 16 becomes resists 16B and 16A that are separated from each other on the insulating film 12 in the dense region 1 and the sparse region 2, respectively, as shown in FIG.

[0019] Next, the insulating film 12 is etched using the resists 16B and 16A as masks. As shown in FIG. 5, an etched portion 30 is formed in the insulating film 12 on the wide conductor 13, a convex portion 32 is formed on the insulating film 12 between the concave portion 22 and the etched portion 30 on the narrow conductor 13, and a convex portion 31 is formed on the insulating film 12 around the concave portion 21 where the insulating film 12 is thick. The resists 16A and 16B are then removed, resulting in the shape shown in FIG. 6. As shown in FIG. 25, a slurry (abrasive) is applied to a polishing pad by CMP, and the surface of the semiconductor device is pressed against the polishing pad and rotated to polish the insulating film 12. This forms a flat portion 42 in the dense region 1 and a flat portion 41 in the sparse region 2. As is clear from FIG. 7, the CMP method results in the insulating film 12 on the photoelectric conversion element 11 (sparse region 2) being thinner than the insulating film 12 on the dense region 1 of the conductor 13.

[0020] As described above, by etching a portion of the insulating film 12 in the sparse region 2 other than the dense region 1, the polishing pad makes strong contact with the convex portions 31 and 32 during the CMP process, so that they are preferentially polished, and planarization to the flat portion 41 progresses.

[0021] According to this embodiment, there is a dense region 1, which is a region where the conductors 13 of the metal wiring are densely packed, and a sparse region 2, which is a sparse region where the conductors 14 of the metal wiring are not densely packed and are isolated.Even if a photoelectric conversion element 11 is arranged in the sparse region 2, no dummy pattern is arranged, and even if an isolated pattern of the conductors 14 in the sparse region 2 exists, the conductors 14 of the metal wiring are not lost, and the thickness of the insulating film 12 on the metal wiring can be made uniform.

[0022] (Variation 1) Fig. 8 is a schematic cross-sectional view showing an example of a manufacturing process for a semiconductor device according to Modification 1, illustrating a process before CMP processing, and Fig. 9 is a schematic cross-sectional view showing a process after CMP processing of the semiconductor device of Fig. 8. Here, Fig. 8 corresponds to the process diagram of Fig. 6 of Embodiment 1, and Fig. 9 corresponds to the process diagram of Fig. 7 of Embodiment 1.

[0023] 8, the height of the conductors 13 and 14 from the upper surface (hereinafter referred to as the "substrate surface") 10s of the semiconductor substrate 10 is d13. Here, the height d22 of the insulating film 12 at the bottom of the recess 22 from the substrate surface 10s is higher than, for example, the height d21 of the insulating film 12 at the bottom of the recess 21 from the substrate surface 10s, and both heights d21 and d22 are higher than the height d13 of the conductors 13 and 14 from the substrate surface 10s. In Modification 1, by polishing down to below the bottoms of the recesses 21 and 22 during the CMP process of FIG. 9, the insulating film 12 can be flattened without leaving the recesses 21 and 22, and flat portions 41 and 42 can be formed. In this application, the height of the insulating film 12 from the substrate surface 10s corresponds to the film thickness of the insulating film 12.

[0024] (Variation 2) Fig. 10 is a schematic cross-sectional view showing an example of a manufacturing process for a semiconductor device according to Modification 2, illustrating a process before CMP processing, and Fig. 11 is a schematic cross-sectional view showing a process after CMP processing of the semiconductor device of Fig. 10. Here, Fig. 10 corresponds to the process diagram of Fig. 6 of Embodiment 1, and Fig. 11 corresponds to the process diagram of Fig. 7 of Embodiment 1.

[0025] 10, the height d30 of the bottom of etched portion 30 formed by partial etching from substrate surface 10s is greater than, for example, height d21 of the bottom of recess 21 from substrate surface 10s. In Modification 2, by polishing down to below the bottoms of recesses 30 and 21 by the CMP process of FIG. 11, insulating film 12 in dense region 1 is polished before insulating film 12 in sparse region 2, preventing the insulating film 12 from reaching conductor 14 of the metal wiring. This CMP process can planarize insulating film 12 without leaving recesses 21 and 22, and form flat portions 41 and 42.

[0026] (Variation 3) 12 is a schematic cross-sectional view showing an example of a manufacturing process for a semiconductor device according to Modification 3. Here, FIG. 12 corresponds to the process diagram of FIG.

[0027] 12, the height d30 from the substrate surface 10s of the bottom of the etched portion 30 formed by partial etching is, for example, higher than the height d21 from the substrate surface 10s of the bottom of the recess 21, and is also higher than the height d22 from the substrate surface 10s of the bottom of the recess 22. By performing the CMP process down to below the bottoms of the recesses 30, 22, and 21, the bottom of the recess 21 is not left behind, and the insulating film 12 can be reliably planarized by the CMP process.

[0028] (Embodiment 2) FIG. 13(A) is a plan view showing a first step of a manufacturing process for a semiconductor device according to embodiment 2, and FIG. 13(B) is a schematic cross-sectional view taken along line B-B' in FIG. 13(A). FIG. 13(A) corresponds to a top view of the process shown in FIG. 3 of embodiment 1, and FIG. 13(B) corresponds to a schematic cross-sectional view of FIG. 3. In FIG. 13(A), the dashed-dotted lines of conductors 13 and 14 indicate the perspective positions when viewed from above the semiconductor device, and the dashed-dotted line 20h indicates the inner peripheral position of mask hole 20h in conductor pattern reversal mask 20 (the inner peripheral position of the mask hole exposed using lithography). The dashed-dotted lines 13 and 14 and the dashed-dotted line 20h have the same meanings in the following embodiments and modifications.

[0029] In FIG. 13, a conductor pattern reversal mask 20 is formed on the insulating film 12 on the conductors 13 and 14 of the metal wiring in the dense region 1 other than the sparse region 2, so that resist 16 is disposed inward from the outer periphery of the conductors 13 and 14 with an equal overlap width wo (FIG. 13(A)). Further inward, a conductor pattern reversal mask 20 is formed so that resist 16 is not disposed. This masks the insulating film 12 for etching, while the conductor region of the thin, isolated metal wiring is masked by the conductor pattern reversal mask 20, so that resist 16 is disposed in the conductor region, preventing etching of the insulating film on the thin, isolated metal wiring. These are referred to as the "etching conditions of the second embodiment." Here, the conductor width of the thin, isolated metal wiring that is not etched is, for example, approximately three times the overlap width wo or less. For example, when the width of the conductors 13 and 14 is 6 μm, the overlap width wo is 2 μm.

[0030] As described above, according to this embodiment, it is possible to prevent the etching portion 30 from protruding from the conductors 13 and 14 of the metal wiring due to dimensional variations in the conductor pattern reversal mask 20.

[0031] (Embodiment 3) Fig. 14(A) is a plan view showing a first step of an example of a manufacturing process for a semiconductor device according to embodiment 3, and Fig. 14(B) is a schematic cross-sectional view taken along line CC' in Fig. 14(A). Fig. 14(A) corresponds to a top view of the step of Fig. 3 of embodiment 1, and Fig. 14(B) corresponds to a schematic cross-sectional view of Fig. 3.

[0032] In FIG. 14, when the overlap width wo is set to, for example, 2 μm, as shown in FIG. 14(A), the insulating film 12 on the conductor 13 of a thin isolated metal wiring having a predetermined width wm of, for example, 6 μm or less (for example, the central conductor of the three conductors 13 in FIG. 14(A)) is not etched. The above are referred to as the "etching conditions of the third embodiment."

[0033] As described above, according to this embodiment, it is possible to prevent the etching portion 30 from protruding from the conductors 13 and 14 of the metal wiring due to dimensional variations in the conductor pattern reversal mask 20.

[0034] (Variation 4) Fig. 15(A) is a plan view showing a first step as an example of a manufacturing process for a semiconductor device according to Modification 4, and Fig. 15(B) is a schematic cross-sectional view taken along line D-D' in Fig. 15(A). Fig. 15(A) corresponds to a top view of the step of Fig. 3 of Embodiment 1, and Fig. 15(B) corresponds to a schematic cross-sectional view of Fig. 3. The semiconductor device in Fig. 15 differs from the semiconductor device in Fig. 13 in the following respects.

[0035] (1) Of the three conductors 13 in the dense area 1, the right conductor 13 is not rectangular or strip-shaped, but has an L-shaped hexagonal shape, and has a conductor extension portion 13E extending parallel to the line D-D' perpendicular to the longitudinal direction of the conductor 13. (2) Here, the conductor extending portion 13E is subjected to a lithography process by applying the etching conditions of the second embodiment to form a conductor pattern reversal mask 20 having mask holes 20h with a predetermined width.

[0036] As described above, according to the fourth modification, similar to the second embodiment, it is possible to prevent the etching portion 30 from protruding from the conductor 13 of the metal wiring due to dimensional variations in the conductor pattern reversal mask 20.

[0037] (Variation 5) Fig. 16(A) is a plan view showing a first step of an example of a manufacturing process for a semiconductor device according to Modification 5, and Fig. 16(B) is a schematic cross-sectional view taken along line E-E' in Fig. 16(A). Fig. 16(A) corresponds to a top view of the step of Fig. 3 of Embodiment 1, and Fig. 16(B) corresponds to a schematic cross-sectional view of Fig. 3. The semiconductor device in Fig. 16 differs from the semiconductor device in Fig. 14 in the following respects.

[0038] (1) Of the three conductors 13 in the dense area 1, the right conductor 13 is not rectangular or strip-shaped, but has an L-shaped hexagonal shape, and has a conductor extension portion 13E extending parallel to the E-E' line perpendicular to the longitudinal direction of the conductor 13. (2) Here, the conductor extending portion 13E is subjected to a lithography process by applying the etching conditions of the third embodiment to form a conductor pattern reversal mask 20 having mask holes 20h with a predetermined width.

[0039] As described above, according to the fifth modification, similarly to the third embodiment, it is possible to prevent the etching portion 30 from protruding from the conductors 13 and 14 of the metal wiring due to dimensional variations in the conductor pattern reversal mask 20.

[0040] (Variation 6) Fig. 17(A) is a plan view showing a first step of an example of a manufacturing process for a semiconductor device according to Modification 6, and Fig. 17(B) is a schematic cross-sectional view taken along line F-F' in Fig. 17(A). Fig. 17(A) corresponds to a top view of the step of Fig. 3 of Embodiment 1, and Fig. 17(B) corresponds to a schematic cross-sectional view of Fig. 3. The semiconductor device in Fig. 17 differs from the semiconductor device in Fig. 13 in the following respects.

[0041] (1) Instead of the three conductors 13 in the dense region 1, two conductor portions are joined at the edge by a conductor joining portion 13C in a U-shape, and the conductor joining portion 13C extends parallel to the line F-F' perpendicular to the longitudinal direction of the conductor 13. (2) Here, the conductor coupling portion 13C is subjected to a lithography process by applying the etching conditions of the second embodiment to form a conductor pattern reversal mask 20 having mask holes 20h with a predetermined width.

[0042] As described above, according to the sixth modification, similar to the second embodiment, it is possible to prevent the etching portion 30 from protruding from the conductor 13 of the metal wiring due to dimensional variations in the conductor pattern reversal mask 20.

[0043] (Variation 7) Fig. 18(A) is a plan view showing a first step of an example of a manufacturing process for a semiconductor device according to Modification 7, and Fig. 18(B) is a schematic cross-sectional view taken along line G-G' in Fig. 18(A). Fig. 18(A) corresponds to a top view of the step of Fig. 3 of Embodiment 1, and Fig. 18(B) corresponds to a schematic cross-sectional view of Fig. 3. The semiconductor device in Fig. 18 differs from the semiconductor device in Fig. 14 in the following respects.

[0044] (1) Instead of the three conductors 13 in the dense region 1, two conductor portions are connected at the edge by a conductor connecting portion 13C in a U-shape, and the conductor connecting portion 13C extends parallel to the line G-G' which is perpendicular to the longitudinal direction of the conductor 13. (2) Here, the conductor coupling portion 13C is subjected to a lithography process by applying the etching conditions of the third embodiment to form a conductor pattern reversal mask 20 having mask holes 20h with a predetermined width.

[0045] As described above, according to the seventh modification, similar to the third embodiment, it is possible to prevent the etching portion 30 from protruding from the conductors 13 and 14 of the metal wiring due to dimensional variations in the conductor pattern reversal mask 20.

[0046] (Variation 8) Fig. 19(A) is a plan view showing a first step as an example of a manufacturing process for a semiconductor device according to Modification 8, and Fig. 19(B) is a schematic cross-sectional view taken along line H-H' in Fig. 19(A). Fig. 19(A) corresponds to a top view of the step of Fig. 3 of Embodiment 1, and Fig. 19(B) corresponds to a schematic cross-sectional view of Fig. 3. The semiconductor device in Fig. 19 differs from the semiconductor device in Fig. 13 in the following respects.

[0047] (1) In place of the rightmost conductor 13 of the three conductors 13 in the dense region 1, three narrow conductors 13a are formed, and the conductors 13a are formed so as to be parallel to the longitudinal direction of the conductors 13 (the direction perpendicular to the H-H' line). (2) Here, the conductor 13a is subjected to a lithography process by applying the etching conditions of the second embodiment to form a conductor pattern reversal mask 20 having mask holes 20h with a predetermined width.

[0048] As described above, according to the eighth modification, similar to the second embodiment, it is possible to prevent the etching portion 30 from protruding from the conductor 13 of the metal wiring due to dimensional variations in the conductor pattern reversal mask 20.

[0049] (Variation 9) Fig. 20(A) is a plan view showing a first step of an example of a manufacturing process for a semiconductor device according to Modification 9, and Fig. 20(B) is a schematic cross-sectional view taken along line II' in Fig. 20(A). Fig. 20(A) corresponds to a top view of the step of Fig. 3 of Embodiment 1, and Fig. 20(B) corresponds to a schematic cross-sectional view of Fig. 3. The semiconductor device in Fig. 20 differs from the semiconductor device in Fig. 14 in the following respects.

[0050] (1) In place of the rightmost conductor 13 of the three conductors 13 in the dense region 1, three narrow conductors 13a are formed, and the conductors 13a are formed so as to be parallel to the longitudinal direction of the conductors 13 (the direction perpendicular to line I-I'). (2) Here, when the spacing wn between a pair of adjacent conductors 13a among the three conductors 13a is narrower than the overlap width wo, a collective virtual conductor region 13P is set that includes the area of ​​the three conductors 13a and is expanded by adding a predetermined additional width wp in the width direction on both sides, and the etching conditions of embodiment 2 are applied to the collective virtual conductor region 13P to form a conductor pattern inversion mask 20 having a mask hole 20h with a predetermined width, and a lithography process is performed. Here, Figure 20 is one example, and other embodiments can be implemented by setting the additional width wp. For example, as shown in Figure 21, which shows a modified example, the inner end face of the conductor pattern inversion mask 20 can be positioned inside the conductors 13a.

[0051] As described above, according to variant example 9, when the spacing wn between the conductors 13a is narrower than the overlap width wo, a collective virtual conductor area 13P is set, and the etching conditions of embodiment 2 are applied to the collective virtual conductor area 13P, thereby preventing the etching portion 30 from extending beyond the conductors 13, 14 of the metal wiring due to dimensional variations in the conductor pattern inversion mask 20, as in embodiment 2.

[0052] (Variation 10) Fig. 22(A) is a plan view showing a first step of an example of a manufacturing process for a semiconductor device according to Modification 10, and Fig. 22(B) is a schematic cross-sectional view taken along line J-J' in Fig. 22(A). Fig. 22(A) corresponds to a top view of the step of Fig. 3 of Embodiment 1, and Fig. 22(B) corresponds to a schematic cross-sectional view of Fig. 3. The semiconductor device in Fig. 22 differs from the semiconductor device in Fig. 20 in the following respects.

[0053] (1) Above the formation position of the three narrow conductors 13a in Figure 22(A), the wide conductor 13b was formed at a narrow interval wn from the three conductors 13a, extending longitudinally (perpendicular to line J-J') from the three narrow conductors 13a. (2) Here, when there are three narrow conductors 13a and one wide conductor 13b, and the spacing wn between adjacent pairs of the three conductors 13a and 13b is narrower than the overlap width wo, a collective virtual conductor region 13P is set that includes the areas of the three conductors 13a and the area of ​​the conductor 13b and is expanded by adding a predetermined additional width wp in the width direction on both sides, and the etching conditions of embodiment 2 are applied to the collective virtual conductor region 13P to form a conductor pattern inversion mask 20 having a mask hole 20h of a predetermined width, and a lithography process is performed.

[0054] As described above, according to variant example 10, when the spacing wn between conductors 13a and between conductors 13a and 13b is narrower than the overlap width wo, a collective virtual conductor area 13P is set, and the etching conditions of embodiment 2 are applied to the collective virtual conductor area 13P, thereby preventing the etching portion 30 from extending beyond the conductors 13 and 14 of the metal wiring due to dimensional variations in the conductor pattern inversion mask 20, as in embodiment 2.

[0055] (Another variation) In the above embodiment and modified examples, a semiconductor substrate 10 is used, but the present invention is not limited to this, and a substrate such as a dielectric substrate may also be used.

[0056] In the above embodiment and modified examples, an imaging element such as the photoelectric conversion element 11 is used, but the present invention is not limited to this, and a predetermined semiconductor element may also be used.

[0057] Furthermore, although the CMP method has been described as a planarization method, the present invention is not limited to this, and dry etching using a plasma reaction may also be used.

[0058] Furthermore, although the photolithography method has been described using a positive resist, the present invention is not limited to this, and a negative resist may also be used. [Industrial Applicability]

[0059] As described above, according to the semiconductor device manufacturing method of the present invention, a first convex portion of the insulating film is formed on the dense region by etching a portion of the insulating film on the dense region, a second convex portion of the insulating film is formed on the sparse region, and then the plane of the insulating film including the first convex portion and the second convex portion is planarized. This makes it possible to make the insulating film thickness on the conductor wiring in the sparse region uniform without losing the conductor even when the insulating film is planarized by the subsequent CMP process. [Explanation of symbols]

[0060] 1 dense area 2 Coarse area 10. Semiconductor substrate 10s Substrate surface (top surface of semiconductor substrate) 11 Photoelectric conversion element 12 insulating film 13, 13a, 13b, 14 Conductors 13C Conductor Joint 13E Conductor extension 13P Collective virtual conductor area 15 Polishing Pads 16, 16A, 16B Resist 20 Conductor pattern inversion mask 20h Mask Hole 21,22 Recess 30,30A Etching section 31,32 Convex part 41,42 Flat area 51,52 Recess 53.54 Flat area 60 Exposure

Claims

1. a dense region on a substrate in which elements and a plurality of first conductors are formed at first inter-conductor intervals; a rough region on the substrate in which isolated second conductors are formed or at least one second conductor is formed with a second conductor spacing wider than the first conductor spacing; a method for manufacturing a semiconductor device having an insulating film covering the dense region and the sparse region, the method comprising: forming a first convex portion of the insulating film on the dense region by etching a part of the insulating film on the dense region and forming a second convex portion of the insulating film on the sparse region; Next, a step of planarizing the surface of the insulating film including the first convex portion and the second convex portion; A method for manufacturing a semiconductor device comprising:

2. the insulating film in the dense region has a first recess; the insulating film in the rough region has a second recess; the insulating film in the second recess has a thickness smaller than the thickness of the insulating film in the first recess; The method for manufacturing a semiconductor device according to claim 1 .

3. a thickness of the insulating film in the second recess and a thickness of the insulating film in the first recess are greater than the thicknesses of the first conductor and the second conductor; The method for manufacturing a semiconductor device according to claim 2 .

4. the step of forming the first convex portion and the second convex portion includes forming an etched portion on the first conductor by etching a part of an insulating film on the dense region; the insulating film in the etched portion has a thickness greater than the insulating film in the second recessed portion; The method for manufacturing a semiconductor device according to claim 2 or 3.

5. the insulating film in the etched portion has a thickness greater than the insulating film in the first recess; The method for manufacturing a semiconductor device according to claim 4 .

6. the step of forming the first convex portion and the second convex portion includes etching a part of the insulating film on the dense region using a conductor pattern inversion mask having a predetermined overlap width inside each width and length in a longitudinal direction of the first conductor and the second conductor; The method for manufacturing a semiconductor device according to claim 1 or 2.

7. When the first conductor and the second conductor have a width or a length in a longitudinal direction that is smaller than a predetermined multiple of the overlap width, the conductor pattern inversion mask does not have the overlap width. The method for manufacturing a semiconductor device according to claim 6 .

8. the first conductor has a conductor extension portion extending in a direction perpendicular to a longitudinal direction of the first conductor, the step of forming the first convex portion and the second convex portion includes etching a part of the insulating film on the dense region using a conductor pattern inversion mask having the overlap width inside the width and longitudinal length of the conductor extension portion; The method for manufacturing a semiconductor device according to claim 6 .

9. When the conductor extension portion has a width or a length in the longitudinal direction that is smaller than a predetermined multiple of the overlap width, the conductor pattern inversion mask does not have the overlap width. The method for manufacturing a semiconductor device according to claim 8 .

10. the first conductor includes at least two conductor portions connected by a conductor connecting portion; the step of forming the first convex portion and the second convex portion includes etching a part of the insulating film on the dense region using a conductor pattern inversion mask having the overlap width inside a width of the conductor coupling portion; The method for manufacturing a semiconductor device according to claim 6 .

11. When the conductor coupling portion has a width or a length in a longitudinal direction that is smaller than a predetermined multiple of the overlap width, the conductor pattern inversion mask does not have the overlap width. The method for manufacturing a semiconductor device according to claim 10.

12. the first conductors include at least two first conductors; the step of forming the first convex portion and the second convex portion includes, when a distance between adjacent first conductors among the at least two first conductors is smaller than the overlap width, etching using a conductor pattern inversion mask formed by setting a collective virtual conductor region that is increased by adding a predetermined additional width to the regions of the at least two first conductors; The method for manufacturing a semiconductor device according to claim 6 .

13. the first conductors include at least two first conductors and another first conductor; the step of forming the first convex portion and the second convex portion includes, when a distance between adjacent first conductors among the at least two first conductors is smaller than the overlap width, increasing the distance by adding a predetermined additional width to the regions of the at least two first conductors, and etching using a conductor pattern inversion mask formed by setting a collective virtual conductor region including the region of another first conductor; The method for manufacturing a semiconductor device according to claim 6 .

14. a dense region on a substrate in which elements and a plurality of first conductors are formed at first inter-conductor intervals; a rough region on the substrate in which isolated second conductors are formed or at least one second conductor is formed with a second conductor spacing wider than the first conductor spacing; an insulating film covering the dense region and the sparse region, a first convex portion of the insulating film is formed on the dense region by etching a part of the insulating film on the dense region, and a second convex portion of the insulating film is formed on the sparse region; The semiconductor device is configured by planarizing the surface of the insulating film including the first convex portion and the second convex portion.

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