Printed circuit board

Abstract

This invention provides a printed circuit board that facilitates the formation of fine circuits by ensuring excellent flatness, has a coreless multilayer substrate structure, and enables cost reduction. [Solution] The present invention relates to a printed circuit board comprising a first insulator and a plurality of first wiring layers disposed on or inside the lower surface of the first insulator, wherein the uppermost of the plurality of first wiring layers is embedded in the upper side of the first insulator, and a portion of the upper surface of the uppermost first wiring layer is exposed from the upper surface of the first insulator; and a second wiring section comprising a second insulator disposed above the first wiring section and covering at least a portion of the upper surface of the uppermost first wiring layer, and a plurality of second wiring layers disposed on or inside the upper surface of the second insulator, wherein the minimum pitch of the wiring of the plurality of second wiring layers is smaller than the minimum pitch of the wiring of the remaining first wiring layers excluding the uppermost first wiring layer.

Description

Technical Field

[0001] The present invention relates to a printed circuit board.

Background Art

[0002] Due to the higher performance of semiconductor chips such as smartphone APs, server CPUs, and AI accelerators, the demand for package substrates including high-density circuits is increasing. Along with this, the bump pitch is decreasing, and multilayer and large-area configurations are required. In particular, in order to accommodate the increasing input / output terminals, the technology for realizing fine circuits is important.

Summary of the Invention

Problems to be Solved by the Invention

[0003] One of the various objects of the present invention is to provide a printed circuit board on which fine circuits can be easily formed by ensuring excellent flatness.

[0004] Another one of the various objects of the present invention is to provide a printed circuit board having a coreless multilayer substrate structure.

[0005] Yet another one of the various objects of the present invention is to provide a printed circuit board capable of cost reduction.

Means for Solving the Problems

[0006] One of the various solutions proposed in the present invention is to form a wiring layer including an ETS pattern on a detach core and an additional wiring layer, then detach the laminate, and further form a wiring layer including fine circuits on the flat surface on which the ETS pattern is formed, and form an additional wiring layer on the opposite side as needed to realize a coreless multilayer substrate.

[0007] For example, a printed circuit board according to one example includes a first insulator and a plurality of first wiring layers disposed on or inside the lower surface of the first insulator, wherein the uppermost of the plurality of first wiring layers is embedded on the upper side of the first insulator, and at least a portion of the upper surface of the uppermost first wiring layer is exposed from the upper surface of the first insulator, and a second wiring section includes a second insulator disposed above the first wiring section and covering at least a portion of the upper surface of the uppermost first wiring layer, and a plurality of second wiring layers disposed on or inside the upper surface of the second insulator, wherein the minimum pitch of the wiring included in at least one of the plurality of second wiring layers can be smaller than the minimum pitch of the wiring included in at least one of the remaining first wiring layers excluding the uppermost first wiring layer.

[0008] For example, a printed circuit board according to one example includes a plurality of first insulating layers, a plurality of first wiring layers, and a plurality of first via layers, wherein the uppermost first wiring layer among the plurality of first wiring layers is embedded above the uppermost first insulating layer among the plurality of first insulating layers, and at least a portion of the upper surface of the uppermost first wiring layer is exposed from the upper surface of the uppermost first insulating layer, and includes a second wiring section disposed above the first wiring section and including one or more second insulating layers, one or more second wiring layers, and one or more second via layers, wherein the first connecting vias included in each of the plurality of first via layers and the second connecting vias included in each of the one or more second via layers may have substantially tapered sides in opposite directions in cross-section. [Effects of the Invention]

[0009] One of the various effects of the present invention is the provision of a printed circuit board that facilitates the formation of fine circuits by ensuring excellent flatness.

[0010] As another of the various effects of the present invention, it is possible to provide a printed circuit board having a coreless multilayer substrate structure.

[0011] Another effect of the present invention, among its various advantages, is the provision of a printed circuit board that enables cost reduction. [Brief explanation of the drawing]

[0012] [Figure 1] This is a block diagram illustrating an example of an electronic equipment system. [Figure 2] This is a schematic cross-sectional view showing an example of a printed circuit board. [Figure 3] Figure 2 is a schematic cross-sectional view showing an example of the manufacturing process of a printed circuit board. [Figure 4] Figure 2 is a schematic cross-sectional view showing an example of the manufacturing process of a printed circuit board. [Modes for carrying out the invention]

[0013] The present invention will be described below with reference to the attached drawings. In the drawings, the shape and size of elements may be enlarged or reduced (or highlighted or simplified) for clearer explanation.

[0014] Figure 1 is a block diagram illustrating an example of an electronic equipment system.

[0015] Referring to the drawing, the electronic device 1000 houses the main board 1010. The main board 1010 is physically and / or electrically connected to chip-related components 1020, network-related components 1030, and other components 1040, etc. These, in combination with other electronic components described later, form various signal lines 1090.

[0016] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPUs), graphics processors (e.g., GPUs), digital signal processors, cryptographic processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). It goes without saying that these chip-related components 1020 may also be combined with each other. The chip-related components 1020 may also be in the form of a package containing the aforementioned chips and electronic components.

[0017] Network-related component 1030 includes, but is not limited to, any other wireless and wired protocols designated as Wi-Fi® (IEEE 802.11 family, etc.), WiMAX® (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth®, 3G, 4G, 5G, and later. It also goes without saying that network-related component 1030 may be combined with chip-related component 1020.

[0018] Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCCs (low-temperature co-firing ceramics), EMI (electromagnetic interference) filters, and MLCCs (multi-layer ceramic condensers). However, they are not limited to these, and may also include passive elements in chip component form used for various other applications. It goes without saying that other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030.

[0019] Depending on the type of electronic device 1000, it may include other electronic components that are or may not be physically and / or electrically connected to the main board 1010. Examples of other electronic components include, but are not limited to, audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage devices (e.g., hard disk drives), CDs (compact disks), DVDs (digital versatile disks), etc. It goes without saying that other electronic components used for various purposes may also be included, depending on the type of electronic device 1000.

[0020] The electronic device 1000 can be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, a server, etc. However, it is not limited thereto, and it goes without saying that any other electronic device that processes data may also be used.

[0021] FIG. 2 is a cross-sectional view schematically showing an example of a printed circuit board.

[0022] Referring to the drawings, a printed circuit board 100 according to an example can include a first wiring portion 110 and a second wiring portion 120 disposed above the first wiring portion 110. The first wiring portion 110 can include a first insulator 115 and a plurality of first wiring layers 112 respectively disposed on or within the lower surface of the first insulator 115. The uppermost first wiring layer M1 among the plurality of first wiring layers 112 can be embedded above the first insulator 115, and at least a part of the upper surface of the uppermost first wiring layer M1 can be exposed from the upper surface of the first insulator 115. For example, the uppermost first wiring layer M1 can be an ETS (Embedded Trace Substrate) pattern. The second wiring portion 120 can include a second insulator 125 covering at least a part of the upper surface of the uppermost first wiring layer M1 and a plurality of second wiring layers 122 respectively disposed on or within the upper surface of the second insulator 125. The second wiring portion 120 can include a wiring region with a relatively higher density than the first wiring portion 110, excluding the uppermost first wiring layer M1.

[0023] As described above, in the printed circuit board 100 according to one example, the uppermost first wiring layer M1 of the first wiring portion 110 can form a fine circuit and can be an ETS pattern layer having excellent flatness. Therefore, the second wiring portion 120 formed thereon can be formed with high density. For example, a fine circuit can be easily formed in the second wiring portion 120. For example, the plurality of second wiring layers 122 included in the second wiring portion 120 can be used as a 2.1D RDL (Redistribution Layer) for connecting a chip and a substrate. Further, when forming the second wiring portion 120, build-up can be further performed below the first wiring portion 110. Therefore, build-up on both sides becomes possible. Such a structure can be manufactured in a coreless form. For example, the first and second wiring portions 110 and 120 can each have a coreless substrate structure. Therefore, the number of layers can be reduced to reduce the thickness of the entire package, and it can easily cope with high multi-layerization and large area. Therefore, by enabling die-to-die connection at the substrate level, the process difficulty, cost, etc. can be reduced.

[0024] For example, the minimum pitch P2 of the wiring included in at least one of the plurality of second wiring layers 122 may be smaller than the minimum pitch P1 of the wiring included in at least one of the remaining first wiring layers 112 excluding the first wiring layer M1 disposed on the uppermost side. For example, the minimum pitch P2 of the wiring included in each of the plurality of second wiring layers 122 may be smaller than the minimum pitch P1 of the wiring included in each of the remaining first wiring layers 112. Further, the minimum pitch P3 of the wiring included in the first wiring layer M1 disposed on the uppermost side may be smaller than the minimum pitch P1 of the wiring included in each of the remaining first wiring layers 112. On the other hand, the pitch can be the distance between the center lines between adjacent wirings, and the wiring can be a line, a trace, etc.

[0025] Furthermore, the minimum line width L2 and minimum spacing S2 of the wiring included in at least one of the multiple second wiring layers 122 may be smaller than the minimum line width L1 and minimum spacing S1 of the wiring included in at least one of the remaining first wiring layers 112. For example, the minimum line width L2 and minimum spacing S2 of the wiring included in each of the multiple second wiring layers 122 may be smaller than the minimum line width L1 and minimum spacing S1 of the wiring included in each of the remaining first wiring layers 112. Also, the minimum line width L3 and minimum spacing S3 of the wiring included in the uppermost first wiring layer M1 may be smaller than the minimum line width L1 and minimum spacing S1 of the wiring included in each of the remaining first wiring layers 112. On the other hand, the line width and spacing may be L (line) / S (space), and the wiring can be lines, traces, etc.

[0026] Furthermore, the minimum insulation distance between multiple second wiring layers 122 may be smaller than the minimum insulation distance between multiple first wiring layers 112, and the thickness of the second insulator 125 may be thinner than the thickness of the first insulator 115.

[0027] On the other hand, the first wiring section 110 may further include a plurality of first via layers 113, each disposed within the first insulator 115, which electrically connect a plurality of first wiring layers 112 to one another. The second wiring section 120 may further include a plurality of second via layers 123, each disposed within the second insulator 125, which electrically connect a plurality of second wiring layers 122 to one another. The lowest second via layer 123 among the plurality of second via layers 123 can electrically connect the lowest second wiring layer 122 among the plurality of second wiring layers 122 to the uppermost first wiring layer M1. The first and second connecting vias included in each of the plurality of first and second via layers 113, 123 may have substantially tapered sides in a cross-section in opposite directions to one another. For example, the first connecting vias included in each of the plurality of first via layers 113 may have substantially tapered sides in a cross-section such that the width of the lower end is wider than the width of the upper end. Furthermore, each of the multiple second via layers 123 may have substantially tapered sides such that the width of the upper end is wider than the width of the lower end in cross-section. For example, in the first and second wiring sections 110 and 120 of the structure described above, the multiple first and second via layers 113 and 123 may have such a tapered structure.

[0028] On the other hand, a first passivation layer 161 can be placed on the lower surface of the first insulator 115, having a plurality of first openings h1 that each expose at least a portion of the lowest first wiring layer 112 among a plurality of first wiring layers 112. Also, a second passivation layer 162 can be placed on the upper surface of the second insulator 125, having any of the second openings h2 that expose at least a portion of the uppermost second wiring layer 122 among a plurality of second wiring layers 122. Each of the plurality of first openings h1 can expose at least a portion of each of the plurality of wiring patterns included in the lowest first wiring layer 112. The second openings h2 can both expose at least a portion of each of the plurality of wiring patterns included in the uppermost second wiring layer 122. For example, solder balls or the like can be placed on each of the wiring patterns exposed through the plurality of first openings h1, and the printed circuit board 100 can be mounted on another board such as a main board via these. Furthermore, solder bumps and the like can be placed on the wiring patterns exposed through the second opening h2, and electronic components such as semiconductor chips can be mounted on the printed circuit board 100 via these.

[0029] In the following section, the components of an example printed circuit board 100 will be described in more detail with reference to the drawings.

[0030] The first and second insulators 115 and 125 may each include an organic insulating material. The organic insulating material may be a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or may include inorganic fillers, organic fillers and / or glass fibers together with these insulating resins. For example, the first and second insulators 115 and 125 may include, but are not limited to, an insulating material containing an insulating resin and an inorganic filler, such as Ajinomoto Build-Up Film (ABF), and may also include a photosensitive insulating material (PID). The first and second insulators 115 and 125 may each include a plurality of first and second insulating layers 111 and 121. The plurality of first insulating layers 111 may be separated from each other by boundaries or may be integrated with each other without boundaries. The plurality of second insulating layers 121 may be separated from each other by boundaries or may be integrated with each other without boundaries. If necessary, the second insulator 125 may also include one or more second insulating layers 121.

[0031] The multiple first and second wiring layers 112, 122 can each contain a metal. The metals can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the remaining first wiring layers 112 and the multiple second wiring layers 122, excluding the uppermost first wiring layer M1, can each contain chemical copper formed by electroless plating as a seed layer, and electroplated copper formed by electroplating on this base can be included as a pattern plating layer. On the other hand, the seed layer may include a titanium (Ti) layer and a copper (Cu) layer formed by sputtering. On the other hand, the uppermost first wiring layer M1 does not need to contain a separate seed layer and can contain electroplated copper formed by electroplating as a pattern plating layer. The multiple first and second wiring layers 112, 122 can each perform various functions depending on the design. For example, the multiple first and second wiring layers 112, 122 may each include signal transfer wiring, power transfer wiring, ground transfer wiring, etc. On the other hand, these wirings may have various pattern forms such as lines, traces, planes, pads, and lands. If the second insulator 125 includes one or more second insulating layers 121 as needed, the second wiring section 120 may include one or more second wiring layers 122 instead of multiple second wiring layers 122.

[0032] The multiple first and second via layers 113, 123 can each contain a metal. The metals can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the multiple first and second via layers 113, 123 can each contain chemical copper formed by electroless plating as a seed layer, and electrocopper formed by electroplating on this as a base as a pattern plating layer. On the other hand, the seed layer may also contain a titanium (Ti) layer and a copper (Cu) layer formed by sputtering. The multiple first and second via layers 113, 123 can each perform various functions depending on the design. For example, the multiple first and second via layers 113, 123 can each contain signal transfer vias, power transfer vias, ground transfer vias, etc. Each of the multiple first and second via layers 113, 123 may contain multiple first and second connecting vias. Each of the multiple first and second via layers 113, 123 may have a fill-plated via structure, but is not limited to this, and may also have a conformally plated via structure. If the second insulator 125 contains one or more second insulating layers 121 as necessary, the second wiring section 120 may contain one or more second via layers 123 instead of multiple second via layers 123.

[0033] The first and second passivation layers 161 and 162 may each contain an organic insulating material. The organic insulating material may be a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or may contain an inorganic filler and / or organic filler together with the resin. For example, the organic insulating material may be, but is not limited to, Ajinomoto build-up film (ABF), photosensitive insulating material (PUD), solder resist (SR), etc. The wiring patterns exposed through each of the multiple first openings h1 of the first passivation layer 161 may be of SMD (Solder Mask Defined) and / or NSMD (Non Solder Mask Defined) type. Any of the second openings h2 of the second passivation layer 162 may be a through-cavity structure, but may also be a blind cavity structure that covers a portion of the side of the exposed wiring pattern, if necessary.

[0034] Figures 3 and 4 are schematic cross-sectional views illustrating an example of the manufacturing process of the printed circuit board shown in Figure 2.

[0035] Referring to Figure 3, a first wiring layer M1 can be formed on the detached core 210. For example, a first wiring layer M1 that may include a fine circuit, such as an ETS pattern, can be formed on the copper foil of the detached core 210 by a lithography process and a plating process. Next, two layers of a first insulating layer 111, two layers of a first wiring layer 112, and two layers of a first via layer 113 can be formed on the detached core 210 by a build-up process. The build-up process may involve repeating processes such as lamination of an appropriate insulating material, via hole formation using UV laser processing, and a plating process. Next, the intermediate of the first wiring section 110 manufactured from the detached core 210 can be separated. After detachment, the copper foil of the detached core 210 remaining on the intermediate of the first wiring section 110 can be removed by etching, and at this time, a concave step can be formed on the first wiring layer M1 if necessary. Alternatively, a barrier layer such as a nickel layer may be formed on the copper foil in advance to prevent concave steps from occurring in the first wiring layer M1. On the other hand, the above-described process can be performed simultaneously on both sides of the detached core 210, in which case multiple intermediate units of the first wiring section 110 can be manufactured after detachment.

[0036] Referring to Figure 4, the second insulating layer 121, the second wiring layer 122, and the second via layer 123 can be formed in a build-up process on the substantially flat surface of the first insulating layer 111 where the first wiring layer M1 of the intermediate body of the first wiring section 110 described above is exposed. On the opposite side, the first insulating layer 111, the first wiring layer 112, and the first via layer 113 can also be formed in a build-up process. For example, the build-up process can be performed on both sides. Therefore, the second wiring layer 122 can be formed at a higher density through the microcircuit process. In addition, a coreless multilayer substrate structure can be easily realized. Therefore, the number of layers can be reduced, and the overall thickness of the package can be reduced, making it easy to accommodate high multilayering and large area. Therefore, die-to-die linking can be made at the substrate level, which can reduce process difficulty and cost. On the other hand, the build-up process may consist of repeating processes such as lamination of appropriate insulating material, via hole formation using UV laser processing, and plating. Next, the build-up process can be further performed on both sides as needed. Through such a build-up process, the first wiring section 110 and the second wiring section 120 can be formed. On the other hand, the build-up process may involve repeating processes such as lamination of appropriate insulating material, via hole formation using UV laser processing, and plating. Next, if necessary, first and second passivation layers 161 and 162 can be formed on the first and second wiring sections 110 and 120, respectively, and multiple first openings h1 and any of the second openings h2 can be formed in the first and second passivation layers 161 and 162, respectively. The first and second passivation layers 161 and 162 can be formed using coating, lamination, etc., of appropriate insulating material. The multiple first openings h1 and any of the second openings h2 can be formed by photolithography or laser processing, respectively, depending on the material of the first and second passivation layers 161 and 162.

[0037] Through a series of processes, the printed circuit board 100 according to the example described above can be manufactured, and the other details can be applied substantially in the same manner as described above.

[0038] In this invention, the expression "cover" can include not only covering the entire surface but also covering at least a portion of it, and can include not only direct covering but also indirect covering. Similarly, the expression "fill" can include not only completely filling the surface but also filling at least a portion of it, and can also include roughly filling the surface. For example, it can include cases where there are some gaps or voids. Furthermore, the expression "enclose" can include not only completely enclosing the surface but also partially enclosing or roughly enclosing it. Moreover, "expose" can include not only completely exposing the surface but also partially exposing it, and exposure can mean exposing the structure from being embedded. For example, an opening exposing a pad may mean exposing the pad from the resist layer, and a surface treatment layer or the like may be further placed on the exposed pad.

[0039] In this invention, the determination can be made by including process errors, positional deviations, and measurement errors that occur during the manufacturing process. For example, being substantially coplane may include not only cases where the surfaces are perfectly coplane, but also cases where they are roughly coplane. Similarly, having a substantially specific shape may include not only cases where the surfaces are exactly that shape, but also cases where they are roughly that shape. Furthermore, substantially identical insulating materials may include not only completely identical insulating materials, but also insulating materials of the same type. Therefore, while the composition of the insulating materials may be substantially identical, their specific composition ratios may differ slightly.

[0040] In this invention, "cross-sectional" can mean the cross-sectional shape when the object is cut vertically, or the cross-sectional shape when the object is viewed from the side. "Planar" can mean the planar shape when the object is cut horizontally, or the planar shape when the object is viewed from the top or bottom.

[0041] In this invention, terms such as "lower side," "lower part," and "lower surface" are used for convenience to mean the downward direction relative to the cross-section of the drawing, while terms such as "upper side," "upper part," and "upper surface" are used to mean the opposite direction. However, this is merely a definition of direction for explanatory purposes, and it goes without saying that the scope of rights in the patent claims is not particularly limited by such descriptions of direction, and the concepts of "up" and "down" can change at any time.

[0042] In this invention, the term "connected" includes not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, the term "electrically connected" includes both physical connection and non-connection. In addition, expressions such as "first," "second," etc., are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the rights, the first component may be named the second component, and similarly, the second component may be named the first component.

[0043] In this invention, thickness, width, length, depth, line width, spacing, pitch, separation distance, surface roughness, etc., can be measured using a scanning microscope or optical microscope, based on a cross-section obtained by polishing or cutting the printed circuit board. The cut cross-section can be a vertical or horizontal cross-section, and each value can be measured based on the required cut cross-section. For example, the width of the upper and / or lower ends of a via can be measured on a cross-section obtained by cutting the central axis of the via. On the other hand, if the measured values ​​are not constant, the value can be determined by taking the average of the values ​​measured at any five locations.

[0044] The expression "example" as used in this invention does not mean that each embodiment is identical to the others, but is provided to highlight and explain the unique and distinct features of each. However, the examples presented above do not preclude their implementation in combination with features of other examples. For example, even if a matter described in one example is not described in another example, it can be understood as a description related to the other example, unless there is a description in the other example that contradicts or is contrary to that description.

[0045] The terms used in this invention are for illustrative purposes only and are not intended to limit the invention. In this context, singular expressions include plural expressions unless they clearly mean something different in context. [Explanation of symbols]

[0046] 1000 electronic equipment 1010 Mainboard 1020 Chip-related components 1030 Network-related components 1040 Other parts 1050 Camera 1060 Antenna 1070 Display 1080 Battery 1090 signal line 100B Printed Circuit Board 110, 120 Wiring section 111, 121 Insulating layer 112, 122, M1 wiring layer 113, 123 via layers 115, 125 Insulator 161, 162 Passivation Layer 210 detachable cores h1, h2 opening P1, P2, P3 Minimum pitch L1, L2, L3, S1, S2 minimum spacing

Claims

1. A first wiring portion comprising a first insulator and a plurality of first wiring layers disposed on or within the lower surface of the first insulator, wherein the uppermost of the plurality of first wiring layers is embedded above the first insulator, and at least a portion of the upper surface of the uppermost first wiring layer is exposed from the upper surface of the first insulator, The second wiring section includes a second insulator positioned above the first wiring section and covering at least a portion of the upper surface of the uppermost first wiring layer, and a plurality of second wiring layers positioned on or within the upper surface of the second insulator, The minimum pitch of the wiring included in at least one of the plurality of second wiring layers is smaller than the minimum pitch of the wiring included in at least one of the remaining first wiring layers, excluding the uppermost first wiring layer. Printed circuit board.

2. The minimum pitch of the wiring included in each of the plurality of second wiring layers is smaller than the minimum pitch of the wiring included in each of the remaining first wiring layers. A printed circuit board according to claim 1.

3. The minimum pitch of the wiring included in the uppermost first wiring layer is smaller than the minimum pitch of the wiring included in each of the remaining first wiring layers. A printed circuit board according to claim 2.

4. The minimum line width and minimum spacing between wires included in at least one of the plurality of second wiring layers are smaller than the minimum line width and minimum spacing between wires included in at least one of the remaining first wiring layers. A printed circuit board according to claim 1.

5. The minimum line width and minimum spacing between wires included in each of the plurality of second wiring layers are smaller than the minimum line width and minimum spacing between wires included in each of the remaining first wiring layers. The printed circuit board according to claim 4.

6. The minimum line width and minimum spacing between wires in the uppermost first wiring layer are smaller than the minimum line width and minimum spacing between wires in each of the remaining first wiring layers. The printed circuit board according to claim 5.

7. The minimum insulation distance between the plurality of second wiring layers is smaller than the minimum insulation distance between the plurality of first wiring layers. A printed circuit board according to claim 1.

8. The thickness of the second insulator is thinner than the thickness of the first insulator. A printed circuit board according to claim 7.

9. The first wiring section further includes a plurality of first via layers, each disposed within the first insulator, which electrically connect the plurality of first wiring layers to one another. The second wiring section further includes a plurality of second via layers, each disposed within the second insulator, which electrically connect the plurality of second wiring layers to one another. The second via layer located at the bottom of the plurality of second via layers electrically connects the first wiring layer located at the top and the second wiring layer located at the bottom of the plurality of second wiring layers. A printed circuit board according to claim 1.

10. Each of the plurality of first via layers has a tapered side surface such that the width of the lower end is wider than the width of the upper end in cross-section. Each of the plurality of second via layers has a tapered side surface such that the width of the upper end is wider than the width of the lower end in cross-section. A printed circuit board according to claim 9.

11. A first passivation layer is disposed on the lower surface of the first insulator and has a plurality of first openings that expose at least a portion of the lowest first wiring layer among the plurality of first wiring layers, The present invention further includes a second passivation having a second opening that is positioned on the upper surface of the second insulator and exposes at least a portion of the uppermost of the plurality of second wiring layers, A printed circuit board according to claim 1.

12. Each of the plurality of first openings exposes at least a portion of each of the plurality of wiring patterns included in the first wiring layer located at the bottom. The second opening exposes at least a portion of each of the multiple wiring patterns included in the uppermost second wiring layer. A printed circuit board according to claim 11.

13. The device includes a plurality of first insulating layers, a plurality of first wiring layers, and a plurality of first via layers, wherein the uppermost of the plurality of first wiring layers is embedded above the uppermost of the plurality of first insulating layers, and at least a portion of the upper surface of the uppermost first wiring layer is a first wiring portion exposed from the upper surface of the uppermost first insulating layer. A second wiring section is located above the first wiring section and includes one or more second insulating layers, one or more second wiring layers, and one or more second via layers. Each of the plurality of first via layers has a first connecting via, and each of the one or more second via layers has a second connecting via, with tapered sides in opposite directions in cross-section. Printed circuit board.

14. Each of the plurality of first via layers has a tapered side surface such that the width of the lower end is wider than the width of the upper end in cross-section. Each of the one or more second via layers has a tapered side surface such that the width of the upper end is wider than the width of the lower end in cross-section. The printed circuit board according to claim 13.

15. The lowest of the one or more second insulating layers covers at least a portion of the upper surface of the first wiring layer located at the top. The plurality of first wiring layers and the one or more second wiring layers are electrically connected to each other via the plurality of first via layers and the one or more second via layers. The printed circuit board according to claim 13.

16. The first wiring section and the second wiring section each have a coreless substrate structure. The printed circuit board according to claim 13.

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