Method for evaluating the resistivity of silicon single crystals

Abstract

This invention provides a method for evaluating the resistivity of a silicon single crystal that can eliminate crystal regions whose in-plane resistivity distribution does not meet the desired quality standards. [Solution] The system includes an ingot growth step S11 in which a silicon single crystal ingot is grown by the CZ method, a block extraction step S12 in which a silicon block is extracted from the silicon single crystal ingot, a block quality determination step S14 in which the entire silicon block is determined to be good if the measurement result of the in-plane resistivity distribution of sample wafers cut from both ends of the silicon block satisfies a desired resistivity distribution, and a defective wafer determination step S15 in which wafers cut from crystal portions grown during a period in which a silicon block determined to be good is grown, are determined to be defective wafers, if the deviation between the actual value of the pulling speed of the silicon single crystal ingot and the pulling speed profile exceeds a preset threshold.

Description

Technical Field

[0001] The present invention relates to a method for evaluating the resistivity of a silicon single crystal, and particularly to a method for evaluating the in-plane resistivity distribution of a silicon wafer cut out from a silicon single crystal.

Background Art

[0002] Silicon wafers are widely used as substrate materials for semiconductor devices. In the manufacture of silicon wafers, a silicon single crystal ingot grown by the CZ method is peripherally ground to adjust the diameter, and then the top and tail parts are cut off and processed into a silicon block of a predetermined length. At this time, sample wafers for quality inspection are also cut out simultaneously from both ends of the silicon block, and the quality of the silicon block is judged by inspecting the resistivity, oxygen concentration, carrier recombination lifetime, presence or absence of crystal defects, etc.

[0003] When the quality inspection of the silicon block is passed, the product processing of the silicon block is advanced. In the processing of the silicon block, a large number of silicon wafers are cut out at once by slicing the silicon block using a wire saw. Thereafter, post-processes such as lapping, etching, double-sided polishing, single-sided polishing, and cleaning are performed to complete the wafer product.

[0004] Regarding the method for evaluating the resistivity of a silicon single crystal, for example, in Patent Document 1, it is described that a silicon single crystal ingot is cut into blocks using a band saw or the like, sample wafers are cut out from both ends of the silicon block, and the quality of the silicon block is judged by evaluating the resistivity and the like.

[0005] Patent Document 2 describes a resistivity calculation program that calculates the axial resistivity profile of a single crystal using the charge amount of the raw material melt, the amount of dopant added, the pressure inside the furnace, and the pulling speed of the single crystal as parameters. Patent Document 3 describes a method for manufacturing a silicon wafer having an RRG (Radial Resistivity Gradient) of 5% or less. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2018-093086 [Patent Document 2] Japanese Patent Publication No. 2011-093770 [Patent Document 3] International Publication No. 2019 / 107190 Brochure [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] As described above, conventionally, sample wafers were cut from both ends of the silicon block, and their resistivity was measured. If the resistivity of both sample wafers met the desired resistivity range, the entire silicon block was considered to meet the desired quality, and the quality of the entire silicon block was guaranteed.

[0008] However, relying solely on inspection results from sample wafers at both ends of a silicon block to guarantee the overall quality of the block may lead to overlooking quality defects in parts of the block.

[0009] Shortening the block length and increasing the number of sample wafers inspected can improve inspection reliability, but this can lead to increased lead times and measurement costs. Furthermore, if the block length becomes too short, it may become difficult to cut the ingot using a wire saw in the subsequent slicing process, potentially making it impossible to discharge the wafer to the next stage.

[0010] Therefore, an object of the present invention is to provide a method for evaluating the resistivity of a silicon single crystal that can eliminate crystal regions in which the in-plane resistivity distribution does not meet the desired quality. [Means for solving the problem]

[0011] To solve the above problems, the resistivity evaluation method for silicon single crystals according to the present invention is characterized by comprising: an ingot growing step of growing a silicon single crystal ingot to which a dopant has been added by the CZ method while controlling the pulling speed based on a preset target value; a block sampling step of taking a silicon block from the silicon single crystal ingot grown in the ingot growing step; a resistivity distribution measurement step of cutting out a sample wafer from both ends of the silicon block obtained in the block sampling step and measuring the in-plane resistivity distribution of the sample wafer; a block quality determination step of determining the entire silicon block as good in terms of resistivity if the result measured in the resistivity distribution measurement step satisfies a desired in-plane resistivity distribution; and a defective wafer determination step of determining a silicon wafer cut out from a crystal portion grown during a period in which the deviation between the actual value of the pulling speed of the silicon single crystal ingot and the target value during the period in which the silicon block determined to be good in the block quality determination step was grown exceeds a preset threshold, as a defective wafer in terms of resistivity.

[0012] According to the present invention, it is possible to prevent crystal regions whose in-plane resistivity distribution does not meet the desired quality from being included in the final product without increasing the number of sample wafers to be inspected. Therefore, the reliability of quality assurance regarding the resistivity of silicon wafers can be improved.

[0013] In the present invention, the threshold is preferably ±0.03 mm / min of the target value of the pulling speed. This makes it possible to increase the yield of wafer products in which the in-plane resistivity distribution meets the desired quality.

[0014] Furthermore, the resistivity evaluation method for silicon single crystals according to the present invention is characterized by comprising: an ingot growth step of growing a silicon single crystal ingot to which a dopant has been added by the CZ method while controlling the pulling speed based on a preset pulling speed profile; and a defective part determination step of determining that crystal parts grown during a period in which the deviation between the actual value of the pulling speed of the straight body portion of the silicon single crystal ingot and the pulling speed profile exceeds a preset threshold are defective parts with respect to resistivity.

[0015] According to the present invention, it is possible to identify and remove crystalline regions whose in-plane resistivity distribution does not meet the desired quality, thereby increasing the yield of wafer products whose in-plane resistivity meets the desired quality. Therefore, the reliability of quality assurance regarding the resistivity of silicon wafers can be improved.

[0016] The resistivity evaluation method for silicon single crystals according to the present invention preferably further comprises a defect removal step of removing the defective portion from the straight body portion. This makes it possible to remove the defective portion at a very early stage in the wafer processing process.

[0017] The resistivity evaluation method for silicon single crystals according to the present invention further comprises a block sampling step of sampling a silicon block from the straight body portion, and a block quality determination step of determining the entire silicon block as good in terms of resistivity if the measurement results of the in-plane resistivity distribution of sample wafers cut from both ends of the silicon block satisfy a desired in-plane resistivity distribution, wherein the defective part determination step preferably determines whether the silicon block determined to be good in the block quality determination step contains the defective part. This makes it possible to remove the defective part contained in the silicon block determined to be good.

[0018] The resistivity evaluation method of a silicon single crystal according to the present invention preferably further includes a defective part removal step of removing the defective part from the silicon block when the defective part is included in the silicon block determined to be a good product in the block quality determination step. Thereby, it is possible to prevent the defective part from being a target for wafer processing.

[0019] The resistivity evaluation method of a silicon single crystal according to the present invention preferably further includes a slicing step of cutting out a plurality of silicon wafers from the silicon block, and in the defective part determination step, it is preferable to determine a silicon wafer cut out from the defective part included in the silicon block as a defective wafer. Thereby, the defective part can be removed without performing a dedicated cutting process.

[0020] The resistivity evaluation method of a silicon single crystal according to the present invention preferably further includes a defective wafer removal step of delivering the good wafers excluding the defective wafers to a subsequent process. Thereby, the reliability of quality assurance regarding the resistivity of the silicon wafers can be enhanced.

Effects of the Invention

[0021] According to the present invention, it is possible to provide a resistivity evaluation method of a silicon single crystal capable of excluding crystal parts whose in-plane resistivity distribution does not satisfy desired quality.

Brief Description of the Drawings

[0022] [Figure 1] FIG. 1 is a flowchart schematically showing a resistivity evaluation method of a silicon single crystal according to an embodiment of the present invention. [Figure 2] FIG. 2 is a flowchart schematically showing an ingot growth process. [Figure 3] FIG. 3 is an explanatory diagram of a method for growing a silicon single crystal by the CZ method. [Figure 4] FIG. 4 is an explanatory diagram of a resistivity evaluation method of a silicon single crystal, particularly an explanatory diagram from a block sampling step to a block quality determination step. [Figure 5] Figure 5 is an explanatory diagram of a method for evaluating the resistivity of a silicon single crystal, and in particular, it is an explanatory diagram of the process from the defect detection step to the defect removal step. [Figure 6] Figure 6 is a graph showing the set value (target value) and actual value of the pulling rate for silicon single crystals. [Figure 7] Figure 7 is a graph showing the in-plane resistivity distribution of a silicon wafer cut from the crystalline region B1 shown in Figure 6, where the horizontal axis represents the solidification rate (%) and the vertical axis represents the relative value of the resistivity (%). [Figure 8] Figure 8 is a graph showing the in-plane resistivity distribution of a silicon wafer cut from crystalline region B2 shown in Figure 6, where the horizontal axis represents the solidification rate (%) and the vertical axis represents the relative value of resistivity (%). [Figure 9] Figure 9 is a graph showing the in-plane resistivity distribution of a silicon wafer cut from crystalline region B3 shown in Figure 6, where the horizontal axis represents the solidification rate (%) and the vertical axis represents the relative value of the resistivity (%). [Figure 10] Figure 10 is a graph showing the relationship between the variation in the pulling rate at crystal regions B1, B2, and B3 shown in Figure 6 and the RRG of the silicon wafer cut from those crystal regions. [Modes for carrying out the invention]

[0023] Preferred embodiments of the present invention will be described in detail below with reference to the attached drawings.

[0024] Figure 1 is a flowchart illustrating a schematic method for evaluating the resistivity of a silicon single crystal according to an embodiment of the present invention.

[0025] As shown in Figure 1, the resistivity evaluation method for silicon single crystals according to this embodiment includes an ingot growth step S11 in which a silicon single crystal ingot with a dopant added is grown by the CZ method; a block extraction step S12 in which a silicon block is cut out from the silicon single crystal ingot; a resistivity distribution measurement step S13 in which the in-plane resistivity distribution of sample wafers cut out from both ends of the silicon block is measured; a block quality determination step S14 in which the entire silicon block is determined to be good in terms of resistivity if the measurement result of the in-plane resistivity distribution of the sample wafer satisfies a desired in-plane resistivity distribution; a defective part determination step S15 in which crystal parts grown during the period in which the silicon block determined to be good in the block quality determination step S14 was grown, in which the deviation between the actual value and the target value (pulling speed profile) of the pulling speed of the silicon single crystal ingot exceeds a preset threshold, are determined to be defective parts in terms of resistivity; and a defective part removal step S16 in which defective parts (defective wafers) are removed from the silicon block or the silicon wafer cut out from the silicon block.

[0026] Figure 2 is a flowchart illustrating the ingot growth process S11. Figure 3 is an explanatory diagram of the silicon single crystal growth method using the CZ method.

[0027] As shown in Figures 2 and 3, in the ingot growth process S11, polycrystalline silicon raw material is first filled into a quartz crucible 11 placed inside the CZ furnace 10 together with a dopant (step S21). When pulling n-type silicon single crystals, the dopant is, for example, phosphorus (P), arsenic (As), or antimony (Sb), and when pulling p-type silicon single crystals, the dopant is, for example, boron (B), aluminum (Al), gallium (Ga), or indium (In). By adding a predetermined amount of dopant to the polycrystalline silicon raw material, a semiconductor single crystal with a desired resistivity can be grown.

[0028] Next, the polycrystalline silicon raw material is heated with the heater 12 to generate a silicon melt 6 containing the dopant (step S22). Then, the seed crystal 7 attached to the tip of the wire 13 is lowered and deposited into the silicon melt 6 (step S23).

[0029] Next, a crystal pulling process (steps S24-S27) is performed in which a large single crystal 1 is grown at the lower end of the seed crystal 7 by rotating the quartz crucible 11 and the seed crystal 7 respectively, while maintaining contact with the silicon melt 6 and gradually pulling up the seed crystal 7.

[0030] In the crystal pulling process (steps S24-S27), the following steps are performed in order: necking step S24 to form a neck portion 1a with a narrowed crystal diameter for dislocation-free formation; shoulder portion growth step S25 to grow a shoulder portion 1b with a gradually increasing crystal diameter; straight body portion growth step S26 to grow a straight body portion 1c with a crystal diameter maintained at a nearly constant diameter (for example, about 310 mm); and tail portion growth step S27 to grow a tail portion 1d with a gradually decreasing crystal diameter. Finally, the single crystal is separated from the surface of the silicon melt 6. This completes a silicon single crystal ingot 1I having a shoulder portion 1b, a straight body portion 1c, and a tail portion 1d (see Figure 4).

[0031] In the crystal pulling process (S24-S27), the pulling of the silicon single crystal 1 is controlled based on a pre-set pulling rate profile so that a desired crystal diameter is obtained as the crystal grows. In particular, in the straight section growth process S26, a target value for the pulling rate (pulling rate profile) is pre-set so that the crystal diameter remains constant. In the straight section growth process S26, the pulling rate is often maintained constant along its entire length, but the pulling rate may also be changed according to the crystal growth stage. Thus, the pulling rate of the silicon single crystal 1 is controlled based on a pulling rate profile that defines a target value for the pulling rate according to the crystal length.

[0032] The control unit 16 drives the crystal pulling mechanism 14 based on the pulling speed profile to control the pulling speed of the silicon single crystal 1. The control unit 16 also collects the actual pulling speed values ​​sent from the crystal pulling mechanism 14 at a predetermined sampling period and records them in memory.

[0033] During the crystal pulling process (S24-S27), changes in crystal diameter are unavoidable. Therefore, the crystal diameter near the solid-liquid interface is monitored using the camera 15, and feedback control of the crystal diameter is performed to obtain the desired diameter. The image captured by the camera 15 is sent to the image processing unit 17, where the crystal diameter is determined. The control unit 16 increases the pulling speed to decrease the crystal diameter if the measured crystal diameter is larger than the target value, and decreases the pulling speed to increase the crystal diameter if it is smaller than the target value. In this way, by controlling the pulling speed in real time according to changes in the furnace environment, the measured crystal diameter can be brought closer to the target value.

[0034] During the crystal pulling process (S24-S27), the actual pulling speed of the silicon single crystal 1, images captured by camera 15, and other changes in crystal growth conditions over time are meticulously recorded at a predetermined sampling period and registered in a database. This data is used for analyzing the quality of the silicon single crystal, such as its resistivity, as described later.

[0035] Figure 4 is an explanatory diagram of a method for evaluating the resistivity of a silicon single crystal, and is particularly an explanatory diagram of the process from the block sampling process S12 to the block quality determination process S14.

[0036] As shown in Figure 4, the block extraction process S12 cuts out one or more silicon blocks from the silicon single crystal ingot 1I that satisfy the desired resistivity range. Since the dopant concentration in the silicon single crystal changes in the direction of the pulling axis due to segregation, the resistivity also changes in the direction of the pulling axis. Therefore, if the acceptable range of resistivity required for the wafer product is very narrow, the entire straight body portion 1c cannot be used for productization. In such cases, by cutting out a silicon block that satisfies the desired resistivity range and using this as the wafer processing target, it is possible to prevent crystal portions that do not meet the desired resistivity quality from being used for wafer processing. If the entire straight body portion 1c satisfies the desired resistivity range, the entire straight body portion 1c can be used as the silicon block, as shown in the figure.

[0037] When cutting multiple silicon blocks 2 from a silicon single crystal ingot 1I, the shoulder portion 1b and tail portion 1d are removed from the ingot 1I, and then a block cutting process, in which silicon blocks 2 are cut from the straight body portion 1c, and a wafer cutting process, in which sample wafers 3 are cut, are performed alternately. This allows multiple silicon blocks 2 to be cut from the ingot 1I, and sample wafers 3 to be cut from both ends of each silicon block 2. Cutting machines using band saws, inner blades, outer blades, etc., are used to cut the silicon blocks 2 and sample wafers 3. In the wafer cutting process, two or more sample wafers may be cut consecutively.

[0038] As described above, in the crystal pulling process (S24-S27), the time change of the actual pulling speed is recorded as pulling speed data 20. This makes it possible to know the pulling speed at any position in the straight body section 1c. The pulling speed data 20 is used to determine the location of the resistivity defect, which will be described later.

[0039] In the resistivity distribution measurement step S13, the in-plane resistivity distribution of the sample wafers 3 cut from both ends of the silicon block 2 is first measured. For the measurement of the in-plane resistivity distribution, the resistivity is measured at a total of 5 points, for example, one point at the center of the wafer, two points at a position half the radius from the center, and two points 5 mm inward from the outer edge, using, for example, a four-probe method. Note that the measurement points are not limited to 5 points. For example, a total of 9 points may be measured: one point at the center of the wafer, two points in the x-axis and y-axis directions each at a position half the radius from the center, and two points 5 mm inward from the outer edge. Alternatively, measurements may be taken at intervals of, for example, 15 mm from the center, or at multiple measurement points set arbitrarily.

[0040] Subsequently, in block quality determination step S14, the quality of the resistivity distribution of the silicon block is determined based on the resistivity measurement results of the sample wafer 3. Specifically, if the resistivity measurement results of both sample wafers 3 satisfy the desired in-plane resistivity distribution, the entire silicon block 2 is considered to have the desired in-plane resistivity distribution, and the entire silicon block is determined to be a good product. If the resistivity measurement result of either one of the sample wafers 3 does not satisfy the desired in-plane resistivity distribution, the entire silicon block 2 is determined to be a defective product. In the example in Figure 4, silicon blocks 2a and 2b are determined to be good products, and silicon blocks 2c and 2d are determined to be defective products.

[0041] In the defective part determination process S15, if the deviation between the actual pulling speed of the silicon single crystal ingot 1I during the period in which the silicon block 2, which was determined to be a good product in the block quality determination process S14, was grown exceeds a threshold, the crystal portion grown at a pulling speed exceeding the threshold is determined to be a defective part, and the silicon wafer cut from that crystal portion is determined to be a defective wafer.

[0042] Figure 5 is an explanatory diagram of a method for evaluating the resistivity of a silicon single crystal, and is particularly an explanatory diagram of the process from the defective area determination step S15 to the defective area removal step S16.

[0043] As shown in Figure 5, in the defective area determination step S15, the pulling speed data 20a of the silicon single crystal ingot 1I during the period in which the silicon block 2 (here, silicon block 2a) that was determined to be good in the block quality determination step S14 was grown is referenced, and the actual value of the pulling speed is compared with the target value (pulling speed profile). If the deviation between the actual value of the pulling speed and the target value exceeds a threshold, the crystal portion grown at a pulling speed exceeding that threshold is determined to be a defective area in terms of resistivity. That is, if the deviation exceeds the upper threshold or falls below the lower threshold, the crystal portion grown during that period is determined to be a defective area 2f. Crystal portions other than the defective area 2f are determined to be good areas 2g.

[0044] The defective area 2f is preferably defined as the range from -10mm, where the deviation in the pulling speed exceeds the threshold, to +10mm, where it returns to within the threshold. This ensures that crystal portions whose resistivity does not meet the desired quality can be reliably eliminated.

[0045] The threshold is preferably ±0.03 mm / min of the pulling speed profile. That is, crystal regions grown during the period when the actual pulling speed exceeds the upper threshold of the pulling speed profile +0.03 mm / min are determined to be defective regions. Similarly, crystal regions grown during the period when the actual pulling speed falls below the lower threshold of the pulling speed profile -0.03 mm / min are also determined to be defective regions. By setting the threshold to ±0.03 mm / min of the pulling speed profile, the yield of wafer products with an RRG of less than 10% can be increased.

[0046] In the defective part removal process S16, the defective part 2f is removed from the silicon block 2a. The removal of the defective part 2f may be performed before or after slicing the silicon block 2a. In the former case, slicing is performed on the silicon block from which the defective part 2f has been removed to produce a silicon wafer 4 (good wafer 4g).

[0047] In the latter case, a slicing process is performed using a wire saw or the like to cut multiple silicon wafers 4 from the silicon block 2a. Then, the wafers cut from the defective area 2f are excluded from the product line as defective wafers 4f. The remaining good wafers 4g are sent to the next process, where they undergo processing necessary for product development, such as lapping, etching, double-sided polishing, single-sided polishing, and cleaning.

[0048] The determination of defective areas 2f in the in-plane resistivity distribution based on the actual pulling speed of the silicon single crystal can be performed at any time after the silicon single crystal has been grown. That is, it can be done before cutting out the silicon block 2 from the silicon single crystal ingot 1I, or after cutting out the silicon block 2. It can also be done before cutting out the silicon wafer 4 from the silicon block 2, or after cutting out the silicon wafer 4 from the silicon block 2. If the silicon wafer 4 has been cut out from the silicon block 2, the wafer cut out from the defective area 2f can be determined to be a defective wafer 4f and excluded from subsequent processes.

[0049] As described above, the resistivity evaluation method for silicon single crystals according to this embodiment determines whether the in-plane resistivity distribution of the silicon single crystal is within an acceptable range based on fluctuations in the pulling speed of the silicon single crystal ingot taken during the ingot growth process. Therefore, it is possible to prevent crystal portions whose in-plane resistivity distribution does not meet the desired quality from being included in the product without directly measuring the resistivity. Accordingly, the reliability of quality assurance for silicon wafers with respect to resistivity can be improved. It is possible.

[0050] Although preferred embodiments of the present invention have been described above, it goes without saying that the present invention is not limited to the above embodiments, and various modifications are possible without departing from the spirit of the invention, and these modifications are also included within the scope of the present invention. [Examples]

[0051] A silicon single crystal ingot with a diameter of approximately 200 mm was grown using the CZ method. The actual pulling speed of the silicon single crystal ingot was recorded. Figure 6 shows the pulling speed data during the growth period of the straight section. In the graph in Figure 6, the horizontal axis represents the solidification rate, and the vertical axis represents the pulling speed (relative value).

[0052] As shown in Figure 6, the pulling speed during the growth of the straight section is generally stable, but there are large fluctuations in the pulling speed midway through, indicating that the pulling speed is temporarily unstable.

[0053] Next, three silicon wafers were successively cut from each of the three crystalline regions B1, B2, and B3 of the straight body of the silicon single crystal ingot, and the RRG (Radial Resistivity Gradient) of these 3×3=9 wafers was measured using the four-probe method. Crystalline region B1 was cut from the section where the pulling speed was relatively stable and the solidification rate was 14-16%. Crystalline region B2 was cut from the section where the pulling speed was relatively stable and the solidification rate was 19-21%. Crystalline region B3 was cut from the section where the pulling speed became unstable and the solidification rate was 25-27%. Resistivity was measured at 17 points in the radial direction, including the center of the wafer.

[0054] RRG is an evaluation index for in-plane resistivity distribution, representing the maximum value ρ among resistivity measurements taken at any multiple locations within the plane of a single silicon wafer. max and minimum value ρ min The difference is the minimum value ρ min This is the value obtained by dividing by the given factor and expressed as a percentage. In other words, RRG is expressed by the following formula: RRG(%)={(ρ max -ρ min ) / ρ min}×100

[0055] Figures 7 to 9 are graphs showing the in-plane resistivity distribution of silicon wafers cut from crystalline regions B1 to B3. The vertical axis represents the distance from the wafer center (mm), and the vertical axis represents the relative resistivity (%) based on the measured resistivity value Ce at a measurement point 15 mm radially from the wafer center.

[0056] As shown in Figure 7, the in-plane variation in resistivity of silicon wafers cut from crystal region B1, where the pulling speed fluctuation was small, was sufficiently small, within 5%.

[0057] As shown in Figure 8, the in-plane variation in resistivity of silicon wafers cut from crystal region B2, where the pulling speed fluctuation was small, was within 8%.

[0058] As shown in Figure 9, the in-plane variation in resistivity of silicon wafers cut from crystal region B3, where the pulling speed fluctuates greatly, was large, exceeding 8%.

[0059] Figure 10 is a graph showing the relationship between the fluctuation range of the pulling speed in crystal regions B1, B2, and B3 shown in Figure 6, and the RRG of the silicon wafer cut from those crystal regions. The horizontal axis represents the absolute value of the fluctuation range of the pulling speed (mm / min), and the vertical axis represents the RRG (%).

[0060] As shown in Figure 10, we observed a tendency for RRG to increase as the fluctuation in lifting speed increased. Furthermore, we found that RRG could be reduced to 8% or less if the fluctuation range of the lifting speed was 0.03 mm / min or less. [Industrial applicability]

[0061] One aspect of the present invention is useful in the field of single-crystal silicon wafer manufacturing. It can provide a method for evaluating the resistivity of a silicon single crystal that can remove crystal regions from a silicon block whose in-plane resistivity distribution does not meet the desired quality. This prevents the outflow of substandard silicon wafers, allows for meeting greater demand, and improves the productivity of the semiconductor industry as a whole. Thus, one aspect of the present invention can contribute to promoting economic growth (Development Goal: SDG 8). [Explanation of Symbols]

[0062] 1. Silicon single crystal 1I Silicon single crystal ingot 1a Neck section 1b Shoulder section 1c Straight body part 1d Tail section 2,2a,2b,2c,2d Silicone Blocks 2f defective part 2g Good part 3 Sample wafers 4. Silicon wafer 4f Defective wafer 4g good quality wafers 6. Silicon melt 7 seed crystal 10 CZ furnace 11 Quartz Crucible 12 Heater 13 wires 14. Crystal pulling mechanism 15 Cameras 16 Control Unit 20,20a Actual data on lifting speed S11 Ingot Growing Process S12 Block Sampling Process S13 Resistivity distribution measurement process S14 Block quality determination process S15 Defective part determination process S16 Defective part removal process S21 Raw material filling process S22 Silicon melt generation process S23 Liquid application process S24 Necking process S25 Shoulder section development process S26 Straight trunk growth process S27 Tail section development process

Claims

1. An ingot growing process in which a silicon single crystal ingot with a dopant added is grown by the CZ method while controlling the pulling speed based on a predetermined target value, A block extraction step is performed to extract a silicon block from the silicon single crystal ingot grown in the ingot growth step, A resistivity distribution measurement step is performed in which a sample wafer is cut from both ends of the silicon block obtained in the block sampling step, and the in-plane resistivity distribution of the sample wafer is measured. A block quality determination step is performed in which, if the results measured in the resistivity distribution measurement step satisfy the desired in-plane resistivity distribution, the entire silicon block is determined to be a good product in terms of resistivity. A method for evaluating the resistivity of a silicon single crystal, comprising: a defective wafer determination step, in which a silicon wafer cut from a crystal portion grown during a period in which the silicon block determined to be a good product in the block quality determination step is grown, is determined to be a defective wafer in terms of resistivity.

2. The resistivity evaluation method for a silicon single crystal according to claim 1, wherein the threshold is ±0.03 mm / min of the target value of the pulling speed.

3. An ingot growing process in which a silicon single crystal ingot with a dopant added is grown by the CZ method while controlling the pulling speed based on a pre-set pulling speed profile, A method for evaluating the resistivity of a silicon single crystal, comprising a defective part determination step, in which crystal portions grown during a period in which the deviation between the actual value of the pulling speed of the straight section of the silicon single crystal ingot and the pulling speed profile exceeds a preset threshold are determined to be defective parts with respect to resistivity.

4. The method for evaluating the resistivity of a silicon single crystal according to claim 3, further comprising a defect removal step of removing the defective portion from the straight body portion.

5. A block sampling step for taking a silicon block from the straight cylinder portion, The system further includes a block quality determination step in which, if the measurement results of the in-plane resistivity distribution of sample wafers cut from both ends of the silicon block satisfy a desired resistivity distribution, the entire silicon block is determined to be a good product in terms of resistivity. The method for evaluating the resistivity of a silicon single crystal according to claim 3, wherein the defective part determination step determines whether or not the silicon block determined to be good in the block quality determination step contains the defective part.

6. The method for evaluating the resistivity of a silicon single crystal according to claim 5, further comprising a defective part removal step in which, if a silicon block determined to be good in the block quality determination step contains the defective part, the defective part is removed from the silicon block.

7. The process further comprises a slicing step for cutting multiple silicon wafers from the aforementioned silicon block, The method for evaluating the resistivity of a silicon single crystal according to claim 5, wherein the defective portion determination step determines that a silicon wafer cut from the defective portion contained in the silicon block is a defective wafer.

8. The method for evaluating the resistivity of a silicon single crystal according to claim 7, further comprising a defective wafer removal step of discharging good wafers, excluding the defective wafers, to a subsequent process.

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