Wiring board and method for manufacturing a wiring board

Abstract

To provide a wiring board that can improve the filling properties of the filling insulating layer. [Solution] The wiring board 10 has an insulating layer 42, wiring layers 43A and 43B laminated on the upper surface of the insulating layer 42, an insulating layer 44 formed on the upper surface of the insulating layer 42 so as to cover the sides and top surfaces of the wiring layers 43A and 43B, and insulating layers 45, 47, and 49 laminated on the upper surface of the insulating layer 44. The wiring board 10 has a cavity 40X formed in the insulating layers 45, 47, and 49, an opening 44X formed on the upper surface of the insulating layer 44 exposed from the cavity 40X, and a connection terminal 70 formed on the upper surface of the wiring layer 43A exposed from the opening 44X. The wiring board 10 has an electronic component 60 disposed in the cavity 40X and mounted on the connection terminal 70, an insulating layer 50 that fills the cavity 40X and covers the electronic component 60, and a wiring layer 51 laminated on the upper surface of the insulating layer 50.

Description

Technical Field

[0001] The present invention relates to a wiring board and a method for manufacturing the wiring board.

Background Art

[0002] Conventionally, a wiring board incorporating electronic components has been known (see, for example, Patent Document 1). As this type of wiring board, there has been proposed one in which an electronic component is mounted on a conductive pad exposed at the bottom of a cavity formed in a plurality of insulating layers, and a filling insulating layer is formed to fill the cavity so as to cover the electronic component. Such a wiring board is manufactured, for example, by the following manufacturing method. First, a conductive pad is formed, and after forming a protective material that covers the conductor pad, a plurality of insulating layers that cover the conductive pad and the protective material are laminated. Subsequently, after forming a cavity that exposes the protective material by removing a predetermined region of the plurality of insulating layers, the conductive pad is exposed by removing the protective material. Next, after mounting an electronic component on the conductive pad, a filling insulating layer that fills the cavity and covers the electronic component is formed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, in the above wiring board, improvement in the filling property of the filling insulating layer is desired.

Means for Solving the Problems

[0005] According to one aspect of the present invention, a first insulating layer, a first wiring layer and a second wiring layer laminated on the upper surface of the first insulating layer, a second insulating layer formed on the upper surface of the first insulating layer so as to cover the side and top surfaces of the first wiring layer and the side and top surfaces of the second wiring layer, an N-layer insulating layer (where N is a natural number of 1 or more) laminated on the upper surface of the second insulating layer, a cavity formed in the N-layer insulating layer and formed so as to expose the first surface of the second insulating layer, and the first insulating layer formed on the first surface and penetrating the second insulating layer in the thickness direction The wiring cavity has an opening that exposes a portion of the upper surface of the wiring layer, a connection terminal formed on the upper surface of the first wiring layer exposed through the opening, an electronic component disposed in the cavity and mounted on the connection terminal, a filling insulating layer that fills the cavity and covers the electronic component, and a third wiring layer laminated on the upper surface of the filling insulating layer and electrically connected to the electronic component, wherein the first wiring layer is provided in a position that overlaps with the cavity in a plan view, and the second wiring layer may be provided in a position that does not overlap with the cavity in a plan view. [Effects of the Invention]

[0006] According to one aspect of the present invention, the filling properties of the filling insulating layer can be improved. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 is a schematic cross-sectional view showing a wiring board of the first embodiment. [Figure 2] Figure 2 is a schematic cross-sectional view showing an enlarged portion of the wiring board of the first embodiment. [Figure 3] Figure 3 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 4] Figure 4 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 5] Figure 5 is a schematic cross-sectional view showing the manufacturing method of a wiring board according to the first embodiment. [Figure 6] Figure 6 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 7] Figure 7 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 8] Figure 8 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 9] Figure 9 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 10] Figure 10 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 11] Figure 11 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 12] Figure 12 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 13] Figure 13 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 14] Figure 14 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 15] Figure 15 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 16] Figure 16 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 17] Figure 17 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 18] Figure 18 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 19] Figure 19 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 20] Figure 20 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 21] Figure 21 is a schematic cross-sectional view showing an enlarged portion of the wiring board of the second embodiment. [Figure 22] Figure 22 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the second embodiment. [Figure 23] Figure 23 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the second embodiment. [Figure 24] FIG. 24 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to the second embodiment. [Figure 25] FIG. 25 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to the second embodiment. [Figure 26] FIG. 26 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to the second embodiment. [Figure 27] FIG. 27 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to the second embodiment. [Figure 28] FIG. 28 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to the second embodiment. [Figure 29] FIG. 29 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to the second embodiment. [Figure 30] FIG. 30 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to the second embodiment. [Figure 31] FIG. 31 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to the second embodiment. [Figure 32] FIG. 32 is a schematic enlarged cross-sectional view showing a part of a wiring board according to the third embodiment. [Figure 33] FIG. 33 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to the third embodiment. [Figure 34] FIG. 34 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to the third embodiment. [Figure 35] FIG. 35 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to the third embodiment. [Figure 36] FIG. 36 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to the third embodiment. [Figure 37] FIG. 37 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to the third embodiment. [Figure 38] FIG. 38 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to the third embodiment. [Figure 39] FIG. 39 is a schematic enlarged cross-sectional view showing a part of a wiring board according to the fourth embodiment. [Figure 40]Figure 40 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the fourth embodiment. [Figure 41] Figure 41 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the fourth embodiment. [Figure 42] Figure 42 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the fourth embodiment. [Figure 43] Figure 43 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the fourth embodiment. [Figure 44] Figure 44 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the fourth embodiment. [Figure 45] Figure 45 is a schematic cross-sectional view showing a magnified portion of the modified wiring board. [Figure 46] Figure 46 is a schematic cross-sectional view showing a magnified portion of the modified wiring board. [Figure 47] Figure 47 is a schematic cross-sectional view showing a magnified portion of the modified wiring board. [Modes for carrying out the invention]

[0008] The embodiments will be described below with reference to the attached drawings. Note that, for convenience, the attached drawings may show enlarged versions of characteristic parts to make the features easier to understand, and the dimensional ratios of each component may differ in each drawing. Furthermore, in the cross-sectional views, to make the cross-sectional structure of each member easier to understand, the hatching of some members has been replaced with a textured pattern, and the hatching of some members has been omitted. In this specification, "plan view" refers to viewing the object from the vertical direction (up and down direction in the drawing) as shown in Figure 1, and "planar shape" refers to the shape of the object as viewed from the vertical direction as shown in Figure 1. Also, in this specification, "up and down direction" and "left and right direction" refer to the direction in which the symbols indicating each member in each drawing are correctly readable. Furthermore, unless otherwise stated, the numerical range of "X1~X2" defined by the upper limit X1 and lower limit X2 in this disclosure refers to a range of X1 to X2.

[0009] (First Embodiment) The first embodiment will be described below with reference to Figures 1 to 20. (Overall configuration of the wiring board 10) As shown in Figure 1, the wiring board 10 includes a core substrate 20, a wiring structure 30, a wiring structure 40, a cavity 40X formed in the wiring structure 40, and one or more (one in this embodiment) electronic components 60 disposed within the cavity 40X. The wiring board 10 also includes an underfill resin 66, a solder resist layer 80, and external connection terminals 90. The wiring board 10 is a wiring board with embedded electronic components 60. The wiring structure 40 and the external connection terminals 90 are located on one side of the core substrate 20, while the wiring structure 30 and the solder resist layer 80 are located on the other side of the core substrate 20.

[0010] In this embodiment, for convenience, the side of the wiring board 10 with the external connection terminals 90 in Figure 1 is referred to as one side or the upper side, and the side of the wiring board 10 with the solder resist layer 80 is referred to as the other side or the lower side. Also, in this embodiment, for convenience, the side of each part with the external connection terminals 90 is referred to as one side or the upper surface, and the side of each part with the solder resist layer 80 is referred to as the other side or the lower surface. However, the wiring board 10 can be used upside down or positioned at any angle.

[0011] As the core substrate 20, for example, a so-called glass epoxy substrate can be used, which is made by impregnating glass cloth with a thermosetting insulating resin such as epoxy resin. As the core substrate 20, for example, a substrate may be used in which woven or nonwoven fabrics such as glass fibers, carbon fibers, or aramid fibers are impregnated with a thermosetting insulating resin such as epoxy resin. Note that the illustration of glass cloth, etc., is omitted in each figure.

[0012] The core substrate 20 has a plurality of through holes 20X that penetrate through the core substrate 20 in the thickness direction. Through electrodes 21 that penetrate through the core substrate 20 in the thickness direction are formed inside the through holes 20X. The through electrodes 21 are formed, for example, to fill the through holes 20X. As the material for the through electrodes 21, for example, copper (Cu) or a copper alloy can be used.

[0013] The core substrate 20 has one or more (in this embodiment, one) openings 20Y that penetrate the core substrate 20 in the thickness direction. Electronic components 22 are housed inside the openings 20Y. A resin portion 23 is filled into the openings 20Y so as to cover the electronic components 22. The resin portion 23 is formed to cover, for example, the bottom surface and sides of the electronic components 22. Examples of electronic components 22 include semiconductor elements, crystal oscillators, and chip components. Examples of chip components include chip capacitors, chip resistors, and chip inductors. Note that the core substrate 20 is not limited to one type of electronic component 22, but may contain multiple types of electronic components 22. As the material for the resin portion 23, an insulating resin such as epoxy resin can be used.

[0014] (Configuration of wiring structure 30) The wiring structure 30 is laminated on the lower surface of the core substrate 20. The wiring structure 30 in this embodiment has a structure in which a wiring layer 31, an insulating layer 32, a wiring layer 33, an insulating layer 34, a wiring layer 35, an insulating layer 36, a wiring layer 37, an insulating layer 38, and a wiring layer 39 are laminated in that order on the lower surface of the core substrate 20.

[0015] For example, copper or copper alloys can be used as the material for the wiring layers 31, 33, 35, 37, and 39. The thickness of each of the wiring layers 31, 33, 35, 37, and 39 can be, for example, about 8 μm to 35 μm.

[0016] The insulating layers 32, 34, 36, and 38 are insulating layers mainly composed of a non-photosensitive resin. The insulating layers 32, 34, 36, and 38 can be mainly composed of thermosetting non-photosensitive resins such as epoxy resins, imide resins, phenolic resins, and cyanate resins. The thickness of each insulating layer 32, 34, 36, and 38 can be, for example, about 35 μm to 100 μm.

[0017] The wiring layer 31 is laminated on the lower surface of the core substrate 20. The wiring layer 31 is electrically connected to the through-electrode 21. The insulating layer 32 is formed on the lower surface of the core substrate 20 so as to cover the wiring layer 31. The wiring layer 33 is laminated on the lower surface of the insulating layer 32. The wiring layer 33 is electrically connected to the wiring layer 31 via via wiring that penetrates the insulating layer 32 in the thickness direction.

[0018] The insulating layer 34 is formed on the lower surface of the insulating layer 32 so as to cover the wiring layer 33. The wiring layer 35 is laminated on the lower surface of the insulating layer 34. The wiring layer 35 is electrically connected to the wiring layer 33 via via wiring that penetrates the insulating layer 34 in the thickness direction. The insulating layer 36 is formed on the lower surface of the insulating layer 34 so as to cover the wiring layer 35. The wiring layer 37 is laminated on the lower surface of the insulating layer 36. The wiring layer 37 is electrically connected to the wiring layer 35 via via wiring that penetrates the insulating layer 36 in the thickness direction. The insulating layer 38 is formed on the lower surface of the insulating layer 36 so as to cover the wiring layer 37. The wiring layer 39 is laminated on the lower surface of the insulating layer 38. The wiring layer 39 is electrically connected to the wiring layer 37 via via wiring that penetrates the insulating layer 38 in the thickness direction.

[0019] (80-layer solder resist configuration) The solder resist layer 80 is the outermost insulating layer provided on the outermost layer (in this case, the bottom layer) of the wiring board 10. The solder resist layer 80 is formed on the underside of the insulating layer 38 so as to cover the bottommost wiring layer 39. The solder resist layer 80 is an insulating layer mainly composed of a photosensitive resin. As the material for the solder resist layer 80, for example, a photosensitive insulating resin mainly composed of a phenolic resin or a polyimide resin can be used.

[0020] The solder resist layer 80 has an opening 80X formed therein to expose a portion of the underside of the bottommost wiring layer 39 as an external connection pad P1. External connection terminals used when mounting the wiring board 10 onto a mounting board such as a motherboard are connected to the external connection pad P1.

[0021] A surface treatment layer 81 is formed on the wiring layer 39 exposed through the opening 80X, if necessary. Examples of surface treatment layers 81 include an Au layer, a Ni / Au layer (a metal layer formed by stacking a Ni layer and an Au layer in that order), and a Ni / Pd / Au layer (a metal layer formed by stacking a Ni layer, a Pd layer, and an Au layer in that order). Here, the Au layer is a metal layer made of Au or an Au alloy, the Ni layer is a metal layer made of Ni or a Ni alloy, and the Pd layer is a metal layer made of Pd or a Pd alloy. For example, metal layers formed by electroless plating (electroless plating layers) can be used for these Au, Ni, and Pd layers. Alternatively, an OSP (Organic Solderability Preservative) film formed by applying an anti-oxidation treatment such as OSP treatment to the surface of the external connection pad P1 can be used as the surface treatment layer 81. For example, an organic film such as an azole compound or an imidazole compound can be used as the OSP film. Furthermore, the wiring layer 39 exposed through the opening 80X (or, if a surface treatment layer 81 is formed on the wiring layer 39, the surface treatment layer 81 itself) may also be used as an external connection terminal.

[0022] (Configuration of wiring structure 40) The wiring structure 40 is laminated on the upper surface of the core substrate 20. The wiring structure 40 has a structure in which a wiring layer 41, an insulating layer 42, a wiring layer 43, an insulating layer 44, an insulating layer 45, a wiring layer 46, an insulating layer 47, a wiring layer 48, an insulating layer 49, an insulating layer 50, a wiring layer 51, an insulating layer 52, and a wiring layer 53 are laminated in that order on the upper surface of the core substrate 20.

[0023] For the wiring layers 41, 43, 46, 48, 51, and 53, for example, copper or copper alloys can be used. The thickness of each wiring layer 41, 43, 46, 48, 51, and 53 can be, for example, about 10 μm to 30 μm.

[0024] The insulating layers 42, 44, 45, 47, 49, 50, and 52 are, for example, insulating layers mainly composed of a non-photosensitive resin. The insulating layers 42, 44, 45, 47, 49, 50, and 52 can be mainly composed of thermosetting non-photosensitive resins such as epoxy resins, imide resins, phenolic resins, and cyanate resins. The insulating layer 52 may be an insulating layer mainly composed of a photosensitive resin, similar to the solder resist layer 80. In this case, the material for the insulating layer 52 can be, for example, a photosensitive insulating resin mainly composed of a phenolic resin or a polyimide resin.

[0025] The wiring layer 41 is laminated on the upper surface of the core substrate 20. Some of the wiring layer 41 is electrically connected to the wiring layer 31 via through electrodes 21. Some of the wiring layer 41 is electrically connected to the electronic components 22. The insulating layer 42 is formed on the upper surface of the core substrate 20 to cover the wiring layer 41. The insulating layer 42 is formed to cover the upper surface of the electronic components 22 and the upper surface of the resin part 23. The thickness from the upper surface of the wiring layer 41 to the upper surface of the insulating layer 42 can be, for example, about 20 μm to 60 μm.

[0026] The wiring layer 43 is laminated on the upper surface of the insulating layer 42. The wiring layer 43 is electrically connected to the wiring layer 41 via via wiring 43V that penetrates the insulating layer 42 in the thickness direction. The wiring layer 43 has a wiring layer 43A and a wiring layer 43B. The wiring layer 43A is located in a position that overlaps with the cavity 40X in a plan view. The wiring layer 43B is located in a position that does not overlap with the cavity 40X in a plan view.

[0027] The insulating layer 44 is formed on the upper surface of the insulating layer 42 so as to cover the wiring layer 43. The insulating layer 44 is formed so as to cover the upper and side surfaces of the wiring layer 43. The thickness from the upper surface of the wiring layer 43 to the upper surface of the insulating layer 44 can be, for example, about 5 μm to 20 μm.

[0028] The insulating layer 45 is laminated on the upper surface of the insulating layer 44. The insulating layer 45 is formed to cover the upper surface of the insulating layer 44. The thickness from the upper surface of the insulating layer 44 to the upper surface of the insulating layer 45 can be, for example, about 20 μm to 45 μm.

[0029] The wiring layer 46 is laminated on the upper surface of the insulating layer 45. The wiring layer 46 is electrically connected to the wiring layer 43B via via wiring 46V that penetrates the insulating layers 44 and 45 in the thickness direction. The wiring layer 46 is positioned so as not to overlap with the cavity 40X in a plan view.

[0030] The insulating layer 47 is formed on the upper surface of the insulating layer 45 so as to cover the wiring layer 46. The thickness from the upper surface of the wiring layer 46 to the upper surface of the insulating layer 47 can be, for example, about 20 μm to 60 μm.

[0031] The wiring layer 48 is laminated on the upper surface of the insulating layer 47. The wiring layer 48 is electrically connected to the wiring layer 46 via via wiring that penetrates the insulating layer 47 in the thickness direction. The wiring layer 48 is positioned so as not to overlap with the cavity 40X in a plan view.

[0032] The insulating layer 49 is formed on the upper surface of the insulating layer 47 so as to cover the wiring layer 48. The thickness from the upper surface of the wiring layer 48 to the upper surface of the insulating layer 49 can be, for example, about 20 μm to 45 μm.

[0033] The cavity 40X is formed in the insulating layers 45, 47, and 49. The cavity 40X is formed to be recessed downward from the upper surface of the insulating layer 49. The cavity 40X is formed to penetrate the insulating layers 45, 47, and 49 in the thickness direction. The cavity 40X is formed in accordance with the embedded electronic component 60. That is, the cavity 40X is formed at the mounting position of the electronic component 60.

[0034] As shown in Figure 2, the cavity 40X of this embodiment is configured such that a through hole 49X penetrates the insulating layer 49 in the thickness direction, a through hole 47X penetrates the insulating layer 47 in the thickness direction, and a through hole 45X penetrates the insulating layer 45 in the thickness direction are in communication with each other. For example, the inner wall surfaces of the through hole 49X, the through hole 47X, and the through hole 45X are formed to be continuous. The through holes 49X, 47X, and 45X are formed, for example, coaxially with each other. That is, the central axes of the through hole 49X, 47X, and 45X have planar positions that coincide with each other. The cavity 40X is formed such that, for example, a part of the upper surface of the insulating layer 44 is exposed. In other words, the bottom surface of the cavity 40X is formed by the upper surface of the insulating layer 44. The depth of the cavity 40X, that is, the thickness from the top surface of the insulating layer 44 to the top surface of the insulating layer 49, can be, for example, about 80 μm to 200 μm.

[0035] The cavity 40X is formed in a tapered shape, for example, in Figure 2, where the opening width decreases from the top (top surface of the insulating layer 49) to the bottom (side of the insulating layer 44). In other words, the cavity 40X is formed so that the upper opening widens relative to the lower opening. The space enclosed by the inner wall surface of the cavity 40X and the bottom surface of the cavity 40X, that is, the internal space of the cavity 40X, becomes a housing space for accommodating the electronic component 60.

[0036] Thus, in the wiring board 10 of this embodiment, the three insulating layers 45, 47, and 49 laminated on the insulating layer 44 serve as insulating layers for cavity formation. Note that in Figure 2, the insulating layer 52, wiring layer 53, and external connection terminals 90 are omitted from the illustration for the sake of simplicity.

[0037] A recess 45Y is formed at the lower end of the insulating layer 45 that constitutes the inner wall surface of the cavity 40X. More specifically, a recess 45Y is formed on the inner wall surface of the cavity 40X that is in contact with the insulating layer 44, causing that inner wall surface to recede into the interior of the insulating layer 45. The recess 45Y is formed to communicate with the cavity 40X. In this way, a recess 45Y is formed at the bottom of the cavity 40X, which widens the opening width of the cavity 40X.

[0038] The recess 45Y is formed, for example, around the entire circumference of the cavity 40X. Alternatively, the recess 45Y may be formed only on a portion of the cavity 40X in the circumferential direction. The dimensions of the recess 45Y along the thickness direction (vertical direction in the figure) of the insulating layer 45, that is, the depth dimension of the recess 45Y, are smaller than, for example, the thickness dimension of the wiring layer 46. The depth dimension of the recess 45Y can be, for example, about 5 μm to 25 μm.

[0039] A metal layer 55 is formed inside the recess 45Y. The metal layer 55 is formed to be in contact with the upper surface of the insulating layer 44. The metal layer 55 is formed to be in contact with the inner surface of the recess 45Y. When the metal layer 55 is formed, the space enclosed by the metal layer 55, the lower surface of the insulating layer 45 exposed from the metal layer 55, and the upper surface of the insulating layer 44 exposed from the metal layer 55 becomes the recess 45Y.

[0040] An opening 44X is formed on the upper surface of the insulating layer 44 exposed from the cavity 40X, penetrating the insulating layer 44 in the thickness direction and exposing a portion of the upper surface of the wiring layer 43A. The opening 44X is formed in a tapered shape, for example, in Figure 2, where the opening width decreases from the upper side (the upper surface side of the insulating layer 44) to the lower side (the wiring layer 43A side).

[0041] Electronic components 60 are mounted on the wiring layer 43A exposed from the cavity 40X and the opening 44X. The wiring layer 43A functions as a conductive pad for mounting electronic components to electrically connect to the electronic components 60.

[0042] A connection terminal 70 is formed on the upper surface of the wiring layer 43A exposed through the opening 44X. The connection terminal 70 is formed to cover the entire upper surface of the wiring layer 43A exposed through the opening 44X. For example, a metal layer such as an Au layer, a Ni layer / Au layer, or a Ni layer / Pd layer / Au layer can be used as the connection terminal 70.

[0043] The connection terminal 70 of this embodiment has a structure in which a first metal layer 71 and a second metal layer 72 are laminated together. The first metal layer 71 is formed to cover the entire upper surface of the wiring layer 43A exposed through the opening 44X. The first metal layer 71 is formed, for example, to fill the opening 44X. The first metal layer 71 is formed, for example, to protrude upward above the upper surface of the insulating layer 44. The portion of the first metal layer 71 that protrudes upward above the upper surface of the insulating layer 44, that is, the first metal layer 71 exposed from the insulating layer 44, is formed, for example, to protrude outward from the opening 44X in a planar direction (left-right direction in the figure) perpendicular to the thickness direction of the insulating layer 44. The side surface of the first metal layer 71 exposed from the insulating layer 44 is formed, for example, an arc-shaped curved surface in cross-sectional view. The side surface of the first metal layer 71 exposed from the insulating layer 44 is curved toward the center of the plane of the first metal layer 71 as it approaches the upper surface of the first metal layer 71. The upper surface of the first metal layer 71 is formed, for example, a plane that extends horizontally along the planar direction. The upper corner of the first metal layer 71, that is, the corner formed by the upper surface and the side surface of the first metal layer 71, is formed as a curved surface in an arc shape when viewed in cross-section. The material of the first metal layer 71 is preferably a conductive material that has higher adhesion to the wiring layer 43A than the metal constituting the second metal layer 72. In this embodiment, the first metal layer 71 is a Ni layer. As the first metal layer 71, for example, an electroless plating layer formed by an electroless plating method can be used.

[0044] The second metal layer 72 is formed to cover the entire surface of the first metal layer 71. The second metal layer 72 is formed to cover the entire upper surface of the first metal layer 71 and the entire side surface of the first metal layer 71. The second metal layer 72 is formed in a shape that conforms to the surface of the first metal layer 71. In this embodiment, the second metal layer 72 is an Au layer. As the second metal layer 72, for example, an electroless plating layer formed by an electroless plating method can be used. The thickness of the first metal layer 71 can be, for example, about 1 μm to 25 μm. The thickness of the second metal layer 72 can be, for example, about 10 nm to 90 nm.

[0045] (Configuration of electronic component 60) Now, let's describe the structure of the electronic component 60. The electronic component 60 has a main body 61, a first electrode 62 provided on the lower surface of the main body 61, a second electrode 63 provided on the upper surface of the main body 61, and a through electrode 64. The electronic component 60 in this embodiment has a plurality of first electrodes 62, a plurality of second electrodes 63, and a plurality of through electrodes 64. The electronic component 60 is flip-chip mounted, for example, on a wiring layer 43A exposed from an opening 44X. Specifically, the first electrode 62 of the electronic component 60 is electrically connected to a connection terminal 70 formed on the upper surface of the wiring layer 43A exposed from the opening 44X. More specifically, the first electrode 62 is electrically connected to the connection terminal 70 via a bonding member 65. Thus, the electronic component 60 is electrically connected to the wiring layer 43A via the first electrode 62, the bonding member 65, and the connection terminal 70. As shown in Figure 1, some of the first electrodes 62 are electrically connected to the electronic component 22 via the bonding member 65, the connection terminal 70, the wiring layer 43A, the via wiring 43V, and the wiring layer 41. In addition, some of the first electrodes 62 are electrically connected to the through electrode 21 via the bonding member 65, the connection terminal 70, the wiring layer 43A, the via wiring 43V, and the wiring layer 41.

[0046] Examples of electronic components 60 include semiconductor elements, crystal oscillators, and chip components. Examples of chip components include chip capacitors, chip resistors, and chip inductors. The electronic components 60 embedded in the wiring board 10 are not limited to one type, but may include multiple types of electronic components 60.

[0047] The main body 61 is formed, for example, in the shape of a rectangular parallelepiped. The thickness of the main body 61 can be, for example, about 50 μm to 200 μm. The main body 61 is formed from, for example, silicon (Si) or silicon carbide (SiC).

[0048] For the materials of the first electrode 62, the second electrode 63, and the through electrode 64, for example, metals such as aluminum (Al) and copper (Cu), or alloys containing at least one metal selected from these metals can be used.

[0049] As shown in Figure 2, the first electrode 62 is formed to protrude downward from, for example, the lower surface of the main body 61. The thickness of the first electrode 62 can be, for example, about 2 μm to 20 μm. The first electrode 62 may also be formed to be embedded in the main body 61.

[0050] The second electrode 63 is provided on the opposite side of the first electrode 62. The second electrode 63 is formed to be embedded in the main body 61, for example. The upper surface of the second electrode 63 is formed to be exposed from the upper surface of the main body 61. The upper surface of the second electrode 63 is formed to be flush with the upper surface of the main body 61, for example. The thickness of the second electrode 63 can be, for example, about 2 μm to 20 μm. The second electrode 63 may also be formed to protrude upward from the upper surface of the main body 61.

[0051] The through electrode 64 is formed to penetrate the main body 61 in the thickness direction. The through electrode 64 extends linearly along the thickness direction of the main body 61, for example. The through electrode 64 electrically connects the first electrode 62 and the second electrode 63 to each other.

[0052] (Configuration of the joining member 65) The bonding member 65 is, for example, bonded to the first electrode 62 and also to the connection terminal 70. The bonding member 65 electrically connects the first electrode 62 and the connection terminal 70. As the bonding member 65, for example, a solder layer can be used. As the material of the solder layer, for example, lead (Pb)-free solder of the tin (Sn)-silver (Ag), Sn-Cu, or Sn-Ag-Cu type can be used. The thickness of the bonding member 65 can be, for example, about 5 μm to 30 μm.

[0053] (Composition of underfill resin 66) An underfill resin 66 is formed between the electronic component 60 and the bottom surface of the cavity 40X. The underfill resin 66 is formed to fill the gap between the lower surface of the main body 61 of the electronic component 60 and the bottom surface of the cavity 40X, in this case the upper surface of the insulating layer 44. The underfill resin 66 is formed to seal the first electrode 62, the bonding member 65, and the connection terminal 70. As the material for the underfill resin 66, an insulating resin such as epoxy resin can be used, for example.

[0054] (Configuration of wiring structure 40) The insulating layer 50 is a filling insulating layer that fills the cavity 40X. The insulating layer 50 is formed to cover the upper surface of the insulating layer 49 and to fill the cavity 40X and cover the electronic component 60. The insulating layer 50 is formed to fill the recess 45Y. The insulating layer 50 is formed to cover the underfill resin 66. The insulating layer 50 is formed, for example, to cover the entire side surface of the underfill resin 66. The insulating layer 50 is formed, for example, to cover the entire bottom surface of the cavity 40X exposed from the underfill resin 66. The insulating layer 50 is formed, for example, to cover the entire inner wall surface of the cavity 40X. The insulating layer 50 is formed, for example, to completely cover the electronic component 60 exposed from the underfill resin 66. For example, the insulating layer 50 is formed to cover the side and top surfaces of the main body 61 exposed from the underfill resin 66. The insulating layer 50 is formed, for example, to cover the upper surface of the second electrode 63.

[0055] The insulating layer 50 is formed, for example, to cover the entire upper surface of the insulating layer 49. Through holes VH1 are formed in the insulating layers 49 and 50 at required locations, penetrating them in the thickness direction and exposing a portion of the upper surface of the wiring layer 48. Through holes VH2 are formed in the insulating layer 50 at required locations, penetrating them in the thickness direction and exposing a portion of the upper surface of the second electrode 63. The through holes VH1 and VH2 are formed in a tapered shape, for example, in Figure 2, where the diameter (opening width) decreases from the top (upper surface side of the insulating layer 49) to the bottom. The through holes VH1 and VH2 are formed in an inverted frustoconical shape, for example, where the opening diameter of the lower opening end is smaller than the opening diameter of the upper opening end. The thickness from the upper surface of the insulating layer 49 to the upper surface of the insulating layer 50 can be, for example, about 15 μm to 45 μm.

[0056] The wiring layer 51 is laminated on the upper surface of the insulating layer 50. The wiring layer 51 has a wiring pattern that is electrically connected to the wiring layer 48 via via wiring filled in through holes VH1, for example. The wiring layer 51 has a wiring pattern that is electrically connected to the second electrode 63 via via wiring filled in through holes VH2, for example. The wiring layer 51 is formed integrally with the via wiring filled in through holes VH1 or VH2, for example. The wiring layer 51 may be routed in a planar direction on the upper surface of the insulating layer 50. Furthermore, the wiring layer 51 connected to the wiring layer 48 and the wiring layer 51 connected to the second electrode 63 may be electrically connected to each other by the wiring layer 51 routed in this manner.

[0057] As shown in Figure 1, the insulating layer 52 is formed to cover the wiring layer 51 on the upper surface of the insulating layer 50. The insulating layer 52 is the outermost insulating layer provided on the outermost layer (in this case, the top layer) of the wiring board 10. The thickness from the upper surface of the wiring layer 51 to the upper surface of the insulating layer 52 can be, for example, about 15 μm to 40 μm.

[0058] The wiring layer 53 is laminated on the upper surface of the insulating layer 52. The wiring layer 53 is electrically connected to the wiring layer 51 via via wiring that penetrates the insulating layer 52 in the thickness direction. The wiring layer 53 is, for example, the outermost (in this case, the topmost) wiring layer of the wiring board 10. The wiring layer 53 functions as a pad for mounting electronic components, for example, electronic components such as semiconductor elements (not shown) for electrical connection.

[0059] If necessary, a surface treatment layer may be formed on the surface (top and side surfaces, or top surface only) of the wiring layer 53. As the surface treatment layer, metal layers such as an Au layer, Ni layer / Au layer, or Ni layer / Pd layer / Au layer, or an OSP film can be used.

[0060] An external connection terminal 90 is provided on the upper surface of the wiring layer 53. For example, a solder ball can be used as the external connection terminal 90. For example, Sn-Ag, Sn-Cu, or Sn-Ag-Cu lead-free solder can be used as the material for the solder ball.

[0061] (Manufacturing method for wiring board 10) Next, the manufacturing method of the wiring board 10 will be described. For the sake of clarity, the parts that will ultimately become components of the wiring board 10 will be denoted by their final component reference numerals.

[0062] First, in the process shown in Figure 3, a structure is formed that includes a core substrate 20 having through holes 20X and openings 20Y, through electrodes 21, electronic components 22, a resin part 23, and wiring layers 41 and 31 formed on the upper and lower surfaces of the core substrate 20, respectively. Since this structure can be manufactured by known manufacturing methods, a detailed explanation is omitted here.

[0063] Next, in the process shown in Figure 4, an insulating layer 32 covering the wiring layer 31 is formed on the lower surface of the core substrate 20, and an insulating layer 42 covering the wiring layer 41 is formed on the upper surface of the core substrate 20. When a resin film is used as the insulating layers 32 and 42, for example, the resin film is laminated to the lower or upper surface of the core substrate 20. Then, the insulating layers 32 and 42 can be formed by heat-treating the resin film at a temperature above the curing temperature (for example, around 130°C to 200°C) while pressing it down and curing it. As the resin film, for example, a thermosetting resin film mainly composed of epoxy resin can be used. Also, when a liquid or paste-like insulating resin is used as the insulating layers 32 and 42, the liquid or paste-like insulating resin is applied to the lower or upper surface of the core substrate 20 by a spin-coating method or the like. Then, the insulating layers 32 and 42 can be formed by heat-treating the applied insulating resin at a temperature above the curing temperature and curing it. As the liquid or paste-like insulating resin, for example, a thermosetting resin mainly composed of epoxy resin can be used.

[0064] Next, through holes 32X are formed at predetermined locations in the insulating layer 32 so that a portion of the lower surface of the wiring layer 31 is exposed, and through holes 42X are formed at predetermined locations in the insulating layer 42 so that a portion of the upper surface of the wiring layer 41 is exposed. The through holes 32X and 42X can be formed by laser processing methods, such as using a CO2 laser or a UV-YAG laser.

[0065] Next, if the through holes 32X and 42X are formed by laser processing, a desmear treatment is performed to remove the resin smear adhering to the exposed surfaces of the wiring layers 31 and 41 exposed at the bottom of the through holes 32X and 42X. As an example of the desmear treatment in this step, a wet desmear treatment using a potassium permanganate solution or the like can be used.

[0066] The following section details the manufacturing method of the structure formed on the upper surface of the core substrate 20, that is, the structure shown in Figure 2. In the process shown in Figure 5, a seed layer 91 is formed so as to cover the entire upper surface of the insulating layer 42 and the entire inner surface of the through-hole 42X. The seed layer 91 can be formed, for example, by sputtering or electroless plating. For example, when forming the seed layer 91 by sputtering, first, titanium (Ti) is deposited by sputtering on the upper surface of the insulating layer 42 and the inner surface of the through-hole 42X to form a Ti layer. Then, copper is deposited on the Ti layer by sputtering to form a Cu layer. This makes it possible to form a seed layer 91 with a two-layer structure (Ti layer / Cu layer). Alternatively, when forming the seed layer 91 by electroless plating, for example, a seed layer 91 consisting of a Cu layer (single-layer structure) can be formed by electroless copper plating.

[0067] Next, a resist layer 100 having an opening pattern 100X at a predetermined location is formed on the seed layer 91. The opening pattern 100X is formed so as to expose the portion of the seed layer 91 corresponding to the formation area of ​​the wiring layer 43 (see Figure 2). As the material for the resist layer 100, for example, a material that is resistant to plating in the subsequent electroplating process can be used. For example, as the material for the resist layer 100, a photosensitive dry film resist or a liquid photoresist (for example, a dry film resist or liquid resist such as a novolac resin or acrylic resin) can be used. When using a photosensitive dry film resist, the dry film is laminated to the upper surface of the seed layer 91 by thermocompression, and the dry film is patterned by photolithography to form a resist layer 100 having an opening pattern 100X. Note that when using a liquid photoresist, the resist layer 100 can also be formed by a similar process.

[0068] Next, in the process shown in Figure 6, the resist layer 100 is used as a plating mask, and an electrolytic plating method is applied to the seed layer 91, utilizing the seed layer 91 as a plating power supply layer. That is, an electrolytic plating method, in this case an electrolytic Cu plating method, is applied to the upper surface of the seed layer 91 exposed from the opening pattern 100X of the resist layer 100. This process forms a metal layer 92 that fills the through-holes 42X inside the seed layer 91, and a metal layer 93 provided inside the opening pattern 100X.

[0069] Next, in the process shown in Figure 7, the resist layer 100 shown in Figure 6 is removed using an alkaline stripping solution (for example, an organic amine-based stripping solution, caustic soda, acetone, or ethanol). Next, in the process shown in Figure 8, the unnecessary seed layer 91 is removed by etching using the metal layer 93 as an etching mask. In this process, via wiring 43V that fills the through hole 42X is formed by the seed layer 91 and the metal layer 92 formed inside the through hole 42X, and a wiring layer 43 composed of the seed layer 91 and the metal layer 93 is formed on the upper surface of the insulating layer 42. At this time, the wiring layer 43 has a wiring layer 43A that is located in a position that overlaps with the cavity 40X (see Figure 2) formed in a later process in a plan view, and a wiring layer 43B that is located in a position that does not overlap with the cavity 40X in a plan view. In Figures 9 to 20 thereafter, the seed layer 91 and the metal layers 92 and 93 are not shown, and the via wiring 43V and wiring layer 43 are shown as a single layer.

[0070] Next, in the process shown in Figure 9, an insulating layer 44 covering the wiring layer 43 is laminated on the upper surface of the insulating layer 42. The insulating layer 44 is formed to cover the entire upper surface and entire side surface of the wiring layer 43A, and the entire upper surface and entire side surface of the wiring layer 43B. The insulating layer 44 is formed so that the thickness of the portion covering the upper surface of the wiring layer 43 is reduced, specifically so that the thickness of the portion covering the upper surface of the wiring layer 43 is about 5 μm to 20 μm. For example, after forming the insulating layer 44 in the same manner as the insulating layer 42, the insulating layer 44 may be thinned from the upper side by CMP (Chemical Mechanical Polishing) or ashing (dry etching using oxygen plasma).

[0071] Next, in the process shown in Figure 10, a metal layer 55 is formed on the upper surface of the insulating layer 44. The metal layer 55 is positioned to overlap with the wiring layer 43A in a plan view. The metal layer 55 is provided in a portion corresponding to the formation area of ​​the cavity 40X (see Figure 2) that is formed in a later process. The metal layer 55 functions as a barrier layer to protect the wiring layer 43A, which is provided below the insulating layer 44. For example, copper or a copper alloy can be used as the material for the metal layer 55. Alternatively, a metal different from the metal constituting the wiring layer 43, such as nickel or a nickel alloy, can be used as the material for the metal layer 55.

[0072] Next, an insulating layer 45 is laminated onto the upper surface of the insulating layer 44 to cover the metal layer 55. At this time, the insulating layer 45 is formed to cover the entire upper surface and the entire side surface of the metal layer 55. Next, in the process shown in Figure 11, a wiring layer 46 is laminated on the upper surface of the insulating layer 45 by performing the same process as in Figures 5 to 8. The wiring layer 46 is electrically connected to the wiring layer 43B via via wiring 46V that penetrates the insulating layer 44 and the insulating layer 45 in the thickness direction.

[0073] Next, in the process shown in Figure 12, the same process as in Figures 4 to 8 is performed to laminate the insulating layer 47 and the wiring layer 48 on the upper surface of the insulating layer 45. Furthermore, an insulating layer 49 that covers the wiring layer 48 is laminated on the upper surface of the insulating layer 47. At this time, the insulating layer 49 is formed to cover the entire upper surface and the entire side surface of the wiring layer 48.

[0074] Next, in the process shown in Figure 13, a cavity 40X is formed that is recessed from the upper surface of the insulating layer 49 toward the insulating layer 44, so that the upper surface of the metal layer 55 is exposed. Specifically, a through hole 49X is formed that penetrates the insulating layer 49 in the thickness direction, a through hole 47X is formed that communicates with the through hole 49X and penetrates the insulating layer 47 in the thickness direction, and a through hole 45X is formed that communicates with the through hole 47X and penetrates the insulating layer 45 in the thickness direction. In other words, a cavity 40X is formed that penetrates multiple insulating layers 45, 47, and 49 in the thickness direction, exposing a part of the upper surface of the metal layer 55. At this time, the planar size of the cavity 40X is formed to be slightly smaller than the planar size of the metal layer 55. For this reason, the peripheral portion of the metal layer 55 is covered by the insulating layer 45. The through holes 45X, 47X, and 49X can be formed by laser processing methods such as a CO2 laser or a UV-YAG laser. In this case, the metal layer 55 functions as a stopper layer for laser processing. This effectively prevents damage to the insulating layer 44 and the wiring layer 43A, which are located beneath the insulating layer 45, due to excessive laser processing, for example.

[0075] Next, the metal layer 55 is removed by etching. For example, the insulating layers 45, 47, and 49 are used as etching masks, and the metal layer 55 is removed by isotropic etching. This isotropic etching removes the metal layer 55 covering the insulating layer 45 due to the side-etch phenomenon, where the etching progresses in the in-plane direction of the metal layer 55. As a result, as shown in Figure 14, a recess 45Y is formed at the lower end of the insulating layer 45 that constitutes the inner wall surface of the through hole 45X. At this time, depending on the etching conditions of this step, the metal layer 55 that covered the insulating layer 45 may be completely removed, or a portion of the metal layer 55 that covered the insulating layer 45 may remain, as shown in Figure 14.

[0076] Next, in the process shown in Figure 15, an opening 44X is formed at a predetermined location on the upper surface of the insulating layer 44 exposed at the bottom of the cavity 40X, such that a portion of the upper surface of the wiring layer 43A is exposed. The opening 44X is formed to penetrate the insulating layer 44 in the thickness direction and expose a portion of the upper surface of the wiring layer 43A. The opening 44X can be formed, for example, by a laser processing method using a CO2 laser or a UV-YAG laser.

[0077] Next, if the opening 44X is formed by laser processing, a desmear treatment is performed to remove the resin smear adhering to the exposed surface of the wiring layer 43A exposed at the bottom of the opening 44X. As an example of the desmear treatment in this step, a wet desmear treatment using a potassium permanganate solution or the like can be used.

[0078] Next, in the process shown in Figure 16, a connection terminal 70 is formed on the upper surface of the wiring layer 43A exposed from the opening 44X. The connection terminal 70 fills the opening 44X and is formed to protrude above the upper surface of the insulating layer 44. The connection terminal 70 can be formed, for example, by an electroless plating method. In detail, first, a first metal layer 71 (Ni layer) is formed by an electroless plating method (here, an electroless Ni plating method) to fill the opening 44X and protrude above the upper surface of the insulating layer 44. Subsequently, a second metal layer 72 (Au layer) is formed by an electroless plating method (here, an electroless Au plating method) to cover the entire surface of the first metal layer 71 exposed from the insulating layer 44.

[0079] Next, in the process shown in Figure 17, an electronic component 60 having a main body 61, a first electrode 62, a second electrode 63, and a through electrode 64 is prepared. Then, the electronic component 60 is mounted on the connection terminal 70 inside the cavity 40X. Specifically, the first electrode 62 of the electronic component 60 is joined to the connection terminal 70 formed on the surface of the wiring layer 43A via a bonding member 65. For example, if the bonding member 65 is a solder layer, flux (not shown) is applied to the connection terminal 70 as appropriate, and the connection terminal 70 and the first electrode 62 are aligned with the bonding member 65 in between. After that, a reflow process is performed at a temperature of about 230°C to 260°C. This melts the bonding member 65, which is a solder layer, and electrically connects the connection terminal 70 and the first electrode 62 via the bonding member 65. After that, underfill resin 66 is filled between the bottom surface of the cavity 40X and the bottom surface of the main body 61 of the electronic component 60 and cured. Furthermore, the underfill resin 66 can be pre-applied to the underside of the main body 61 of the electronic component 60, and then filled to the bottom of the cavity 40X when mounting the electronic component 60.

[0080] Next, in the process shown in Figure 18, the same process as in Figure 4 is performed to cover the upper surface of the insulating layer 49 and to form an insulating layer 50 that fills the cavity 40X. The insulating layer 50 is formed to cover the entire side surface of the underfill resin 66 and the entire surface of the electronic components 60 exposed from the underfill resin 66. The insulating layer 50 is formed to fill the recess 45Y. In this process, the side and top surfaces of the wiring layer 43A are covered by the insulating layer 44. Therefore, the cavity 40X can be formed shallower compared to the case where the side and top surfaces of the wiring layer 43A are exposed from the insulating layer 44. As a result, the volume of the cavity 40X can be reduced, and the filling performance of the insulating layer 50 into the cavity 40X can be improved. As a result, the generation of voids (air bubbles) in the insulating layer 50 can be suitably suppressed.

[0081] Next, in the process shown in Figure 19, by performing the same process as in Figure 4, through-holes VH1 are formed at predetermined locations in the insulating layers 49 and 50, penetrating the insulating layers 49 and 50 in the thickness direction and exposing a portion of the upper surface of the wiring layer 48. In addition, through-holes VH2 are formed at predetermined locations in the insulating layer 50, penetrating the insulating layer 50 in the thickness direction and exposing a portion of the upper surface of the second electrode 63.

[0082] Next, in the process shown in Figure 20, a via wiring that fills the through hole VH1 is formed by performing the same process as in Figures 5 to 8, and a wiring layer 51 that is electrically connected to the wiring layer 48 via the via wiring is laminated on the upper surface of the insulating layer 50. In addition, a via wiring that fills the through hole VH2 is formed, and a wiring layer 51 that is electrically connected to the second electrode 63 via the via wiring is laminated on the upper surface of the insulating layer 50.

[0083] The structure shown in Figure 2 can be manufactured through the above manufacturing process. Subsequently, the wiring board 10 of this embodiment can be manufactured by forming the insulating layer 52, wiring layer 53, etc., shown in Figure 1.

[0084] In this embodiment, insulating layer 42 is an example of a first insulating layer, wiring layer 43A is an example of a first wiring layer, wiring layer 43B is an example of a second wiring layer, insulating layer 44 is an example of a second insulating layer, the upper surface of insulating layer 44 is an example of a first surface, and insulating layers 45, 47, and 49 are examples of N-layer insulating layers. In addition, insulating layer 50 is an example of a fill insulating layer, wiring layer 51 is an example of a third wiring layer, insulating layer 45 is an example of a third insulating layer, wiring layer 46 is an example of a fourth wiring layer, and recess 45Y is an example of a first recess.

[0085] (Effects of the first embodiment) Next, the effects and advantages of this embodiment will be explained. (1-1) The wiring board 10 has an insulating layer 42, wiring layers 43A and 43B laminated on the upper surface of the insulating layer 42, and an insulating layer 44 formed on the upper surface of the insulating layer 42 so as to cover the sides and top of the wiring layer 43A and the sides and top of the wiring layer 43B. The wiring board 10 has N layers (here, 3 layers) of insulating layers 45, 47, and 49 laminated on the upper surface of the insulating layer 44, and a cavity 40X formed in the 3 layers of insulating layers 45, 47, and 49, and formed so as to expose the upper surface of the insulating layer 44. The wiring board 10 has an opening 44X formed on the upper surface of the insulating layer 44 exposed from the cavity 40X, which penetrates the insulating layer 44 in the thickness direction and exposes a part of the upper surface of the wiring layer 43A, and a connection terminal 70 formed on the upper surface of the wiring layer 43A exposed from the opening 44X. The wiring board 10 is placed within the cavity 40X and has electronic components 60 mounted on connection terminals 70, and an insulating layer 50 that fills the cavity 40X and covers the electronic components 60. The wiring board 10 has a wiring layer 51 that is laminated on the upper surface of the insulating layer 50 and is electrically connected to the electronic components 60. The wiring layer 43A is provided in a position that overlaps with the cavity 40X in a plan view. The wiring layer 43B is provided in a position that does not overlap with the cavity 40X in a plan view.

[0086] In this configuration, the sides and top surface of the wiring layer 43A are covered by the insulating layer 44 at the bottom of the cavity 40X. Therefore, the cavity 40X can be formed shallower compared to the case where the cavity 40X is formed so that the sides and top surface of the wiring layer 43A are exposed from the insulating layer 44. As a result, the volume of the cavity 40X can be reduced, and thus the filling of the insulating layer 50 into the cavity 40X can be improved. As a result, the inclusion of voids into the insulating layer 50 can be effectively suppressed. Furthermore, because the filling of the insulating layer 50 into the cavity 40X can be improved, the flatness of the top surface of the insulating layer 50 can be improved.

[0087] (1-2) The insulating layer 44 covering the sides and top of the wiring layer 43B, which is located in a position that does not overlap with the cavity 40X in a plan view, covers the sides and top of the wiring layer 43A, which is located in a position that overlaps with the cavity 40X in a plan view. Therefore, the structure of the wiring board 10 can be simplified compared to the case where the insulating layer covering the sides and top of the wiring layer 43A and the insulating layer covering the sides and top of the wiring layer 43B are separate components. As a result, for example, the manufacturing process when manufacturing the wiring board 10 can be reduced.

[0088] (1-3) The method for manufacturing the wiring board 10 includes the steps of laminating wiring layers 43A and 43B on the upper surface of the insulating layer 42, and forming an insulating layer 44 on the upper surface of the insulating layer 42 that covers the sides and top surfaces of the wiring layers 43A and 43B. The method for manufacturing the wiring board 10 includes the steps of forming a metal layer 55 on the upper surface of the insulating layer 44 at a position that overlaps with the wiring layer 43A in a plan view, and forming N layers (in this case, 3 layers) of insulating layers 45, 47, and 49 on the upper surface of the insulating layer 44 so as to cover the metal layer 55. The method for manufacturing the wiring board 10 includes the steps of forming a cavity 40X that exposes the upper surface of the metal layer 55 in the 3 layers of insulating layers 45, 47, and 49 by laser processing, and removing the metal layer 55. The method for manufacturing the wiring board 10 includes the step of forming an opening 44X on the upper surface of an insulating layer 44 exposed at the bottom of the cavity 40X, which penetrates the insulating layer 44 in the thickness direction and exposes a part of the upper surface of the wiring layer 43A. The method for manufacturing the wiring board 10 includes the step of forming a connection terminal 70 on the upper surface of the wiring layer 43A exposed through the opening 44X, and the step of mounting an electronic component 60 on the connection terminal 70 within the cavity 40X. The method for manufacturing the wiring board 10 includes the step of filling the cavity 40X and forming an insulating layer 50 that covers the electronic component 60, and the step of laminating a wiring layer 51 on the upper surface of the insulating layer 50.

[0089] In this configuration, a metal layer 55, which functions as a barrier layer, is formed on the upper surface of the insulating layer 44 that covers the upper and side surfaces of the wiring layer 43A. Therefore, the metal layer 55 is formed so as not to be in direct contact with the upper and side surfaces of the wiring layer 43A. This makes the process of forming the metal layer 55 and the process of removing the metal layer 55 simpler compared to the case where the barrier layer is formed in direct contact with the upper and side surfaces of the wiring layer 43A. Furthermore, in the process of removing the metal layer 55, the upper and side surfaces of the wiring layer 43A are covered by the insulating layer 44. Therefore, when removing the metal layer 55 by etching or the like, etching of a portion of the upper and side surfaces of the wiring layer 43A can be effectively suppressed.

[0090] (1-4) The wiring board 10 has a wiring layer 46 which is laminated on the upper surface of the insulating layer 45 and electrically connected to the wiring layer 43B via via wiring 46V that penetrates the insulating layer 44 and the insulating layer 45 in the thickness direction. With this configuration, two insulating layers 44 and 45 are interposed between the wiring layer 43B and the wiring layer 46. Therefore, even when a predetermined thickness is required between the wiring layer 43B and the wiring layer 46, the insulating layer 44 covering the upper surfaces of the wiring layers 43A and 43B can be made thinner compared to the case where only one insulating layer 44 is formed between the wiring layer 43B and the wiring layer 46. As a result, the thickness from the upper surfaces of the wiring layers 43A and 43B to the upper surface of the insulating layer 44 can be made thinner, and the opening 44X can be made shallower. As a result, for example, the connection terminal 70 formed in the opening 44X can be easily formed to protrude upward from the upper surface of the insulating layer 44.

[0091] (Second Embodiment) The second embodiment will be described below with reference to Figures 21 to 31. The following description will focus on the differences from the first embodiment. Components identical to those shown in Figures 1 to 20 will be denoted by the same reference numerals, and detailed explanations of each of these elements will be omitted.

[0092] As shown in Figure 21, the wiring structure 40A of the wiring board 10A has a structure in which a wiring layer 41, an insulating layer 42, a wiring layer 43, an insulating layer 44A, a wiring layer 46, an insulating layer 47, a wiring layer 48, an insulating layer 49, an insulating layer 50, and a wiring layer 51 are stacked in that order. The wiring structure 40A has a cavity 40Y in which an electronic component 60 is housed.

[0093] The insulating layer 44A is formed on the upper surface of the insulating layer 42 so as to cover the wiring layer 43. The insulating layer 44A is formed to cover the upper and side surfaces of the wiring layer 43A, which is located in a position that overlaps with the cavity 40Y in a plan view, and to cover the upper and side surfaces of the wiring layer 43B, which is located in a position that does not overlap with the cavity 40Y in a plan view. The insulating layer 44A is formed to be thicker than, for example, the insulating layer 44 of the first embodiment. The thickness from the upper surface of the wiring layer 43 to the upper surface of the insulating layer 44A is formed to be thicker than, for example, the thickness from the upper surface of the wiring layer 43 to the upper surface of the insulating layer 44 shown in Figure 2. The thickness from the upper surface of the wiring layer 43 to the upper surface of the insulating layer 44A can be, for example, about 20 μm to 60 μm.

[0094] The wiring layer 46 is laminated on the upper surface of the insulating layer 44A. The wiring layer 46 is electrically connected to the wiring layer 43B via via wiring 46W that penetrates the insulating layer 44A in the thickness direction. The wiring layer 46 is positioned so as not to overlap with the cavity 40Y in a plan view. The insulating layer 47 is formed on the upper surface of the insulating layer 44A so as to cover the wiring layer 46.

[0095] Cavity 40Y is formed in insulating layers 47 and 49. Cavity 40Y is formed to be recessed downward from the upper surface of insulating layer 49. Cavity 40Y is formed to penetrate insulating layers 47 and 49 in the thickness direction.

[0096] In this embodiment, the cavity 40Y is configured such that a through-hole 49X penetrating the insulating layer 49 in the thickness direction and a through-hole 47X penetrating the insulating layer 47 in the thickness direction are in communication with each other. The cavity 40Y is formed such that, for example, a part of the upper surface of the insulating layer 44A is exposed. In other words, the bottom surface of the cavity 40Y is formed by the upper surface of the insulating layer 44A. The depth of the cavity 40Y, that is, the thickness from the upper surface of the insulating layer 44A to the upper surface of the insulating layer 49, can be, for example, about 60 μm to 150 μm.

[0097] The cavity 40Y is formed in a tapered shape, for example, in Figure 21, where the opening width decreases from the top side (the top surface side of the insulating layer 49) to the bottom side (the side of the insulating layer 44A). In other words, the cavity 40Y is formed so that the upper opening widens relative to the lower opening.

[0098] Thus, in the wiring board 10A of this example, the two insulating layers 47 and 49 laminated on the insulating layer 44A serve as insulating layers for cavity formation. A recess 47Y is formed at the lower end of the insulating layer 47 that constitutes the inner wall surface of the cavity 40Y. More specifically, a recess 47Y is formed on the inner wall surface of the cavity 40Y that is in contact with the insulating layer 44A, causing that inner wall surface to recede into the interior of the insulating layer 47. The recess 47Y is formed to communicate with the cavity 40Y. In this way, a recess 47Y is formed at the bottom of the cavity 40Y to widen the opening width of the cavity 40Y.

[0099] The recess 47Y is formed, for example, around the entire circumference of the cavity 40Y. Alternatively, the recess 47Y may be formed only on a portion of the cavity 40Y in the circumferential direction. The dimensions of the recess 47Y along the thickness direction (vertical direction in the figure) of the insulating layer 47, that is, the depth dimension of the recess 47Y, are set to be approximately the same size as the thickness dimension of the wiring layer 46. The depth dimension of the recess 47Y can be, for example, about 5 μm to 35 μm.

[0100] A metal layer 55 is formed inside the recess 47Y, for example. The metal layer 55 is formed to be in contact with the upper surface of the insulating layer 44A. The metal layer 55 is formed to be in contact with the inner surface of the recess 47Y. When the metal layer 55 is formed, the space enclosed by the metal layer 55, the lower surface of the insulating layer 47 exposed from the metal layer 55, and the upper surface of the insulating layer 44A exposed from the metal layer 55 becomes the recess 47Y.

[0101] An opening 44Y is formed on the upper surface of the insulating layer 44A exposed from the cavity 40Y, penetrating the insulating layer 44A in the thickness direction and exposing a portion of the upper surface of the wiring layer 43A. The opening 44Y is formed deeper than, for example, the opening 44X in the first embodiment. For example, in Figure 21, the opening 44Y is formed in a tapered shape, with the opening width decreasing from the upper side (upper surface side of the insulating layer 44A) to the lower side (side of the wiring layer 43A).

[0102] A connection terminal 70 is formed on the upper surface of the wiring layer 43A exposed through the opening 44Y. In this embodiment, the connection terminal 70 has a structure in which a first metal layer 71 and a second metal layer 72 are laminated together.

[0103] The first metal layer 71 is formed to cover the entire upper surface of the wiring layer 43A exposed from the opening 44Y. The first metal layer 71 is formed, for example, to fill the lower part of the opening 44Y. The upper surface of the first metal layer 71 is provided, for example, in a recessed position below the upper surface of the insulating layer 44A. The upper surface of the first metal layer 71 is formed, for example, as a plane that extends horizontally along the plane direction. The second metal layer 72 is formed to cover the entire upper surface of the first metal layer 71. The second metal layer 72 is provided, for example, inside the opening 44Y.

[0104] The electronic component 60 is flip-chip mounted on a wiring layer 43A exposed from, for example, a cavity 40Y and an opening 44Y. Specifically, the first electrode 62 of the electronic component 60 is electrically connected to a connection terminal 70 formed on the upper surface of the wiring layer 43A exposed from the opening 44Y. More specifically, the first electrode 62 is electrically connected to the connection terminal 70 via a bonding member 65. Thus, the electronic component 60 is electrically connected to the wiring layer 43A via the first electrode 62, the bonding member 65, and the connection terminal 70. Here, the bonding member 65 is formed to fill the opening 44Y exposed from the connection terminal 70, for example.

[0105] The underfill resin 66 is formed to fill the gap between the lower surface of the main body 61 of the electronic component 60 and the bottom surface of the cavity 40Y, in this case the upper surface of the insulating layer 44A. The underfill resin 66 is formed, for example, to seal the first electrode 62 and the bonding member 65.

[0106] The insulating layer 50 is formed to fill the cavity 40Y and the recess 47Y. The insulating layer 50 is formed to cover the entire upper surface of the insulating layer 49. Although not shown in the diagram, similar to the wiring board 10 shown in Figure 1, an insulating layer 52 and a wiring layer 53 are sequentially stacked on the upper surface of the insulating layer 50 of the wiring board 10A, and an external connection terminal 90 is formed on the upper surface of the wiring layer 53.

[0107] (Manufacturing method for wiring board 10A) Next, the manufacturing method of the wiring board 10A will be described. For the sake of clarity, the parts that will ultimately become components of the wiring board 10A will be labeled with their final component reference numerals.

[0108] In the process shown in Figure 22, a structure is formed in which a wiring layer 43 is laminated on the upper surface of an insulating layer 42 by performing the same process as in Figures 4 to 8. Subsequently, an insulating layer 44A is laminated on the upper surface of the insulating layer 42 to cover the wiring layer 43. The insulating layer 44A is formed to be thicker than, for example, the insulating layer 44 shown in Figure 9.

[0109] Next, in the process shown in Figure 23, the same process as in Figures 5 to 8 is performed to form the wiring layer 46 and the metal layer 55 on the upper surface of the insulating layer 44A. The wiring layer 46 and the metal layer 55 are formed simultaneously, for example, in the same process. The wiring layer 46 is electrically connected to the wiring layer 43A via via wiring 46W that penetrates the insulating layer 44A in the thickness direction. The metal layer 55 is provided in a position that overlaps with the wiring layer 43A in a plan view. The metal layer 55 is provided in a portion corresponding to the formation area of ​​the cavity 40Y (see Figure 21) that is formed in a later process. The metal layer 55 functions as a barrier layer that protects the wiring layer 43A, which is provided in the layer below the insulating layer 44A.

[0110] Next, in the process shown in Figure 24, an insulating layer 47 covering the wiring layer 46 and the metal layer 55 is laminated on the upper surface of the insulating layer 44A. Next, in the process shown in Figure 25, the wiring layer 48 and the insulating layer 49 are laminated on the upper surface of the insulating layer 47. At this time, the insulating layer 49 is formed to cover the entire upper surface and the entire side surface of the wiring layer 48.

[0111] Next, in the process shown in Figure 26, a cavity 40Y is formed that is recessed from the upper surface of the insulating layer 49 toward the insulating layer 44A, by performing the same process as in Figure 13, so that the upper surface of the metal layer 55 is exposed. Specifically, a through hole 49X is formed that penetrates the insulating layer 49 in the thickness direction, and a through hole 47X is formed that communicates with the through hole 49X and penetrates the insulating layer 47 in the thickness direction. That is, a cavity 40Y is formed that penetrates multiple insulating layers 47 and 49 in the thickness direction, exposing a part of the upper surface of the metal layer 55. At this time, the planar size of the cavity 40Y is formed to be slightly smaller than the planar size of the metal layer 55. For this reason, the peripheral edge of the metal layer 55 is covered by the insulating layer 47. In this process, the metal layer 55 functions as a stopper layer for laser processing.

[0112] Next, in the process shown in Figure 27, the metal layer 55 is removed by etching by performing the same process as in Figure 14. This process forms a recess 47Y at the lower end of the insulating layer 47 that constitutes the inner wall surface of the through hole 47X.

[0113] Next, in the process shown in Figure 28, an opening 44Y is formed at a predetermined location on the upper surface of the insulating layer 44A exposed at the bottom of the cavity 40Y by performing the same process as in Figure 15, such that a portion of the upper surface of the wiring layer 43A is exposed.

[0114] Next, if the opening 44Y is formed by laser processing, desmear treatment is performed to remove the resin smear adhering to the exposed surface of the wiring layer 43A exposed at the bottom of the opening 44Y.

[0115] Next, in the process shown in Figure 29, a connection terminal 70 is formed on the upper surface of the wiring layer 43A exposed through the opening 44Y by performing the same process as in Figure 16. The connection terminal 70 is formed to fill the lower part of the opening 44Y.

[0116] Next, in the process shown in Figure 30, the same process as in Figure 17 is performed to mount the electronic component 60 on the connection terminal 70 within the cavity 40Y. After that, underfill resin 66 is filled between the bottom surface of the cavity 40Y and the bottom surface of the main body 61 of the electronic component 60 and cured. Alternatively, the underfill resin 66 can be applied to the bottom surface of the main body 61 of the electronic component 60 in advance and then filled to the bottom surface of the cavity 40Y when mounting the electronic component 60.

[0117] Next, in the process shown in Figure 31, an insulating layer 50 that fills the cavity 40Y is formed by performing the same process as shown in Figures 18 to 20, and a wiring layer 51 is laminated on the upper surface of the insulating layer 50.

[0118] The structure shown in Figure 21 can be manufactured through the above manufacturing process. In this embodiment, insulating layer 42 is an example of a first insulating layer, wiring layer 43A is an example of a first wiring layer, wiring layer 43B is an example of a second wiring layer, insulating layer 44A is an example of a second insulating layer, the upper surface of insulating layer 44A is an example of a first surface, and insulating layers 47 and 49 are examples of insulating layers of layer N. In addition, insulating layer 47 is an example of a fourth insulating layer, insulating layer 50 is an example of a filling insulating layer, wiring layer 51 is an example of a third wiring layer, wiring layer 46 is an example of a fourth wiring layer, and recess 47Y is an example of a third recess.

[0119] (Effects of the second embodiment) According to the embodiments described above, in addition to the effects (1-1) to (1-3) of the first embodiment, the following effects can be achieved.

[0120] (2-1) The wiring board 10A is laminated on the upper surface of the insulating layer 44A and has a wiring layer 46 which is electrically connected to the wiring layer 43B via via wiring 46W that penetrates the insulating layer 44A in the thickness direction. The insulating layer 47 is formed to cover the wiring layer 46.

[0121] In this configuration, one insulating layer 44A is interposed between the wiring layer 43B and the wiring layer 46. Therefore, the structure of the wiring board 10A can be simplified compared to the case where multiple insulating layers are formed between the wiring layer 43B and the wiring layer 46. This makes it possible to reduce the manufacturing process when producing the wiring board 10A, for example.

[0122] (Third embodiment) The third embodiment will be described below with reference to Figures 32 to 38. The following description will focus on the differences from the second embodiment. Components identical to those shown in Figures 1 to 31 will be denoted by the same reference numerals, and detailed explanations of each of these elements will be omitted.

[0123] As shown in Figure 32, the wiring structure 40A of the wiring board 10B has a cavity 40Y in which an electronic component 60 is housed. The cavity 40Y in this embodiment is formed to be recessed from the upper surface of the insulating layer 49 to an intermediate position in the thickness direction of the insulating layer 44A. The cavity 40Y in this embodiment is configured by communicating a through hole 49X that penetrates the insulating layer 49 in the thickness direction, a through hole 47X that penetrates the insulating layer 47 in the thickness direction, and a recess 44Z formed on the upper surface of the insulating layer 44A. The inner wall surface of the recess 44Z is formed to extend, for example, perpendicular to the upper surface of the insulating layer 44A. Alternatively, the inner wall surface of the recess 44Z may be formed as an inclined surface that slopes toward the center of the plane of the recess 44Z as it approaches the bottom surface of the recess 44Z. The bottom surface of the recess 44Z, that is, the bottom surface of the cavity 40Y, is located at an intermediate position in the thickness direction of the insulating layer 44A. The bottom surface of cavity 40Y is located above the top surface of wiring layer 43A and below the bottom surface of wiring layer 46.

[0124] Thus, in the wiring board 10B of this embodiment, the three insulating layers 44A, 47, and 49 laminated on the bottom insulating layer 42 of the wiring structure 40A serve as insulating layers for cavity formation. In this embodiment, the recess 47Y is located at an intermediate position on the inner wall surface of the cavity 40Y. The recess 47Y is located above the recess 44Z. In other words, the recess 44Z is formed to recess downward from the recess 47Y. Inside the recess 47Y, for example, a metal layer 55 is formed.

[0125] An opening 44Y is formed at the bottom of the recess 44Z, penetrating the insulating layer 44A in the thickness direction and exposing a portion of the upper surface of the wiring layer 43A. The opening 44Y is formed to be shallower than, for example, the opening 44Y of the second embodiment by the depth of the recess 44Z. For example, in Figure 32, the opening 44Y is formed in a tapered shape, with the opening width decreasing from the top side (bottom surface side of recess 44Z) to the bottom side (wiring layer 43A side).

[0126] A connection terminal 70 is formed on the upper surface of the wiring layer 43A exposed through the opening 44Y. The first metal layer 71 is formed, for example, to fill the opening 44Y. The first metal layer 71 is formed, for example, to protrude upward from the bottom surface of the recess 44Z. The second metal layer 72 is formed to cover the entire surface of the first metal layer 71.

[0127] The electronic component 60 is flip-chip mounted, for example, on a wiring layer 43A exposed from the cavity 40Y and the opening 44Y. The underfill resin 66 is formed to fill the gap between the lower surface of the main body 61 of the electronic component 60 and the bottom surface of the cavity 40Y, in this case the bottom surface of the recess 44Z.

[0128] The insulating layer 50 is formed to fill the cavity 40Y and the recess 47Y. The insulating layer 50 is formed to fill the through holes 47X and 49X and the recess 44Z. The insulating layer 50 is formed to cover the entire upper surface of the insulating layer 49.

[0129] Although not shown in the diagram, similar to the wiring board 10 shown in Figure 1, an insulating layer 52 and a wiring layer 53 are sequentially laminated on the upper surface of the insulating layer 50 of the wiring board 10B, and an external connection terminal 90 is formed on the upper surface of the wiring layer 53.

[0130] (Manufacturing method for wiring board 10B) Next, the manufacturing method of the wiring board 10B will be described. For the sake of clarity, the parts that will ultimately become components of the wiring board 10B will be labeled with their final component reference numerals.

[0131] First, in the process shown in Figure 33, the structure shown in Figure 33 is formed by performing the same process as in Figures 22 to 27. In this structure, through holes 47X and 49X are formed that penetrate the insulating layers 47 and 49 in the thickness direction, and recesses 47Y are formed at the lower end of the inner wall surface of the through hole 47X.

[0132] Next, the insulating layer 44A exposed from the through holes 47X and 49X is thinned from the top side. That is, the insulating layer 44A exposed by the removal of the metal layer 55 is thinned from the top side. As a result, a recess 44Z is formed that is recessed downward from the top surface of the insulating layer 44A, as shown in Figure 34. This process forms a cavity 40Y composed of the through holes 47X and 49X and the recess 44Z. The thinning of the insulating layer 44A can be performed, for example, by ashing (dry etching using oxygen plasma). Note that the insulating layer 49 may be thinned at the same time as the insulating layer 44A is thinned.

[0133] Next, in the process shown in Figure 35, an opening 44Y is formed at a predetermined location on the bottom surface of the recess 44Z by performing the same process as in Figure 15, such that a portion of the upper surface of the wiring layer 43A is exposed.

[0134] Next, if the opening 44Y is formed by laser processing, desmear treatment is performed to remove the resin smear adhering to the exposed surface of the wiring layer 43A exposed at the bottom of the opening 44Y.

[0135] Next, in the process shown in Figure 36, a connection terminal 70 is formed on the upper surface of the wiring layer 43A exposed through the opening 44Y by performing the same process as in Figure 16. The connection terminal 70 fills the opening 44Y and is formed to protrude above the bottom surface of the recess 44Z.

[0136] Next, in the process shown in Figure 37, the same process as in Figure 17 is performed to mount the electronic component 60 on the connection terminal 70 within the cavity 40Y. After that, underfill resin 66 is filled between the bottom surface of the cavity 40Y and the bottom surface of the main body 61 of the electronic component 60 and cured. Alternatively, the underfill resin 66 can be applied to the bottom surface of the main body 61 of the electronic component 60 in advance and then filled to the bottom surface of the cavity 40Y when mounting the electronic component 60.

[0137] Next, in the process shown in Figure 38, an insulating layer 50 that fills the cavity 40Y is formed by performing the same process as shown in Figures 18 to 20, and a wiring layer 51 is laminated on the upper surface of the insulating layer 50.

[0138] The structure shown in Figure 32 can be manufactured through the above manufacturing process. In this embodiment, recess 47Y is an example of a third recess, recess 44Z is an example of a fourth recess, and the bottom surface of recess 44Z is an example of a first surface.

[0139] (Effects of the third embodiment) According to the embodiments described above, in addition to the effects of (1-1) to (1-3) of the first embodiment and (2-1) of the second embodiment, the following effects can be achieved.

[0140] (3-1) The cavity 40Y of the wiring board 10B is configured such that through holes 47X and 49X that penetrate the N-layer (in this case, 2-layer) insulating layers 47 and 49 in the thickness direction are connected to a recess 44Z formed on the upper surface of the insulating layer 44A that is exposed from the through holes 47X and 49X. With this configuration, even if the thickness from the upper surface of the wiring layer 43B to the upper surface of the insulating layer 44A is formed to be thick, the thickness from the upper surface of the wiring layer 43A to the bottom surface of the recess 44Z can be made thin by providing the recess 44Z. In other words, the thickness of the insulating layer 44A in the portion covering the upper surface of the wiring layer 43A can be made thin. As a result, the opening 44Y can be made shallow, so for example, a connection terminal 70 formed in the opening 44Y can be easily formed to protrude upward from the bottom surface of the recess 44Z.

[0141] (3-2) The manufacturing method of the wiring board 10B includes a step of forming a recess 44Z that is recessed downward from the upper surface of the insulating layer 44A by thinning the insulating layer 44A that has been exposed by removing the metal layer 55 from the upper surface. With this configuration, the thickness of the insulating layer 44A in the portion that covers the upper surface of the wiring layer 43A can be suitably adjusted by the thinning process.

[0142] (Fourth Embodiment) The fourth embodiment will be described below with reference to Figures 39 to 44. The following description will focus on the differences from the first embodiment. Components identical to those shown in Figures 1 to 38 will be denoted by the same reference numerals, and detailed explanations of each of these elements will be omitted.

[0143] As shown in Figure 39, the wiring structure 40 of the wiring board 10C has a cavity 40X in which electronic components 60 are housed. The cavity 40X in this embodiment is formed to be recessed from the upper surface of the insulating layer 49 to an intermediate position in the thickness direction of the insulating layer 44. The cavity 40X in this embodiment is configured by communicating through holes 45X, 47X, and 49X that penetrate the insulating layers 45, 47, and 49 in the thickness direction with a recess 44D formed on the upper surface of the insulating layer 44. The inner wall surface of the recess 44D is formed to extend, for example, perpendicular to the upper surface of the insulating layer 44. Alternatively, the inner wall surface of the recess 44D may be formed as an inclined surface that slopes toward the center of the plane of the recess 44D as it approaches the bottom surface of the recess 44D. The bottom surface of the recess 44D, that is, the bottom surface of the cavity 40X, is located at an intermediate position in the thickness direction of the insulating layer 44. The bottom surface of the recess 44D is located above the top surface of the wiring layer 43A and below the bottom surface of the wiring layer 46.

[0144] Thus, in the wiring board 10C of this embodiment, the four insulating layers 44, 45, 47, and 49 laminated on the bottom insulating layer 42 of the wiring structure 40 serve as insulating layers for cavity formation. In this embodiment, the recess 45Y is located at an intermediate position on the inner wall surface of the cavity 40Y. The recess 45Y is located above the recess 44D. In other words, the recess 44D is formed to recess downward from the recess 45Y. Inside the recess 45Y, for example, a metal layer 55 is formed.

[0145] An opening 44X is formed at the bottom of the recess 44D, penetrating the insulating layer 44A in the thickness direction and exposing a portion of the upper surface of the wiring layer 43A. The opening 44X is formed to be shallower than, for example, the opening 44X of the first embodiment by the depth of the recess 44D. For example, in Figure 39, the opening 44X is formed in a tapered shape, with the opening width decreasing from the top side (bottom surface side of recess 44D) to the bottom side (wiring layer 43A side).

[0146] A connection terminal 70 is formed on the upper surface of the wiring layer 43A exposed through the opening 44X. The first metal layer 71 is formed, for example, to fill the opening 44X. The first metal layer 71 is formed, for example, to protrude upward from the bottom surface of the recess 44D. The second metal layer 72 is formed to cover the entire surface of the first metal layer 71.

[0147] The electronic component 60 is flip-chip mounted, for example, on a wiring layer 43A exposed from the cavity 40X and the opening 44X. The underfill resin 66 is formed to fill the gap between the lower surface of the main body 61 of the electronic component 60 and the bottom surface of the cavity 40X, in this case the bottom surface of the recess 44D.

[0148] Although not shown in the diagram, similar to the wiring board 10 shown in Figure 1, an insulating layer 52 and a wiring layer 53 are sequentially laminated on the upper surface of the insulating layer 50 of the wiring board 10C, and an external connection terminal 90 is formed on the upper surface of the wiring layer 53.

[0149] (Manufacturing method for wiring board 10C) Next, the manufacturing method of the wiring board 10C will be described. For the sake of clarity, the parts that will ultimately become components of the wiring board 10C will be labeled with their final component reference numerals.

[0150] First, in the process shown in Figure 40, the structure shown in Figure 40 is formed by performing the same process as in Figures 3 to 14. In this structure, through holes 45X, 47X, and 49X are formed that penetrate the insulating layers 45, 47, and 49 in the thickness direction, and recesses 45Y are formed at the lower end of the inner wall surface of the through hole 45X.

[0151] Next, the insulating layer 44 exposed through the through holes 45X, 47X, and 49X is thinned from the top side. That is, the insulating layer 44 exposed by the removal of the metal layer 55 is thinned from the top side. As a result, a recess 44D is formed that is recessed downward from the top surface of the insulating layer 44, as shown in Figure 41. This process forms a cavity 40X composed of the through holes 45X, 47X, and 49X and the recess 44D. The thinning of the insulating layer 44 can be carried out, for example, by an ashing process. Note that the insulating layer 49 may be thinned at the same time as the insulating layer 44 is thinned.

[0152] Next, in the process shown in Figure 42, an opening 44X is formed at a predetermined location on the bottom surface of the recess 44D by performing the same process as in Figure 15, such that a portion of the upper surface of the wiring layer 43A is exposed.

[0153] Next, if the opening 44X is formed by laser processing, desmear treatment is performed to remove the resin smear adhering to the exposed surface of the wiring layer 43A exposed at the bottom of the opening 44X.

[0154] Next, in the process shown in Figure 43, a connection terminal 70 is formed on the upper surface of the wiring layer 43A exposed through the opening 44X by performing the same process as in Figure 16. The connection terminal 70 fills the opening 44X and is formed to protrude above the bottom surface of the recess 44D.

[0155] Next, the same process as shown in Figure 17 is performed to mount the electronic component 60 on the connection terminal 70 within the cavity 40X. After that, underfill resin 66 is filled between the bottom surface of the cavity 40X and the bottom surface of the main body 61 of the electronic component 60 and cured. Alternatively, the underfill resin 66 can be applied to the bottom surface of the main body 61 of the electronic component 60 in advance and then filled to the bottom surface of the cavity 40X when mounting the electronic component 60.

[0156] Next, in the process shown in Figure 44, an insulating layer 50 that fills the cavity 40X is formed by performing the same process as shown in Figures 18 to 20, and a wiring layer 51 is laminated on the upper surface of the insulating layer 50.

[0157] The structure shown in Figure 39 can be manufactured through the above manufacturing process. In this embodiment, recess 45Y is an example of a first recess, recess 44D is an example of a second recess, and the bottom surface of recess 44D is an example of a first surface.

[0158] (Effects of the fourth embodiment) According to the embodiments described above, the same effects and advantages as those of (1-1) to (1-4) of the first embodiment and (3-1) and (3-2) of the third embodiment can be achieved.

[0159] (Example of change) Each of the above embodiments can be implemented with the following modifications. Each of the above embodiments and the following modifications can be combined with each other to the extent that they do not contradict each other technically.

[0160] The structure of the connection terminal 70 in each of the above embodiments can be modified as appropriate. Below, an example of modification of the connection terminal 70 in the first embodiment will be illustrated and explained, but the connection terminal 70 in the second, third, and fourth embodiments can be modified in the same way.

[0161] For example, as shown in Figure 45, the upper surface of the connection terminal 70 may be modified to have a structure having a recess 70X that is recessed downward from the upper surface of the connection terminal 70. More specifically, the first metal layer 71 in this modified example has a recess 71X that is recessed downward from the upper surface of the first metal layer 71. The first metal layer 71 is formed, for example, to fill the opening 44X. The upper surface of the first metal layer 71 is formed, for example, to be flush with the upper surface of the insulating layer 44. The second metal layer 72 is formed to cover the entire surface of the first metal layer 71. The second metal layer 72 is formed, for example, to cover the entire upper surface of the first metal layer 71 and the entire inner surface of the recess 71X. The second metal layer 72 is formed in a shape that conforms to the upper surface of the first metal layer 71 and the inner surface of the recess 71X. As a result, a recess 72X is formed on the upper surface of the second metal layer 72 that is recessed downward from the upper surface of the second metal layer 72. The recess 70X is formed by the recesses 71X and 72X described above.

[0162] In the modified example shown in Figure 45, the upper surface of the first metal layer 71 may be positioned above the upper surface of the insulating layer 44, or it may be positioned below the upper surface of the insulating layer 44.

[0163] For example, as shown in Figure 46, the upper surface of the connection terminal 70 may be modified to a curved structure that protrudes upward. More specifically, the upper surface of the connection terminal 70 may be formed to curve upward towards the center of the plane of the connection terminal 70. In this modified example, the surface of the first metal layer 71 that protrudes upward from the upper surface of the insulating layer 44 is formed in a spherical shape. The second metal layer 72 is formed to cover the entire surface of the first metal layer 71. The surface of the second metal layer 72 is formed in a spherical shape, for example.

[0164] For example, as shown in Figure 47, the connection terminal 70 may be modified to a structure in which a first metal layer 73, a second metal layer 74, and a third metal layer 75 are stacked in order. The first metal layer 73 is formed to cover the entire upper surface of the wiring layer 43A exposed from the opening 44X. The first metal layer 73 is formed to fill the opening 44X, for example. The first metal layer 73 is formed to protrude above the upper surface of the insulating layer 44, for example. The portion of the first metal layer 73 that protrudes above the upper surface of the insulating layer 44 is provided only in positions that overlap with the opening 44X in a plan view. In other words, the portion of the first metal layer 73 that protrudes above the upper surface of the insulating layer 44 is formed so as not to protrude outward from the opening 44X in the planar direction. The side surface of the first metal layer 73 exposed from the insulating layer 44 is formed, for example, an arc-shaped curved surface in a cross-sectional view. The upper surface of the first metal layer 73 is formed, for example, a plane that extends horizontally along the planar direction. The second metal layer 74 is formed, for example, to cover the entire surface of the first metal layer 73, that is, the entire top surface and the entire side surface of the first metal layer 73. The second metal layer 74 is formed in a shape that conforms to the surface of the first metal layer 73. The third metal layer 75 is formed, for example, to cover the entire surface of the second metal layer 74, that is, the entire top surface and the entire side surface of the second metal layer 74. The third metal layer 75 is formed in a shape that conforms to the surface of the second metal layer 74.

[0165] Here, the material for the first metal layer 73 can be, for example, copper or a copper alloy. For the first metal layer 73, for example, an electroplated layer formed by an electroplating method can be used. For the material for the second metal layer 74, a conductive material that has higher adhesion to the first metal layer 73 than the metal constituting the third metal layer 75 can be used. The second metal layer 74 is, for example, a Ni layer. The third metal layer 75 is, for example, an Au layer. For the second metal layer 74 and the third metal layer 75, for example, an electroless plated layer formed by an electroless plating method or an electroplated layer formed by an electroplating method can be used.

[0166] In the modified example shown in Figure 47, the upper surface of the first metal layer 73 may be modified to have a structure having a recess that is recessed downward from the upper surface of the first metal layer 73. Alternatively, the upper surface of the first metal layer 73 may be modified to have a curved structure that protrudes upward.

[0167] The structures of the wiring boards 10, 10A, 10B, and 10C in each of the above embodiments can be modified as appropriate. Each of the insulating layers 32, 34, 36, 38, 42, 47, 49, 50, and 52 in the above embodiments may be formed by creating a single layer from multiple resin layers, as in insulating layers 44 and 45.

[0168] The number of wiring layers, their routing, and the number of insulating layers in the wiring structure 30 of each of the above embodiments can be modified and changed in various ways. The solder resist layer 80 in each of the above embodiments may be omitted.

[0169] The wiring structure 30 in each of the above embodiments may be omitted. The number of wiring layers, their routing, and the number of insulation layers in the wiring structures 40 and 40A of the above embodiments can be modified and changed in various ways.

[0170] In the wiring structures 40 and 40A of the above embodiments, the number of insulating layers for cavity formation may be changed as appropriate. The metal layer 55 provided inside the recesses 45Y and 47Y in each of the above embodiments may be omitted.

[0171] In the wiring boards 10, 10A, 10B, and 10C of each of the above embodiments, the number of wiring layers and insulating layers laminated on the upper surface of the insulating layer 50 for cavity filling is not particularly limited. The electronic components 22 built into the core substrate 20 in each of the above embodiments may be omitted.

[0172] In each of the above embodiments, the upper and lower wiring layers 41 and 31 of the core substrate 20 are electrically connected to each other via through electrodes 21 that fill the through holes 20X of the core substrate 20. However, the invention is not limited to this, and for example, the upper and lower wiring layers 41 and 31 of the core substrate 20 may be electrically connected to each other via a through-hole plating layer provided on the inner wall of the through holes 20X. In this case, the holes of the through holes 20X formed inside the through-hole plating layer may be filled with resin.

[0173] • In the above embodiments, the wiring boards 10, 10A, 10B, and 10C are embodied as build-up wiring boards having a core board 20, but the invention is not limited to this. For example, the wiring boards 10, 10A, 10B, and 10C may be embodied as wiring boards having the form of coreless boards without a core board 20.

[0174] The number of electronic components 60 to be embedded in the wiring boards 10, 10A, 10B, and 10C of each of the above embodiments is not limited. For example, multiple electronic components 60 may be embedded in the wiring boards 10, 10A, 10B, and 10C. In this case, the same number of cavities 40X and 40Y as the number of embedded electronic components 60 may be formed, or multiple electronic components 60 may be placed in one cavity 40X or 40Y.

[0175] In the above embodiments, electronic components 60 having through electrodes 64 are embedded in the wiring boards 10, 10A, 10B, and 10C, but the invention is not limited to this. For example, electronic components 60 without through electrodes 64 may be embedded in the wiring boards 10, 10A, 10B, and 10C.

[0176] In each of the above embodiments, an electronic component 60 having two types of electrodes, namely a first electrode 62 and a second electrode 63, is incorporated into the wiring boards 10, 10A, 10B, and 10C, but the invention is not limited to this. For example, an electronic component 60 having three or more types of electrodes may be incorporated into the wiring boards 10, 10A, 10B, and 10C.

[0177] The structure of the electronic component 60 in each of the above embodiments can be modified as appropriate. For example, the second electrode 63 may be omitted. In this case, the electronic component 60 has the first electrode 62 only on the lower surface of the main body 61.

[0178] • In the above embodiments, the manufacturing method is exemplified for single-piece (one-piece) production, but it may also be exemplified for multi-piece production. [Explanation of Symbols]

[0179] 10, 10A, 10B, 10C Wiring board 40, 40A Wiring Structure 40X, 40Y Cavity 41 Wiring layer 42 Insulating layer 43A wiring layer 43B wiring layer 44,44A insulating layer 44D, 44Z recess 44X,44Y opening 45, 47, 49 Insulating layer 45X,47X,49X through hole 45Y, 47Y recess 46 Wiring layer 46V via wiring 46W via wiring 48 wiring layer 50 Insulating layer 51 Wiring layer 60 Electronic Components 61 Main body 62 1st electrode 63 2nd electrode 64 Through electrode 65 Joining member 70 Connection terminals 71,73 1st metal layer 72,74 2nd metal layer 81 Surface treatment layer 90 External connection terminals 91 Seed Layer 92 Metal layer 93 Metal layer 100 resist layers 100X Aperture Pattern

Claims

1. The first insulating layer and A first wiring layer and a second wiring layer are laminated on the upper surface of the first insulating layer, A second insulating layer is formed on the upper surface of the first insulating layer so as to cover the side and upper surfaces of the first wiring layer and the side and upper surfaces of the second wiring layer, An N-layer (where N is a natural number of 1 or more) insulating layer is laminated on the upper surface of the second insulating layer, A cavity formed in the insulating layer of the N layer and formed so as to expose the first surface of the second insulating layer, An opening is formed on the first surface and penetrates the second insulating layer in the thickness direction, exposing a part of the upper surface of the first wiring layer, A connection terminal formed on the upper surface of the first wiring layer exposed from the opening, The electronic components are arranged within the cavity and mounted on the connection terminals, A filling insulating layer that fills the cavity and covers the electronic component, It has a third wiring layer laminated on the upper surface of the filling insulating layer, The first wiring layer is provided in a position that overlaps with the cavity in a plan view, The wiring board is provided in a position where the second wiring layer does not overlap with the cavity in a plan view.

2. The insulating layer of the N layer has a third insulating layer laminated on the upper surface of the second insulating layer. The aforementioned wiring board is A fourth wiring layer is laminated on the upper surface of the third insulating layer and is electrically connected to the second wiring layer via via wiring that penetrates the second insulating layer and the third insulating layer in the thickness direction, The wiring board according to claim 1, further comprising: a first recess provided at the lower end of the third insulating layer constituting the inner wall surface of the cavity, and formed to widen the opening width of the cavity.

3. The cavity is formed so as to penetrate the insulating layer of the N layer in the thickness direction and expose a part of the upper surface of the second insulating layer. The wiring board according to claim 2, wherein the first surface is the upper surface of the second insulating layer.

4. The cavity is configured such that a through hole penetrating the insulating layer of the N layer in the thickness direction and a second recess formed on the upper surface of the second insulating layer exposed from the through hole are in communication with each other. The first surface is the bottom surface of the second recess, The wiring board according to claim 2, wherein the second recess is provided below the first recess.

5. The insulating layer of the N layer has a fourth insulating layer laminated on the upper surface of the second insulating layer. The aforementioned wiring board is A fourth wiring layer is laminated on the upper surface of the second insulating layer and electrically connected to the second wiring layer via via wiring that penetrates the second insulating layer in the thickness direction, The present invention further includes a third recess provided at the lower end of the fourth insulating layer that constitutes the inner wall surface of the cavity, and formed to widen the opening width of the cavity, The wiring board according to claim 1, wherein the fourth insulating layer is formed to cover the fourth wiring layer.

6. The cavity is configured such that a through hole penetrating the insulating layer of the N layer in the thickness direction and a fourth recess formed on the upper surface of the second insulating layer exposed from the through hole are in communication with each other. The first surface is the bottom surface of the fourth recess, The wiring board according to claim 5, wherein the fourth recess is provided below the third recess.

7. The electronic component comprises a main body, a first electrode provided on the lower surface side of the main body, a second electrode provided on the opposite side of the first electrode, and a through electrode that penetrates the main body in the thickness direction and electrically connects the first electrode and the second electrode. The first electrode is electrically connected to the connection terminal via a bonding member. The wiring board according to claim 1, wherein the third wiring layer is electrically connected to the second electrode.

8. The wiring board according to claim 1, wherein the connection terminals fill the opening and are formed to protrude above the first surface.

9. A step of forming a first insulating layer, The process involves laminating a first wiring layer and a second wiring layer on the upper surface of the first insulating layer, A step of forming a second insulating layer on the upper surface of the first insulating layer, which covers the side and upper surfaces of the first wiring layer and the side and upper surfaces of the second wiring layer, A step of forming a metal layer on the upper surface of the second insulating layer at a position that overlaps with the first wiring layer in a plan view, A step of forming an N-layer (where N is a natural number of 1 or more) insulating layer on the upper surface of the second insulating layer so as to cover the metal layer, A step of forming a cavity in the insulating layer of the N layer that exposes the upper surface of the metal layer by a laser processing method, The process of removing the aforementioned metal layer, A step of forming an opening on the first surface of the second insulating layer exposed at the bottom of the cavity, which penetrates the second insulating layer in the thickness direction and exposes a part of the upper surface of the first wiring layer, A step of forming a connection terminal on the upper surface of the first wiring layer exposed from the opening, Within the cavity, the process involves mounting electronic components on the connection terminals, A step of filling the cavity and forming a filling insulating layer that covers the electronic component, The process includes a step of laminating a third wiring layer on the upper surface of the aforementioned filling insulating layer, The first wiring layer is provided in a position that overlaps with the cavity in a plan view, A method for manufacturing a wiring board, wherein the second wiring layer is provided in a position that does not overlap with the cavity in a plan view.

10. After the step of removing the metal layer, The process includes a step of forming a recess that is recessed downward from the upper surface of the second insulating layer by thinning the second insulating layer that has been exposed by removing the metal layer, The method for manufacturing a wiring board according to claim 9, wherein the opening is formed on the bottom surface of the recess.

Images