Elastic wave devices

Abstract

To provide an elastic wave device with improved heat dissipation. [Solution] An elastic wave device comprising a package substrate, a piezoelectric substrate mounted on the package substrate, a first ladder-type filter formed on the piezoelectric substrate and including a first series resonator, a second series resonator, and a first parallel resonator, a first series resonator wiring that electrically connects the first series resonator and the second series resonator, a first ground pad electrically connected to the first parallel resonator, and a sealing portion that hermetically seals the piezoelectric substrate together with the package substrate, wherein the first series resonator wiring is located on the outer edge of the piezoelectric substrate, relative to the first parallel resonator and the first ground pad.

Description

Technical Field

[0001] This disclosure relates to elastic wave devices.

Background Art

[0002] Due to recent technological advancements, smartphones and the like, typified by mobile communication terminals, have been remarkably miniaturized and lightened. As elastic wave devices used in such mobile communication terminals, elastic wave devices that can be miniaturized are used.

[0003] With miniaturization, ensuring the power resistance of elastic wave devices has become more stringent. That is, a structure with better heat dissipation performance than conventional ones is required.

[0004] To improve the heat dissipation of elastic wave devices, for example, Patent Document 1 discloses a technique for enhancing the heat dissipation from a device chip including a piezoelectric substrate or the like to the package substrate side using dummy bumps.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, in the elastic wave device described in Patent Document 1, the heat dissipation is not sufficient.

[0007] This disclosure has been made to solve the above problems. The object of this disclosure is to provide an elastic wave device with improved heat dissipation and a module including the elastic wave device.

Means for Solving the Problems

[0008] The elastic wave device relating to this disclosure is Package substrate and A piezoelectric substrate mounted on the aforementioned package substrate, A first ladder-type filter is formed on the piezoelectric substrate and includes a first series resonator, a second series resonator, and a first parallel resonator, A wiring that electrically connects the first series resonator and the second series resonator, The first parallel resonator and the first ground pad are electrically connected, The package substrate and the piezoelectric substrate are provided together with a sealing portion that hermetically seals the piezoelectric substrate, The wiring between the first series resonators is an elastic wave device located at the outer edge of the piezoelectric substrate, relative to the first parallel resonator and the first ground pad.

[0009] In one embodiment of the present invention, the first parallel resonator includes a first parallel divided resonator and a second parallel divided resonator connected in parallel, and the first ground pad is positioned between the first parallel divided resonator and the second parallel divided resonator.

[0010] In one embodiment of this disclosure, the first ground pad is positioned on the outer edge side of the piezoelectric substrate rather than at the center of the first parallel resonator.

[0011] One embodiment of the present invention is to provide a first heat dissipation floating pad between the first parallel divided resonator and the second parallel divided resonator, which is positioned closer to the center of the piezoelectric substrate than to the center of the first parallel resonator.

[0012] A third series resonator, a fourth series resonator, and a second parallel resonator formed on the piezoelectric substrate, A second ground pad electrically connected to the second parallel resonator, A wiring harness between the second series resonators electrically connects the third series resonator and the fourth series resonator, It further includes a second ladder-type filter, In one embodiment of the present invention, the wiring between the second series resonators is positioned on the outer edge of the piezoelectric substrate, relative to the second parallel resonator and the second ground pad.

[0013] The second ladder filter is, The fifth series resonator and the third parallel resonator, A third ground pad electrically connected to the third parallel resonator, The third series resonator wiring further includes an electrical connection between the fourth series resonator and the fifth series resonator, In one embodiment of this disclosure, the wiring between the third series resonators is positioned on the outer edge of the piezoelectric substrate, relative to the third parallel resonator and the third ground pad.

[0014] In one embodiment of this disclosure, the fourth series resonator is positioned between the second and third ground pads, and the second and third ground pads are positioned on the outer edge of the piezoelectric substrate rather than in the center of the second series resonator.

[0015] One embodiment of this disclosure is that the first ladder filter and the second ladder filter have common input / output pads and constitute a single bandpass filter.

[0016] One embodiment of the present disclosure is that the aforementioned bandpass filter has a relative bandwidth of 6% or more and 9% or less.

[0017] One embodiment of the present disclosure is that the bandpass filter comprises a first ladder-type filter which constitutes the high-frequency passband and a second ladder-type filter which constitutes the low-frequency passband.

[0018] A second heat dissipation floating pad formed between the first parallel divided resonator and the second ground pad, Another aspect of the present disclosure is to further include a third heat dissipation floating pad formed between the second parallel division resonator and the third ground pad.

Advantages of the Invention

[0019] According to the present disclosure, the heat dissipation performance of the elastic wave device can be improved.

Brief Description of the Drawings

[0020] [Figure 1] FIG. 1 is a longitudinal sectional view of an elastic wave device 20 in Embodiment 1. [Figure 2] FIG. 2 is a diagram showing an example of an elastic wave element (resonator) of the elastic wave device 20 in Embodiment 1. [Figure 3] FIG. 3 is a diagram showing an example of the elastic wave device 20 in Embodiment 1. [Figure 4] FIG. 4 is a plan view showing the configuration of each layer of the package substrate of the elastic wave device 20 in Embodiment 1. [Figure 5] FIG. 5 is a circuit diagram of the elastic wave device 20 in Embodiment 1. [Figure 6] FIG. 6 is a diagram showing the passing characteristics of the elastic wave device 20 in Embodiment 1.

Modes for Carrying Out the Invention

[0021] Embodiments will be described with reference to the accompanying drawings. In each figure, the same or corresponding parts are denoted by the same reference numerals, and redundant descriptions of such parts will be simplified or omitted as appropriate.

[0022] Embodiment 1. FIG. 1 is a longitudinal sectional view of an elastic wave device 20 in Embodiment 1. [[ID=’46]]

[0023] As shown in FIG. the elastic wave device 20 includes a package substrate 23, external connection terminals 24, a device chip 25, a metal pattern 26, bumps 27, and a sealing portion 28.

[0024] For example, the package substrate 23 is a multilayer substrate made of resin. For example, the package substrate 23 is a low-temperature co-fired ceramics (LTCC) multilayer substrate made of multiple dielectric layers.

[0025] Multiple external connection terminals 24 are formed on the lower surface of the package substrate 23.

[0026] Multiple metal patterns 26 are formed on the main surface of the package substrate 23, i.e., the mounting surface for the device chip 25. For example, the metal patterns 26 are formed of copper or a copper-containing alloy. For example, the thickness of the metal patterns 26 is 10 μm to 20 μm.

[0027] For example, the package substrate 23 includes a first substrate 231, a second substrate 232, and a third substrate 233, and may also include many more stacked substrates. Between the first substrate 231 and the second substrate 232, although not shown in Figure 1, multiple metal patterns are formed and electrically connected to a metal pattern 26 via vias formed to penetrate the first substrate 231. Between the second substrate 232 and the third substrate 233, although not shown in Figure 1, multiple metal patterns are formed and electrically connected to multiple metal patterns formed between the first substrate 231 and the second substrate 232 via vias formed to penetrate the second substrate 232.

[0028] The bumps 27 are formed on the upper surface of each of the metal patterns 26. For example, the bumps 27 are gold bumps. For example, the height of the bumps 27 is between 10 μm and 50 μm.

[0029] The device chip 25 is mounted on the package substrate 23 by flip-chip bonding via bumps 27. The device chip 25 is electrically connected to multiple metal patterns 26 via multiple bumps 27.

[0030] The device chip 25 is, for example, a surface acoustic wave device chip. The device chip 25 comprises a piezoelectric substrate formed of a piezoelectric material. The piezoelectric substrate is a substrate formed of a piezoelectric single crystal such as lithium tantalate, lithium niobate, or quartz.

[0031] The thickness of the piezoelectric substrate can be, for example, 100 μm to 300 μm. In another example, the piezoelectric substrate is a substrate made of piezoelectric ceramics.

[0032] In yet another example, the device chip 25 is a substrate in which a piezoelectric substrate and a support substrate are bonded directly or indirectly via an intermediate layer. The support substrate is, for example, a substrate made of sapphire, silicon, alumina, spinel, quartz, or glass. In this case, the thickness of the piezoelectric substrate can be, for example, 0.3 μm to 5 μm.

[0033] Acoustic wave elements are formed on a piezoelectric substrate. For example, a bandpass filter including multiple acoustic wave elements is formed on the main surface of the device chip 25.

[0034] In another example, a duplexer including a transmit filter and a receive filter is formed on the main surface of the device chip 25.

[0035] A transmitting filter is designed to allow electrical signals within a desired frequency band to pass through. For example, a transmitting filter is a ladder filter consisting of multiple series resonators and multiple parallel resonators.

[0036] A receiving filter is designed to allow electrical signals of a desired frequency band to pass through. For example, a receiving filter is a ladder filter.

[0037] The sealing portion 28 is formed to cover the device chip 25. For example, the sealing portion 28 is formed of an insulator such as a synthetic resin. For example, the sealing portion 28 is formed of metal.

[0038] When the sealing portion 28 is formed of a synthetic resin, the synthetic resin may be an epoxy resin, polyimide, or the like. Preferably, the sealing portion 28 is made of an epoxy resin and formed using a low-temperature curing process.

[0039] A gap 29 is formed in the region where the package substrate 23 and the device chip 25 face each other. This ensures space for the elastic wave element 52 to be excited by its physical movement.

[0040] Next, an example of an elastic wave element 52 formed on the device chip 25 will be explained using Figure 2. Figure 2 is a diagram showing an example of an elastic wave element (resonator) of the elastic wave device 20 in Embodiment 1.

[0041] As shown in Figure 2, the IDT (Interdigital Transducer) electrode 52a and the pair of reflectors 52b are formed on the main surface of the device chip 25. The IDT electrode 52a and the pair of reflectors 52b are arranged to excite elastic waves (mainly SH waves).

[0042] For example, the IDT electrode 52a and the pair of reflectors 52b are formed from an alloy of aluminum and copper. For example, the IDT 52a and the pair of reflectors 52b are formed from suitable metals such as aluminum, copper, platinum, molybdenum, iridium, tungsten, cobalt, nickel, ruthenium, chromium, strontium, titanium, palladium, and silver, or alloys thereof, or laminates thereof.

[0043] For example, the IDT electrode 52a and the pair of reflectors 52b are formed from a laminated metal film in which multiple metal layers are stacked. For example, the thickness of the IDT electrode 52a and the pair of reflectors 52b is between 150 nm and 450 nm.

[0044] The IDT electrode 52a comprises a pair of comb-shaped electrodes 52c. The pair of comb-shaped electrodes 52c face each other. The comb-shaped electrodes 52c comprises a plurality of electrode fingers 52d and a busbar 52e.

[0045] Multiple electrode fingers 52d are arranged with their longitudinal directions aligned. A busbar 52e connects the multiple electrode fingers 52d.

[0046] One of the pair of reflectors 52b is adjacent to one side of the IDT electrode 52a. The other of the pair of reflectors 52b is adjacent to the other side of the IDT electrode 52a.

[0047] Next, an example of a bandpass filter formed on the device chip 25 will be explained using Figure 3. Figure 3 is a diagram showing an example of an elastic wave device 20 in Embodiment 1.

[0048] As shown in Figure 3, a first ladder filter LD1, a second ladder filter LD2, and multiple pads are formed on the device chip 25. In Figure 3, the symbols for each pad indicate their circuit function.

[0049] The first ladder-type filter LD1 includes a first series resonator S1, a second series resonator S2, a first parallel resonator P1, and a first series resonator wiring SS1 that electrically connects the first series resonator S1 and the second series resonator S2.

[0050] Furthermore, the first parallel resonator P1 consists of a first parallel divided resonator PD1 and a second parallel divided resonator PD2 connected in parallel. A first ground pad GP1 is also formed, electrically connected to the first parallel resonator P1. The first ground pad GP1 is formed between the first parallel divided resonator PD1 and the second parallel divided resonator PD2. The first ground pad GP1 is also formed on the outer edge side of the device chip 25, rather than in the center of the first parallel divided resonator PD1 and the second parallel divided resonator PD2. Note that each resonator is appropriately divided into series to ensure sufficient power handling capacity.

[0051] The first series inter-resonator wiring SS1 is formed on the outer edge side of the device chip 25, relative to the first parallel divided resonator PD1 and the first ground pad GP1.

[0052] In a ladder-type filter, the wiring between series resonators is prone to overheating because the heat generated by the excitation of the two series and parallel resonators is not easily dissipated. This makes the resonators more susceptible to thermal failure, making it difficult to meet the power handling requirements. In particular, resonators further from the pads are more prone to thermal failure due to poor heat dissipation. The wiring SS1 between the first series resonators is not connected to the pads and therefore has poor heat dissipation, so it is placed on the outer edge to promote heat dissipation.

[0053] Furthermore, as a measure to withstand high power, for example, the first series resonator S1 and the second series resonator S2 are divided into five series sections. The first parallel divided resonator PD1 and the second parallel divided resonator PD2 are also each divided into two series sections. Generally, parallel resonators are connected to ground pads and heat is easily dissipated to the substrate 23 side through ground bumps.

[0054] The first series inter-resonator wiring SS1 is located on the outer edge side of the device chip 25 and is in contact with or close to the sealing portion 28 that covers the device chip 25 and is bonded to the device chip 25, thus making it easy to dissipate heat through the sealing portion 28.

[0055] Furthermore, since the first series inter-resonator wiring SS1 is also close to the first ground pad GP1, heat is easily dissipated to the package substrate 23 side through the first ground pad GP1. Thus, the first series inter-resonator wiring SS1 is easily dissipated heat because it has paths on both sides that facilitate heat dissipation. Specifically, the width of the first series inter-resonator wiring SS1 was set to 20 μm. Also, the distance between the first series inter-resonator wiring SS1 and the first ground pad GP1 was set to 5 μm.

[0056] A first heat dissipation floating pad UP1 is formed between the first parallel divided resonator PD1 and the second parallel divided resonator PD2. Furthermore, the first heat dissipation floating pad UP1 is formed closer to the center of the device chip 25 than the center of the first parallel divided resonator PD1 and the second parallel divided resonator PD2.

[0057] A heat dissipation floating pad is a bump pad that is not in contact with other metal patterns on the device chip 25. The first heat dissipation floating pad UP1 is not in contact with other metal patterns on the device chip 25. On the device chip 25, the central side is less efficient at dissipating heat than the outer edge side which is in contact with or close to the sealing portion 28, and therefore tends to become hotter. The first heat dissipation floating pad UP1 is positioned on the central side of the device chip 25 and serves as a heat dissipation path that more effectively dissipates heat to the package substrate 23 via the bumps.

[0058] By forming the first ground pad GP1 on the outer edge side of the device chip 25, rather than the center of the first parallel divided resonator PD1 and the second parallel divided resonator PD2, and by positioning the first heat dissipation floating pad UP1 towards the center of the device chip 25, the wiring SS1 between the first series resonators is dissipated from both sides, and heat can be dissipated from the center of the device chip 25 via the first heat dissipation floating pad UP1 and the bumps, resulting in a highly efficient layout for improving heat dissipation.

[0059] The second ladder-type filter LD2 includes a third series resonator S3, a fourth series resonator S4, a fifth series resonator S5, a second parallel resonator P2, a third parallel resonator P3, a fourth parallel resonator P4, and a fifth parallel resonator P5. The third series resonator S3 is divided in series into three parts, two of which are located close to the common input / output pad CP1, and the remaining one is located via wiring. The fifth parallel resonator P5 is divided in series into two parts, which are arranged vertically in Figure 3.

[0060] Furthermore, some of the other resonators are divided into series as appropriate to ensure sufficient power handling. It also includes a second series resonator wiring SS2 that electrically connects the third series resonator S3 and the fourth series resonator S4. It also includes a third series resonator wiring SS3 that electrically connects the fourth series resonator S4 and the fifth series resonator S5. Additionally, a second ground pad GP2 is formed, electrically connected to the second parallel resonator P2. Furthermore, a third ground pad GP3 is formed, electrically connected to the third parallel resonator P3.

[0061] It is preferable to position the second ground pad GP2 closer to the outer edge of the device chip 25 than to the center of the second parallel resonator P2. This is because the proximity of the second series resonator wiring SS2 to the second ground pad GP2 allows for easier heat dissipation via the bumps. Similarly, it is preferable to position the third ground pad GP3 closer to the outer edge of the device chip 25 than to the center of the third parallel resonator P3. This is because the proximity of the third series resonator wiring SS3 to the third ground pad GP3 allows for easier heat dissipation via the bumps.

[0062] The second series inter-resonator wiring SS2 is formed on the outer edge side of the device chip 25, beyond the second parallel resonator P2 and the second ground pad GP2. Similarly, the third series inter-resonator wiring SS3 is formed on the outer edge side of the device chip 25, beyond the third parallel resonator P3 and the third ground pad GP3.

[0063] The second series inter-resonator wiring SS2 is located on the outer edge side of the device chip 25 and is in contact with or close to the sealing portion 28 that covers the device chip 25 and is joined to the device chip 25, thus allowing heat to be easily dissipated through the sealing portion 28. Furthermore, since the second series inter-resonator wiring SS2 is also close to the second ground pad GP2, heat can be easily dissipated to the package substrate 23 side through the second ground pad GP2. In this way, the second series inter-resonator wiring SS2 is well-dissipated because it has paths on both sides that facilitate heat dissipation. The same applies to the third series inter-resonator wiring SS3.

[0064] A second heat dissipation floating pad UP2 is formed so as to surround the first parallel divided resonator PD1, the second parallel resonator P2, and the fourth series resonator S4. A third heat dissipation floating pad UP3 is formed so as to surround the second parallel divided resonator PD2, the fourth series resonator S4, and the third parallel resonator P3. Furthermore, the second heat dissipation floating pad UP2 and the third heat dissipation floating pad UP3 are positioned closer to the center of the device chip 25 than the center of the fourth series resonator S4.

[0065] In the device chip 25, the central side is less efficient at dissipating heat than the outer edge side, which is in contact with or close to the sealing portion, and therefore tends to become hotter. The second heat dissipation floating pad UP2 and the third heat dissipation floating pad UP3 are positioned on the central side of the device chip 25 and function more effectively as heat dissipation paths via the bumps.

[0066] By forming the second ground pad GP2 on the outer edge side of the device chip 25 rather than the center of the second parallel resonator P2, and by positioning the second heat dissipation floating pad UP2 towards the center of the device chip 25, the wiring SS2 between the second series resonators is dissipated from both sides, and heat can be dissipated from the center of the device chip 25 via the second heat dissipation floating pad UP2 and bumps, resulting in a highly efficient layout for improving heat dissipation.

[0067] Similarly, with respect to the third ground pad GP3, by forming the third ground pad GP3 on the outer edge side of the device chip 25 rather than the center of the third parallel resonator P3, and by positioning the third heat dissipation floating pad UP3 towards the center of the device chip 25, the wiring SS3 between the third series resonators can dissipate heat from both sides, and the center of the device chip 25 can dissipate heat via the third heat dissipation floating pad UP3 and the bumps, resulting in a highly efficient layout for improving heat dissipation.

[0068] The fourth heat dissipation floating pad UP4 is formed so as to surround the second series resonator S2, the third parallel resonator P3, and the fifth series resonator S5. Since series resonators are not connected to the ground pad, heat tends to accumulate in them in particular. Therefore, placing a heat dissipation floating pad in the region sandwiched between multiple series resonators (the second series resonator S2 and the fifth series resonator S5) is useful from the viewpoint of improving heat dissipation.

[0069] The first ladder filter LD1 and the second ladder filter LD2 have common input / output pads CP1 and CP2. The first ladder filter LD1 and the second ladder filter LD2 constitute a single bandpass filter. The first ladder filter LD1 constitutes the high-frequency passband, and the second ladder filter LD2 constitutes the low-frequency passband. This is because a smaller number of parallel resonators constitutes the high-frequency passband, reducing the need to ensure low-frequency attenuation, thus allowing for the efficient construction of a wideband bandpass filter.

[0070] A bandpass filter composed of a first ladder filter LD1 and a second ladder filter LD2 can have a relative bandwidth of 6% to 9%. To construct a wideband bandpass filter, a typical lithium tantalate single crystal substrate with a Y-cut angle of 42 degrees lacks sufficient electromechanical coupling coefficient. On the other hand, the transmit / receive band 41 requires high power handling, making the use of a ladder filter desirable. Therefore, by employing two ladder filters, one for the high-frequency passband and the other for the low-frequency passband, a wideband bandpass filter with high power handling can be constructed.

[0071] Figure 4 is a plan view showing the configuration of each layer of the package substrate 23 of the elastic wave device 20 in Embodiment 1. Figures 4(b) to 4(f) are plan views seen through the plane of Figure 4(a). Vias V formed in Figures 4(a) to 4(e) are electrically connected to the corresponding positions of each metal pattern in Figures 4(b) to 4(f). For example, via V shown in Figure 4(a) electrically connects the metal pattern in Figure 4(a) and the metal pattern in Figure 4(b). Here, the metal pattern MP is a concept that comprehensively includes metal-patterned elements such as the heat dissipation pad HDP, antenna pad ANT, transmit / receive pad TRx, ground pad GNDL, GNDmL, and inductor pattern, which will be described later.

[0072] Figure 4(a) shows the configuration of the mounting surface of the package substrate 23. The device chip 25 is flip-chip bonded to the mounting surface via a plurality of bumps. As shown in Figure 4(a), a plurality of metal patterns MP are formed on the mounting surface. Nine metal patterns MP are formed on the mounting surface. The plurality of metal patterns MP include a heat dissipation pad HDP. The heat dissipation pad HDP has the largest area among the plurality of metal patterns. The mounting surface includes an antenna pad ANT, a transmit / receive pad TRx, a ground pad GNDL, and GNDmL.

[0073] Furthermore, since the device chip 25 layout shown in Figure 3 is flip-chip bonded, for example, the common input / output pads CP1 and CP2 in Figure 3 are flipped and bonded to the transmit / receive pad TRx and antenna pad ANT in Figure 4(a) via bumps.

[0074] Figure 4(b) shows the configuration of the metal pattern MP of the first inner layer (first inner layer) as viewed from the mounting side. Eight metal pattern MPs are formed in the first inner layer. The first metal pattern MP1 is formed in the first inner layer. As shown in Figure 4(b), the first metal pattern MP1 is the metal pattern with the largest area in the first inner layer.

[0075] Also, referring to Figure 4(a) in conjunction, the heat dissipation pad HDP and the first metal pattern MP1 are electrically connected by four vias V. Furthermore, the area of ​​the first metal pattern MP1 is larger than that of the heat dissipation pad HDP. In addition, a first inductor pattern L1 is formed in the first inner layer. The first inductor pattern L1 is electrically connected to the ground pad GNDL in Figure 4(a) via vias V.

[0076] Furthermore, a small inductance pattern GNDmL is formed in the first inner layer. The small inductance pattern GNDmL is electrically connected to the ground pad GNDmL in Figure 4(a) via via V. In high-frequency circuits, even with via V and metal patterns for via reception, the small inductance component generated therein is often considered or utilized to construct optimal pass characteristics. Therefore, in high-frequency circuits, in order to obtain optimal pass characteristics through more precise design, it is desirable that only bumps bonded to the heat dissipation floating pad be connected to the heat dissipation pad HDP.

[0077] Figure 4(c) shows the configuration of the second inner layer (second inner layer) metal pattern MP as viewed from the mounting side. Seven metal pattern MPs are formed in the second inner layer. The second metal pattern MP2 is formed in the second inner layer. As shown in Figure 4(c), the second metal pattern MP2 is the metal pattern with the largest area in the second inner layer.

[0078] Also, referring to Figure 4(b), the second metal pattern MP2 and the first metal pattern MP1 are electrically connected by eight vias V. Furthermore, the area of ​​the second metal pattern MP2 is larger than that of the first metal pattern MP1. In addition, a second inductor pattern L2 is formed in the second inner layer. The second inductor pattern L2 is electrically connected to the first inductor pattern L1 in Figure 4(b) via vias V.

[0079] Furthermore, a small inductor pattern GNDmL is also formed in the second inner layer. This small inductor pattern GNDmL is electrically connected to the small inductor pattern GNDmL in Figure 4(b) via via V.

[0080] Figure 4(d) shows the configuration of the third inner layer (third inner layer) as viewed from the mounting side. Six metal patterns MP are formed in the third inner layer. The third metal pattern MP3 is formed in the third inner layer. As shown in Figure 4(d), the third metal pattern MP3 is the largest metal pattern in the third inner layer.

[0081] Also, referring to Figure 4(c), the third metal pattern MP3 and the second metal pattern MP2 are electrically connected by 10 vias V. Furthermore, a third inductor pattern L3 is formed in the third inner layer. The third inductor pattern L3 is electrically connected to the second inductor pattern L2 in Figure 4(c) via vias V.

[0082] Furthermore, a small inductor pattern GNDmL is also formed in the third inner layer. This small inductor pattern GNDmL is electrically connected to the small inductor pattern GNDmL in Figure 4(c) via via V. Here, the small inductor pattern GNDmL in the third inner layer is electrically connected to the third metal pattern MP3.

[0083] Figure 4(e) shows the configuration of the metal pattern MP of the fourth inner layer (fourth inner layer) as viewed from the mounting side. Three metal pattern MPs are formed on the fourth inner layer. The fourth metal pattern MP4 is formed on the fourth inner layer.

[0084] Also, referring to Figure 4(d), the fourth metal pattern MP4 and the third metal pattern MP3 are electrically connected by 14 vias V. Furthermore, the fourth metal pattern MP4 is electrically connected to the third inductor pattern L3 of the third inner layer via vias V.

[0085] Figure 4(f) is a plan view showing the configuration of the external connection terminals 24 of the package substrate 23. The external connection terminals include the transmit / receive terminal TRx, the antenna terminal ANT, and the ground terminal GND.

[0086] Here, the heat dissipation pad HDP, the first metal pattern MP1, the second metal pattern MP2, and the third metal pattern MP3 are composed only of large metal patterns until they are electrically connected to the small inductor pattern GNDmL of the third inner layer and finally reach ground potential. The inventors have found that by using multiple large metal patterns in the stacking direction without intervening with inductor patterns or wiring patterns from the bumps bonded to the heat dissipation floating pad, a package substrate 23 with high heat dissipation can be constructed.

[0087] In ladder-type filters, inductor patterns are often constructed on the package substrate 23 to ensure sufficient ground inductance. However, the area of ​​the inductor pattern has a small metal pattern area and a small number of vias, resulting in poor heat dissipation. In addition, heat tends to accumulate in the central region of the device chip.

[0088] Therefore, it was found that heat dissipation is improved by providing a heat dissipation floating pad and a bump bonded to the heat dissipation floating pad in the central region of the device chip, and by arranging a large-area metal pattern as a heat dissipation pad (HDP) on the package substrate side, and by using multiple large metal patterns in the stacking direction without using inductor patterns or the like.

[0089] Furthermore, focusing on the fact that heat diffuses radially, we adopted a configuration that follows the natural laws of heat diffusion by making the area of ​​the first metal pattern MP1 larger than the area of ​​the heat dissipation pad HDP, and the area of ​​the second metal pattern MP2 larger than the area of ​​the first metal pattern MP1.

[0090] Furthermore, for similar reasons, it is desirable to increase the number of vias connecting the first metal pattern MP and the second metal pattern MP2 compared to the number of vias connecting the heat dissipation pad HDP and the first metal pattern MP1, thereby creating a configuration that conforms to the natural laws of heat diffusion.

[0091] Figure 5 shows a circuit diagram of the elastic wave device 20 in Embodiment 1. As shown in Figure 5, the elastic wave device 20 in Embodiment 1 consists of a first ladder-type filter LD1 including a first series resonator S1, a second series resonator S2, and a first parallel resonator P1, and a second ladder-type filter LD2 including a third series resonator S3, a fourth series resonator S4, a fifth series resonator S5, a second parallel resonator P2, and a third parallel resonator S3.

[0092] The first series resonator S1 consisted of five resonators connected in series, each with an aperture length of 17.01λ, a logarithm of 135.5, and a resonator capacitance of 1.50pF. The second series resonator S2 consisted of five resonators connected in series, each with an aperture length of 17.01λ, a logarithm of 132.5, and a resonator capacitance of 1.45pF. The third series resonator S3 consisted of three resonators connected in series, each with an aperture length of 17.41λ, a logarithm of 158.0, and a resonator capacitance of 1.86pF. The fourth series resonator S4 consisted of three resonators connected in series, each with an aperture length of 17.48λ, a logarithm of 168.5, and a resonator capacitance of 1.98pF. The fifth series resonator S5 consisted of three resonators connected in series, each with an aperture length of 17.50λ, a logarithm of 100.0, and a resonator capacitance of 1.20pF. The first parallel resonator P1 was configured by connecting in parallel the first parallel divided resonator PD1 and the second parallel divided resonator PD2, each consisting of two resonators with an aperture length of 20.88λ, a logarithm of 179.0, and a resonator capacitance of 2.54pF, in series. The second parallel resonator P2 was configured by connecting two resonators with an aperture length of 17.56λ, a logarithm of 139.0, and a resonator capacitance of 1.74pF, in series. The third parallel resonator P3 had an aperture length of 20.36λ, a logarithm of 147.5, and a resonator capacitance of 2.09pF.

[0093] The second ladder-type filter LD2 includes a fourth parallel resonator S4 positioned between the node between the transmit / receive terminal TRx and the third series resonator S3 and the TRx matching inductor L1, and a fifth parallel resonator S5 positioned between the node between the antenna terminal ANT and the fifth series resonator S5 and the antenna matching inductor L2.

[0094] The fourth parallel resonator P4 had an aperture length of 17.83λ, a logarithm of 61.0, and a resonator capacitance of 0.78pF. The fifth parallel resonator P5 consisted of two resonators connected in series, each with an aperture length of 17.95λ, a logarithm of 106.5, and a resonator capacitance of 1.38pF. The TRx matching inductor TRxL was set to 3.3nH. The antenna matching inductor ANTL was also set to 3.3nH.

[0095] Figure 6 shows the passband characteristics of the elastic wave device 20 in Embodiment 1. As shown in Figure 6, the elastic wave device 20 in Embodiment 1 realizes a broadband band 41 transmit / receive filter. Band 41 has a frequency passband from 2496 MHz to 2690 MHz. The relative bandwidth is 7.48%. Because it is used for transmit and receive, a high level of power handling capacity is required, so a ladder-type filter is adopted.

[0096] Furthermore, in order to realize a wideband bandpass filter, a ladder-type filter that constitutes the high-frequency passband, shown by the dashed line LD1, and a ladder-type filter that constitutes the low-frequency passband, shown by the dashed line LD2, were combined to achieve the passband shown by the solid line B41.

[0097] Initially, simply using a ladder-type filter was insufficient to achieve the high power handling capacity required for bandpass filters used for transmission and reception. However, the layout of the device chip 25 in Embodiment 1 improved heat dissipation and increased power handling capacity by 0.3 dB, enabling the provision of an elastic wave device 20 that met the power handling requirements. Furthermore, by using a package substrate with improved heat dissipation, it was possible to provide an elastic wave device 20 with even greater heat dissipation and power handling capacity.

[0098] While several aspects of at least one embodiment have been described, it should be understood that various modifications, alterations, and improvements will be readily conceivable to those skilled in the art. Such modifications, alterations, and improvements are intended to be part of and within the scope of this disclosure.

[0099] It should be understood that the embodiments of the methods and apparatus described herein are not limited to their application to the structural and arrangement details of the components described above or illustrated in the accompanying drawings. The methods and apparatus can be implemented in other embodiments and carried out or performed in various ways.

[0100] Specific implementation examples are provided here for illustrative purposes only and are not intended to be limiting.

[0101] The expressions and terms used in this disclosure are for illustrative purposes only and should not be considered limiting. The use herein of “includes,” “equips,” “possesses,” “contains,” and variations thereof means the inclusion of the items listed herein and their equivalents, as well as the supplementary items.

[0102] The use of "or" can be interpreted as meaning that any term used with "or" refers to one, more than one, or all of the terms described.

[0103] References to front / back, left / right, top / bottom / top / bottom, width / height, and front / back are all intended for convenience of description. Such references do not mean that the components of this disclosure are limited to any single positional or spatial orientation. Accordingly, the above description and drawings are illustrative only. [Explanation of symbols]

[0104] 20 Elastic wave device, 23 Package substrate, 24 External connection terminals 25 Device chip, 26 Electrode pads, 27 Bumps, 28 Encapsulation section 52 Elastic wave element, 52a IDT electrode, 52b reflector 52c Comb-shaped electrode, 52d Electrode finger, 52e Busbar SS1 Wiring between first series resonators, SS2 Wiring between second series resonators SS3 Third series resonator wiring,

Claims

1. Package substrate and A piezoelectric substrate mounted on the aforementioned package substrate, A first ladder-type filter is formed on the piezoelectric substrate and includes a first series resonator, a second series resonator, and a first parallel resonator, A wiring that electrically connects the first series resonator and the second series resonator, A first ground pad electrically connected to the first parallel resonator, The package substrate and the piezoelectric substrate are provided together with a sealing portion that hermetically seals the piezoelectric substrate, The first series inter-resonator wiring is an elastic wave device located at the outer edge of the piezoelectric substrate, relative to the first parallel resonator and the first ground pad.

2. The elastic wave device according to claim 1, wherein the first parallel resonator includes a first parallel divided resonator and a second parallel divided resonator connected in parallel, and the first ground pad is located between the first parallel divided resonator and the second parallel divided resonator.

3. The elastic wave device according to claim 2, wherein the first ground pad is positioned on the outer edge side of the piezoelectric substrate rather than the center of the first parallel resonator.

4. The elastic wave device according to claim 2, further comprising a first heat dissipation floating pad positioned between the first parallel resonator and the second parallel resonator, on the side of the piezoelectric substrate that is closer to the center of the first parallel resonator.

5. A third series resonator, a fourth series resonator, and a second parallel resonator formed on the piezoelectric substrate, A second ground pad electrically connected to the second parallel resonator, A second series resonator wiring that electrically connects the third series resonator and the fourth series resonator, It further includes a second ladder-type filter, The elastic wave device according to claim 1, wherein the wiring between the second series resonators is located on the outer edge of the piezoelectric substrate, relative to the second parallel resonator and the second ground pad.

6. The second ladder-type filter is, The fifth series resonator and the third parallel resonator, The third parallel resonator and the third ground pad are electrically connected, The third series resonator wiring further includes an electrical connection between the fourth series resonator and the fifth series resonator, The elastic wave device according to claim 5, wherein the wiring between the third series resonators is located on the outer edge of the piezoelectric substrate, relative to the third parallel resonator and the third ground pad.

7. The elastic wave device according to claim 6, wherein the fourth series resonator is positioned between the second ground pad and the third ground pad, and the second ground pad and the third ground pad are positioned at the outer edge of the piezoelectric substrate rather than at the center of the second series resonator.

8. The elastic wave device according to claim 5, wherein the first ladder filter and the second ladder filter have common input / output pads and constitute a single bandpass filter.

9. The elastic wave device according to claim 8, wherein the bandpass filter has a relative bandwidth of 6% or more and 9% or less.

10. The elastic wave device according to claim 8, wherein the first ladder-type filter comprising the bandpass filter constitutes the high-frequency passband and the second ladder-type filter constitutes the low-frequency passband.

11. A second heat dissipation floating pad formed between the first parallel divided resonator and the second ground pad, The elastic wave device according to claim 7, further comprising a third heat dissipation floating pad formed between the second parallel divided resonator and the third ground pad.

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