Power semiconductor devices and methods for manufacturing power semiconductor devices

Abstract

A power semiconductor device (1) is defined, comprising: - a first electrode (2); - a first semiconductor layer (3) of a first conductivity type; - a drift layer (4) of a first conductivity type; - a second semiconductor layer (5) of a second conductivity type different from the first conductivity type; and - a second electrode (6), wherein - the first semiconductor layer (3) is structured by several doped regions (7) of the second conductivity type in the terminal region (8) surrounding the active region (9) of the power semiconductor device (1); and - at least one of the first semiconductor layer (3) and the second semiconductor layer (5) has a slope structure (19). Furthermore, a method for manufacturing the power semiconductor device (1) is defined.

Description

Technical Field

[0001] The present disclosure relates to a power semiconductor device and a method for manufacturing a power semiconductor device.

Summary of the Invention

Means for Solving the Problems

[0002] Embodiments of the present disclosure relate to power semiconductor devices with improved performance. Further embodiments of the present disclosure relate to methods for manufacturing such power semiconductor devices.

[0003] This is achieved by the subject matter of the independent claims. Further embodiments are apparent from the dependent claims in the following description.

[0004] A power semiconductor device is described. Here, in the following, the term "power" refers to, for example, a power semiconductor module, a power semiconductor device, and / or a power semiconductor chip configured to handle voltages and currents above 100 V and / or above 10 A, illustratively a voltage of up to 10 kV and a current of up to 10 kA in amperes.

[0005] According to one embodiment, the power semiconductor device comprises a first electrode. The first electrode illustratively extends laterally. For example, the first electrode is configured to be conductively contacted from the outside. Illustratively, the first electrode contains or consists of a metal.

[0006] The first electrode may include a first layer and a second layer stacked on top of each other in a lateral, vertical, and vertical direction. For example, the first layer may contain a metal different from the metal contained in the second layer. The first layer may, exemplary, contain molybdenum, and the second layer may, exemplary, contain aluminum, and / or other metals such as copper, titanium, and / or nickel. In particular, the first layer may be configured to be electrically contactable from the outside, and the second layer may be metallization. For example, metallization may be applied by a sputtering process or a vapor deposition process.

[0007] According to the embodiment, the power semiconductor device comprises a first semiconductor layer of a first conductivity type. The first semiconductor layer is exemplary in its transverse direction. For example, the first semiconductor layer comprises or consists of a semiconductor material. Exemplarily, the semiconductor material is silicon-based. The first semiconductor layer comprises, for example, a first dopant of a first conductivity type.

[0008] According to the embodiment, the power semiconductor device comprises a drift layer of a first conductivity type. The drift layer is exemplary in its laterally extending direction. For example, the drift layer comprises or consists of a semiconductor material. Exemplarily, the semiconductor material comprises or consists of the same material as the first semiconductor layer. The drift layer comprises, for example, a further first dopant of the first conductivity type. The further first dopant of the drift layer is, for example, the same dopant as the first semiconductor layer.

[0009] For example, the maximum doping concentration of the drift layer is lower than the maximum doping concentration of the first semiconductor layer.

[0010] According to the embodiment, the power semiconductor device comprises a second semiconductor layer having a second conductivity type different from that of a first conductivity type. The second semiconductor layer is exemplary in its lateral extension. For example, the second semiconductor layer comprises or consists of a semiconductor material. Exemplarily, the semiconductor material comprises or consists of the same material as the first semiconductor layer. The first semiconductor layer comprises, for example, a second dopant of the second conductivity type.

[0011] For example, the first conductivity type may be n-type and the second conductivity type may be p-type, or vice versa.

[0012] According to the embodiment, the power semiconductor device includes a second electrode, which is exemplary in its laterally extending configuration. For example, the second electrode is configured to be electrically contactable from the outside. Exemplarily, the second electrode includes or is made of a metal.

[0013] The second electrode may include a third and a fourth layer stacked on top of each other in the vertical direction. For example, the third layer may contain a metal different from the metal contained in the fourth layer. The third layer may include, exemplary, aluminum, and / or other metals such as copper, titanium, nickel, tungsten, platinum, and / or gold, and the fourth layer may include, exemplary, molybdenum. In particular, the third layer is a metallization, and the further layers are configured to be electrically contacted from the outside.

[0014] For example, the first electrode is the cathode electrode of a power semiconductor device, and the second electrode is the anode electrode of a power semiconductor device, or vice versa.

[0015] The first and fourth layers are not present in, for example, the power semiconductor device. The first and fourth layers are provided, for example, for handling the power semiconductor device, and the first electrode includes only the second layer, and the second electrode includes only the third layer.

[0016] According to an embodiment of a power semiconductor device, the first semiconductor layer is structured by several doped regions of a second conductivity type within a terminal region surrounding the active region of the power semiconductor device. The terminal region is the peripheral region of the power semiconductor device, and the active region is the central region of the power semiconductor device. The peripheral region completely surrounds the active region in the lateral direction.

[0017] The active region is located at the center of mass of the power semiconductor device and extends laterally toward at least one edge of the power semiconductor device. The termination region extends laterally along the edge region of the power semiconductor device that defines the active region.

[0018] The doped regions extend within the terminal regions. Exemplarily, each doped region completely encloses the active region laterally. For example, each doped region has a shape that is a polygon such as a circle, ellipse, or quadrilateral in plan view. In particular, the plan view shape of the doped regions corresponds to the plan view outline of the power semiconductor device, especially the drift layer.

[0019] For example, the doped region extends vertically within the first semiconductor layer to a predetermined depth. The predetermined depth is less than the height of the first semiconductor layer in the vertical direction.

[0020] The dope region may, for example, include a further second dopant. The further second dopant may be the same dopant as the second dopant.

[0021] The maximum doping concentration of the first semiconductor layer is, exemplary, greater than or equal to the maximum doping concentration of the doped region. Preferably, the maximum doping concentration of the first semiconductor is higher than the maximum doping concentration of the doped region.

[0022] For example, the power semiconductor described herein is a fast recovery diode, in particular a free-floating discrete fast recovery diode. Furthermore, the power semiconductor described herein may be a reverse-conducting integrated gate commutation thyristor, i.e., an RC-IGCTS. The RC-IGCTS comprises a diode portion and a GCT portion, with an isolation region disposed between the diode portion and the GCT portion. The diode comprises all the elements described herein in the active region, and the isolation region is formed from all the elements of the termination region.

[0023] In summary, such a power semiconductor device having a first semiconductor layer interrupted in the terminal region by doped regions of different conductivity types can offer, among other advantages, the following:

[0024] Conveniently, the doped region reduces the emitter injection efficiency in the termination region. Due to the doped region, the termination region of the power semiconductor device is effectively electrically isolated from conduction (on) operation by significantly reducing the emitter injection efficiency in the termination region. Conveniently, less heat is generated in the termination region, which has lower cooling capacity. Therefore, thermal stability is improved in frequency operation or surge current events, enabling the power semiconductor device to operate at higher temperatures.

[0025] According to a further embodiment of the power semiconductor device, a first electrode, a first semiconductor layer, a drift layer, a second semiconductor layer, and a second electrode are stacked on top of each other along a vertical stacking direction. Directly adjacent elements, for example, are in direct contact with each other. Exemplarily, the first layer of the first electrode faces away from the first semiconductor layer, and the second layer of the first electrode faces the first semiconductor layer. Exemplarily, the third layer of the second electrode faces the second semiconductor layer, and the fourth layer of the second electrode faces away from the second semiconductor layer.

[0026] According to a further embodiment of the power semiconductor device, the first semiconductor layer includes a first sub-layer facing the first electrode and a second sub-layer facing the drift layer. For example, the maximum doping concentration of the first sub-layer is higher than the maximum doping concentration of the second sub-layer. The maximum doping concentration of the first sub-layer is, for example, at least one order of magnitude higher than the maximum doping concentration of the second sub-layer.

[0027] For example, the predetermined depth of each doped region is smaller than the height of the first sub-layer in the vertical direction.

[0028] According to a further embodiment of the power semiconductor device, the second semiconductor layer includes a third sub-layer facing the drift layer and a fourth sub-layer facing the second electrode. For example, the maximum doping concentration of the fourth sub-layer is higher than the maximum doping concentration of the third sub-layer. The maximum doping concentration of the fourth sub-layer is, for example, at least one order of magnitude higher than the maximum doping concentration of the third sub-layer. For example, the maximum doping concentration of the fourth sub-layer is equal to the maximum doping concentration of the doped region. Alternatively, the maximum doping concentration of the doped region can be made higher than the maximum doping concentration of the fourth sub-layer.

[0029] According to a further embodiment of the power semiconductor device, one of the first electrode and the second electrode extends over the active region and the termination region. In particular, only one of the first electrode and the second electrode extends over the active region and the termination region.

[0030] For example, the first electrode extends laterally to completely cover the first semiconductor layer. In particular, the second layer of the first electrode completely covers the lower surface of the first sub-layer of the first semiconductor layer, especially in the active region and the termination region. Exemplarily, the first layer of the first electrode covers the second layer of the first electrode only in the active region. This means that the first layer of the first electrode extends only laterally in the active region.

[0031] Alternatively, the second electrode extends to completely cover the second semiconductor layer in the lateral direction. In particular, the third layer of the second electrode completely covers the upper surface of the fourth sublayer of the second semiconductor layer, especially in the active and terminal regions. Exemplarily, the fourth layer of the second electrode covers the third layer of the second electrode only in the active region. This means that the fourth layer of the second electrode extends only in the active region in the lateral direction.

[0032] According to a further embodiment of the power semiconductor device, the other of the first electrode and the second electrode extends only to the active region.

[0033] If the first electrode completely covers the first semiconductor layer in the lateral direction, i.e., extends to the active and terminal regions, then the second electrode extends only to the active region. In particular, the third and fourth layers of the second electrode have the same extent in the lateral direction.

[0034] If the second electrode completely covers the second semiconductor layer in the lateral direction, i.e., extends to the active and terminal regions, then the first electrode extends only to the active region. In particular, the first and second layers of the first electrode have the same extent in the lateral direction.

[0035] According to a further embodiment of the power semiconductor device, the fourth sublayer extends laterally into the active region and the termination region. For example, in a plan view, the fourth sublayer overlaps with the active region and at least partially overlaps with the termination region. If the second semiconductor layer has a beveled structure, the fourth sublayer overlaps with the termination region by at least 20% or at least 50% in a plan view.

[0036] In a further embodiment of the power semiconductor device, the fourth sublayer extends only to the active region. In particular, the fourth sublayer overlaps only with the active region and not with the termination region in a plan view.

[0037] This, conveniently, further reduces the emitter efficiency in the terminating region. According to an embodiment of a power semiconductor device, at least one of the first semiconductor layer and the second semiconductor layer has a beveled surface structure. Exemplarily, each of the first and second semiconductor layers has a lower surface and an upper surface that extend laterally, and the upper and lower surfaces are connected by at least one side surface. At least one side surface of the first and second semiconductor layers is inclined with respect to the vertical direction in the termination region.

[0038] For example, the slope structure is placed in the terminal region. In particular, the slope structure is placed only in the terminal region. Exemplarily, the slope structure defines the extent of the terminal region in the lateral direction.

[0039] According to a further embodiment of the power semiconductor device, the third and fourth sublayers are tapered toward the second electrode in the termination region. This means that a bevel structure is arranged within the second semiconductor layer such that the sides of the second semiconductor layer formed by the sides of the third and fourth sublayers surround the top surface of the drift layer at an angle of less than 90°.

[0040] The joint depth can be predetermined according to the angle, that is, according to the steepness of the slope structure. This means that the emitter efficiency in the terminal region can be precisely pre-set according to the angle.

[0041] In a further embodiment of the power semiconductor device, the third sublayer is tapered toward the second electrode in the termination region. This means that, when the fourth sublayer extends only into the active region, a bevel structure is arranged within the second semiconductor layer such that the side surface of the second semiconductor layer formed on the side of the third sublayer surrounds the top surface of the drift layer at an angle of less than 90°.

[0042] Conveniently, the emitter efficiency in the termination region can be precisely preset depending on the angle.

[0043] In a further embodiment of the power semiconductor device, the first sublayer and doped region are tapered toward the first electrode in the terminating region. This means that a bevel structure is arranged within the first semiconductor layer such that the side surface of the first semiconductor layer formed on the side surface of the first sublayer surrounds the lower surface of the drift layer at an angle of less than 90°.

[0044] For example, the height of the doped region and the height of the first sublayer decrease in the direction from the active region to the edge of the power semiconductor device due to the slanted structure.

[0045] Furthermore, the second sublayer may be tapered toward the first electrode in the terminal region. This means that the side surface of the second sublayer surrounds the lower surface of the drift layer at a further angle of less than 90°. The side surface of the first semiconductor layer is formed in particular by the side surface of the first sublayer and the side surface of the second sublayer. The angle is, exemplary, smaller than the further angle.

[0046] In a further embodiment of the power semiconductor device, the doped regions are separated from each other laterally by a first sublayer. This means that the first sublayer is positioned between directly adjacent doped regions. Exemplarily, in a plan view, the doped regions do not overlap with the first sublayer.

[0047] For example, the second sublayer is directly adjacent to the doped region between two regions of the first sublayer. In particular, the vertical height of the second sublayer is higher where the doped region is adjacent to the second sublayer than the height of the second sublayer where the first sublayer is adjacent to the second sublayer.

[0048] According to a further embodiment of the power semiconductor device, the first sublayer is divided into segments laterally by the doped regions. Exemplarily, the segments are separated laterally by the doped regions, meaning that directly adjacent segments are not in physical contact with each other.

[0049] For example, a segment can be embedded in a doped region. This means that at least one or all of the outer surfaces of each segment are covered by the doped region, or in particular, completely covered.

[0050] Exemplary, the segments extend within the terminal region. For example, each segment completely encloses the active region in the lateral direction. This means that each segment has a shape that is a polygon such as a circle, ellipse, or quadrilateral in plan view. In particular, the shape of the segment in plan view corresponds to the outline of the power semiconductor device, especially the drift layer, in plan view.

[0051] This means that the emitter efficiency will conveniently decrease even further. According to further embodiments of power semiconductor devices, each segment has a cross-sectional shape that is quadrangular, circular, elliptical, or polygonal. The polygons are, for example, quadrilateral or hexagonal. In particular, the cross-sectional shape is defined perpendicular to the transverse direction.

[0052] According to a further embodiment of the power semiconductor device, the first sublayer comprises several further doped regions of a second conductivity type within the active region. The further doped regions are located in the lateral direction from the interface between the active region and the terminal region toward the center of mass of the power semiconductor device. For example, the further doped regions extend completely in the lateral direction from the interface between the active region and the terminal region to the interface opposite the active region and the terminal region.

[0053] Further doped regions extend within the active region. Illustratively, each of these further doped regions completely surrounds the center of mass of the terminal region. Illustratively, each of these further doped regions has a shape in plan view that corresponds to the shape of the doped region in plan view.

[0054] An additional doping region, exemplary, contains a second additional dopant. This means that the doping region and the additional doping region contain the same dopant. Exemplarily, the maximum doping concentration of the additional doping region is exemplary, equal to the maximum doping concentration of the doping region.

[0055] According to a further embodiment of the power semiconductor device, further doped regions are separated from each other laterally by a first sublayer. For example, the first sublayer is separated laterally into further segments by further doped regions within the active region. Exemplarily, the further segments are separated laterally by further doped regions. This means that directly adjacent further segments are not in physical contact with each other in particular.

[0056] For example, additional segments can be embedded in additional doped regions. This means that at least one or all of the outer surfaces of each additional segment are covered, and in particular completely covered, by the additional doped region. Each additional segment has, for example, a cross-sectional shape corresponding to the segment.

[0057] Exemplary, the further doped region extends vertically within the first semiconductor layer from the lower surface of the first semiconductor layer facing the first electrode to a further predetermined depth. This further predetermined depth is less than the height of the first semiconductor layer, particularly the first sublayer, in the vertical direction.

[0058] According to a further embodiment of the power semiconductor device, the lateral width of each doped region is equal to at least some further widths of the further doped regions. The widths and further widths correspond to the minimum extents of the doped region and the further doped regions in the lateral direction, respectively.

[0059] If further doped regions extend laterally from the terminal region within the active region to the extent of the extension distance, the width of each doped region is equal to the further width of each of the further doped regions.

[0060] If further doped regions extend laterally from the interface to a distance greater than the extension distance, the width of each doped region is equal to the further width of each further doped region within the extension distance, and the width of each doped region is different from the further width of each further doped region not located within the extension distance.

[0061] If further segments extend laterally from the terminal region within the active region to the extent of the extension distance, the width of each segment is equal to the further width of each of the further segments.

[0062] If further doped segments extend laterally from the interface to a distance greater than the extension distance, the width of each segment is equal to the further width of each further segment within the extension distance, and the width of each segment is different from the further width of each further segment not located within the extension distance.

[0063] According to a further embodiment of the power semiconductor device, the lateral width of each doped region is smaller than the width of at least some further doped regions.

[0064] If further doped regions extend laterally from the interface to a further distance, the width of each doped region is equal to the further width of each further doped region within the extension distance, and the width of each doped region is smaller than the further width of each further doped region not located within the extension distance.

[0065] Alternatively, the width of each doped region is smaller than the further width of each of the further doped regions within the active region.

[0066] If further segments extend laterally from the interface to a further distance, the width of each segment is equal to the further width of each further segment within the extension distance, and the width of each segment is smaller than the further width of each further segment not located within the extension distance.

[0067] Alternatively, the width of each segment is smaller than the further width of each of the further segments within the active region.

[0068] The width of a doped region can define the width of a segment. Furthermore, the further width of a further doped region can define the further width of a further segment. Moreover, the width of a segment and / or the width of a further segment depends on the number of doped regions and / or further doped regions. The number of doped regions may be the same as or different from the number of segments, and further / or the number of further doped regions may be the same as or different from the number of further segments.

[0069] For example, at least one of the segment and the further segment has a width of 30 μm to 300 μm, particularly 100 μm to 200 μm. Exemplarily, at least one of the directly adjacent segments and the further directly adjacent segments have a distance from each other in the lateral direction of 30 μm to 400 μm, particularly 100 μm to 200 μm. The distance corresponds to at least one of the width of the doped region and the further width of the further doped region.

[0070] According to a further embodiment of the power semiconductor device, the additional doped region extends laterally from the terminal region into the active region to an extended distance. In particular, the additional doped region extends laterally from the interface between the terminal region and the active region into the active region to an extended distance.

[0071] According to a further embodiment of the power semiconductor device, the extension distance is between 1 and 7 times the vertical height of the drift layer. In particular, the extension distance is between 3 and 5 times the height of the drift layer.

[0072] Such an extended distance favorably reduces the emitter efficiency at the interface between the terminal region and the active region.

[0073] In further embodiments, the power semiconductor device includes passivation, which, for example, encloses layers of the power semiconductor device. The first and second electrodes, in particular, do not have passivation in part. Exemplarily, the first layer of the first electrode and the fourth layer of the second electrode do not have passivation.

[0074] Passivation includes electrically insulating materials such as dielectric materials. For example, passivation materials include semi-insulating materials on a silicon surface. In addition to insulating the semiconductor surface from its surroundings, the role of such materials is to dissipate leakage current to one of the electrodes, especially at high temperatures.

[0075] In a further embodiment of the power semiconductor device, the first electrode, the first semiconductor layer, the drift layer, the second semiconductor layer, and the second electrode are surrounded by passivation in the termination region. For example, the sides of the layer and the electrode are completely covered by passivation.

[0076] For example, a slope structure is completely embedded in passivation. This means that the sides forming the slope structure are completely covered with passivation.

[0077] Conveniently, power semiconductor devices are protected from the environment by passivation.

[0078] According to a further embodiment of the power semiconductor device, an oxide layer extending within the active region is disposed on at least one of the first semiconductor layer or the second semiconductor layer.

[0079] The oxide layer extends within the active region, particularly from the terminal region toward the center of mass. Exemplarily, the oxide layer has a polygonal shape, such as a circle, ellipse, or quadrilateral, in plan view. In particular, the planar shape of the oxide layer corresponds to the planar shape of the power semiconductor device, especially the drift layer.

[0080] For example, the oxide layer is placed on a semiconductor layer that does not have doped regions. If the first semiconductor layer includes doped regions, the oxide layer is placed on the second semiconductor layer. If the second semiconductor layer includes doped regions, the oxide layer is placed on the first semiconductor layer.

[0081] When the oxide layer is placed on the first sublayer, the oxide layer faces the first electrode. When the oxide layer is placed on the fourth sublayer, the oxide layer faces the second electrode.

[0082] By using oxide layers, particularly combinations of oxide layers and doped regions, the emitter efficiency can be precisely predetermined and reduced.

[0083] Furthermore, a method for manufacturing power semiconductor devices is described herein, by which the power semiconductor devices described herein can be manufactured or are manufactured. Thus, features relating to power semiconductor devices are also disclosed relating to methods, and vice versa.

[0084] According to one embodiment of this method, a drift layer is provided on a semiconductor material. For example, the semiconductor material is silicon-based. The semiconductor material is provided particularly as a wafer.

[0085] Exemplary, the first conductive drift layer is generated during the pulling of the silicon ingot. In other words, it is present in the silicon wafer at the start before manufacturing.

[0086] According to this embodiment of the method, a first semiconductor layer of a first conductivity type is formed in the drift layer from the first side. For example, a first dopant may be introduced into the wafer, e.g., the drift layer, from the first side by at least one of an ion implantation or deposition process, and then a diffusion process may be carried out.

[0087] According to this embodiment of the method, a second semiconductor layer having a second conductivity type different from the first conductivity type is formed within the drift layer from the second side opposite to the first side. For example, a second dopant may be introduced into the wafer, e.g., the drift layer, from the second side by at least one of an ion implantation or deposition process, and then a diffusion process may be carried out.

[0088] According to this embodiment of the method, the sloped surface structure is formed on at least one of the first semiconductor layer and the second semiconductor layer in the terminal region surrounding the active region of the power semiconductor device.

[0089] According to this embodiment of the method, the first semiconductor layer is structured such that the first semiconductor layer has several doped regions of a second conductivity type within the terminal region.

[0090] According to a further embodiment of this method, the slope structure is formed by a grinding process. According to a further embodiment of the present method, the doped region is generated by an injection process. For example, the doped region is generated from the first side. Exemplarily, a further second dopant is introduced into the wafer by using a mask.

[0091] The attached diagrams are included to provide further understanding. In the diagrams, elements of the same structure and / or function may be referred to by the same reference numerals. Please understand that the embodiments shown in the diagrams are illustrative and not necessarily drawn to a specific scale. [Brief explanation of the drawing]

[0092] [Figure 1] This is a cross-sectional view of a power semiconductor device according to an exemplary embodiment. [Figure 2] This is a cross-sectional view of a power semiconductor device according to an exemplary embodiment. [Figure 3] This is a cross-sectional view of a power semiconductor device according to an exemplary embodiment. [Figure 4]This is a cross-sectional view of a power semiconductor device according to an exemplary embodiment. [Figure 5] This is a cross-sectional view of a power semiconductor device according to an exemplary embodiment. [Figure 6] This is a cross-sectional view of a power semiconductor device according to an exemplary embodiment. [Figure 7] This is a schematic plan view of a power semiconductor device according to an exemplary embodiment. [Modes for carrying out the invention]

[0093] The power semiconductor device 1 according to the exemplary embodiment shown in Figure 1 comprises a first electrode 2 having a first layer 14 and a second layer 15, and a second electrode 6 having a third layer 16 and a fourth layer 17. The power semiconductor device 1 further comprises a first semiconductor layer 3 of a first conductivity type having a first sublayer 10 and a second sublayer 11, and a second semiconductor layer 5 of a second conductivity type having a third sublayer 12 and a fourth sublayer 13. Furthermore, the power semiconductor device 1 comprises a drift layer 4.

[0094] The first electrode 2, particularly the first layer 14 and the second layer 15, the first semiconductor layer 3, particularly the first sub-layer 10 and the second sub-layer 11, the drift layer 4, the second semiconductor layer 5, particularly the third sub-layer 12 and the fourth sub-layer 13, and the second electrode 6, particularly the third layer 16 and the fourth layer 17, are stacked on top of each other in a stacking direction corresponding to the vertical direction. Each layer extends in a horizontal direction perpendicular to the vertical direction. Furthermore, each layer is in direct contact with each other. The bottom surface of each layer faces the first electrode 2, and the top surface of each layer faces the second electrode 6.

[0095] The second layer 15 of the first electrode 2 completely covers the underside of the first sublayer 10 of the first semiconductor layer 3. The first layer 14 of the first electrode 2 completely covers the underside of the second layer 15 only in the active region 9 of the power semiconductor device 1. This means that the first layer 14 completely overlaps, and in particular is congruent to, the active region 9 in the lateral direction in a plan view.

[0096] In particular, the plan view shows the top surface of each element of the power semiconductor device 1 viewed from above and below.

[0097] The active region 9 is located at the center of mass of the power semiconductor device 1 and extends laterally around it. Figure 1 shows only half of the power semiconductor device 1. Illustratively, the left edge of Figure 1 contains the center of mass.

[0098] The termination region 8 extends laterally along the edge region of the power semiconductor device 1 that defines the active region 9. The first layer 14 of the first electrode 2 does not exist in the termination region 8. This means that the first layer 14 does not overlap with the termination region 8 in the later direction in a plan view.

[0099] The third layer 16 of the second electrode 6 completely covers the upper surface of the fourth sublayer 13 of the second semiconductor layer 5, but only in the active region 9. The fourth layer 17 of the second electrode 6 completely covers the upper surface of the third layer 16. This means that the third layer 16 and the fourth layer 17 each completely overlap, and in particular are congruent, with the active region 9 in the lateral direction in a plan view.

[0100] The third layer 16 and the fourth layer 17 of the second electrode 6 are not present in the terminal region 8. This means that the third layer 16 and the fourth layer 17 do not overlap with the terminal region 8 in the lateral direction in a plan view.

[0101] The second semiconductor layer 5 has a sloped structure 19 in the termination region 8. The side surface of the second semiconductor layer 5 connecting the upper and lower surfaces is inclined with respect to the vertical direction. The side surface of the second semiconductor layer 5 is inclined only in the termination region 8. The angle between the side surface of the second semiconductor layer 5 and the lower surface of the second semiconductor layer 5 is less than 90°, and especially less than 45°. This means that the third sublayer 12 and the fourth sublayer 13 are tapered toward the second electrode 6 in the termination region 8.

[0102] The first sublayer 10 of the first semiconductor layer 3 is structured in the terminal region 8 by several doped regions 7 of a second conductivity type. That is, the first sublayer 10 is structured by the doped regions 7 and divided into segments 20. Laterally, one of the doped regions 7 is positioned between directly adjacent segments. The doped regions 7 and segments 20 are arranged alternately laterally from the interface between the active region 9 and the terminal region 8 to the edge of the power semiconductor device 1. The alternating arrangement begins at the interface with one of the doped regions 7. This means that the segments 20 are separated from the first sublayer 10 in the active region 9 by the doped regions. Directly adjacent doped regions 7 and segments 20 are in direct contact with each other.

[0103] The doped region 7 has a width that defines the spacing between the segments 20 in the lateral direction. The width of each doped region is the same, and the width of each segment 20 is the same.

[0104] The lower surfaces of the first sublayer 10 and segment 20, as well as the lower surface of the doped region 7, terminate flat with respect to each other and extend within a common plane. The doped region 7 extends vertically from its lower surface to a predetermined depth. This predetermined depth is less than the height of the first semiconductor layer 3 in the vertical direction.

[0105] In a plan view, the doped region 7 completely overlaps with the second sublayer 11. Furthermore, in a plan view, the doped region 7 does not overlap with the first sublayer 10, particularly with segment 20. This means that the upper surface of the doped region 7 is completely covered by the second sublayer 11, which extends completely between segments 20 up to the doped region 7.

[0106] The power semiconductor device 1 further comprises a passivation 18. The passivation 18 encloses the layers of the power semiconductor device 1, and the first electrode 2 and the second electrode 6, in particular, do not have the passivation 18 in part.

[0107] In addition to the exemplary embodiment shown in Figure 1, the first sublayer 10 of the first semiconductor layer 3 is structured by several further doped regions 21 in the active region 9, according to the exemplary embodiment shown in Figure 2. That is, the first sublayer 10 is structured by further doped regions 21 in the active region 9 and divided into further segments 22.

[0108] In the lateral direction, one of the further doped regions 21 is positioned between directly adjacent further segments 22. The further doped regions 21 and further segments 22 are alternately arranged laterally from the interface toward the center of mass of the power semiconductor device 1. The alternating arrangement begins at the interface with one of the further segments 22. Directly adjacent further doped regions 21 and further segments 22 are in direct contact with each other.

[0109] The further doped region 21 has a width that defines the spacing of further segments 22 in the lateral direction and the further width of segment 20.

[0110] The lower surfaces of the first sublayer 10 and segment 20, as well as the lower surface of the further doped region 21, terminate flat with respect to each other and extend within a common plane. The further doped region 21 extends vertically from its lower surface to a further predetermined depth. This further predetermined depth is less than the height of the first semiconductor layer 3 in the vertical direction and equal to the predetermined depth.

[0111] The further doped region 21 completely overlaps with the second sublayer 11 in plan view. Furthermore, the further doped region 21 does not overlap with the first sublayer 10, in particular with the further segments 22, in plan view. This means that the upper surface of the further doped region 21 is completely covered by the second sublayer 11, which extends completely between the further segments 22 to the further doped region 21.

[0112] Alternatively, segment 20 and / or further segment 22 may be embedded in doped region 7 and / or further doped region 21. In this case, doped region 7 and / or further doped region 21 are formed continuously and completely cover the outer surfaces of each of segment 20 and / or further segment 22. In this case, doped region 7 and / or further doped region 21 completely overlap with the first sublayer 10, i.e., segment 20 and / or further segment 22, in a plan view.

[0113] The further doped region 21 extends laterally from the interface between the active region 9 and the terminal region 8 into the active region 9 to an extension distance 23. The extension distance 23 is between 1 and 7 times the vertical height of the drift layer 4.

[0114] Each doped region has the same width, and each further doped region has the same width. Furthermore, each segment has the same width, and each further segment has the same width.

[0115] In this embodiment, the width of segment 20 is equal to the width of a further segment 22. Furthermore, the width of doped region 7 is equal to the width of a further doped region 21.

[0116] In contrast to the exemplary embodiment in Figure 2, according to the exemplary embodiment in Figure 3, the first sublayer 10 of the first semiconductor layer 3 is fully structured in the active region 9 by several further doped regions 21. This means that the first sublayer 10 is structured in the active region 9 by further doped regions 21 and divided into further segments 22, and the further doped regions 21 and further segments 22 extend throughout the active region 9.

[0117] In this embodiment, the width of segment 20 is smaller than the width of the further segment 22. Furthermore, the width of doped region 7 is smaller than the width of the further doped region 21.

[0118] In the exemplary embodiment of Figure 4, the width of the further segments 22 is not the same for all of the further segments 22, in contrast to Figure 3.

[0119] In this embodiment, the width of segment 20 is equal to the width of the further segment 22 within the extended distance 23. Furthermore, the width of doped region 7 is equal to the width of the further doped region 21 within the extended distance 23. In the remaining part of the active region 9 excluding the extended distance 23, the width of segment 20 is smaller than the width of the further segment 22. Furthermore, in the remaining part of the active region 9 excluding the extended distance 23, the width of doped region 7 is smaller than the width of the further doped region 21.

[0120] In the exemplary embodiment shown in Figure 5, the fourth sublayer 13 extends only to the active region 9, in contrast to Figures 1-4. In plan view, the fourth sublayer 13 does not overlap with the terminal region 8.

[0121] According to the exemplary embodiment shown in Figure 6, the inclined surface structure 19 is arranged on the first semiconductor layer 3, in contrast to Figures 1 to 5.

[0122] The side surfaces of the first semiconductor layer 3, particularly the side surfaces of the first sub-layer 10, that connect the upper and lower surfaces of the first semiconductor layer 3 are inclined with respect to the vertical direction. The side surfaces of the first sub-layer 10 are inclined only in the termination region 8. The angle between the side surfaces of the first sub-layer 10 and the upper surface of the first semiconductor layer 3 is less than 90°, and especially less than 45°. This means that the first sub-layer 10 is tapered toward the first electrode 2 in the termination region 8. The lower surfaces of the doped region 7 and segment 20 are formed by the side surfaces of the first sub-layer 10. Because the side surfaces of the first sub-layer 10 are inclined, the vertical height of the doped region 7 and segment 20 decreases from the interface toward the passivation 18.

[0123] The sides formed by the sides of the second sublayer 11, the drift layer 4, and the second semiconductor layer 5 lie in a common plane. This common plane is inclined with respect to the vertical direction and also inclined with respect to the sides of the first sublayer 10.

[0124] The power semiconductor device 1 according to an exemplary embodiment shown in Figure 7 is a plan view of one of the power semiconductor devices 1 according to one of Figures 1 to 6. In plan view, the top surface of the fourth layer 17 and the passivation 18 are freely accessible. The external shape of the power semiconductor device 1 is circular.

[0125] The doped regions 7 are not visible in this figure and are therefore shown as dashed lines. The doped regions 7 extend within the terminal region 8, and each of the doped regions 7 completely surrounds the active region 9 in the lateral direction. In particular, each of the doped regions 7 has a circular shape in plan view, corresponding to the outline of the power semiconductor device 1 in plan view. [Explanation of symbols]

[0126] Reference sign 1. Power semiconductor devices 2. First electrode 3. First semiconductor layer 4 Drift Layer 5. Second semiconductor layer 6. Second electrode 7 Doping Area 8 Termination area 9 Active area 10. First sublayer 11. Second sublayer 12. Third sublayer 13. The fourth sublayer 14. The first layer 15. The second layer 16. The third layer 17. The fourth layer 18 Passivation 19 Slope structure 20 segments 21 Further doping areas 22 Further segments 23. Extended in distance

Claims

1. - The first electrode (2), - A first semiconductor layer (3) of the first conductivity type, - The first conductive drift layer (4) and, - A second semiconductor layer (5) having a second conductivity type different from the first conductivity type, - The second electrode (6) and A power semiconductor device (1) comprising, - The first semiconductor layer (3) is structured by several doped regions (7) of the second conductivity type in the terminal region (8) surrounding the active region (9) of the power semiconductor device (1), - A power semiconductor device (1) wherein at least one of the first semiconductor layer (3) and the second semiconductor layer (5) has a sloped surface structure (19) within the termination region (8).

2. - The power semiconductor device (1) according to claim 1, wherein the first electrode (2), the first semiconductor layer (3), the drift layer (4), the second semiconductor layer (5), and the second electrode (6) are stacked on each other along the vertical stacking direction.

3. - The first semiconductor layer (3) comprises a first sublayer (10) facing the first electrode (2) and a second sublayer (11) facing the drift layer (4), - The maximum doping concentration of the first sublayer (10) is higher than the maximum doping concentration of the second sublayer (11). - The second semiconductor layer (5) comprises a third sublayer (12) facing the drift layer (4) and a fourth sublayer (13) facing the second electrode (6). - The power semiconductor device (1) according to claim 1 or 2, wherein the maximum doping concentration of the fourth sublayer (13) is higher than the maximum doping concentration of the third sublayer (12).

4. - One of the first electrode (2) and the second electrode (6) extends to the active region (9) and the terminal region (8), - The power semiconductor device (1) according to claims 1 to 3, wherein the other of the first electrode (2) and the second electrode (6) extends only to the active region (9).

5. - The fourth sublayer (13) extends laterally to the active region (9) and the terminal region (8), or - The power semiconductor device (1) according to claim 3 or 4, wherein the fourth sublayer (13) extends only to the active region (9).

6. - The third sublayer (12) and the fourth sublayer (13) are tapered toward the second electrode (6) in the terminal region (8), - Only the third sublayer (12) is tapered toward the second electrode (6) in the terminal region (8), or - The power semiconductor device (1) according to any one of claims 3 to 5, wherein the first sublayer (10) and the doped region (7) are tapered toward the first electrode (2) in the terminal region (8).

7. - The power semiconductor device (1) according to any one of claims 1 to 6, wherein the doped regions (7) are separated from each other in the lateral direction by the first sub-layer (10).

8. - The first sublayer (10) is divided into segments (20) in the lateral direction by the doped region (7), - A power semiconductor device (1) according to any one of claims 1 to 7, wherein each segment (20) has a cross-sectional shape that is quadrangular, circular, elliptical, or polygonal.

9. - The first sublayer (10) comprises several further doped regions (21) of the second conductive type within the active region (9), - The power semiconductor device (1) according to any one of claims 1 to 8, wherein the further doped regions (21) are separated from each other laterally by the first sublayer (10).

10. - The lateral width of each of the doped regions (7) is the same as the width of at least some of the further doped regions (21), and - The lateral width of each of the doped regions (7) is smaller than the width of at least some of the further doped regions (21), A power semiconductor device (1) according to claim 9, which is at least one of the two.

11. - The further doped region (21) extends within the active region (9) from the terminal region (8) to a laterally extending distance (23), - The power semiconductor device (1) according to claim 9 or 10, wherein the extension distance (23) is 1 to 7 times the vertical height of the drift layer (4).

12. - Further equipped with passivation (18), - The power semiconductor device (1) according to any one of claims 1 to 11, wherein the first electrode (2), the first semiconductor layer (3), the drift layer (4), the second semiconductor layer (5), and the second electrode (6) are surrounded by the passivation (18) in the termination region (8).

13. - The power semiconductor device (1) according to any one of claims 1 to 12, wherein the oxide layer extending within the active region (9) is disposed on at least one of the first semiconductor layer (3) or the second semiconductor layer (5).

14. A method for manufacturing semiconductor devices, - A first conductive drift layer (4) is provided in the semiconductor material, - Manufacturing the first semiconductor layer (3) of the first conductivity type within the drift layer (4) from the first side, - A second semiconductor layer (5) having a second conductivity type different from the first conductivity type is manufactured within the drift layer (4) from the second side opposite to the first side, - A slanted surface structure (19) is manufactured in at least one of the first semiconductor layer (3) and the second semiconductor layer (5) in the terminal region (8) surrounding the active region (9) of the power semiconductor device (1), - The first semiconductor layer (3) is structured such that the first semiconductor layer (3) has several doped regions (7) of the second conductivity type within the terminal region (8). Includes, - A method wherein the semiconductor device further comprises a first electrode (2) and a second electrode (6).

15. - The inclined surface structure (19) is manufactured by a grinding process, and - The doped region (7) is produced by an injection process. The method according to claim 14, wherein at least one of the above.

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