Coating components for semiconductor processing using fluorine-containing materials

Abstract

An exemplary processing method may include providing a semiconductor processing component to a processing area of ​​a processing chamber. The method may include providing one or more deposition precursors to the processing area. One or more deposition precursors may include a metal-containing precursor and a fluorine-containing precursor. The method may include depositing a layer of material on the semiconductor processing component in the processing area. The layer of material includes a material containing a metal and fluorine.

Description

[Technical Field]

[0001] Cross-reference with related applications

[0001] This application claims the benefits and priority of U.S. Patent Application No. 18 / 135,434, filed on April 17, 2023, entitled “COATING COMPONENTS FOR SEMICONDUCTOR PROCESSING WITH FLUORINE-CONTAINING MATERIALS,” which is incorporated herein by reference in its entirety.

[0002] Technical field

[0002] This technology relates to a coating process and components of a semiconductor chamber. More specifically, this technology relates to modified components and component materials. [Background technology]

[0003]

[0003] Integrated circuits are made possible by a process that creates layers of intricately patterned material on the surface of a substrate. Generating patterned material on a substrate requires a controlled method for forming and removing exposed material. The deposition and removal operation may include, for example, generating a remote or local plasma in the processing area of ​​a semiconductor processing chamber between a showerhead or gas distributor and a substrate support. Components of the semiconductor processing chamber may be exposed to plasma species during processing. If components are repeatedly exposed to corrosive species, degradation of the components and contamination of the substrate being processed may occur. Therefore, a topcoat may be provided to protect the underlying components from corrosion and / or erosion. However, applying a topcoat may require the use of volatile precursors and may be a time-consuming process.

[0004]

[0004] Therefore, there is a need for improved systems and methods that can be used to manufacture high-quality devices and structures. These and other needs are addressed by this technology. [Overview of the project]

[0005]

[0005] An exemplary processing method may include providing semiconductor processing components in a processing region of a processing chamber. The method may include providing one or more deposition precursors in the processing region. The one or more deposition precursors may include a metal-containing precursor and a fluorine-containing precursor. The method may include depositing a layer of material on the semiconductor processing components in the processing region. The layer of material includes a material containing metal and fluorine.

[0006]

[0006] In some embodiments, the semiconductor processing components may be or include a ceramic-containing material. The ceramic-containing material may be or include aluminum oxide (Al2O3), aluminum oxyfluoride (AlO y , y , x F y ), yttrium oxide (Y2O3), yttrium oxyfluoride (YO x F y ), magnesium oxide (MgO), magnesium oxyfluoride (MgO x F y ), titanium oxide (TiO2), titanium oxyfluoride (TiO x F y ), aluminum nitride (AlN), aluminum oxynitride (AlO x N y ), silicon nitride (Si3N4) or silicon oxynitride (SiO x N y ). The metal-containing precursor may include a hexafluoroacetylacetone compound. The metal-containing precursor may include aluminum, calcium, erbium, lanthanum, magnesium, scandium, titanium, yttrium or zirconium. The fluorine-containing precursor may be or include hydrogen fluoride (HF), ammonium fluoride (NH4F) or ammonium bifluoride ([NH4]F·HF). The layer of material may be or include aluminum fluoride (AlF3), aluminum oxyfluoride (AlO x F y ), calcium fluoride (CaF2), calcium oxyfluoride (CaO x F y), yttrium fluoride (YF3), yttrium oxyfluoride (YO x F y ), zirconium fluoride (ZrF4), zirconium oxyfluoride (ZrO x F y ), scandium fluoride (ScF3) or scandium oxyfluoride (ScO x F y ) may be. One or more deposition precursors further comprise oxygen-containing precursors. The material layer may be a material containing metal, fluorine, and oxygen. The oxygen-containing precursors include water vapor (H2O), molecular oxygen (O2), ozone (O3), nitrous oxide (N2O), hydrogen peroxide (H2O2), oxygen-containing plasma, or alcohol-based plasma. The material layer further comprises nitrogen. The method may include generating plasma emissions of one or more deposition precursors. The method may include annealing the semiconductor processing components after depositing the material layer. The semiconductor processing components may be annealed in a pressure-controlled oxygen-containing environment, an inert environment, or an active gas environment. The temperature in the processing area may be maintained below about 2,000°C. The semiconductor processing components may be or include lids, nozzles, faceplates, gas distribution plates, heaters, screws, substrate supports, support platens, liners, edge rings, process kit rings, or lift pins.

[0007]

[0007] Some embodiments of the present technology encompass processing methods. The method may include providing a semiconductor processing component in a processing area of ​​a processing chamber. The method may include depositing a layer of material on the semiconductor processing component in the processing area. The layer of material may be or include a material containing a metal and fluorine. Depositing the layer of material may include exposing the semiconductor processing component to plasma emissions of a first precursor, purging the processing area, and exposing the semiconductor processing component to plasma emissions of a second precursor. The layer of material may include reaction products of plasma emissions from the first precursor and plasma emissions from the second precursor. The temperature inside the processing chamber may be maintained at about 400°C or higher.

[0008]

[0008] In some embodiments, the semiconductor processing component may be or include aluminum oxide (Al2O3), aluminum oxyfluoride (AlO x F y ), yttrium oxide (Y2O3), yttrium oxyfluoride (YO x F y ), magnesium oxide (MgO), magnesium oxyfluoride (MgO x F y ), titanium oxide (TiO2), titanium oxyfluoride (TiO x F y ), aluminum nitride (AlN), aluminum oxynitride (AlO x N y ), silicon nitride (Si3N4) or silicon oxynitride (SiO x N y ). The layer of material may be or include a material containing metal, fluorine, and oxygen.

[0009]

[0009] Some embodiments of the present technology may include semiconductor processing components. The components may include ceramic components for semiconductor processing. The components may include a layer of a material containing metal and fluorine on the semiconductor processing component. The layer of the material containing metal and fluorine may be formed on the semiconductor processing ceramic component using a fluorine-containing precursor containing ammonium fluoride (NH4F) or ammonium bifluoride ([NH4]F-HF), a metal-containing precursor containing a hexafluoroacetylacetone compound, or both. The temperature during the formation of the layer of the material containing metal and fluorine on the semiconductor processing component may be maintained at about 400 °C or higher.

[0010]

[0010] In some embodiments, the semiconductor processing component may be or include a lid, nozzle, faceplate, gas distribution plate, heater, screw, substrate support, support platen, liner, edge ring, process kit ring, or lift pin.

[0011]

[0011] Such a technique can bring many advantages compared to the prior art. For example, the present method can provide a coated component for semiconductor processing with improved compatibility for plasma processing applications. For example, the component can be chemically reduced to remove the passivation layer on the grain of the component. In this way, for example, by atomic layer deposition, a layer of material can be directly coated on the component. Further, specific precursors and / or operating conditions can be utilized to facilitate the process for forming a layer of corrosion-resistant and / or erosion-resistant material on the component. The precursors and / or operating conditions can also improve throughput and reduce the waiting time of the coated component. Thus, the coated component for semiconductor processing can exhibit improved thermal, mechanical, and / or chemical properties, including in a halogen plasma environment where semiconductor processing operations are performed. Along with these numerous advantages and features, these embodiments and other embodiments will be described in further detail in conjunction with the following description and the accompanying drawings.

[0012]

[0012] The nature and advantages of the disclosed technology can be further understood by referring to the remainder of this specification and the drawings.

Brief Description of the Drawings

[0013] [Figure 1]

[0013] A schematic diagram of an exemplary processing chamber according to some embodiments of the present technology is shown. [Figure 2]

[0014] An exemplary operation in a deposition method according to some embodiments of the present technology is shown. [Figure 3]

[0015] A schematic diagram of a component during the process of a deposition method according to some embodiments of the present technology is shown. [Figure 4]

[0016] A schematic diagram of an exemplary processing chamber component formed by a method according to some embodiments of the present technology is shown.

Best Mode for Carrying Out the Invention

[0014]

[0017] Some drawings are included as schematic diagrams. Please understand that the drawings are for illustrative purposes only, and scale should not be considered unless specifically indicated. Furthermore, as schematic diagrams, they are provided to aid understanding and may not include all aspects or information compared to a realistic depiction, and may include exaggerated material for illustrative purposes.

[0015]

[0018] In the attached drawings, similar components and / or features may have the same reference numeral. Furthermore, various components of the same type may be distinguished according to their reference numerals by letters that distinguish them from similar components. Where only a first reference numeral is used herein, the description is applicable to any of the similar components having the same first reference numeral, regardless of the letters.

[0016]

[0019] As part of semiconductor processing technology, deposition and removal operations may include generating remote or local plasma in a processing area of ​​a semiconductor processing chamber, for example, between a showerhead or gas distributor and a substrate support. The components of the semiconductor processing chamber may be or include ceramic materials. To protect the ceramic material during plasma-based operations, a topcoat may be provided to protect the underlying material. The topcoat may be a combination of materials, such as a metallic fluoride. However, forming a metallic fluoride may require a corrosive fluorine-containing precursor or a slow deposition operation that requires a long processing time to form a layer of material on the components.

[0017]

[0020] Conventional techniques have attempted to deposit metal fluorides using corrosive fluorine-containing precursors. These corrosive precursors require careful handling during processing. Furthermore, conventional techniques used time-consuming deposition methods to deposit metal fluorides, resulting in reduced throughput. This technology overcomes these limitations by implementing an improved deposition method that removes the natural passivation layer from the constituent material, thereby enabling material deposition on the constituent material by means of atomic layer deposition, for example. In addition, concerns about corrosivity during processing can be mitigated by using specific fluorine-containing precursors that are less corrosive than conventional fluorine-containing precursors. Moreover, material formation can be accelerated by performing the deposition process at higher temperatures than conventional processes. Depositing material at a faster rate than conventional processes improves throughput and reduces waiting times. This could enable, for example, the preparation of coated components for semiconductor processing, which can be applied to plasma processing chamber components with tuned thermal, mechanical, and chemical properties under conditions used for semiconductor processing. As a result, coated components for semiconductor processing can be implemented in semiconductor processing chambers exposed to plasma processing.

[0018]

[0021] After describing a general configuration of a chamber according to embodiments of this technique in which plasma processing can be performed, specific methodologies and component configurations may be described. Since this technique can be used to improve many film formation processes and can be applied to various processing chambers and operations, it will be understood that this technique is not intended to be limited to the specific films and processes described.

[0019]

[0022] Figure 1 shows a schematic diagram of an exemplary processing chamber 100 according to several embodiments of the present technology. The figure may show an overview of a system that incorporates one or more aspects of the present technology and / or can perform one or more processes according to embodiments of the present technology. Further details of the chamber 100 or the method performed may be described further below. Although the chamber 100 may be used to form a film layer according to several embodiments of the present technology, it should be understood that the method can be similarly performed in any chamber in which film formation may be performed. The processing chamber 100 may include a chamber body 102, a plasma system 104 within the chamber body 102, a temperature control system 106, and a remote plasma system 108 coupled to the chamber body 102 and configured to provide plasma emitters to a processing area 120 of the chamber body 102.

[0020]

[0023] Components for semiconductor processing may be supplied to the processing area 120 via material feedthroughs such as ports or conduits that can be sealed for processing using slit valves, gate valves, or doors. Precursors, such as those described below, may be supplied to the chamber 100 through a gas supply system 110. Although Figure 1 illustrates a single inlet for the gas supply system 110, the chamber 100 may include multiple gas inlets coupled to the chamber body 102 at one or more locations. For example, a plasma precursor may be introduced into the chamber body through a remote plasma system 108, while a second gas inlet may provide gases whose plasma dissociation would adversely affect the deposition process. The gases may be removed from the chamber body 102 by a gas removal system 112. The gas removal system 112 may include a vacuum system configured to facilitate depressurization operations during the deposition process and to evacuate the chamber to remove process emissions and unreacted treatment gases. A measurement and control system may be coupled to the chamber to measure operating pressure at one or more locations, such as the gas supply system 110, the gas removal system 112, or the processing area 120. In another example, the temperature control system 106 may include a temperature sensor and a heating element configured to supply heat to or remove heat from the processing area 120. In this way, the chamber 100 can perform controlled deposition and removal processes, such as plasma etching and removal, and atomic layer deposition.

[0021]

[0024] As part of performing plasma processing of semiconductor processing components within the chamber 100 according to the method described below, the plasma system 104 may be configured to form a plasma within the processing region 120. The plasma system 104 may be or include an indirect plasma system, such as an RF capacitively coupled plasma, configured to form a plasma within the processing region 120 by generating a sufficiently strong electric field inside the chamber body 102. In some embodiments, the plasma system 104 may be or include a direct plasma system such that one or more electrode surfaces are located inside the chamber body. In this way, the processing region 120 can be defined between the active electrode of the plasma system 104 and a reference ground electrode. The plasma system 104 may also include control systems and power supply systems, such as impedance matching circuits and a 13.56 MHz RF power supply.

[0022]

[0025] Similarly, the remote plasma system 108 may be or include a direct or indirect plasma system, such as an inductively coupled RF plasma system or a capacitively coupled RF plasma system. These may be configured to decompose a precursor into plasma emitters that can be provided to the processing area 120. For example, the gas supply system 110 may include a quartz inlet tube coupled to a feedthrough to the chamber body 102. In such a configuration, the remote plasma system 108 may be or include an ICP or CCP system located outside the quartz inlet tube and configured to form plasma inside the quartz inlet tube. As further illustrated with reference to Figure 2, the precursor may include an inert carrier gas and a reaction precursor that may be or may include a vapor or gas. In this way, the remote plasma system 108 may form an indirect plasma in the precursor and decompose the precursor. The decomposed precursor may be or may include a carrier gas, an unreacted precursor, and plasma emitters that may be or may include plasma-generating species. Plasma-generated species can function as reactants in conformal deposition processes, including but not limited to chemical vapor deposition (CVD) and atomic layer deposition (ALD), as well as in direct-line deposition processes, including but not limited to physical vapor deposition (PVD), ion beam (IB) deposition, electron beam (EB) deposition, or electron beam-ion-assisted deposition (EB-IAD). Similar to plasma system 104, remote plasma system 108 may also include control systems and power supply systems, such as impedance matching circuits and a 13.56 MHz RF power supply.

[0023]

[0026] The temperature control system 106 may be configured to maintain the internal temperature of the processing area according to the processing method. For example, as part of atomic layer deposition, a deposition substrate, such as a component for semiconductor processing, may be heated to a preferred reaction temperature for specific reaction products. In an exemplary example, a surface reaction that forms a layer of material on a deposition substrate may be thermodynamically favorable at high temperatures. Thus, the temperature control system 106 may provide heat to the processing area. In some embodiments, the temperature control system may be at least partially integrated into the plasma system 104. For example, the electrodes of the plasma system 104 may incorporate heating and / or cooling elements, enabling the plasma system to operate within an operating temperature range.

[0024]

[0027] In some embodiments, the chamber 100 may be configured to prepare coated components for semiconductor processing, in which the components are coated with one or more layers of material. As described with reference to the following methods and systems, the chamber 100 can enable the preparation of improved coated ceramic-containing components for semiconductor processing that can be incorporated into semiconductor processing systems. Such components may exhibit improved thermal, mechanical, and / or chemical properties under processing conditions characteristic of plasma deposition and removal operations as part of semiconductor processing.

[0025]

[0028] Figure 2 shows exemplary steps in Method 200 according to several embodiments of the present technology. The method may be carried out in various processing chambers, including the processing chamber 100 described above. Method 200 may include several optional steps that may or may not be particularly relevant to some embodiments of the method according to the present technology. For example, many of the steps described are provided to offer a broader range of structure formation, but may be performed by alternative methods that are not critical to the technology or that can be easily understood.

[0026]

[0029] Method 200 describes a process schematically shown in Figure 3, the illustration of which will be explained in relation to the process of Method 200. Figure 4 shows an exemplary semiconductor processing system incorporating materials manufactured according to several embodiments of Method 200. Figures 3 and 4 are schematic diagrams of only parts, and it will be understood that the processing system may include subsystems as illustrated in the figures, as well as alternative subsystems, and may be of any size or configuration from which the embodiments of this technology can still be beneficial.

[0027]

[0030] Figure 3 shows a schematic diagram of a semiconductor processing component 300 in the process of Method 200 according to several embodiments of the present technology. In some embodiments, Method 200 may include one or more steps preceding the steps shown in Figure 2. For example, one or more steps may be performed to form the semiconductor processing component 300 from raw material. For example, the semiconductor processing component 300 may be formed by chemically converting an oxide to a nitride and may be cleaned by, for example, baking, etching, or degreasing. Examples of nitride synthesis include, but are not limited to, carbon thermal nitriding and / or direct nitriding. Furthermore, the semiconductor processing component 300 may be introduced into a processing chamber such as a chamber 100 having a passivation layer 305. For example, the semiconductor processing component 300 may be or contain aluminum nitride, which may form an oxide passivation layer by exposure to oxygen during cleaning or to air under ambient conditions.

[0028]

[0031] Method 200 may include additional steps before commencing the enumerated steps. For example, as shown in Figure 3, Method 200 may include removing a passivation layer 305, such as a native oxide or surface oxide, before coating the components. Removing the passivation layer may include supplying hydrogen to the processing area of ​​the chamber. Hydrogen may allow the formation of a hydrogen plasma, hydrogen-rich plasma, or trace hydrogen plasma in the processing area as an approach to chemically reduce the passivation layer 305. Hydrogen may be supplied to the processing area of ​​the chamber together with an inert carrier gas. In a plasma system, an inert carrier gas (also called a forming gas) facilitates plasma ignition and control of plasma conditions. For example, by providing a predetermined inert gas fraction to the hydrogen, the plasma can be operated under controlled plasma conditions such as ionization fraction, ion temperature, or electron temperature. After introducing hydrogen to the processing area, Method 200 may include impregnating the processing area with plasma. The plasma may be or may contain hydrogen plasma and may contain high-energy plasma species such as hydrogen ions, hydrogen radicals, or metastable diatomic hydrogen. The hydrogen plasma may be formed in the processing region while the semiconductor processing component 300 is positioned in the processing region. Plasma processing can be performed based on hydrogen supplied together with a carrier gas such as argon or helium to generate the plasma, and hydrogen may constitute a proportion of the material in the mixed gas.

[0029]

[0032] During method 200, the semiconductor processing component 300 may be positioned within the processing area. In step 205, method 200 may include delivering the semiconductor processing component 300 to the processing area of ​​a semiconductor processing chamber, such as the processing chamber 100, or another chamber that may contain the above-mentioned component. The semiconductor processing component 300 may comprise a plurality of individual particles. The particles constituting the semiconductor processing component 300 may be made of any type of material, and in embodiments may be made of a ceramic-containing material. For example, the particles of the semiconductor processing component 300 may be aluminum oxide (Al2O3), aluminum oxyfluoride (AlO3), etc. x Fy ), yttrium oxide (Y2O3), yttrium oxyfluoride (YO x F y ), magnesium oxide (MgO), magnesium oxyfluoride (MgO x F y ), titanium dioxide (TiO2), titanium oxyfluoride (TiO2) x F y ), aluminum nitride (AlN), aluminum oxynitride (AlO x N y ), silicon nitride (Si3N4) or silicon oxynitride (SiO2 x N y ) may include, but is not limited to, these.

[0030]

[0033] In some embodiments, method 200 may optionally include oxidizing the semiconductor processing component in an optional step 210. The optional step 210 may include introducing oxygen into the processing area of ​​the chamber. Introducing oxygen into the processing area as part of plasma-enhanced deposition may make it possible to form a controlled oxide layer on the semiconductor processing component 300. In contrast to the passivation layer 305, the controlled oxide layer may be formed under controlled conditions, such as in an oxygen plasma within the processing area, so that an oxide layer with a characteristic and uniform thickness can be formed on the semiconductor processing component 300. Furthermore or alternatively, the optional step 210 may include thermal oxidation of the semiconductor processing component 300 following the removal of the passivation film 305. The surface oxide layer may, for example, act as a diffusion barrier, thereby providing improved control over the thermal, mechanical, and / or chemical properties of the semiconductor processing component 300. In this way, it may be advantageous to reduce the semiconductor processing component 300 to remove the passivation layer 305, and then oxidize the semiconductor processing component 300 under controlled conditions to reform the oxide layer.

[0031]

[0034] After oxidizing the semiconductor processing component 300 in an optional step 210, method 200 may include forming a layer of material 315 on the semiconductor processing component 300 in step 215. In some embodiments, forming the layer of material 315 on the semiconductor processing component 300 may include performing an atomic layer deposition (ALD) process, thereby uniformly coating the semiconductor processing component 300. However, as previously stated, forming the layer of material 315 can be carried out using various deposition methods. For example, step 215 may include introducing plasma emitters into the processing area. The plasma emitters may be or include plasma-generated species formed by a remote plasma system, such as the remote plasma system 108 in Figure 1, which is in communication with the processing area. The introduction of plasma emitters may include introducing a carrier gas containing the plasma emitters. By introducing plasma emitters into the processing area in this way, the semiconductor processing component 300 can be exposed to plasma emitters of one or more plasma-decomposed precursors. Therefore, the plasma emitters may be or contain ions, activated radicals, metastable species, and other decomposition products, and may be characterized by a lower average energy distribution than that of a direct plasma system. By exposing the semiconductor processing component 300 to the plasma emitters, a monolayer of adsorbed plasma emitters is formed on the surface of the semiconductor processing component 300, which serves as a precursor for the formation of the material layer 315.

[0032]

[0035] In the second step of atomic layer deposition, the plasma emitters of the first precursor can be removed from the processing area by purging the gas from the processing area while holding the semiconductor processing component 300 having the adsorbed monolayer. Purging the processing area can be performed using a gas removal system such as the gas removal system 112 shown in Figure 1. After purging, the second precursor can be decomposed into second plasma emitters so that the semiconductor processing component 300 is exposed to the second plasma emitters. The second precursor may be selected to decompose into plasma-generated species that react with the monolayer adsorbed on the semiconductor processing component 300 to form a material layer 315. After the material layer 315 is formed, unreacted plasma emitters and reaction by-products can be removed by the gas removal system.

[0033]

[0036] In some embodiments, the first and second precursors may be selected such that the material layer 315 is or contains corrosion-resistant and / or erosion-resistant additives for improving the mechanical properties of the semiconductor processing component 300. For example, the material layer 315 may be a material containing a metal and fluorine. Thus, one precursor may be or contain a metal-containing precursor, and the other precursor may be or contain a fluorine-containing precursor. The metal may be or contain, for example, a rare earth element or a transition metal. For example, one of the precursors may contain a metal such as aluminum, calcium, erbium, lanthanum, magnesium, scandium, titanium, yttrium, or zirconium. In embodiments, the metal-containing precursor may contain a hexafluoroacetylacetone compound. For example, the metal may be present in solution with hexafluoroacetylacetone (hfac). For example, the metal-containing precursor may be or contain Mg(hfac)2 or magnesium(hfac)(dmg)H2O, Al(hfac)3, Y(hfac)3, etc. The other precursor may contain fluorine and may be, for example, hydrogen fluoride (HF), ammonium fluoride (NH4F), or ammonium difluoride ([NH4]F·HF). Other fluorine-containing precursors such as molecular fluorine (F2), nitrogen trifluoride (NF3), and HF-pyridine (HF·C5H5N) are also possible, but these precursors can be corrosive and therefore difficult to handle. Thus, hydrogen fluoride (HF), ammonium fluoride (NH4F), or ammonium difluoride ([NH4]F·HF) may allow for easier processing while providing the desired formation and material properties. Furthermore, one or more co-reactants may be provided along with the metal-containing precursor and / or fluorine-containing precursor. The co-reactants may be, but are not limited to, water or vapor (H2O), molecular oxygen (O2), ozone (O3), nitrous oxide (N2O), hydrogen peroxide (H2O2), oxygen-containing plasma or alcohol-based plasma, or other co-reactants useful for semiconductor processing, such as hydrogen fluoride (HF), F2, or NH4F.Furthermore, in embodiments in which the material layer 315 is to contain nitrogen, a nitrogen-containing precursor may be provided. Depending on the precursor used during deposition, the material layer 315 may be, for example, aluminum fluoride (AlF3), aluminum oxyfluoride (AlO3), etc. x F y ), calcium fluoride (CaF2), calcium oxyfluoride (CaO x F y ), yttrium fluoride (YF3), yttrium oxyfluoride (YO x F y ), zirconium fluoride (ZrF4), zirconium oxyfluoride (ZrO x F y ), scandium fluoride (ScF3) or scandium oxyfluoride (ScO x F y This may include, but materials containing other metals and fluorine are also considered, including a layer 315 of material containing multiple metals.

[0034]

[0037] In the embodiment, an additional layer of material may be formed on the semiconductor processing component 300, and the material layer 315 may contain additional elements. The additional material layer or material layer 315 may contain a plurality of different materials, including oxide or nitride materials, in addition to the material containing metal and fluorine. Other precursors other than the metal-containing precursor and the fluorine-containing precursor may include an oxygen source or a nitrogen source, such as water vapor (H2O), hydrogen peroxide (H2O2), oxygen (O2), oxygen-based plasma, ozone (O3), nitrous oxide (N2O), molecular nitrogen (N2), ammonia (NH3), hydrazine (N2H4), or nitrogen-based plasma. Depending on the precursor used, the additional material layer may be an oxide, nitride, or oxynitride. For example, the additional material layer may be, but is not limited to, aluminum oxide (Al2O3), yttrium oxide (Y2O3), magnesium oxide (MgO), titanium oxide (TiO2), erbium oxide (Er2O3), lanthanum oxide (La2O3), scandium oxide (Sc2O3), zirconium oxide (ZrO2), aluminum nitride (AlN), silicon nitride (SiN), tantalum nitride (TaN), titanium nitride (TiN), or zirconium nitride (ZrN).

[0035]

[0038] In some embodiments, the constructing step 215 may be repeated to deposit multiple single layers of material such that each single layer of material 315 is formed, and the thickness of each layer of material 315 is an integer multiple of the thickness of the single layer and the number of times step 215 is repeated. Furthermore, a second layer of material 320 may be formed on top of the material layer 315 by repeating the process using the same set of first and second precursors, or different sets of first and second precursors, following step 215. For example, if the material layer 315 may be or contain aluminum fluoride, the second material 320 may be or contain yttrium aluminum fluoride, or other fluorine such as other oxides, nitrides, or fluorides. Thus, the coated component 300 for semiconductor processing according to method 200 may include one or more additional layers of different materials, such as the controlled oxide layer, the material layer 315, and the second material layer 320.

[0036]

[0039] The flow rate of the precursor introduced into the chamber may depend at least in part on one or more parameters of the chamber, the semiconductor processing component 300, or the method 200. For example, the flow rate may be adjusted so that a plasma with sufficient energy density or species density, such as ions, free electrons, or an activating precursor, is formed to promote the reduction of the passivation layer 305 or the deposition of the material layer 315.

[0037]

[0040] In relation to the precursor flow rate, the pulse size of the first or second precursor may be less than 75 minutes or about 75 minutes. At times exceeding 75 minutes, the semiconductor processing component 300 becomes completely saturated and can no longer accept the precursor to form a monolayer of the material. Therefore, the pulse size of the first or second precursor may be about 70 minutes or less, about 65 minutes or less, about 60 minutes or less, about 55 minutes or less, about 50 minutes or less, about 45 minutes or less, about 40 minutes or less, about 35 minutes or less, about 30 minutes or less, about 25 minutes or less, about 20 minutes or less, about 15 minutes or less, about 10 minutes or less, about 5 minutes or less, about 2 minutes or less, about 1 minute or less, about 50 seconds or less, about 40 seconds or less, about 30 seconds or less, about 20 seconds or less, about 10 seconds or less, or less.

[0038]

[0041] Similarly, the pulse size of the purge gas for purging the first precursor may be approximately 120 minutes or less, for example, approximately 110 minutes or less, approximately 100 minutes or less, approximately 90 minutes or less, approximately 80 minutes or less, approximately 70 minutes or less, approximately 65 minutes or less, approximately 60 minutes or less, approximately 55 minutes or less, approximately 50 minutes or less, approximately 45 minutes or less, approximately 40 minutes or less, approximately 35 minutes or less, approximately 30 minutes or less, approximately 25 minutes or less, approximately 20 minutes or less, approximately 15 minutes or less, approximately 10 minutes or less, approximately 5 minutes or less, approximately 2 minutes or less, approximately 1 minute or less, or less. The purge may have a longer duration than the precursor to ensure that the precursor is completely removed from the processing area.

[0039]

[0042] During method 200, for example during step 215, the temperature inside the processing chamber can be maintained at 2,000°C or lower. Higher temperatures may be employed, but deposition in this technique is best performed at temperatures below 1,750°C, for example, below approximately 1,500°C, below approximately 1,250°C, below approximately 1,000°C, below approximately 900°C, below approximately 800°C, below approximately 750°C, below approximately 725°C, below approximately 700°C, below approximately 675°C, below approximately 650°C, below approximately 625°C, below approximately 600°C, below approximately 575°C, below approximately 550°C, below approximately 525°C, below approximately 500°C, below approximately 480°C, and below approximately 460°C. The process can be operated at temperatures below approximately 440°C, below approximately 420°C, below approximately 400°C, below approximately 380°C, below approximately 360°C, below approximately 340°C, below approximately 320°C, below approximately 300°C, below approximately 280°C, below approximately 260°C, below approximately 240°C, below approximately 220°C, below approximately 200°C, below approximately 180°C, below approximately 160°C, below approximately 140°C, below approximately 120°C, below approximately 100°C, below approximately 80°C, below approximately 60°C, below approximately 40°C, below approximately 20°C, or below. However, higher temperatures may increase material deposition and improve throughput. In some embodiments, ALD deposition performed at higher temperatures may allow the deposition to proceed more as CVD deposition. Therefore, the temperature inside the processing chamber may be approximately 300°C or higher, for example, approximately 350°C or higher, approximately 400°C or higher, approximately 450°C or higher, approximately 500°C or higher, or even higher.

[0040]

[0043] Furthermore, during method 200, for example during step 215, the pressure in the processing chamber can be maintained at approximately 50 mTorr or less. Higher pressures may also be employed, but the deposition of this technique can be operated at pressures of approximately 50 mTorr or less, for example, approximately 45 mTorr or less, approximately 40 mTorr or less, approximately 35 mTorr or less, approximately 30 mTorr or less, approximately 25 mTorr or less, approximately 20 mTorr or less, approximately 15 mTorr or less, approximately 10 mTorr, approximately 7 mTorr, approximately 5 mTorr or less, approximately 3 mTorr or less, approximately 1 mTorr or less, or less.

[0041]

[0044] The material layer 315 can be formed to a thickness of approximately 3000 nm or less, for example, approximately 2750 nm or less, approximately 2500 nm or less, approximately 2250 nm or less, approximately 2000 nm or less, approximately 1750 nm or less, approximately 1500 nm or less, approximately 1250 nm or less, approximately 1000 nm or less, approximately 750 nm or less, approximately 500 nm or less, approximately 250 nm or less, approximately 100 nm or less, or less. In embodiments, depending on the application, the material layer 315 can be formed to a much smaller thickness, for example, approximately 90 nm or less, approximately 80 nm or less, approximately 70 nm or less, approximately 60 nm or less, approximately 50 nm or less, approximately 40 nm or less, approximately 30 nm or less, approximately 20 nm or less, approximately 10 nm or less, approximately 5 nm or less, approximately 2 nm or less, approximately 1 nm or less, or less.

[0042]

[0045] In an optional step 220, the method 200 may include annealing the semiconductor processing component 300. Annealing the semiconductor processing component 300 in an optional step 220 can change the crystallinity and / or grain size of the material layer 315, or further improve the thermal, mechanical, and / or chemical properties of the material layer 315, such as corrosion resistance and / or erosion resistance, as well as hardness and other microstructural properties. For example, the material layer 315 may be formed as an amorphous structure, but annealing in an optional step 220 may cause the material layer 315 to transition to a crystalline structure. The semiconductor processing component 300 can be annealed in an oxygen-containing environment, an inert environment, or an active gas environment. In embodiments, the active gas environment may include, but is not limited to, a fluorine-containing environment. The fluorine-containing environment may include, but is not limited to, diatomic fluorine (F2). In the embodiment, the semiconductor processing component 300 may be annealed at a temperature of about 300°C or higher, for example, about 350°C or higher, about 400°C or higher, about 450°C or higher, about 500°C or higher, about 550°C or higher, about 600°C or higher, about 650°C or higher, about 700°C or higher, or higher, and may be at a temperature higher than the temperature in step 215. During any step 220, the pressure may be controlled and maintained above atmospheric pressure, below atmospheric pressure, or approximately at atmospheric pressure.

[0043]

[0046] Method 200 and its constituent steps may provide one or more improvements to plasma-enhanced deposition processes for depositing layers of material on semiconductor processing components, for example, by ALD. For example, Method 200 may provide a coated component for semiconductor processing characterized by a core-shell structure, where the core may be or include a ceramic material of the component, such as aluminum nitride or other ceramic material, which includes one or more shells, such as transition metal fluorides or rare earth fluorides. Layerwise deposition in atomic layer deposition allows for precise deposition of the shells, and by repeating step 215 a predetermined number of times, the relative composition of the coated component for semiconductor processing can be determined. Furthermore, plasma removal of the natural passivation layer 305 can improve control of surface chemistry and thus improve the thermal, mechanical, and / or chemical properties of the coated component for semiconductor processing.

[0044]

[0047] As further illustrated with reference to Figure 4, semiconductor processing components may, but are not limited to, lids, nozzles, faceplates, gas distribution plates, heaters, screws, substrate supports, support platens, liners, edge rings, process kit rings, or lift pins. Since these components are generally exposed to corrosive plasma conditions, corrosion-resistant and / or erosion-resistant coatings may be required. By using the coated components for semiconductor processing described above, corrosion-resistant and / or erosion-resistant materials can be efficiently formed on the components, providing the desired corrosion resistance and / or erosion resistance.

[0045]

[0048] Figure 4 shows a schematic diagram of an exemplary plasma processing system including one or more components formed by a method according to several embodiments of the present technology. Figure 4 further shows details of the semiconductor processing system 400 and one or more components that may be or may be incorporated into system 400 as coated components for semiconductor processing. The coated components for semiconductor processing may then be formed by coating a semiconductor processing component, such as a coated component for semiconductor processing prepared by method 200. System 400 is understood to include any feature or embodiment of a semiconductor processing chamber and may be used to perform semiconductor processing steps including deposition, removal, and cleaning steps. System 400 is discussed and may show a partial diagram of a chamber component that may be incorporated into a typical semiconductor processing system, and may show a diagram crossing the center of the pedestal and gas distributor (otherwise it may be of any size). Any embodiment of system 400 may also be incorporated into other processing chambers or systems as will be readily understood by those skilled in the art.

[0046]

[0049] The system 400 may include a semiconductor processing chamber 450, which includes a showerhead 405 through which a precursor 407 is delivered for processing and which may be configured to form plasma 410 in a processing area between the showerhead 405 and a pedestal or substrate support 415. The showerhead 405 can be understood to be at least partially located inside the chamber 450 and electrically isolated from the chamber 450. Thus, the showerhead 405 may function as the active electrode or reference ground electrode of the direct plasma system for exposing a substrate held on the substrate support 415 to plasma-generated species. The substrate support 415 may extend through the bottom surface of the chamber 450. The substrate support may include a support platen 420 that can hold the semiconductor substrate 430 during a deposition or removal process used to form a patterned structure on the semiconductor substrate 430.

[0047]

[0050] The support platen 420 may be or include a coated component for semiconductor processing prepared according to an embodiment of Method 200. The support platen 420 may incorporate embedded electrodes for providing an electrostatic field employed to support a semiconductor substrate. It may also include a thermal control system that can facilitate processing steps including, but not limited to, deposition, etching, annealing, or desorption. In some embodiments, the support platen 420 may incorporate any other distributed equipment of plates, perforated plates, meshes, wire screens, or conductive elements. The embedded electrodes may be or include regulating electrodes for providing further control over the plasma 410, for example, by regulating the electric field near the surface of the support platen. Similarly, bias electrodes and / or electrostatic chuck electrodes may be coupled to the support platen 420. The bias electrodes may be coupled to a power supply such as a DC power supply, a pulsed DC power supply, an RF bias power supply, a pulsed RF power supply or bias power supply, or a combination of these or other power supplies. In this way, the substrate support 415 and the support platen 420 can be used not only to hold the semiconductor substrate 430 during the plasma processing step, but also to adjust the conditions of the plasma 410. Adjusting the plasma conditions may include, for example, performing automatic impedance matching to maintain the plasma conditions during the plasma processing step while the composition of the plasma 410 changes, or when the surface of the semiconductor substrate 430 changes, for example, due to the deposition of a dielectric film on the electrode surface. In this way, precise control of the plasma 410 may depend on the material properties of the substrate support 415 and the support platen 420.

[0048]

[0051] In some cases, the support platen 420 or other chamber components may be formed by coating the semiconductor processing components with a layer of material 435. For example, the semiconductor processing components may be treated to deposit a layer of material 435, such as a corrosion-resistant and / or erosion-resistant material. Pre- and / or post-processing, such as annealing, machining, and assembly of electrical components, can be performed to finish the components and provide working components that can be incorporated into the plasma system. For example, an advantage of using components coated for semiconductor processing is that the finished components having one or more layers of material 435 function as fire-resistant conductors with good electrical conductivity, as well as good thermal deformation properties and chemical resistance to plasma etching.

[0049]

[0052] The foregoing description provides many details for illustrative purposes to provide an understanding of various embodiments of the Technology. However, it will be apparent to those skilled in the art that certain embodiments can be implemented by omitting some of these details or by adding additional details.

[0050]

[0053] While several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, some well-known processes and elements are not described in order to avoid unnecessarily obscuring the current art. Therefore, the above description should not be construed as limiting the scope of the Art. Moreover, while methods or processes may be described sequentially or stepwise, it should be understood that operations may be performed simultaneously or in a different order than those described.

[0051]

[0054] When a range of values ​​is presented, unless the context clearly indicates otherwise, it is understood that each intervening value between the upper and lower limits of that range is also specifically disclosed down to the smallest unit of the lower limit. Any narrow range between any stated or unstated intervening values ​​within the stated range, and any other stated or intervening values ​​within that stated range, are also included. The upper and lower limits of those smaller ranges can be independently included in or excluded from the range, and each range that does not include one of the restrictions, neither, or both restrictions within a smaller range is also technically included, influenced by the restrictions specifically excluded within the stated range. If one or both restrictions are included in the stated range, the range excluding one or both of the included restrictions is also included.

[0052]

[0055] As used herein and in the appended claims, the singular forms “a,” “an,” and “the” include plural references unless otherwise specified in the context. Thus, for example, a reference to “precursor” includes references to multiple such precursors, and a reference to “layer” includes references to one or more layers, as well as their equivalents known to those skilled in the art.

[0053]

[0056] Furthermore, the terms “comprise(s),” “comprising,” “contain(s),” “containing,” “include(s),” and “including,” as used herein and in the claims, are intended to identify the presence of the described features, integers, components, or processes, but not to exclude the presence or addition of one or more other features, integers, components, processes, operations, or groups.

Claims

1. A processing method, To provide semiconductor processing components in the processing area of ​​the processing chamber, The present invention provides one or more deposition precursors in the processing region, wherein the one or more deposition precursors include a metal-containing precursor and a fluorine-containing precursor. The method involves depositing a layer of material on the semiconductor processing component within the processing region, wherein the layer of material includes a material containing a metal and fluorine. A processing method that includes this.

2. The processing method according to claim 1, wherein the semiconductor processing component includes a ceramic-containing material.

3. where the ceramic-containing material is aluminum oxide (Al ２ O ３ ), aluminum oxyfluoride (AlOF ｘ F ｙ ), yttrium oxide (Y ２ O ３ ), yttrium oxyfluoride (YOF ｘ F ｙ ), magnesium oxide (MgO), magnesium oxyfluoride (MgOF ｘ F ｙ ), titanium oxide (TiO ２ ), titanium oxyfluoride (TiO ｘ F ｙ ), aluminum nitride (AlN), aluminum oxynitride (AlON ｘ N ｙ ), silicon nitride (Si ３ N ４ ), or silicon oxynitride (SiO ｘ N ｙ ), the processing method according to claim 2.

4. The treatment method according to claim 1, wherein the metal-containing precursor comprises a hexafluoroacetylacetone compound.

5. The processing method according to claim 1, wherein the metal-containing precursor comprises aluminum, calcium, erbium, lanthanum, magnesium, scandium, titanium, yttrium, or zirconium.

6. The fluorine-containing precursor is hydrogen fluoride (HF), ammonium fluoride (NH4F), or ammonium difluoride ([NH4F] ４ The processing method according to claim 1, including F and HF.

7. The layer of the aforementioned material is aluminum fluoride (AlF ３ ), aluminum oxyfluoride (AlO ｘ F ｙ ), calcium fluoride (CaF ２ ), calcium oxyfluoride (CaO ｘ F ｙ ), yttrium fluoride (YF ３ ), yttrium oxyfluoride (YO ｘ F ｙ ), zirconium fluoride (ZrF ４ ), zirconium oxyfluoride (ZrO ｘ F ｙ ), scandium fluoride (ScF ３ ) or scandium oxyfluoride (ScO ｘ F ｙ The processing method according to claim 1, including ).

8. The processing method according to claim 1, wherein the one or more deposition precursors further contain an oxygen-containing precursor, and the layer of the material contains a material containing a metal, fluorine, and oxygen.

9. The oxygen-containing precursor is water vapor (H ２ O), molecular oxygen (O ２ ), ozone (O ３ ), nitrous oxide ( ２ O), hydrogen peroxide (H ２ O ２ The processing method according to claim 8, comprising oxygen-containing plasma or alcohol-based plasma.

10. The processing method according to claim 1, wherein the layer of the material further contains nitrogen.

11. The processing method according to claim 1, further comprising generating plasma emissions of one or more deposition precursors.

12. The processing method according to claim 1, further comprising annealing the semiconductor processing component after depositing a layer of the material.

13. The processing method according to claim 12, wherein the semiconductor processing component is annealed in a pressure-controlled oxygen-containing environment, an inert environment, or an active gas environment.

14. The processing method according to claim 1, wherein the temperature within the processing area is maintained at approximately 2,000°C or less.

15. The processing method according to claim 14, wherein the semiconductor processing components include a lid, a nozzle, a faceplate, a gas distribution plate, a heater, a screw, a substrate support, a support platen, a liner, an edge ring, a process kit ring, or a lift pin.

16. A processing method, To provide semiconductor processing components in the processing area of ​​the processing chamber, Depositing a layer of material on the semiconductor processing component within the processing region, wherein the layer of material includes a material containing a metal and fluorine, and depositing the layer of material is Exposing the semiconductor processing component to the plasma emission of the first precursor, Purging the aforementioned processing area, Exposing the semiconductor processing component to the plasma emission of the second precursor This involves depositing layers of material, including A processing method comprising a layer of the material comprising a reaction product of the plasma emitters of the first precursor and the plasma emitters of the second precursor, wherein the temperature inside the processing chamber is maintained at approximately 400°C or higher.

17. The aforementioned semiconductor processing component is aluminum oxide (Al ２ O ３ ), aluminum oxyfluoride (AlO ｘ F ｙ ), yttrium oxide (Y ２ O ３ ), yttrium oxyfluoride (YO ｘ F ｙ ), magnesium oxide (MgO), magnesium oxyfluoride (MgO ｘ F ｙ ), titanium oxide (TiO ２ ), titanium oxyfluoride (TiO ｘ F ｙ ), aluminum nitride (AlN), aluminum oxynitride (AlO ｘ N ｙ ), silicon nitride (Si ３ N ４ ) or silicon oxynitride (SiO ｘ N ｙ The processing method according to claim 16, including ).

18. The processing method according to claim 16, wherein the layer of the material comprises a material containing metal, fluorine, and oxygen.

19. A component for semiconductor processing, Ceramic components for semiconductor processing, The semiconductor processing component includes a layer of a material containing metal and fluorine, The layer of the material containing the aforementioned metal and fluorine is ammonium fluoride (NH4F) or ammonium difluoride ([NH ４ A fluorine-containing precursor containing 1F·HF, a metal-containing precursor containing a hexafluoroacetylacetone compound, or both, is used to form the semiconductor processing ceramic component on the semiconductor processing ceramic component; The temperature during the formation of a layer of material containing the metal and fluorine on the semiconductor processing component is maintained at approximately 400°C or higher; Or both. Components for semiconductor processing.

20. A semiconductor processing component according to claim 19, comprising a lid, nozzle, faceplate, gas distribution plate, heater, screw, substrate support, support platen, liner, edge ring, process kit ring, or lift pin.

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