Semiconductor device and method for manufacturing the same

Abstract

Provided is a semiconductor device comprising: a semiconductor substrate including a drift region of a first electroconductive type; a base region of a second electroconductive type provided between the drift region and an upper surface of the semiconductor substrate; a plurality of trenches provided from the upper surface of the semiconductor substrate to below the base region; a lower end region of the second electroconductive type provided so as to be in contact with a lower end of two or more trenches; a well region of the second electroconductive type provided from the upper surface of the semiconductor substrate to below the base region, the well region having a higher doping concentration than the base region; and a high-resistance region of the second electroconductive type disposed between the lower end region and the well region when observed in a top view, the high-resistance region having a lower doping concentration than the lower end region.

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Conventionally, a structure is known in which a P-type floating region separated from a P-type well region is provided at the bottom of a gate trench (see, for example, Patent Document 1). [Prior art document] [Patent documents] [Patent Document 1] JP 2019-91892 A Problem to be Solved

[0003] It is preferable that the breakdown voltage or withstand voltage of the semiconductor device is not reduced.

[0004] In order to solve the above problems, a first aspect of the present invention provides a semiconductor device. The semiconductor device may include a semiconductor substrate having an upper surface and a lower surface, and including a drift region of a first conductivity type. The semiconductor device may include a base region of a second conductivity type provided between the drift region and the upper surface of the semiconductor substrate. The semiconductor device may include a plurality of trench portions provided from the upper surface of the semiconductor substrate to below the base region. The semiconductor device may include a lower end region of the second conductivity type provided in contact with the lower ends of the two or more trench portions. The semiconductor device may include a well region of the second conductivity type that is disposed at a position different from the lower end region in a top view, is provided from the upper surface of the semiconductor substrate to below the base region, and has a doping concentration higher than that of the base region. The semiconductor device may include a high resistance region of the second conductivity type that is disposed between the lower end region and the well region in a top view, and has a doping concentration lower than that of the lower end region.

[0005] The high resistance region may connect the bottom region and the well region.

[0006] The length of the high resistance region in a top view may be greater than the width of the high resistance region in the depth direction of the semiconductor substrate.

[0007] The high resistance region may border the bottom ends of two or more trench portions.

[0008] The semiconductor device may include an active portion surrounded by a well region in a top view, and the high resistance region may be disposed at a position in the active portion that contacts the well region.

[0009] The high resistance region may surround the active portion in a top view.

[0010] The high resistance region may have a first high resistance portion disposed at a corner of the active portion in a top view, and a second high resistance portion having a doping concentration lower than that of the first high resistance portion.

[0011] The high resistance region may have a lower doping concentration than the base region.

[0012] The doping concentration of the high resistance region may be 10% or less of the doping concentration of the bottom region.

[0013] The high resistance region may have a peak of doping concentration in a direction connecting the bottom region and the well region.

[0014] The peak doping concentration in the high resistance region may be 0.5 to 1.5 times the doping concentration in the bottom region.

[0015] The semiconductor device may include an emitter region of a first conductivity type provided between the base region and an upper surface of the semiconductor substrate and having a doping concentration higher than that of the drift region, and a part of the emitter region and a part of the high resistance region may overlap each other in a top view.

[0016] The semiconductor device may include an emitter region of a first conductivity type provided between the base region and an upper surface of the semiconductor substrate and having a doping concentration higher than that of the drift region, and the emitter region and the high resistance region may be spaced apart from each other in a top view.

[0017] The plurality of trench portions may include one or more gate trench portions, and the high resistance region may contact a bottom end of at least one of the gate trench portions.

[0018] The high resistance region may have a lower end portion in contact with the lower end of the gate trench portion, and a low concentration portion having a doping concentration lower than that of the lower end portion.

[0019] The semiconductor device may include an accumulation region provided between the base region and the drift region and having a doping concentration higher than that of the drift region. A part of the accumulation region and a part of the high resistance region may overlap in a top view.

[0020] In a top view, the trench may have a long side in a first direction and a short side in a second direction. A ratio of a first length of the high resistance region connecting the bottom end region and the well region in the first direction to a second length of the high resistance region connecting the bottom end region and the well region in the second direction may be 0.9 or more and 1.1 or less.

[0021] The doping concentration distribution in the high resistance region in the first direction may be flatter than the doping concentration distribution in the high resistance region in the second direction.

[0022] In a second aspect of the present invention, a method for manufacturing a semiconductor device is provided. The manufacturing method may include forming a base region of a second conductivity type between a drift region and the upper surface of a semiconductor substrate having an upper surface and a lower surface and including a drift region of a first conductivity type. The manufacturing method may include forming a plurality of trench portions provided from the upper surface of the semiconductor substrate to a position lower than the base region. The manufacturing method may include forming a lower end region of the second conductivity type provided in contact with the lower ends of two or more trench portions. The manufacturing method may include forming a well region of the second conductivity type that is disposed at a position different from the lower end region in a top view, is provided from the upper surface of the semiconductor substrate to a position lower than the base region, and has a doping concentration higher than that of the base region. The manufacturing method may include forming a high resistance region of the second conductivity type that is disposed between the lower end region and the well region in a top view and has a doping concentration lower than that of the lower end region.

[0023] In the manufacturing method, a dopant of the second conductivity type may be implanted into both the region in which the high resistance region is to be formed and the region in which the bottom region is to be formed. In the manufacturing method, a dopant of the second conductivity type may be further implanted into the region in which the bottom region is to be formed.

[0024] In the manufacturing method, a dopant of the second conductivity type may be implanted at different concentrations into a region in which the high resistance region is to be formed and a region in which the bottom region is to be formed.

[0025] In the manufacturing method, a dopant of the second conductivity type may be injected into a region in which the high resistance region is to be formed, away from a region in which the bottom end region is to be formed, and the dopant may be diffused toward the region in which the bottom end region is to be formed by heat treatment.

[0026] The above summary of the invention does not list all of the necessary features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0027] [Figure 1] FIG. 1 is a top view illustrating an example of a semiconductor device 100 according to an embodiment of the present invention. [Diagram 2] FIG. 2 is an enlarged view of an area D in FIG. [Diagram 3] FIG. 3 is a diagram showing an example of an ee cross section in FIG. 2. [Figure 4] 2 is a diagram showing an example of the arrangement of a well region 11 and a lower end region 202 when viewed from above. FIG. [Figure 5A] FIG. 5 is a diagram showing an example of the ff cross section in FIG. [Figure 5B] FIG. 5B is a diagram showing an example of the net doping concentration distribution in the aa cross section and the bb cross section in FIG. 5A. [Figure 6] FIG. 13 is a diagram showing an example of a doping concentration distribution in the X-axis direction. [Figure 7] FIG. 5 is a diagram showing an example of the gg cross section in FIG. [Figure 8]The results of measuring the relationship between the doping concentration of the high resistance region 204 and the breakdown voltage of the portion in which the high resistance region 204 is formed are shown. [Figure 9] 13 is a diagram showing another example of the arrangement of the high resistance region 204 in a top view. FIG. [Figure 10] 13 is a diagram showing another example of the arrangement of the high resistance region 204 in a top view. FIG. [Figure 11] 2A to 2C are diagrams illustrating some steps in a manufacturing method of the semiconductor device 100. [Figure 12] FIG. 11 is a diagram for explaining an example of a second region forming step S1104. [Figure 13] FIG. 11 is a diagram for explaining another example of the second region forming step S1104. [Figure 14] FIG. 11 is a diagram for explaining another example of the second region forming step S1104. [Figure 15] FIG. 13 is a diagram showing another example of the doping concentration distribution in the X-axis direction. [Figure 16] FIG. 13 is a diagram showing another example of the doping concentration distribution in the X-axis direction. [Figure 17] FIG. 13 is a diagram showing another example of the doping concentration distribution in the X-axis direction. [Figure 18] FIG. 13 is a diagram showing another example of the doping concentration distribution in the X-axis direction. [Figure 19] 11 is a diagram showing another example of the configuration of the lower end region 202 and the high resistance region 204. FIG. [Figure 20] 13 is a diagram showing an example of a doping concentration distribution in a high-resistance region 204. FIG. [Figure 21] 13 is a diagram showing another example of the arrangement of the high-resistance region 204 in the X-axis direction. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0029] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0030] In this specification, technical matters may be explained using orthogonal coordinate axes of X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components, and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without indicating positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0031] In this specification, the orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are the X-axis and the Y-axis. The axis perpendicular to the upper and lower surfaces of the semiconductor substrate is the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. In this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and the Y-axis, may be referred to as the horizontal direction.

[0032] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate may be referred to as the top surface side. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate may be referred to as the bottom surface side.

[0033] In this specification, when the term "same" or "equal" is used, it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0034] In this specification, the conductivity type of a doped region doped with impurities is described as P type or N type. In this specification, the impurity may particularly mean either an N type donor or a P type acceptor, and may be described as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to make it a semiconductor exhibiting an N type conductivity type or a semiconductor exhibiting a P type conductivity type.

[0035] In this specification, the doping concentration means the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding up the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charge. As an example, the donor concentration is N D , acceptor concentration N A Then, the net doping concentration at any position is N D -N A In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0036] A donor has the function of supplying electrons to a semiconductor. An acceptor has the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, a VOH defect, which is a combination of a vacancy (V), oxygen (O), and hydrogen (H) present in a semiconductor, functions as a donor that supplies electrons. In this specification, a VOH defect may be referred to as a hydrogen donor.

[0037] In this specification, the semiconductor substrate has N-type bulk donors distributed throughout. The bulk donor is a donor due to a dopant that is contained almost uniformly in the ingot when the ingot that is the base of the semiconductor substrate is manufactured. The bulk donor in this example is an element other than hydrogen. The dopant of the bulk donor is, for example, phosphorus, antimony, arsenic, selenium, or sulfur, but is not limited thereto. The bulk donor in this example is phosphorus. The bulk donor is also contained in the P-type region. The semiconductor substrate may be a wafer cut from a semiconductor ingot, or may be a chip obtained by dividing the wafer. The semiconductor ingot may be manufactured by any of the Czochralski method (CZ method), the magnetic field-applied Czochralski method (MCZ method), and the float zone method (FZ method). The ingot in this example is manufactured by the MCZ method. The oxygen concentration in the substrate manufactured by the MCZ method is 1×10 17 ~7×10 17 / cm 3 The oxygen concentration in the substrate manufactured by the FZ method is 1×10 15 ~5×10 16 / cm 3 A higher oxygen concentration tends to generate hydrogen donors more easily. The bulk donor concentration may be the chemical concentration of the bulk donors distributed throughout the semiconductor substrate, and may be between 90% and 100% of the chemical concentration. A non-doped substrate that does not contain dopants such as phosphorus may be used as the semiconductor substrate. In this case, the bulk donor concentration (D0) of the non-doped substrate is, for example, 1×10 10 / cm 3 That's it, 5 x 10 12 / cm 3 The bulk donor concentration (D0) of the non-doped substrate is preferably 1×10 11 / cm 3 The bulk donor concentration (D0) of the non-doped substrate is preferably 5×10 12 / cm 3 The concentrations in the present invention may be values ​​at room temperature. For example, the values ​​at room temperature may be values ​​at 300 K (Kelvin) (approximately 26.9° C.).

[0038] In this specification, when P+ type or N+ type is described, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is described, it means that the doping concentration is lower than that of P type or N type. Also, when P++ type or N++ type is described in this specification, it means that the doping concentration is higher than that of P+ type or N+ type. The unit system in this specification is the SI unit system unless otherwise specified. The unit of length may be expressed in cm, but various calculations may be performed after converting to meters (m).

[0039] In this specification, the chemical concentration refers to the atomic density of an impurity measured regardless of the state of electrical activation. The chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The above-mentioned net doping concentration can be measured by voltage-capacitance measurement (CV). The carrier concentration measured by spreading resistance measurement (SR) may be the net doping concentration. The carrier concentration measured by CV or SR may be a value in a thermal equilibrium state. In addition, in an N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in that region may be the donor concentration. Similarly, in a P-type region, the carrier concentration in that region may be the acceptor concentration. In this specification, the doping concentration in an N-type region may be referred to as the donor concentration, and the doping concentration in a P-type region may be referred to as the acceptor concentration.

[0040] In addition, when the concentration distribution of the donor, acceptor or net doping has a peak, the peak value may be taken as the concentration of the donor, acceptor or net doping in the region. In cases where the concentration of the donor, acceptor or net doping is almost uniform, the average value of the concentration of the donor, acceptor or net doping in the region may be taken as the concentration of the donor, acceptor or net doping. In this specification, the concentration per unit volume is expressed in atoms / cm. 3 , or / cm 3This unit is used for donor or acceptor concentration or chemical concentration in a semiconductor substrate. The atom count notation may be omitted.

[0041] The carrier concentration measured by the SR method may be lower than the concentration of the donor or acceptor. In the range where the current flows when measuring the spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The reduction in carrier mobility occurs when the carriers are scattered due to a disorder in the crystal structure caused by lattice defects, etc.

[0042] The donor or acceptor concentration calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element indicating the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which acts as a donor in a silicon semiconductor, or the acceptor concentration of boron, which acts as an acceptor, is about 99% of the chemical concentration. On the other hand, the donor concentration of hydrogen, which acts as a donor in a silicon semiconductor, is about 0.1% to 10% of the chemical concentration of hydrogen.

[0043] Fig. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Fig. 1 shows the positions of each component projected onto the top surface of a semiconductor substrate 10. Fig. 1 shows only some of the components of the semiconductor device 100, and some components are omitted.

[0044] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate made of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has end sides 162 in a top view. When simply referred to as a top view in this specification, it means a view from the top surface side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two pairs of end sides 162 facing each other in a top view. In FIG. 1, the X-axis and the Y-axis are parallel to either of the end sides 162. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10.

[0045] An active portion 160 is provided on the semiconductor substrate 10. The active portion 160 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode is provided above the active portion 160, but is omitted in FIG. 1 . The active portion 160 may refer to a region that overlaps with the emitter electrode in a top view. In addition, a region sandwiched between the active portions 160 in a top view may also be included in the active portion 160.

[0046] The active section 160 is provided with a transistor section 70 including a transistor element such as an IGBT (Insulated Gate Bipolar Transistor). The active section 160 may further be provided with a diode section 80 including a diode element such as a free wheel diode (FWD). In the example of Fig. 1, the transistor sections 70 and the diode sections 80 are alternately arranged along a predetermined arrangement direction (X-axis direction in this example) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 of this example is a reverse conducting IGBT (RC-IGBT).

[0047] In FIG. 1, the region in which the transistor section 70 is arranged is marked with the symbol "I", and the region in which the diode section 80 is arranged is marked with the symbol "F". In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (Y-axis direction in FIG. 1). The transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section described later.

[0048] The diode section 80 has an N+ type cathode region in a region in contact with the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is a region that overlaps with the cathode region in a top view. A P+ type collector region may be provided in a region of the lower surface of the semiconductor substrate 10 other than the cathode region. In this specification, an extension region 81 in which the diode section 80 is extended in the Y-axis direction to a gate wiring to be described later may also be included in the diode section 80. A collector region is provided on the lower surface of the extension region 81.

[0049] The transistor section 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10. In addition, the transistor section 70 has a gate structure, which has an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film, periodically arranged on the upper surface side of the semiconductor substrate 10.

[0050] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 164. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is disposed near an end edge 162. The vicinity of the end edge 162 refers to the region between the end edge 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0051] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to a conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring that connects the gate pad 164 and the gate trench portion. In FIG. 1, the gate wiring is hatched with oblique lines.

[0052] The gate wiring in this example has a peripheral gate wiring 130 and an active side gate wiring 131. The peripheral gate wiring 130 is disposed between the active portion 160 and an edge 162 of the semiconductor substrate 10 in a top view. The peripheral gate wiring 130 in this example surrounds the active portion 160 in a top view. The region surrounded by the peripheral gate wiring 130 in a top view may be the active portion 160. In addition, a well region is formed below the gate wiring. The well region is a P-type region with a higher concentration than a base region described later, and is formed from the top surface of the semiconductor substrate 10 to a position deeper than the base region. The region surrounded by the well region in a top view may be the active portion 160.

[0053] The peripheral gate wiring 130 is connected to the gate pad 164. The peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The peripheral gate wiring 130 may be a metal wiring containing aluminum or the like.

[0054] The active side gate wiring 131 is provided in the active section 160. By providing the active side gate wiring 131 in the active section 160, the variation in wiring length from the gate pad 164 for each region of the semiconductor substrate 10 can be reduced.

[0055] The peripheral gate wiring 130 and the active side gate wiring 131 are connected to a gate trench portion of the active section 160. The peripheral gate wiring 130 and the active side gate wiring 131 are disposed above the semiconductor substrate 10. The peripheral gate wiring 130 and the active side gate wiring 131 may be wiring formed of a semiconductor such as polysilicon doped with impurities.

[0056] The active side gate wiring 131 may be connected to the peripheral gate wiring 130. In this example, the active side gate wiring 131 is provided extending in the X-axis direction from one peripheral gate wiring 130 to the other peripheral gate wiring 130 sandwiching the active portion 160, so as to cross the active portion 160 at approximately the center in the Y-axis direction. When the active portion 160 is divided by the active side gate wiring 131, the transistor portion 70 and the diode portion 80 may be arranged alternately in the X-axis direction in each divided region.

[0057] Furthermore, the semiconductor device 100 may include a temperature sensor (not shown) that is a PN junction diode formed of polysilicon or the like, and a current detector (not shown) that simulates the operation of a transistor section provided in the active section 160.

[0058] In the present example, semiconductor device 100 includes an edge termination structure 90 between active portion 160 and edge 162 when viewed from above. Edge termination structure 90 in the present example is disposed between peripheral gate wiring 130 and edge 162. Edge termination structure 90 relieves electric field concentration on the top surface side of semiconductor substrate 10. Edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf that are provided in an annular shape surrounding active portion 160.

[0059] 2 is an enlarged view of region D in FIG. 1. Region D is a region including a transistor section 70, a diode section 80, and an active side gate wiring 131. The semiconductor device 100 of this example includes a gate trench section 40, a dummy trench section 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 provided inside the upper surface side of a semiconductor substrate 10. The gate trench section 40 and the dummy trench section 30 are each an example of a trench section. The semiconductor device 100 of this example also includes an emitter electrode 52 and an active side gate wiring 131 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active side gate wiring 131 are provided separately from each other.

[0060] An interlayer insulating film is provided between the emitter electrode 52 and the active side gate wiring 131 and the upper surface of the semiconductor substrate 10, but is omitted in Fig. 2. In this example, contact holes 54 are provided in the interlayer insulating film so as to penetrate the interlayer insulating film. In Fig. 2, each contact hole 54 is hatched with oblique lines.

[0061] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole 54. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to the dummy conductive portion of the dummy trench portion 30 at the tip of the dummy trench portion 30 in the Y-axis direction.

[0062] The active side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active side gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The active side gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0063] The emitter electrode 52 is made of a material containing metal. FIG. 2 shows the range in which the emitter electrode 52 is provided. For example, at least a portion of the emitter electrode 52 is made of aluminum or an aluminum-silicon alloy, such as a metal alloy such as AlSi or AlSiCu. The emitter electrode 52 may have a barrier metal made of titanium, a titanium compound, or the like, below the region made of aluminum or the like. Furthermore, the emitter electrode 52 may have a plug formed by embedding tungsten or the like in the contact hole so as to contact the barrier metal and aluminum or the like.

[0064] The well region 11 is provided so as to overlap with the active side gate wiring 131. The well region 11 is also provided so as to extend by a predetermined width to an area where it does not overlap with the active side gate wiring 131. The well region 11 in this example is provided away from the end of the contact hole 54 in the Y-axis direction toward the active side gate wiring 131. The well region 11 is a region of a second conductivity type having a higher doping concentration than the base region 14. In this example, the base region 14 is P- type, and the well region 11 is P+ type.

[0065] Each of the transistor section 70 and the diode section 80 has a plurality of trench sections arranged in the arrangement direction. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the arrangement direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the arrangement direction. In the diode section 80 of this example, no gate trench section 40 is provided.

[0066] The gate trench portion 40 in this example may have two straight line portions 39 (portions of the trench that are straight along the extension direction) extending along an extension direction perpendicular to the arrangement direction, and a tip portion 41 connecting the two straight line portions 39. The extension direction in FIG. 2 is the Y-axis direction.

[0067] At least a part of the tip portion 41 is preferably curved in a top view. By connecting the ends of the two straight portions 39 in the Y-axis direction with each other by the tip portion 41, electric field concentration at the ends of the straight portions 39 can be alleviated.

[0068] In the transistor section 70, the dummy trench section 30 is provided between the respective straight line portions 39 of the gate trench section 40. One dummy trench section 30 may be provided between the respective straight line portions 39, or a plurality of dummy trench sections 30 may be provided. The dummy trench section 30 may have a straight line shape extending in the extension direction, and may have a straight line portion 29 and a tip section 31, similar to the gate trench section 40. The semiconductor device 100 shown in FIG. 2 includes both a straight line dummy trench section 30 without a tip section 31 and a dummy trench section 30 with a tip section 31.

[0069] The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. The ends in the Y-axis direction of the gate trench portion 40 and the dummy trench portion 30 are provided in the well region 11 when viewed from above. That is, at the ends in the Y-axis direction of each trench portion, the bottoms in the depth direction of each trench portion are covered by the well region 11. This makes it possible to alleviate electric field concentration at the bottoms of each trench portion.

[0070] A mesa portion is provided between each trench portion in the arrangement direction. The mesa portion refers to a region sandwiched between the trench portions inside the semiconductor substrate 10. As an example, the upper end of the mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion. The mesa portion in this example is provided on the upper surface of the semiconductor substrate 10, extending in the extension direction (Y-axis direction) along the trench. In this example, the transistor portion 70 is provided with a mesa portion 60, and the diode portion 80 is provided with a mesa portion 61. In this specification, when the term "mesa portion" is simply used, it refers to each of the mesa portion 60 and the mesa portion 61.

[0071] A base region 14 is provided in each mesa portion. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, the region closest to the active side gate wiring 131 is defined as the base region 14-e. In FIG. 2, the base region 14-e is shown at one end in the extension direction of each mesa portion, but the base region 14-e is also provided at the other end of each mesa portion. In each mesa portion, at least one of the emitter region 12 of the first conductivity type and the contact region 15 of the second conductivity type may be provided in a region sandwiched between the base regions 14-e in a top view. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0072] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may be provided with a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0073] Each of the contact region 15 and the emitter region 12 in the mesa portion 60 is provided from one trench portion to the other trench portion in the X-axis direction. As an example, the contact region 15 and the emitter region 12 in the mesa portion 60 are alternately arranged along the extension direction of the trench portion (the Y-axis direction).

[0074] In another example, the contact region 15 and the emitter region 12 of the mesa portion 60 may be provided in a stripe shape along the extension direction (Y-axis direction) of the trench portion. For example, the emitter region 12 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 12.

[0075] No emitter region 12 is provided in the mesa portion 61 of the diode portion 80. A base region 14 and a contact region 15 may be provided on the upper surface of the mesa portion 61. In a region sandwiched between the base regions 14-e on the upper surface of the mesa portion 61, a contact region 15 may be provided in contact with each of the base regions 14-e. In a region sandwiched between the contact regions 15 on the upper surface of the mesa portion 61, a base region 14 may be provided. The base region 14 may be disposed in the entire region sandwiched between the contact regions 15.

[0076] A contact hole 54 is provided above each mesa portion. The contact hole 54 is disposed in a region sandwiched between the base regions 14-e. In this example, the contact holes 54 are provided above the contact region 15, the base region 14, and the emitter region 12. The contact holes 54 are not provided in regions corresponding to the base region 14-e and the well region 11. The contact hole 54 may be disposed in the center of the arrangement direction of the mesa portions 60 (X-axis direction).

[0077] In the diode section 80, an N+ type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate 10. A P+ type collector region 22 may be provided in a region of the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided. The cathode region 82 and the collector region 22 are provided between the lower surface 23 of the semiconductor substrate 10 and the buffer region 20. In FIG. 2, the boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line.

[0078] The cathode region 82 is disposed away from the well region 11 in the Y-axis direction. This ensures a distance between the cathode region 82 and a P-type region (well region 11) that has a relatively high doping concentration and is formed to a deep position, thereby improving the breakdown voltage. In this example, the end of the cathode region 82 in the Y-axis direction is disposed farther from the well region 11 than the end of the contact hole 54 in the Y-axis direction. In another example, the end of the cathode region 82 in the Y-axis direction may be disposed between the well region 11 and the contact hole 54.

[0079] Fig. 3 is a diagram showing an example of an ee cross section in Fig. 2. The ee cross section is an XZ plane passing through the emitter region 12 and the cathode region 82. In this cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.

[0080] The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with the contact hole 54 described in FIG. 2.

[0081] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 passes through a contact hole 54 in the interlayer insulating film 38 and is in contact with the upper surface 21 of the semiconductor substrate 10. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metal material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (the Z-axis direction) is referred to as the depth direction.

[0082] The semiconductor substrate 10 has an N-type or N-type drift region 18. The drift region 18 is provided in each of the transistor section 70 and the diode section 80.

[0083] In the mesa portion 60 of the transistor section 70, an N+ type emitter region 12 and a P- type base region 14 are provided in this order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+ type accumulation region 16 may be provided in the mesa portion 60. The accumulation region 16 is disposed between the base region 14 and the drift region 18.

[0084] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10, and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The emitter region 12 has a higher doping concentration than the drift region 18.

[0085] The base region 14 is provided below the emitter region 12. In this example, the base region 14 is provided in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the mesa portion 60.

[0086] The accumulation region 16 is provided below the base region 14. The accumulation region 16 is an N+ type region having a higher doping concentration than the drift region 18. In other words, the accumulation region 16 has a higher donor concentration than the drift region 18. By providing the high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60.

[0087] A P-type base region 14 is provided in the mesa portion 61 of the diode portion 80 in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. In the mesa portion 61, an accumulation region 16 may be provided below the base region 14.

[0088] In each of the transistor section 70 and the diode section 80, an N+ type buffer region 20 may be provided below the drift region 18. The doping concentration of the buffer region 20 is higher than that of the drift region 18. The buffer region 20 may have a concentration peak having a higher doping concentration than the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. The doping concentration of the drift region 18 may be the average value of the doping concentration in a region where the doping concentration distribution is approximately flat.

[0089] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peak of the buffer region 20 may be provided at the same depth position as the chemical concentration peak of hydrogen (protons) or phosphorus, for example. The buffer region 20 may function as a field stop layer that prevents the depletion layer spreading from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0090] In the transistor portion 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14, or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron.

[0091] In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor concentration of the cathode region 82 is higher than the donor concentration of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. The elements serving as the donor and acceptor of each region are not limited to the above-mentioned examples. The collector region 22 and the cathode region 82 are exposed to the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0092] At least one gate trench portion 40 and at least one dummy trench portion 30 are provided on the upper surface 21 side of the semiconductor substrate 10. Each trench portion is provided from the upper surface 21 of the semiconductor substrate 10, penetrating the base region 14, to below the base region 14. In a region where at least one of the emitter region 12, the contact region 15, and the accumulation region 16 is provided, each trench portion also penetrates these doped regions. The trench portion penetrating the doped region is not limited to a case where the trench portion is formed in the order of forming the doped region and then the trench portion. A case where the trench portion is formed and then the doped region is formed between the trench portions is also included in the case where the trench portion penetrates the doped region.

[0093] As described above, the transistor portion 70 is provided with the gate trench portion 40 and the dummy trench portion 30. The diode portion 80 is provided with the dummy trench portion 30, but is not provided with the gate trench portion 40. In this example, the boundary between the diode portion 80 and the transistor portion 70 in the X-axis direction is the boundary between the cathode region 82 and the collector region 22.

[0094] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate insulating film 42 within the gate trench. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0095] The gate conductive portion 44 may be provided longer in the depth direction than the base region 14. The gate trench portion 40 in this cross section is covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40.

[0096] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided on the inner side of the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0097] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench portion 30 and the gate trench portion 40 may be curved (curved in cross section) convex downward. In this specification, the depth position of the lower end of the gate trench portion 40 is designated as Zt.

[0098] The semiconductor device 100 of this example includes a P-type lower end region 202 provided in contact with the lower end of the trench portion. The doping concentration of the lower end region 202 may be equal to or lower than the doping concentration of the base region 14. The doping concentration of the lower end region 202 of this example is lower than the doping concentration of the base region 14.

[0099] The lower end region 202 is disposed away from the base region 14. Between the lower end region 202 and the base region 14, an N-type region (at least one of the accumulation region 16 and the drift region 18 in this example) is provided.

[0100] The lower end region 202 is provided continuously so as to contact the lower ends of two or more trench portions in the X-axis direction. In other words, the lower end region 202 is provided so as to cover the mesa portion between the trench portions. The lower end region 202 may cover multiple mesa portions.

[0101] The lower end region 202 may be in contact with the lower ends of two or more trench portions in each transistor portion 70. Also, the lower end region 202 may be in contact with the lower ends of two or more gate trench portions 40 in each transistor portion 70. The lower end region 202 may be in contact with the lower ends of all trench portions in at least one transistor portion 70. Also, the lower end region 202 may be in contact with the lower ends of all gate trench portions 40 in at least one transistor portion 70.

[0102] The bottom end region 202 may be in contact with the bottom ends of two or more trench portions in each diode portion 80. The bottom end region 202 may be in contact with the bottom ends of all of the trench portions in at least one diode portion 80.

[0103] The lower end region 202 is provided to extend in the Y-axis direction. The length of the lower end region 202 in the Y-axis direction is shorter than the length of the trench portion in the Y-axis direction. Furthermore, the length of the lower end region 202 in the Y-axis direction may be 50% or more, 70% or more, or 90% or more of the length of the trench portion in the Y-axis direction.

[0104] Providing the bottom end region 202 can suppress a rise in potential near the bottom end of the trench portion when the semiconductor device 100 is turned on. This can reduce the gradient (dv / dt) of the emitter-collector voltage waveform when turned on, thereby reducing noise in the voltage or current waveform during switching.

[0105] The potential of the lower end region 202 is different from the potential of the emitter electrode 52. As described above, the lower end region 202 is disposed apart in the Z-axis direction from the base region 14 connected to the emitter electrode 52. The lower end region 202 is also disposed apart from the well region connected to the emitter electrode 52 in a top view. The active unit 160 may have a portion in which the lower end region 202 is not provided in at least one of the X-axis direction and the Y-axis direction.

[0106] 4 is a diagram showing an example of the arrangement of well regions 11 and lower end regions 202 in a top view. The lower end region 202 in this example is provided in the active section 160. The lower end region 202 may be provided in 50% or more of the area of ​​the active section 160 in a top view, or may be provided in 70% or more of the area, or may be provided in 90% or more of the area.

[0107] A well region 11 is provided below the gate wiring shown in Fig. 1. In top view, the well region 11 and the lower end region 202 are disposed at different positions. As shown in Fig. 4, the well region 11 may be disposed so as to surround the lower end region 202 in top view. As shown in Fig. 4, when the lower end region 202 is divided into a plurality of regions, the well region 11 may surround each of the lower end regions 202.

[0108] In a top view, the well region 11 and the lower end region 202 are arranged apart from each other. The semiconductor device 100 includes a high resistance region 204 arranged between the well region 11 and the lower end region 202 in a top view. The high resistance region 204 may be arranged at a position in contact with the well region 11 in the active portion 160. In FIG. 4, the high resistance region 204 is hatched with oblique lines. The high resistance region 204 may surround the lower end region 202 in a top view. The high resistance region 204 may surround the active portion 160 in a top view.

[0109] The high resistance region 204 is a P-type region with a lower doping concentration than the lower end region 202. In other words, the high resistance region 204 is a region with a higher electrical resistance than the lower end region 202. The high resistance region 204 may connect the lower end region 202 and the well region 11. By providing the lower end region 202, noise during switching can be reduced. By providing the high resistance region 204, the difference in withstand voltage between the region where the lower end region 202 is provided and the region where the lower end region 202 is not provided can be reduced, and the withstand capacity of the semiconductor device 100 can be improved. In addition, by providing the high resistance region 204 between the well region 11 and the lower end region 202, the lower end region 202 can be prevented from becoming the same potential as the well region 11. This prevents the lower end region 202 from becoming the emitter potential, and allows the transistor section 70 and the diode section 80 to operate.

[0110] In this example, the high resistance region 204 is provided in the entire region of the active section 160 where the lower end region 202 is not provided. If there is a portion inside the active section 160 where the lower end region 202 is not provided, the high resistance region 204 may also be provided in that portion. The high resistance region 204 arranged inside the active section 160 may be surrounded by the lower end region 202 in a top view.

[0111] 5A is a diagram showing an example of the ff cross section in FIG. 4. The ff cross section is an XZ plane passing through the lower end region 202, the high resistance region 204, and the well region 11. In other words, the ff cross section is an XZ plane in the vicinity of the boundary between the active portion 160 and the well region 11. Note that FIG. 5A shows the structure of the semiconductor substrate 10, and omits configurations such as electrodes and insulating films disposed above and below the semiconductor substrate 10. Also, in FIG. 5A, the gate trench portion 40 is given the symbol G, and the dummy trench portion 30 is given the symbol E.

[0112] The ff cross section shown in FIG. 5A includes the transistor portion 70 arranged at the end in the X-axis direction among the multiple transistor portions 70. The structure of the transistor portion 70 is the same as that of the transistor portion 70 described in FIG. 2 and FIG. 3. In FIG. 5A, one dummy trench portion 30 is arranged between two gate trench portions 40 as in G / E / G / E / ··, but two dummy trench portions 30 may be arranged between two gate trench portions 40 as in G / E / E / G / E / E / ··. The arrangement of the gate trench portions 40 and the dummy trench portions 30 may have other structures. The region between the transistor portion 70 and the well region 11 shown in FIG. 5A is defined as the boundary portion 210. Of the gate trench portions 40(G) to which the emitter region 12 is provided adjacent, the center of the gate trench portion 40(G) arranged at the end in the X-axis direction is defined as the end of the transistor portion 70 in the X-axis direction. The range of the boundary portion 210 in the X-axis direction is from the gate trench portion 40 (G) to the well region 11.

[0113] The well region 11 is provided from the upper surface 21 of the semiconductor substrate 10 to below the base region 14. The well region 11 is a P+ type region having a higher doping concentration than the base region 14.

[0114] One or more trench portions are provided in the boundary portion 210. In this example, one or more gate trench portions 40 and one or more dummy trench portions 30 are provided in the boundary portion 210. The arrangement of the trench portions in the boundary portion 210 in the X-axis direction may be the same as or different from that of the transistor portion 70.

[0115] A base region 14 is provided in the mesa portion of the boundary portion 210. A contact region 15 may be provided between the base region 14 and the upper surface 21 of the semiconductor substrate 10. Furthermore, among the mesa portions of the boundary portion 210, one or more mesa portions closest to the transistor portion 70 may be provided with an accumulation region 16.

[0116] The lower end region 202 in this example is a P-type region having a lower doping concentration than the well region 11. The lower end region 202 is disposed in at least a portion of the transistor section 70. The lower end region 202 in this example extends toward the well region 11 side beyond the end of the transistor section 70. In another example, the lower end region 202 may terminate at the end of the transistor section 70, or may terminate inside the transistor section 70.

[0117] The high resistance region 204 is a P-type region having a lower doping concentration than the lower end region 202. The high resistance region 204 is provided in at least a part of the boundary portion 210 in the X-axis direction. The high resistance region 204 may be provided in the entire boundary portion 210 in the X-axis direction. The high resistance region 204 may be in contact with the lower end region 202 or may be in contact with the well region 11. The high resistance region 204 in this example is in contact with both the lower end region 202 and the well region 11.

[0118] The high resistance region 204 and the emitter region 12 may be disposed apart from each other in a top view. In other words, the high resistance region 204 does not have to be provided in the transistor portion 70. The distance between the high resistance region 204 and the emitter region 12 in a top view may be equal to or greater than the width of the mesa portion in the X-axis direction.

[0119] The high resistance region 204 may be disposed so as to partially overlap with the accumulation region 16 in a top view. The accumulation region 16 may also be provided in the boundary portion 210.

[0120] The high resistance region 204 may have a portion provided at the same depth position as the lower end region 202. In other words, the range in the Z-axis direction in which the high resistance region 204 is provided and the range in the Z-axis direction in which the lower end region 202 is provided may at least partially overlap. The high resistance region 204 may contact the lower end of the trench portion disposed at the boundary portion 210. At least one of the drift region 18 and the accumulation region 16 may be disposed between the high resistance region 204 and the base region 14.

[0121] The width of the high resistance region 204 in the Z-axis direction is Wz. The width Wz may be the maximum value of the width of the high resistance region 204 in the Z-axis direction. The second length of the high resistance region 204 connecting the well region 11 and the lower end region 202 in the X-axis direction is Lx. The length Lx may be the maximum value of the length of the high resistance region 204 in the X-axis direction. The length Lx is preferably greater than the width Wz. The length Lx may be twice or more, five times or more, ten times or more, or even 100 times or more of the width Wz. The high resistance region 204 may be in contact with the lower ends of two or more trench portions in the X-axis direction. The high resistance region 204 may be in contact with the lower ends of all the trench portions provided in the boundary portion 210. The high resistance region 204 may cover two or more mesa portions in the X-axis direction. By increasing the length Lx of the high resistance region 204, the electrical resistance between the well region 11 and the lower end region 202 can be increased, and the potential difference between the well region 11 and the lower end region 202 can be increased.

[0122] The high resistance region 204 may be in contact with the bottom end of at least one gate trench portion 40. The high resistance region 204 may be in contact with the bottom ends of two or more gate trench portions 40. The high resistance region 204 may be in contact with the bottom ends of all of the gate trench portions 40 provided in the boundary portion 210.

[0123] FIG. 5B is a diagram showing an example of the net doping concentration distribution of the aa cross section and the bb cross section in FIG. 5A. The horizontal axis in FIG. 5B indicates the position in the Z-axis direction with the upper surface 21 of the semiconductor substrate 10 as the reference position (0 μm). In FIG. 5B, the net doping concentration distribution of the aa cross section in the transistor section 70 is shown by a dotted line, and the net doping concentration distribution of the bb cross section at the boundary section 210 is shown by a solid line. The emitter region 12 and the base region 14 are provided near the upper surface 21 of the aa cross section of the transistor section 70. The contact region 15 and the base region 14 are provided near the upper surface 21 of the bb cross section at the boundary section 210. The net doping concentration distribution of the high resistance region 204 (solid line) is lower than the net doping concentration distribution of the lower end region 202 (dotted line). The net doping concentration distributions of the high resistance region 204 and the lower end region 202 may each have a peak or a maximum value. The full width at half maximum (FWHM1) of the high resistance region 204 may be smaller than the full width at half maximum (FWHM2) of the bottom region 202.

[0124] Fig. 6 is a diagram showing an example of a doping concentration distribution in the cc cross section (X-axis direction) of Fig. 5A. Fig. 6 shows concentration distributions in the high-resistance region 204 and the lower end region 202 and well region 11 near the high-resistance region 204. The cc cross section may be a cross section at a peak position Zp in the net doping concentration distribution of the lower end region 202 or the high-resistance region 204 shown in Fig. 5B.

[0125] The doping concentration of the lower end region 202 is D 202 The doping concentration D of the lower end region 202 is 202 The maximum value of the doping concentration in the X-axis direction in the lower end region 202 may be used. The doping concentration of the well region 11 is D 11 The doping concentration D of the well region 11 is 11 The doping concentration of the high resistance region 204 may be expressed as D 204 The doping concentration D of the high resistance region 204 is 204The average value of the doping concentration in the high resistance region 204 in the X-axis direction may be used, or the minimum value may be used.

[0126] Doping concentration D 204 is the doping concentration D 202 Doping concentration D 204 is the doping concentration D of the bottom region 202 202 The doping concentration D of the high resistance region 204 may be 10% or less, 5% or less, or 1% or less. 204 is 1 x 10 14 / cm 3 That's it, 1×10 17 / cm 3 The doping concentration D of the high resistance region 204 may be 204 is 1 x 10 15 / cm 3 The doping concentration D of the high resistance region 204 may be more than 204 is 1 x 10 16 / cm 3 It may be the following.

[0127] The doping concentration at both ends of the high resistance region 204 in the X-axis direction is D b The doping concentration D b is the concentration between the maximum value of the doping concentration in the lower end region 202 and the minimum value of the doping concentration in the high resistance region 204. b may be the concentration midway between the maximum value of the doping concentration in the lower end region 202 and the minimum value of the doping concentration in the high resistance region 204.

[0128] In the direction from the bottom region 202 to the high resistance region 204, the doping concentration first increases to D b The position where the doping concentration first increases to D b The position where the doping concentration is 100% is determined as the boundary between the well region 11 and the high resistance region 204. The high resistance region 204 has an overall doping concentration of D bor less. The high resistance region 204 may have a flat portion 206 in which the doping concentration distribution in the X-axis direction is flat. A flat doping concentration distribution means that the doping concentration varies by ±10% or less. The length of the flat portion 206 in the X-axis direction may be 1 μm or more, 5 μm or more, or 10 μm or more. The length of the flat portion 206 may be 50% or more, or 70% or more of the length Lx of the high resistance region 204.

[0129] In another example, the high resistance region 204 has a doping concentration of D b The high resistance region 204 may include a portion having a doping concentration greater than that of the bottom region 202. In this case, the doping concentration distribution in the X-axis direction in the high resistance region 204 may have a peak. However, the average doping concentration of the high resistance region 204 is lower than the average doping concentration of the bottom region 202.

[0130] 7 is a diagram showing an example of the gg cross section in FIG. 4. The gg cross section is a YZ plane passing through the lower end region 202, the high resistance region 204, and the well region 11. The gg cross section passes through the mesa portion of the transistor portion 70. However, in FIG. 7, the position of the gate trench portion 40 projected onto the gg cross section is shown by a dashed line. Note that FIG. 7 shows the structure of the semiconductor substrate 10, and the configuration of electrodes, insulating films, etc. arranged above and below the semiconductor substrate 10 is omitted.

[0131] In this cross section, the region between the transistor portion 70 and the well region 11 is defined as a boundary portion 210. The end of the emitter region 12 that is disposed at the end furthest in the Y-axis direction is defined as the end portion of the transistor portion 70 in the Y-axis direction. The range of the boundary portion 210 in the Y-axis direction is defined as from the emitter region 12 to the well region 11.

[0132] The emitter regions 12 and the contact regions 15 are alternately arranged along the Y-axis direction on the upper surface 21 of the transistor section 70. The contact regions 15 are provided on the upper surface 21 of the boundary portion 210.

[0133] In this example, the accumulation region 16 is provided extending toward the well region 11 side beyond the end of the transistor portion 70. In another example, the accumulation region 16 may terminate at the end of the transistor portion 70, or may terminate inside the transistor portion 70.

[0134] In this example, the lower end region 202 extends further toward the well region 11 than the end of the transistor portion 70. In another example, the lower end region 202 may terminate at the end of the transistor portion 70, or may terminate inside the transistor portion 70. The accumulation region 16 may extend further toward the well region 11 than the lower end region 202.

[0135] The high resistance region 204 is provided in at least a part of the boundary portion 210 in the Y-axis direction. The high resistance region 204 may be provided in the entire boundary portion 210 in the Y-axis direction. The high resistance region 204 may be in contact with the lower end region 202 or may be in contact with the well region 11. The high resistance region 204 in this example is in contact with both the lower end region 202 and the well region 11. The high resistance region 204 may overlap with the accumulation region 16 in a top view. That is, the end of the accumulation region 16 may be inside the high resistance region 204 or inside the boundary portion 210 in a top view. In another example, the high resistance region 204 may not overlap with the accumulation region 16 in a top view. That is, the end of the accumulation region 16 may be inside (in the -Y-axis direction) the high resistance region 204 or the boundary portion 210 in a top view. The high resistance region 204 may be provided so as not to overlap with the transistor portion 70 in the cross section. In another example, the high resistance region 204 may overlap the transistor portion 70 in the cross section.

[0136] The first length of the high resistance region 204 connecting the well region 11 and the lower end region 202 in the Y-axis direction is defined as Ly. The length Ly may be the maximum length of the high resistance region 204 in the Y-axis direction. The Y-axis direction is the direction in which the trench portion has a long side, and the X-axis direction is the direction in which the trench portion has a short side. The ratio (Ly / Lx) of the length Ly to the length Lx may be 0.9 or more and 1.1 or less. In other words, the length Ly and the length Lx may be approximately equal. This can reduce the variation in the breakdown voltage in the XY plane.

[0137] Furthermore, the length Ly may be greater than the width Wz. The length Ly may be at least twice as long as the width Wz, at least five times as long as the width Wz, at least ten times as long as the width Wz, or at least one hundred times as long as the width Wz.

[0138] Fig. 8 shows the results of measuring the relationship between the doping concentration of the high-resistance region 204 and the breakdown voltage of the portion in which the high-resistance region 204 is formed. In Fig. 8, breakdown voltage VB1 indicates the breakdown voltage of the portion in which the bottom end region 202 is formed, and breakdown voltage VB2 indicates the breakdown voltage when neither the bottom end region 202 nor the high-resistance region 204 is formed.

[0139] The doping concentration of the high resistance region 204 may be set so that the breakdown voltage of the portion where the high resistance region 204 is provided is higher than the breakdown voltage VB2 and lower than the breakdown voltage VB1. In this example, the lower limit of the setting range of the doping concentration of the high resistance region 204 is 1×10 14 / cm 3 That's it, 1×10 15 / cm 3 The upper limit of the setting range is 1×10 15 / cm 3 That's it, 1×10 16 / cm 3 FIG. 8 shows two setting ranges, setting range A and setting range B, as examples of setting ranges. As an example, setting range A is 1×10 14 / cm 3 That's it, 1×10 16 / cm 3 As another example, the setting range B is 7×10 14 / cm 3 That's it, 6 x 1015 / cm 3 or less. The ratio α of the peak concentration of the doping concentration of the high resistance region 204 to the peak concentration of the doping concentration of the bottom region 202 may be 0.05 or more, 0.08 or more, 0.1 or more, or 0.3 or more. The ratio α may be 0.9 or less, 0.8 or less, 0.6 or less, or 0.5 or less.

[0140] 9 is a diagram showing another arrangement example of the high resistance region 204 in a top view. The high resistance region 204 in this example is partially provided in the region between the lower end region 202 and the well region 11. That is, in the region (boundary portion 210) between the lower end region 202 and the well region 11, there are a portion where the high resistance region 204 is provided and a portion where the high resistance region 204 is not provided. In the region where the high resistance region 204 is not provided, the drift region 18 may be provided instead of the high resistance region 204.

[0141] In this example, the high resistance region 204 is disposed at a corner of the active section 160 surrounded by the well region 11. In this example, the active section 160 surrounded by the well region 11 has a side parallel to the Y axis and a side parallel to the X axis. The high resistance region 204 may be provided at a position where the two sides intersect. As shown in FIG. 9, the high resistance region 204 may be disposed at a plurality of corners. Since an electric field is likely to concentrate at these corners, it is preferable to provide the high resistance region 204 to improve the breakdown voltage.

[0142] FIG. 10 is a diagram showing another arrangement example of the high resistance region 204 in a top view. The high resistance region 204 of this example has a first high resistance portion 205-1 and a second high resistance portion 205-2. The second high resistance portion 205-2 (straight portion) is a region having a lower doping concentration than the first high resistance portion 205-1 (corner portion). The first high resistance portion 205-1 is preferably arranged in a portion requiring a higher withstand voltage. The first high resistance portion 205-1 may be arranged in a corner portion similarly to the high resistance region 204 described in FIG. 9. The second high resistance portion 205-2 is arranged in a region between the lower end region 202 and the well region 11 where the first high resistance portion 205-1 is not provided. This makes it possible to suppress variations in withstand voltage in the XY plane. Note that the doping concentration is lower in both the first high resistance portion 205-1 and the second high resistance portion 205-2 than in the lower end region 202.

[0143] 1 to 10, the high resistance region 204 may have a lower doping concentration than the base region 14. The maximum doping concentration in the high resistance region 204 may be half or less, 10% or less, or 1% or less of the maximum doping concentration in the base region 14. The maximum doping concentration in the bottom region 202 may be less than the maximum doping concentration in the base region 14 and greater than the maximum doping concentration in the high resistance region 204.

[0144] Fig. 11 is a diagram showing some steps of a method for manufacturing the semiconductor device 100. In the method for manufacturing the semiconductor device 100, the components described in Fig. 1 to Fig. 10 are formed. The steps shown in Fig. 11 include a first region forming step S1100, a trench forming step S1102, a second region forming step S1104, and a trench structure forming step S1106.

[0145] In the first region formation step S1100, a doped region is formed on the upper surface 21 side of the semiconductor substrate 10. The doped region includes, for example, at least one of the well region 11, the emitter region 12, the base region 14, the contact region 15, and the accumulation region 16. The drift region 18 may be the remaining region where these doped regions are not formed.

[0146] In the trench formation step S1102, trenches are formed in the upper surface 21 of the semiconductor substrate 10. The trenches are grooves for forming each trench portion. Each trench is formed to a depth that reaches from the upper surface 21 to the drift region 18. In the trench formation step S1102, at least the conductive portion in the trench is not formed. An insulating film in the trench may or may not be formed.

[0147] In the second region forming step S1104, the bottom end region 202 and the high resistance region 204 are formed. In the second region forming step S1104, P-type dopant ions may be implanted into the semiconductor substrate 10 through the trench. In the second region forming step S1104, P-type dopant ions may be implanted from the upper surface 21 of the semiconductor substrate 10 with the portions other than the trench masked. This makes it possible to easily implant P-type dopant ions into the region adjacent to the bottom end of the trench. In the first region forming step S1100 and the second region forming step S1104, the semiconductor substrate 10 is heat-treated after the dopant is implanted.

[0148] In the trench structure forming step S1106, a conductive portion and an insulating film are formed inside each trench. In the trench structure forming step S1106, the insulating film may be formed by thermally oxidizing the inner wall of the trench. In the trench structure forming step S1106, the conductive portion may be formed by filling the trench with a conductive material such as polysilicon in the inside of the trench in which the insulating film has been formed.

[0149] 12 is a diagram illustrating an example of the second region forming step S1104. The second region forming step S1104 of this example has a first implantation step S1201 and a second implantation step S1202. Either the first implantation step S1201 or the second implantation step S1202 may be performed first.

[0150] In the first implantation step S1201, a predetermined concentration ( / cm 2 In the second implantation step S1202, P-type dopant ions are implanted in the region where the high resistance region 204 is to be formed at a concentration ( / cm 3 ) different from that in the first implantation step S1201. 2 ) of P-type dopant ions are implanted. The concentration (dose) in the second implantation stage S1202 is lower than that in the first implantation stage S1201. Note that in both the first implantation stage S1201 and the second implantation stage S1202, the dopant may be implanted into the semiconductor substrate 10 through the trench 45. In this case, the mask 300 may be used to mask the regions other than the trench 45. The dopant implanted through the trench 45 is diffused by heat treatment. This allows the formation of the bottom end region 202 and the high resistance region 204 that are continuous in the XY plane.

[0151] 13 is a diagram illustrating another example of the second region forming step S1104. The second region forming step S1104 of this example has a first implantation step S1301 and a second implantation step S1302. Either the first implantation step S1301 or the second implantation step S1302 may be performed first.

[0152] In the first implantation step S1301, a predetermined concentration ( / cm 2 In the second implantation step S1302, a predetermined concentration ( / cm 3 ) of P-type dopant ions is implanted into the region in which the bottom region 202 is to be formed. 2) P-type dopant ions are further implanted. In the second implantation step S1302, dopant ions are not implanted into the region in which the high resistance region 204 is to be formed. Note that in both the first implantation step S1301 and the second implantation step S1302, dopants may be implanted into the semiconductor substrate 10 through the trenches 45. The dopants implanted through the trenches 45 are diffused by heat treatment. This allows the bottom end region 202 and the high resistance region 204, which are continuous in the XY plane, to be formed.

[0153] 14 is a diagram illustrating another example of the second region forming step S1104. The second region forming step S1104 of this example has a first implantation step S1401 and a second implantation step S1402. Either the first implantation step S1401 or the second implantation step S1402 may be performed first, or they may be performed simultaneously.

[0154] In the first implantation step S1401, a predetermined concentration ( / cm 2 In the second implantation step S1402, a predetermined concentration ( / cm 3 ) of P-type dopant ions is implanted into the region where the high resistance region 204 is to be formed. 2 ) P-type dopant ions are implanted. However, in the second implantation step S1402, the dopant of the second conductivity type is implanted into a region 203, which is away from a region where the bottom region 202 is to be formed, among the regions where the high resistance region 204 is to be formed. The region 203 may also be away from the well region 11. The distance in the X-axis direction between the region 203 and the bottom region 202 may be greater than the width in the X-axis direction of one mesa portion of the boundary portion 210. The distance in the X-axis direction between the region 203 and the well region 11 may also be greater than the width in the X-axis direction of one mesa portion of the boundary portion 210.

[0155] After the second implantation step S1402, the semiconductor substrate 10 is heat-treated to diffuse the implanted dopant toward the region where the bottom region 202 is to be formed. This heat treatment also diffuses the dopant toward the well region 11. This forms the high-resistance region 204 described in Figures 1 to 10. The heat treatment is preferably performed at a temperature and for a time that allows the dopant implanted in the region 203 to reach the bottom region 202 and the well region 11.

[0156] Injection concentration ( / cm 2 ) is the injection concentration ( / cm 2 ) may be lower, the same as, or higher than the implantation concentration in the first implantation step S1401. Even if the implantation concentration in the second implantation step S1402 is equal to or higher than the implantation concentration in the first implantation step S1401, the dopant implanted in the second implantation step S1402 diffuses toward the bottom region 202 and the well region 11. This allows the average doping concentration in the high resistance region 204 to be lowered.

[0157] Fig. 15 is a diagram showing another example of the doping concentration distribution in the X-axis direction. Fig. 15 shows the concentration distribution in the high resistance region 204, and the lower end region 202 and well region 11 near the high resistance region 204. The doping concentrations in the lower end region 202 and well region 11 are similar to those in the example of Fig. 6.

[0158] The high resistance region 204 of this example is formed by the method described in Fig. 14. The high resistance region 204 of this example has a peak 207 of doping concentration in a direction (e.g., the X-axis direction) connecting the bottom end region 202 and the well region 11. The apex of the peak 207 may be a flat portion 206.

[0159] The high resistance region 204 may have one or more valleys 208 in the doping concentration distribution in the X-axis direction. The valleys 208 may be located between the peaks 207 and the lower end region 202. The valleys 208 may be located between the peaks 207 and the well region 11. The doping concentration of the valleys 208 is defined as the doping concentration D of the high resistance region 204. 204Doping concentration D 204 is the doping concentration D of the bottom region 202 202 The doping concentration D may be 10% or less, 5% or less, or 1% or less. 204 may be higher than the doping concentration of the drift region 18.

[0160] The doping concentration of peak 207 is D p The doping concentration of peak 207 is D p is the doping concentration D of the bottom region 202 202 The doping concentration D may be 0.5 times or more and 1.5 times or less. p is the doping concentration D 202 The doping concentration D may be 0.7 times or more, or may be 0.9 times or more. p is the doping concentration D 202 The doping concentration D may be 1.3 times or less, or may be 1.1 times or less. p is the doping concentration D 202 may be the same as

[0161] Fig. 16 is a diagram showing another example of the doping concentration distribution in the X-axis direction. Fig. 16 shows the concentration distribution in the high resistance region 204, and the lower end region 202 and well region 11 near the high resistance region 204. The doping concentrations in the lower end region 202 and well region 11 are similar to those in the example of Fig. 6.

[0162] The high resistance region 204 in this example has multiple peaks 207 of doping concentration. p For example, the closer to the well region 11, the greater the doping concentration D p By locally injecting dopants into a plurality of locations in the region where the high resistance region 204 is to be formed, a plurality of peaks 207 can be formed.

[0163] FIG. 17 is a diagram showing another example of the doping concentration distribution in the X-axis direction. FIG. 17 shows the concentration distribution in the high resistance region 204 and the lower end region 202 and well region 11 near the high resistance region 204. The doping concentrations in the lower end region 202 and well region 11 are similar to those in the example of FIG. 6. The high resistance region 204 of this example has a valley 208 of the doping concentration. The valley 208 of this example is disposed on the lower end region 202 side from the center of the high resistance region 204 in the X-axis direction. In the doping concentration distribution, the inclination of the slope from the valley 208 toward the well region 11 may be gentler than the inclination of the slope from the valley 208 toward the lower end region 202.

[0164] FIG. 18 is a diagram showing another example of the doping concentration distribution in the X-axis direction. FIG. 18 shows the concentration distribution in the high resistance region 204 and the lower end region 202 and well region 11 near the high resistance region 204. The doping concentrations in the lower end region 202 and well region 11 are similar to those in the example of FIG. 6. The high resistance region 204 of this example has a valley 208 of the doping concentration. The valley 208 of this example is disposed closer to the well region 11 than the center of the high resistance region 204 in the X-axis direction. In the doping concentration distribution, the inclination of the slope from the valley 208 toward the well region 11 may be steeper than the inclination of the slope from the valley 208 toward the lower end region 202.

[0165] As described in Fig. 6 and Fig. 15 to Fig. 18, the potential distribution in the high resistance region 204 can be controlled by controlling the doping concentration distribution in the high resistance region 204. Note that, although the doping concentration distribution of the high resistance region 204 connecting the well region 11 and the lower end region 202 in the X-axis direction has been described in Fig. 6 and Fig. 15 to Fig. 18, the doping concentration distribution of the high resistance region 204 connecting the well region 11 and the lower end region 202 in the Y-axis direction may be the same.

[0166] 19 is a diagram showing another configuration example of the bottom region 202 and the high resistance region 204. The bottom region 202 has a bottom portion 302 that contacts the bottom end of the trench portion, and a low concentration portion 304 that has a lower doping concentration than the bottom portion 302. The high resistance region 204 also has a bottom portion 312 that contacts the bottom end of the trench portion, and a low concentration portion 314 that has a lower doping concentration than the bottom portion 312. The low concentration portion 304 and the low concentration portion 314 overlap with the center of the mesa portion in the X-axis direction.

[0167] 12 to 14, the bottom region 202 and the high resistance region 204 of this example are formed by injecting dopants into the semiconductor substrate 10 through the trench 45 and thermally diffusing the dopants. Therefore, the doping concentrations of the bottom end portion 302 and the bottom end portion 312 that contact the trench portion are relatively high. On the other hand, the doping concentrations of the low concentration portion 304 and the low concentration portion 314 that are away from the trench portion are relatively low.

[0168] Furthermore, the width in the Z-axis direction of the low-concentration portion 304 is smaller than the width in the Z-axis direction of the bottom end portion 302. Similarly, the width in the Z-axis direction of the low-concentration portion 314 is smaller than the width in the Z-axis direction of the bottom end portion 312.

[0169] A voltage (e.g., −15V) lower than the voltage (e.g., 0V) of the emitter electrode 52 is applied to the gate trench portion 40. For this reason, holes are easily attracted to the vicinity of the lower end of the gate trench portion 40. By increasing the doping concentration of the lower end portion 312, holes attracted to the lower end of the gate trench portion 40 are easily drawn to the upper surface 21 side of the semiconductor substrate 10. This makes it possible to shorten the switching time of the semiconductor device 100. In addition, the lower end regions 202 extending in the horizontal direction (X-axis direction) from adjacent trench portions in the transistor portion 70 are connected at the center of the mesa portion 60, thereby preventing a decrease in the breakdown voltage. The same is true for the boundary portion 210 and the boundary between the boundary portion 210 and the transistor portion 70.

[0170] Fig. 20 is a diagram showing an example of the doping concentration distribution of the high-resistance region 204. Fig. 20 shows the doping concentration distribution in the X-axis direction of the high-resistance region 204 that connects the well region 11 and the lower end region 202 in the X-axis direction, and the doping concentration distribution in the Y-axis direction of the high-resistance region 204 that connects the well region 11 and the lower end region 202 in the Y-axis direction.

[0171] In this example, the high resistance region 204 has bottom end portions 312 and low concentration portions 314 alternating in the X-axis direction. Therefore, the doping concentration distribution in the X-axis direction has high concentration portions and low concentration portions alternating.

[0172] In contrast, since the trench portion extends in the Y-axis direction, the doping concentration distribution of the high resistance region 204 in the Y-axis direction is almost flat. In other words, the doping concentration distribution of the high resistance region 204 in the Y-axis direction is flatter than the doping concentration distribution of the high resistance region 204 in the X-axis direction. The degree of flatness in the doping concentration distribution is expressed by the maximum doping concentration D per unit length L in the X-axis or Y-axis direction. max and the minimum value D min The unit length L may be greater than the arrangement period T of the trench portions in the X-axis direction (or the distance T between peaks of the doping concentration distribution in the high-resistance region 204). According to this example, the electric field distribution in the Y-axis direction can be made flatter. Note that although the high-resistance region 204 has been described with reference to FIG. 20, the doping concentration distribution in the bottom region 202 is similar.

[0173] 21 is a diagram showing another example of the arrangement of the high resistance region 204 in the X-axis direction. In this example, a part of the emitter region 12 and a part of the high resistance region 204 are arranged to overlap each other in a top view. That is, the high resistance region 204 in this example is provided extending into the inside of the transistor section 70. The length Lx1 in the X-axis direction of the high resistance region 204 provided in the boundary section 210 may be greater than the length Lx2 in the X-axis direction of the high resistance region 204 provided in the transistor section 70. The length Lx1 and the length Lx2 may be the same, or the length Lx2 may be greater than the length Lx1.

[0174] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0175] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically indicated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0176] 10 semiconductor substrate, 11 well region, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 18 drift region, 20 buffer region, 21 upper surface, 22 collector region, 23 lower surface, 24 collector electrode, 29 straight portion, 30 dummy trench portion, 31 tip portion, 32 dummy insulating film, 34 dummy conductive portion, 38 interlayer insulating film, 39 straight portion, 40 gate trench portion, 41 tip portion, 42 gate insulating film, 44 gate conductive portion, 45 trench, 52 emitter electrode, 54 contact hole, 60, 61... mesa portion, 70... transistor portion, 80... diode portion, 81... extension region, 82... cathode region, 90... edge termination structure portion, 100... semiconductor device, 130... peripheral gate wiring, 131... active side gate wiring, 160... active portion, 162... edge, 164... gate pad, 202... bottom end region, 203... region, 204... high resistance region, 205... high resistance portion, 206... flat portion, 207... peak, 208... valley portion, 210... boundary portion, 300... mask, 302... bottom end portion, 304... low concentration portion, 312... bottom end portion, 314... low concentration portion

Claims

1. A semiconductor substrate having an upper surface and a lower surface, the semiconductor substrate including a drift region of a first conductivity type; a base region of a second conductivity type provided between the drift region and the upper surface of the semiconductor substrate; a plurality of trenches provided from the upper surface of the semiconductor substrate to a position below the base region; a second conductivity type lower end region provided in contact with lower ends of two or more of the plurality of trench portions; a well region of a second conductivity type that is disposed at a position different from the lower end region when viewed from above, that is provided from the upper surface of the semiconductor substrate to a position lower than the base region, and that has a doping concentration higher than that of the base region; a second conductivity type high resistance region that is disposed between the lower end region and the well region when viewed from the top and has a doping concentration lower than that of the lower end region; Equipped with The high resistance region connects the lower end region and the well region. Semiconductor device.

2. A semiconductor substrate having an upper surface and a lower surface, the semiconductor substrate including a drift region of a first conductivity type; a base region of a second conductivity type provided between the drift region and the upper surface of the semiconductor substrate; a plurality of trenches provided from the upper surface of the semiconductor substrate to a position below the base region; a second conductivity type lower end region provided in contact with lower ends of two or more of the plurality of trench portions; a well region of a second conductivity type that is disposed at a position different from the lower end region when viewed from above, that is provided from the upper surface of the semiconductor substrate to a position lower than the base region, and that has a doping concentration higher than that of the base region; a second conductivity type high resistance region that is disposed between the lower end region and the well region in the top view and has a doping concentration lower than that of the lower end region; an active portion surrounded by the well region when viewed from above; Equipped with the high resistance region is disposed at a position in contact with the well region in the active portion, The high resistance region is a first high resistance portion disposed at a corner of the active portion when viewed from above; a second high resistance portion having a doping concentration lower than that of the first high resistance portion; A semiconductor device having the above structure.

3. A semiconductor substrate having an upper surface and a lower surface, the semiconductor substrate including a drift region of a first conductivity type; a base region of a second conductivity type provided between the drift region and the upper surface of the semiconductor substrate; a plurality of trenches provided from the upper surface of the semiconductor substrate to a position below the base region; a second conductivity type lower end region provided in contact with lower ends of two or more of the plurality of trench portions; a well region of a second conductivity type that is disposed at a position different from the lower end region when viewed from above, that is provided from the upper surface of the semiconductor substrate to a position lower than the base region, and that has a doping concentration higher than that of the base region; a second conductivity type high resistance region that is disposed between the lower end region and the well region in the top view and has a doping concentration lower than that of the lower end region; an emitter region of a first conductivity type provided between the base region and the upper surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; Equipped with A part of the emitter region and a part of the high resistance region overlap each other in a top view. Semiconductor device.

4. A semiconductor substrate having an upper surface and a lower surface, the semiconductor substrate including a drift region of a first conductivity type; a base region of a second conductivity type provided between the drift region and the upper surface of the semiconductor substrate; a plurality of trenches provided from the upper surface of the semiconductor substrate to a position below the base region; a second conductivity type lower end region provided in contact with lower ends of two or more of the plurality of trench portions; a well region of a second conductivity type that is disposed at a position different from the lower end region when viewed from above, that is provided from the upper surface of the semiconductor substrate to a position lower than the base region, and that has a doping concentration higher than that of the base region; a second conductivity type high resistance region that is disposed between the lower end region and the well region when viewed from the top and has a doping concentration lower than that of the lower end region; Equipped with the plurality of trench portions include one or more gate trench portions; The high resistance region is in contact with a lower end of at least one of the gate trench portions. Semiconductor device.

5. The high resistance region is a lower end portion in contact with a lower end of the gate trench portion; a low concentration portion having a doping concentration lower than that of the lower end portion; The semiconductor device according to claim 4 , comprising:

6. A semiconductor substrate having an upper surface and a lower surface, the semiconductor substrate including a drift region of a first conductivity type; a base region of a second conductivity type provided between the drift region and the upper surface of the semiconductor substrate; a plurality of trenches provided from the upper surface of the semiconductor substrate to a position below the base region; a second conductivity type lower end region provided in contact with lower ends of two or more of the plurality of trench portions; a well region of a second conductivity type that is disposed at a position different from the lower end region when viewed from above, that is provided from the upper surface of the semiconductor substrate to a position lower than the base region, and that has a doping concentration higher than that of the base region; a second conductivity type high resistance region that is disposed between the lower end region and the well region in the top view and has a doping concentration lower than that of the lower end region; an accumulation region provided between the base region and the drift region and having a doping concentration higher than that of the drift region; Equipped with A part of the accumulation region and a part of the high resistance region overlap each other in a top view. Semiconductor device.

7. A semiconductor substrate having an upper surface and a lower surface, the semiconductor substrate including a drift region of a first conductivity type; a base region of a second conductivity type provided between the drift region and the upper surface of the semiconductor substrate; a plurality of trenches provided from the upper surface of the semiconductor substrate to a position below the base region; a second conductivity type lower end region provided in contact with lower ends of two or more of the plurality of trench portions; a well region of a second conductivity type that is disposed at a position different from the lower end region when viewed from above, that is provided from the upper surface of the semiconductor substrate to a position lower than the base region, and that has a doping concentration higher than that of the base region; a second conductivity type high resistance region that is disposed between the lower end region and the well region when viewed from the top and has a doping concentration lower than that of the lower end region; Equipped with When viewed from above, the trench portion has a long side in a first direction and a short side in a second direction, A ratio of a first length of the high resistance region connecting the bottom end region and the well region in the first direction to a second length of the high resistance region connecting the bottom end region and the well region in the second direction is not less than 0.9 and not more than 1.

1. Semiconductor device.

8. A semiconductor substrate having an upper surface and a lower surface, the semiconductor substrate including a drift region of a first conductivity type; a base region of a second conductivity type provided between the drift region and the upper surface of the semiconductor substrate; a plurality of trenches provided from the upper surface of the semiconductor substrate to a position below the base region; a second conductivity type lower end region provided in contact with lower ends of two or more of the plurality of trench portions; a well region of a second conductivity type that is disposed at a position different from the lower end region when viewed from above, that is provided from the upper surface of the semiconductor substrate to a position lower than the base region, and that has a doping concentration higher than that of the base region; a second conductivity type high resistance region that is disposed between the lower end region and the well region in the top view and has a doping concentration lower than that of the lower end region; an active portion surrounded by the well region when viewed from above; Equipped with The lower end region is provided in an area of ​​90% or more of the active portion when viewed from above. Semiconductor device.

9. A semiconductor substrate having an upper surface and a lower surface, the semiconductor substrate including a drift region of a first conductivity type; a base region of a second conductivity type provided between the drift region and the upper surface of the semiconductor substrate; a plurality of trenches provided from the upper surface of the semiconductor substrate to a position below the base region; a second conductivity type lower end region provided in contact with lower ends of two or more of the plurality of trench portions; a well region of a second conductivity type that is disposed at a position different from the lower end region when viewed from above, that is provided from the upper surface of the semiconductor substrate to a position lower than the base region, and that has a doping concentration higher than that of the base region; a second conductivity type high resistance region that is disposed between the lower end region and the well region when viewed from the top and has a doping concentration lower than that of the lower end region; Equipped with The high resistance region extends across the plurality of trench portions. Semiconductor device.

10. The length of the high resistance region in the top view is greater than the width of the high resistance region in the depth direction of the semiconductor substrate. The semiconductor device according to claim 3 .

11. The high resistance region contacts the lower ends of two or more of the trench portions. The semiconductor device according to claim 3 .

12. The high resistance region surrounds the active portion in a top view. The semiconductor device according to claim 2 .

13. The high resistance region has a lower doping concentration than the base region.

3. The semiconductor device according to claim 1 or 2.

14. The doping concentration of the high resistance region is 10% or less of the doping concentration of the bottom region.

3. The semiconductor device according to claim 1 or 2.

15. The high resistance region has a peak of doping concentration in a direction connecting the bottom end region and the well region.

3. The semiconductor device according to claim 1 or 2.

16. The peak doping concentration in the high resistance region is 0.5 to 1.5 times the doping concentration in the bottom region. The semiconductor device according to claim 15.

17. an emitter region of a first conductivity type provided between the base region and the upper surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; The emitter region and the high resistance region are disposed apart from each other when viewed from above.

3. The semiconductor device according to claim 1 or 2.

18. When viewed from above, the trench portion has a long side in a first direction and a short side in a second direction, The doping concentration distribution of the high resistance region in the first direction is flatter than the doping concentration distribution of the high resistance region in the second direction.

3. The semiconductor device according to claim 1 or 2.

19. The high resistance region is disposed at a corner of the active portion when viewed from above. The semiconductor device according to claim 2 .

20. The high resistance region is not provided on the top surface of the semiconductor substrate.

3. The semiconductor device according to claim 1 or 2.

21. The doping concentration of the bottom region is higher than the doping concentration of the base region.

3. The semiconductor device according to claim 1 or 2.

22. the semiconductor substrate has a mesa portion which is a region sandwiched between a plurality of the trench portions, The drift region is also provided in the mesa portion, A part of the drift region and a part of the high resistance region provided in the mesa portion overlap each other in a top view. The semiconductor device according to claim 1 .

23. A semiconductor substrate having an upper surface and a lower surface and including a drift region of a first conductivity type, a base region of a second conductivity type provided between the drift region and the upper surface of the semiconductor substrate; a plurality of trenches provided from the upper surface of the semiconductor substrate to a position below the base region; a second conductivity type lower end region provided in contact with lower ends of two or more of the plurality of trench portions; a well region of a second conductivity type that is disposed at a position different from the lower end region when viewed from above, that is provided from the upper surface of the semiconductor substrate to a position lower than the base region, and that has a doping concentration higher than that of the base region; a second conductivity type high resistance region that is disposed between the lower end region and the well region when viewed from the top and has a doping concentration lower than that of the lower end region; Forming Injecting a dopant of a second conductivity type into both a region in which the high resistance region is to be formed and a region in which the bottom end region is to be formed; A second conductive type dopant is further implanted into the region in which the lower end region is to be formed. A method for manufacturing a semiconductor device.

24. A semiconductor substrate having an upper surface and a lower surface and including a drift region of a first conductivity type, comprising: a base region of a second conductivity type provided between the drift region and the upper surface of the semiconductor substrate; a plurality of trenches provided from the upper surface of the semiconductor substrate to a position below the base region; a second conductivity type lower end region provided in contact with lower ends of two or more of the plurality of trench portions; a well region of a second conductivity type that is disposed at a position different from the lower end region when viewed from above, that is provided from the upper surface of the semiconductor substrate to a position lower than the base region, and that has a doping concentration higher than that of the base region; a second conductivity type high resistance region that is disposed between the lower end region and the well region when viewed from the top and has a doping concentration lower than that of the lower end region; Forming In forming the high resistance region, a region other than the plurality of trench portions is masked with a mask, and a dopant is implanted into the semiconductor substrate through the plurality of trench portions. A method for manufacturing a semiconductor device.

25. A second conductive type dopant having different concentrations is implanted into a region in which the high resistance region is to be formed and a region in which the bottom region is to be formed, respectively. The method for manufacturing a semiconductor device according to claim 24.

26. A dopant of a second conductivity type is injected into a region away from a region where the lower end region is to be formed, among the region where the high resistance region is to be formed, and the dopant is diffused toward the region where the lower end region is to be formed by heat treatment. The method for manufacturing a semiconductor device according to claim 24.

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