Semiconductor Device

Abstract

To provide a semiconductor device capable of enhancing ESD resistance.SOLUTION: A semiconductor device includes a first conductivity type semiconductor substrate 21, a second conductivity type epitaxial layer 22 arranged on the semiconductor substrate 21, a high-side circuit region 23 arranged in the semiconductor substrate 21 and the epitaxial layer 22 in plan view, a high breakdown voltage termination region 24 arranged on the outer periphery of the high side circuit region 23 in plan view, and a level shift MOS 26 located in the high breakdown voltage termination region 24 in plan view. The breakdown voltage of the level shift MOS 26 is higher than that of the high breakdown voltage termination region 24 other than the level shift MOS 26.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] FIG. 5 is a plan view showing a conventional semiconductor device equipped with a high-voltage (several hundred V) high-side circuit area and a level shift MOS.

[0003] This semiconductor device has a high-side circuit area 101, and a low-side circuit area 102 is arranged outside the high-side circuit area 101. A high-voltage termination region 103 is arranged between the high-side circuit area 101 and the low-side circuit area 102. A level-shift MOS 104 is arranged in the high-voltage termination region 103. The outside of the level-shift MOS 104 is surrounded by an isolation region 105. In other words, the isolation region 105 separates the region in which the level-shift MOS 104 is formed from the other part of the high-voltage termination region 103.

[0004] 5 has a drain section 11 and a high side potential region 12 of a level shift MOS 104, and an N+ buried layer (NBL) of the same structure is formed in both the drain section 11 and the high side potential region 12. The N+ buried layer (NBL) of the drain section 11 and the high side potential region 12 are made to have the same structure and have the same breakdown voltage design, which simplifies the circuit design.

[0005] The above-mentioned semiconductor device is an example in which the N+ buried layer (NBL) is present in both the drain section 11 and the high side potential region 12, but conventional semiconductor devices may have a structure in which the N+ buried layer (NBL) is absent in both the drain section 11 and the high side potential region 12, and in such cases, the same idea of ​​facilitating design is applied. Patent Document 1 describes technology related to conventional semiconductor devices.

[0006] However, in the above-mentioned conventional semiconductor device (IC), it is difficult in design to mount an ESD (Electro-Static Discharge) protection element between the high-side circuit area and the low-side circuit area, making it impossible to take measures against ESD and difficult to improve ESD tolerance.

[0007] In particular, in semiconductor devices with a low rated voltage of about 200 V, there is a problem in improving ESD resistance. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2017-022678 A Summary of the Invention [Problem to be solved by the invention]

[0009] Various aspects of the present invention have an object to provide a semiconductor device capable of improving ESD resistance. [Means for solving the problem]

[0010] Various aspects of the present invention are described below.

[0011] [1] A semiconductor substrate of a first conductivity type; an epitaxial layer of a second conductivity type disposed on the semiconductor substrate; a high side circuit region disposed in the semiconductor substrate and the epitaxial layer in a plan view; a high-voltage termination region disposed on the periphery of the high-side circuit region in a plan view; a level shift MOS located in the high voltage termination region in a plan view; having The semiconductor device according to claim 1, wherein the withstand voltage of the level shift MOS is higher than the withstand voltage of a high-voltage termination region other than the level shift MOS.

[0012] [2] In paragraph [1] above: a first second conductivity type impurity diffusion layer located in the level shift MOS, located on a high side circuit region side in a plan view, and disposed on a front surface side of the epitaxial layer; a first electrode disposed on the first second-conductivity-type impurity diffusion layer and electrically connected to the first second-conductivity-type impurity diffusion layer; a second second-conductivity-type impurity diffusion layer disposed on a surface side of the epitaxial layer located in the high-voltage termination region other than the region of the level shift MOS, and located on a high-side circuit region side in a plan view; a second electrode disposed on the second second-conductivity-type impurity diffusion layer and electrically connected to the second second-conductivity-type impurity diffusion layer; a second conductive type buried impurity diffusion layer disposed under the second second conductive type impurity diffusion layer and located at a boundary between the semiconductor substrate and the epitaxial layer; having 2. A semiconductor device comprising: a first second-conductivity-type impurity diffusion layer and a second-conductivity-type buried impurity diffusion layer;

[0013] [3] In paragraph [2] above: 2. A semiconductor device comprising: a level shift MOS transistor arranged adjacent to a high side circuit region in a plan view;

[0014] [4] In [2] or [3] above, a second conductivity type epitaxial layer located in the high voltage termination region, the second conductivity type impurity diffusion layer being separated from the first second conductivity type impurity diffusion layer and the second second conductivity type impurity diffusion layer being separated from each other by an isolation region;

[0015] [5] In paragraph [4] above: 11. A semiconductor device comprising: a first semiconductor layer including a first conductivity type impurity diffusion layer disposed in the epitaxial layer of the second conductivity type;

[0016] [6] In paragraph [2] above: In a plan view, the high-withstand voltage termination region has a strip-shaped first region covering the high-side circuit region and a second region disposed outside the first region, The semiconductor device, wherein the level-shift MOS is disposed in the second region in a plan view.

[0017] [7] In paragraph [2] or [6] above, The semiconductor device according to claim 1, wherein the second region is not separated from the first region. [8] In any one of paragraphs [2] to [7] above: the second conductive type buried impurity diffusion layer is disposed in the high side circuit region and the high voltage termination region other than the level shift MOS in a plan view, a second conductive type buried impurity diffusion layer having a higher impurity concentration on a side closer to the level shift MOS and a lower impurity concentration on a side farther from the level shift MOS, [9] In any one of paragraphs [2] to [7] above: the second conductive type buried impurity diffusion layer is disposed in the high side circuit region and the high voltage termination region other than the level shift MOS in a plan view, The semiconductor device is characterized in that the second conductive type buried impurity diffusion layer has an impurity concentration that is uniform when viewed in a plan view.

[0018]

[10] In any one of paragraphs [1] to [9] above, The level shift MOS is a second first conductivity type impurity diffusion layer disposed on a front surface side of the second conductivity type epitaxial layer; a second conductive type source diffusion layer disposed on a surface side of the second first conductive type impurity diffusion layer; a gate insulating film located on a surface of the second conductive type epitaxial layer and adjacent to the second conductive type source diffusion layer; a gate electrode disposed on the gate insulating film; the first second conductivity type impurity diffusion layer electrically connected to the first electrode; a second insulating layer located between the first second conductivity type impurity diffusion layer and the gate electrode and disposed on a surface of the second conductivity type epitaxial layer; A semiconductor device comprising:

[0019]

[11] In any one of paragraphs [1] to

[10] above, The high voltage termination region is a third first conductivity type impurity diffusion layer disposed on a front surface side of the second conductivity type epitaxial layer; a fourth first-conductivity-type impurity diffusion layer disposed on a front surface side of the third first-conductivity-type impurity diffusion layer; a third electrode electrically connected to the fourth first conductivity type impurity diffusion layer; the second second-conductivity-type impurity diffusion layer electrically connected to the second electrode; a third insulating layer located between the second second-conductivity-type impurity diffusion layer and the third first-conductivity-type impurity diffusion layer and disposed on a surface of the second-conductivity-type epitaxial layer; A semiconductor device comprising: Effect of the Invention

[0020] According to various aspects of the present invention, it is possible to provide a semiconductor device capable of improving ESD resistance. [Brief description of the drawings]

[0021] [Figure 1] FIG. 1 is a plan view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 2] 2A is a cross-sectional view taken along line AA' in FIG. 1, and FIG. 2B is a cross-sectional view taken along line BB' in FIG. [Diagram 3] FIG. 1 is a plan view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 4]4(A) is a cross-sectional view taken along line CC' in FIG. 3, and (B) is a cross-sectional view taken along line BB' in FIG. [Diagram 5] FIG. 1 is a plan view showing a conventional semiconductor device equipped with a high-voltage (several hundred V) high-side circuit area and a level shift MOS. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0023] (First embodiment) Fig. 1 is a plan view showing a semiconductor device according to one embodiment of the present invention, Fig. 2(A) is a cross-sectional view taken along line A-A' shown in Fig. 1, and Fig. 2(B) is a cross-sectional view taken along line B-B' shown in Fig. 1.

[0024] The semiconductor device has a first conductive type semiconductor substrate 21. The first conductive type semiconductor substrate 21 has a P + This P + The semiconductor substrate 21 is, for example, a P + The silicon substrate is a silicon substrate.

[0025] A second conductive type epitaxial layer 22 is disposed on a first conductive type semiconductor substrate 21. The second conductive type epitaxial layer 22 is an N-type epitaxial layer shown in Figures 2(A) and (B).

[0026] In plan view, a first conductive type semiconductor substrate (P + A high side circuit region (high side circuit area) 23 is disposed on a type silicon substrate 21 and an epitaxial layer 22 (see FIG. 1).

[0027] 1, in a plan view, a high-voltage termination region 24 is disposed on the outer periphery of a high-side circuit region 23. A low-side circuit region (low-side circuit area) 25 is disposed outside this high-voltage termination region 24.

[0028] In a plan view, the level-shift MOS 26 is located in the high-voltage termination region 24. The level-shift MOS 26 is surrounded by an isolation region 27 (see FIG. 1). In other words, the isolation region 27 isolates the region in which the level-shift MOS 26 is formed from the other part of the high-voltage termination region 24.

[0029] The withstand voltage of the level shift MOS 26 is set higher than the withstand voltage of the high withstand voltage termination region 24 other than the level shift MOS 26. This allows the high withstand voltage termination region 25 other than the level shift MOS 26 to break down first when an ESD surge occurs. As a result, the ESD current can be extracted by the high withstand voltage termination region 24 before the level shift MOS 26, which has low ESD resistance, breaks down, thereby increasing the ESD resistance.

[0030] In particular, even in semiconductor devices with a low rated voltage of about 200 V, the ESD resistance can be improved.

[0031] As shown in FIG. 2A, a first second conductive type impurity diffusion layer (N + ) 16 is disposed. The first second conductivity type impurity diffusion layer (N + )16 is N + This N + The type impurity diffusion layer 16 is located in the level shift MOS 26 and is located on the high side circuit region 23 side in a plan view.

[0032] The first second conductive type impurity diffusion layer (N + A first electrode (Drain) 18 is disposed on the first second conductivity type impurity diffusion layer (N+ The first second conductivity type impurity diffusion layer (N type impurity diffusion layer) 16 is electrically connected to the first second conductivity type impurity diffusion layer (N type impurity diffusion layer) 16 (see FIG. 2(A)). + The N-type impurity diffusion layer 16 is a diffusion layer for making contact with the N-type epitaxial layer 22 and has a higher impurity concentration than the N-type epitaxial layer 22.

[0033] A second second conductive type impurity diffusion layer (N + ) 13 is disposed. A second second conductivity type impurity diffusion layer (N + ) 13 is located on the high side circuit region 23 side in a plan view.

[0034] The second second conductive type impurity diffusion layer (N + A diffusion layer 13 is provided for making contact with the N-type epitaxial layer 22 and has a higher impurity concentration than the N-type epitaxial layer 22 .

[0035] As shown in FIG. 2B, a second second-conductivity type impurity diffusion layer (N + A second electrode (HV) 14 is disposed on the second conductive type impurity diffusion layer (N + ) 13. The second second conductivity type impurity diffusion layer (N + )13 is N + The impurity diffusion layer is a type impurity diffusion layer.

[0036] The second second conductive type impurity diffusion layer (N + A second conductive type buried impurity diffusion layer (NBL) 15 is disposed under the N type epitaxial layer 22. The second conductive type buried impurity diffusion layer (NBL) 15 is located at the boundary between the P type semiconductor substrate 21 and the N type epitaxial layer 22. As shown in FIGS. 2A and 2B, the second conductive type buried impurity diffusion layer (NBL) 15 is + This is a mold-buried layer.

[0037] The first second conductive type impurity diffusion layer (N+ A second conductive type buried impurity diffusion layer (NBL:NBL) is disposed under the second conductive type buried impurity diffusion layer (NBL) 16. + In other words, the second second conductivity type impurity diffusion layer (N type buried layer) 15 shown in FIG. 2B is located in the high voltage termination region 24 other than the region of the level shift MOS 26. + A second conductive type buried impurity diffusion layer (NBL:NBL) is disposed under the second conductive type buried impurity diffusion layer (NBL) 13. + 1A, the first second conductivity type impurity diffusion layer (N + A second conductive type buried impurity diffusion layer (NBL:NBL) is disposed under the second conductive type buried impurity diffusion layer (NBL) 16. + The mold embedding layer 15 is not formed.

[0038] In short, the second conductive type buried impurity diffusion layer (NBL) 15 exists in the entire high-side circuit region 23, but is not disposed in the drain portion of the first electrode 18 of the level shift MOS 26. This allows the withstand voltage of the level shift MOS 26 to be higher than the withstand voltage of the high-voltage termination region 24 other than the level shift MOS 26. In detail, the withstand voltage of the drain portion of the first electrode 18 of the level shift MOS 26 shown in FIG. 2(A) can be higher than the withstand voltage of the high-side potential region of the second electrode (HV) 14 of the high-voltage termination region 24 shown in FIG. 2(B). This allows an ESD current path to be created in the high-voltage termination region 24 other than the level shift MOS 26, thereby increasing the ESD resistance. Specifically, the ESD current can be extracted in the high-voltage termination region 24 before the level shift MOS 26, which has low ESD resistance, is destroyed, thereby increasing the ESD resistance. In other words, when an ESD surge enters from the first electrode 18 and the second electrode 14 shown in FIGS. 2A and 2B, the second electrode (HV) 14 is in contact with the second second-conductivity-type impurity diffusion layer (N + A first conductive type semiconductor substrate (P + This prevents the level shift MOS 26 from being destroyed by being pulled out by the insulating layer 21. In addition, the second conductive type buried impurity diffusion layer (NBL:N + The buried type layer 15 is disposed in the high side circuit region 23 and the high voltage termination region 24 except for the level shift MOS 26 in a plan view (see FIG. 2A and FIG. 1). In addition, N shown in FIG. + The impurity concentration of the NBL 15 is preferably high on the side closer to the level shift MOS 26 and low on the side farther from the level shift MOS 26. + The impurity concentration of the buried type layer 15 is preferably high on the side closer to the first conductivity type impurity diffusion layer (P-type impurity diffusion layer) 31 and low on the side farther from the P-type impurity diffusion layer 31. This makes it more difficult for an ESD current to flow through the level shift MOS 26, and prevents the level shift MOS 26 from being destroyed. In addition, as shown in FIG. + The buried type layer 15 is formed at a predetermined distance from the P-type impurity diffusion layer 31. + This distance is set so that the avalanche resistance of the PN structure formed by the N-type buried layer 15 and the P-type impurity diffusion layer 31 can be ensured, and the breakdown voltage of the level shift MOS 26 is higher than the breakdown voltage of the high-voltage termination region 24 other than the level shift MOS 26. For example, when the sheet resistance of the P-type impurity diffusion layer 31 is 5.0 Ω / sq to 15 Ω / sq and the N + When the sheet resistance of the buried layer 15 is 200 Ω / sq to 250 Ω / sq, the P-type impurity diffusion layer 31 and the N + It is preferable that the distance of the buried type layer 15 is 15 μm or more. This makes it possible to increase the ESD resistance of the level shift MOS 26 while ensuring the avalanche resistance of the above-mentioned PN structure. In addition, the second conductive type buried impurity diffusion layer (NBL:N + The impurity concentration of the N-type buried layer 15 may be uniform in plan view. This allows the ESD current to be extracted in a uniform area of ​​the high side circuit region 23 and the high voltage termination region 24, thereby increasing the ESD resistance. +The impurity concentration of the buried layer 15 is uniform in plan view. + By forming the mold buried layer 15 in a single impurity ion introduction step, it is meant that the impurity concentration is uniform on the same plane or at the same depth.

[0039] Furthermore, if a MOS structure is present in the current path, a parasitic transistor may operate, causing latch-up and resulting in destruction, but this can be avoided.

[0040] 1, the level shift MOS 26 is disposed adjacent to the high side circuit region 23 in a plan view. This allows the chip area of ​​the semiconductor device to be reduced. At the same time, by making the withstand voltage of the level shift MOS 26 higher than the withstand voltage of the high withstand voltage termination region 24 other than the level shift MOS 26, an ESD current path can be created in the high withstand voltage termination region 24 other than the level shift MOS 26.

[0041] The semiconductor device is disposed in a second conductive type epitaxial layer (N-type epitaxial layer) 22 located in a high voltage termination region 24, and a first second conductive type impurity diffusion layer (N + type impurity diffusion layer) 16 and the second second conductivity type impurity diffusion layer (N + The high-voltage termination region 24 has an isolation region 27 which isolates the level-shift MOS 26 from the high-voltage termination region 24. The isolation region 27 can prevent the area occupied by the high-voltage termination region 24 from increasing even if the level-shift MOS 26 is disposed in the high-voltage termination region 24.

[0042] The isolation region 27 shown in FIG. 1 is isolated by a first first-conductivity-type impurity diffusion layer 31 disposed in the second-conductivity-type epitaxial layer (N-type epitaxial layer) 22 shown in FIG. 2(A). The first first-conductivity-type impurity diffusion layer 31 is a P-type impurity diffusion layer. An insulating layer 32 such as SiO2 is disposed on the first first-conductivity-type impurity diffusion layer (P-type impurity diffusion layer) 31. In other words, the first first-conductivity-type impurity diffusion layer (P-type impurity diffusion layer) 31 is a P +The semiconductor substrate 21 and the first insulating layer 32 are in contact with each other.

[0043] FIG. 2 is explained in more detail below. As shown in FIG. 2(A), the level shift MOS 26 has a second first-conductivity-type impurity diffusion layer (P) 41 arranged on the front surface side of the second-conductivity-type epitaxial layer (N-type epitaxial layer) 22, and the second first-conductivity-type impurity diffusion layer 41 is a P-type impurity diffusion layer.

[0044] The P-type impurity diffusion layer 41 is located in the level shift MOS 26 surrounded by the isolation region 27 (see FIGS. 1 and 2A).

[0045] A second conductive type source diffusion layer 42 is disposed on the surface side of the second first conductive type impurity diffusion layer (P type impurity diffusion layer) 41. The second conductive type source diffusion layer 42 is an N + The source diffusion layer.

[0046] As shown in FIG. 2A, the surface side of the P-type impurity diffusion layer 41 is + A P type impurity diffusion layer 45 is disposed. + The N-type impurity diffusion layer 45 and + An electrode 46 is disposed on the source diffusion layer 42. The electrode 46 is a P + The N-type impurity diffusion layer 45 and + The electrodes 46 are electrically connected to the source diffusion layers 42. The electrodes 46 are made of a metal such as Al or an Al alloy.

[0047] A gate insulating film is formed on the surface of the second conductive type epitaxial layer (N type epitaxial layer) 22. This gate insulating film is connected to the second conductive type source diffusion layer (N + The gate insulating film is disposed adjacent to the gate electrode (source diffusion layer) 42. The gate insulating film is, for example, a silicon oxide film.

[0048] A gate electrode 43 is disposed on the gate insulating film. 2A, the gate electrode 43 is electrically connected to a wiring 47. The gate electrode 43 is made of, for example, a polysilicon film. The wiring 47 is made of, for example, a metal such as Al or an Al alloy.

[0049] The level shift MOS 26 also has a first second conductive type impurity diffusion layer 16 electrically connected to a first electrode (Drain) 18, and the first second conductive type impurity diffusion layer 16 is in contact with the N-type epitaxial layer 22. The first second conductive type impurity diffusion layer 16 is an N+ type impurity diffusion layer.

[0050] The first second conductive type impurity diffusion layer (N + A second insulating layer 44 such as SiO2 is disposed between the N-type impurity diffusion layer 16 and the gate electrode 43, and the second insulating layer 44 is formed on the surface of the second conductivity type epitaxial layer (N-type epitaxial layer) 22.

[0051] The semiconductor device of this embodiment includes the level shift MOS 26 described above.

[0052] In addition, a P-type impurity diffusion layer 58 is formed in the N-type epitaxial layer 22. + The P-type semiconductor substrate 21 is electrically connected to the P-type impurity diffusion layer 58. The P-type impurity diffusion layer 58 is located between the low-side circuit area 25 and the high-voltage termination region 24. The isolation region 27 has a first insulating layer 32 such as SiO2 and a P-type impurity diffusion layer 31. The P-type impurity diffusion layer 31 is a P + The N-type epitaxial layer 22 located in the high-side circuit area 23 is electrically connected to the N-type semiconductor substrate 21. + The N-type impurity diffusion layer 48 is formed. + An electrode (HV) 49 is disposed on the N-type impurity diffusion layer 48. + The N-type epitaxial layer 22 is electrically connected to the N-type impurity diffusion layer 48. +An insulating layer 50 such as SiO2 is disposed adjacent to the N-type impurity diffusion layer 48. + The impurity diffusion layer 48 and the insulating layer 50 are an N+ buried layer (NBL). + The buried layer 15 is located on the substrate 10 .

[0053] As shown in FIG. 2(B), the high-voltage termination region 24 has a third first-conductivity-type impurity diffusion layer (P) 51 arranged on the front surface side of the second-conductivity-type epitaxial layer (N-type epitaxial layer) 22, and the third first-conductivity-type impurity diffusion layer 51 is a P-type impurity diffusion layer.

[0054] A fourth first-conductivity-type impurity diffusion layer 52 is disposed on the front surface side of the third first-conductivity-type impurity diffusion layer (P-type impurity diffusion layer) 51. The fourth first-conductivity-type impurity diffusion layer 52 is a P + The impurity diffusion layer is a type impurity diffusion layer.

[0055] P + The P-type impurity diffusion layer 52 is in contact with the P-type silicon substrate 21 through the P-type impurity diffusion layer 51 and the P-type impurity diffusion layer 58 .

[0056] The fourth first conductivity type impurity diffusion layer (P + A third electrode 53 is formed on the fourth first conductivity type impurity diffusion layer (P + The gate electrode 51 is electrically connected to the gate electrode 52 (type impurity diffusion layer).

[0057] The high voltage termination region 24 is electrically connected to the second electrode (HV) 14 through a second second conductivity type impurity diffusion layer (N + type impurity diffusion layer) 13, and a second second conductivity type impurity diffusion layer (N + The N-type impurity diffusion layer 13 is in contact with the N-type epitaxial layer 22 .

[0058] The second second conductive type impurity diffusion layer (N +A third insulating layer 54 such as SiO2 is disposed between the first conductivity type impurity diffusion layer (P-type impurity diffusion layer) 13 and the third first conductivity type impurity diffusion layer (P-type impurity diffusion layer) 51, and the third insulating layer 54 is formed on the surface of the second conductivity type epitaxial layer (N-type epitaxial layer) 22.

[0059] The surface of the N-type epitaxial layer 22 is + An insulating layer 50 such as SiO2 is disposed next to the N-type impurity diffusion layer 13. The insulating layer 50 is made of N + It is located on the negative buried layer (NBL) 15 and is located in the high side circuit area 23 .

[0060] In addition, an insulating film (not shown) is formed on the N-type epitaxial layer 22 shown in Figures 2(A) and (B), and this insulating film covers the surface of the N-type epitaxial layer 22, the third electrode 53, the third insulating layer 54, the insulating layer 50, and the second electrode (HV) 14. The semiconductor device of this embodiment has the high-voltage termination region 24 described above.

[0061] Second embodiment Fig. 3 is a plan view showing a semiconductor device according to one embodiment of the present invention. Fig. 4(A) is a cross-sectional view taken along line CC' in Fig. 3, and Fig. 4(B) is a cross-sectional view taken along line BB' in Fig. 3. Fig. 4(B) shows a similar configuration to Fig. 2(B).

[0062] In FIG. 4(A), the same parts as those in FIG. 2(A) are denoted by the same reference numerals, so the explanation thereof will be omitted, and only the different parts will be explained below.

[0063] In the semiconductor device shown in Fig. 2(A), an isolation region 27 having a P-type impurity diffusion layer 31 and a first insulating layer 32 is disposed in the N-type epitaxial layer 22, but in the semiconductor device shown in Fig. 4(A), such an isolation region is not disposed. + type impurity diffusion layer 13 and N +A first insulating layer 32 such as SiO2 is formed between the type impurity diffusion layers 16. The first insulating layer 32 functions as a separation portion 57 by being formed so as to provide a sufficient distance between the first region 24a and the second region 24b.

[0064] As shown in FIG. 3, in a plan view, the high-voltage termination region 24 has a strip-shaped first region 24a that covers the high-side circuit region 23, and a second region 24b that is disposed outside the first region 24a.

[0065] In addition, the level shift MOS 26 is disposed in the second region 24b in plan view. That is, by disposing the level shift MOS 26 in the second region 24b disposed outside the first region 24a, the level shift MOS 26 can be located farther from the high side circuit region 23 than the level shift MOS shown in FIG. 1. Therefore, a necessary withstand voltage can be obtained from the high side circuit region 23.

[0066] In addition, the second conductive type buried impurity diffusion layer (NBL:N + The buried type layer 15 exists in the entire high-side circuit region 23, but is not disposed in the drain portion of the first electrode 18 of the level-shift MOS 26. This allows the withstand voltage of the level-shift MOS 26 to be higher than the withstand voltage of the high-voltage termination region 24 other than the level-shift MOS 26. In detail, the withstand voltage of the drain portion of the first electrode 18 of the level-shift MOS 26 shown in FIG. 4(A) can be higher than the withstand voltage of the high-side potential region of the second electrode (HV) 14 of the high-voltage termination region 24 shown in FIG. 4(B). This allows an ESD current path to be created in the high-voltage termination region 24 other than the level-shift MOS 26, thereby increasing the ESD resistance. Specifically, the ESD current can be extracted in the high-voltage termination region 24 before the level-shift MOS 26, which has low ESD resistance, is destroyed, thereby increasing the ESD resistance. In other words, when an ESD surge enters from the first electrode 18 and the second electrode 14 shown in FIGS. 4A and 4B, the second electrode (HV) 14 is electrically connected to the second second-conductivity-type impurity diffusion layer (N +A first conductive type semiconductor substrate (P + This prevents the level shift MOS 26 from being destroyed by being pulled out by the insulating layer 21.

[0067] As shown in Fig. 3, the second region 24b is not isolated from the first region 24a. In other words, the isolation region 27 as shown in Fig. 1 is not formed in the high-voltage termination region 24 shown in Fig. 3, but by arranging the level-shift MOS 26 in the second region 24b arranged outside the first region 24a as described above, the level-shift MOS 26 can obtain a necessary withstand voltage for the high-side circuit region 23 even if the second region 24b is not isolated from the first region 24a.

[0068] The above first and third embodiments can also be implemented in combination with each other. [Explanation of symbols]

[0069] 13 Second second conductive type impurity diffusion layer (N + type impurity diffusion layer) 14 Second electrode (HV) 15 Second conductive type buried impurity diffusion layer (NBL:N + Mold embedding layer) 16 First second conductive type impurity diffusion layer (N + type impurity diffusion layer) 18 First electrode (Drain) 21 First conductive type semiconductor substrate (P + Mold silicon substrate) 22 Second conductive type epitaxial layer (N-type epitaxial layer) 23 High side circuit area (High side circuit area) 24 High voltage termination area 24a Band-shaped first area 24b Second area 26 Level shift MOS 27 Separation area 31 First first conductive type impurity diffusion layer (P type impurity diffusion layer) 32 First insulating layer 41 Second first conductive type impurity diffusion layer (P type impurity diffusion layer) 42 Second conductive type source diffusion layer (N + type source diffusion layer) 43 Gate electrode 44 Second insulating layer 48 N + Impurity diffusion layer 49 Electrode (HV) 50 Insulating layer 51 Third first conductive type impurity diffusion layer (P type impurity diffusion layer) 52 Fourth first conductivity type impurity diffusion layer (P + type impurity diffusion layer) 53 Third Electrode 54 Third insulating layer 58 P-type impurity diffusion layer

Claims

1. a semiconductor substrate of a first conductivity type; an epitaxial layer of a second conductivity type disposed on the semiconductor substrate; a high side circuit region disposed in the semiconductor substrate and the epitaxial layer in a plan view; a high-voltage termination region disposed on the outer periphery of the high-side circuit region in a plan view; a level shift MOS located in the high voltage termination region in a plan view; having The semiconductor device is characterized in that the withstand voltage of the level shift MOS is higher than the withstand voltage of a high-voltage termination region other than the level shift MOS.

2. In claim 1, a first second conductivity type impurity diffusion layer located in the level shift MOS, located on a high side circuit region side in a plan view, and disposed on a front surface side of the epitaxial layer; a first electrode disposed on the first second-conductivity-type impurity diffusion layer and electrically connected to the first second-conductivity-type impurity diffusion layer; a second second conductivity type impurity diffusion layer disposed on a surface side of the epitaxial layer located in the high voltage termination region other than the region of the level shift MOS, and located on a high side circuit region side in a plan view; a second electrode disposed on the second second-conductivity-type impurity diffusion layer and electrically connected to the second second-conductivity-type impurity diffusion layer; a second conductivity type buried impurity diffusion layer disposed under the second second conductivity type impurity diffusion layer and located at a boundary between the semiconductor substrate and the epitaxial layer; having a buried impurity diffusion layer of a second conductivity type is not disposed below the first impurity diffusion layer of the second conductivity type.

3. In claim 2, The semiconductor device according to claim 1, wherein the level shift MOS is disposed adjacent to the high side circuit region in a plan view.

4. In claim 2 or 3, a second conductivity type epitaxial layer located in the high voltage termination region, the second conductivity type impurity diffusion layer being separated from the first second conductivity type impurity diffusion layer and the second second conductivity type impurity diffusion layer being separated from each other by an isolation region.

5. In claim 4, 2. A semiconductor device comprising: a first semiconductor layer including a first conductivity type impurity diffusion layer disposed in the epitaxial layer of the second conductivity type;

6. In claim 2, In a plan view, the high-withstand voltage termination region has a strip-shaped first region covering the high-side circuit region and a second region disposed outside the first region, The level shift MOS is disposed in the second region in a plan view.

7. In claim 6, The semiconductor device according to claim 1, wherein the second region is not separated from the first region.

8. In any one of claims 2 to 7, the second conductive type buried impurity diffusion layer is disposed in the high side circuit region and the high voltage termination region other than the level shift MOS in a plan view, The semiconductor device according to claim 1, wherein the impurity concentration of the second conductive type buried impurity diffusion layer is higher on a side closer to the level shift MOS and is lower on a side farther from the level shift MOS.

9. In any one of claims 2 to 7, the second conductive type buried impurity diffusion layer is disposed in the high side circuit region and the high voltage termination region other than the level shift MOS in a plan view, The semiconductor device is characterized in that the second conductive type buried impurity diffusion layer has an impurity concentration that is uniform in a plan view.

10. In claim 2, The level shift MOS is a second first conductivity type impurity diffusion layer disposed on a front surface side of the second conductivity type epitaxial layer; a second conductivity type source diffusion layer disposed on a front surface side of the second first conductivity type impurity diffusion layer; a gate insulating film located on a surface of the second conductive type epitaxial layer and adjacent to the second conductive type source diffusion layer; a gate electrode disposed on the gate insulating film; the first second conductivity type impurity diffusion layer electrically connected to the first electrode; a second insulating layer located between the first second conductivity type impurity diffusion layer and the gate electrode and disposed on a surface of the second conductivity type epitaxial layer; A semiconductor device comprising:

11. In claim 2, The high voltage termination region is a third first conductivity type impurity diffusion layer disposed on a front surface side of the second conductivity type epitaxial layer; a fourth first conductivity type impurity diffusion layer disposed on a front surface side of the third first conductivity type impurity diffusion layer; a third electrode electrically connected to the fourth first conductivity type impurity diffusion layer; the second second-conductivity-type impurity diffusion layer electrically connected to the second electrode; a third insulating layer located between the second second-conductivity-type impurity diffusion layer and the third first-conductivity-type impurity diffusion layer and disposed on a surface of the second-conductivity-type epitaxial layer; A semiconductor device comprising:

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