Semiconductor Devices

Abstract

A semiconductor device comprises a semiconductor substrate, at least one transistor that is provided on the semiconductor substrate and includes a plurality of semiconductor layers, wiring provided on the transistor, a first insulating film that has a first opening in a region overlapping the transistor and the wiring in plan view along a first direction perpendicular to the semiconductor substrate, a first rewiring layer that is provided on the first insulating film, is superimposed on the at least one transistor in plan view along the first direction, and is electrically connected to the wiring via the first opening, a second insulating film that is provided over the first rewiring layer and the first insulating film and has a second opening in a region overlapping at least a part of the first rewiring layer in plan view along the first direction, and bumps electrically connected to the first rewiring layer via the second opening. The width of the first opening on the first insulating film in a second direction parallel to the semiconductor substrate is larger than that of the second opening of the second insulating film in the second direction.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 describes a semiconductor device equipped with a heterojunction bipolar transistor. The semiconductor device described in Patent Document 1 has a bump provided directly above the transistor. The bump is electrically connected to the emitter electrode of the transistor through an opening in an organic insulating film (resin film) covering the transistor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-149485 Summary of the Invention [Problem to be solved by the invention]

[0004] If a bump is provided so as to overlap the entire area of ​​the mesa structure of a transistor, heat dissipation will improve (i.e., thermal resistance will be reduced), but stress from the bump may cause cracks in the mesa structure, reducing the reliability of the semiconductor device.

[0005] An object of the present invention is to provide a semiconductor device capable of suppressing stress generated in a transistor. [Means for solving the problem]

[0006] a first insulating film having a first opening in a region overlapping with the transistor and the wiring when viewed in a plane in a first direction perpendicular to the semiconductor substrate; a first redistribution layer provided on the first insulating film, overlapping with at least one of the transistors when viewed in a plane in the first direction, and electrically connected to the wiring through the first opening; a second insulating film covering the first redistribution layer and the first insulating film, having a second opening in a region overlapping with at least a portion of the first redistribution layer when viewed in a plane in the first direction; and a bump electrically connected to the first redistribution layer through the second opening, wherein the width of the first opening in the first insulating film in a second direction parallel to the semiconductor substrate is greater than the width of the second opening in the second insulating film in the second direction. [Effects of the Invention]

[0007] According to the semiconductor device of the present invention, stress occurring in the transistor can be suppressed. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II' of FIG. [Figure 3] FIG. 3 is a table for explaining the relationship between the opening width and the occurrence of defects in the semiconductor devices according to the example and the comparative example. [Figure 4] FIG. 4 is a cross-sectional view of the semiconductor device according to the second embodiment. [Figure 5] FIG. 5 is a cross-sectional view of the semiconductor device according to the third embodiment. [Figure 6] FIG. 6 is an explanatory diagram of a semiconductor device according to a modification of the third embodiment. [Figure 7] FIG. 7 is an explanatory diagram for explaining the manufacturing process of the semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the semiconductor device of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to these embodiments. Each embodiment is an example, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. From the second embodiment onwards, a description of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, similar effects resulting from similar configurations will not be mentioned in each embodiment.

[0010] (First embodiment) Fig. 1 is a plan view of a semiconductor device according to a first embodiment. Fig. 1 omits the detailed configuration of each transistor BT and shows a schematic diagram of the arrangement of the mesa structure including the base layer 4 of each transistor and the emitter electrode 6. In Fig. 1, bumps 21 are indicated by two-dot chain lines to make the drawing easier to see.

[0011] As shown in FIG. 1, the semiconductor device 100 includes a semiconductor substrate 1, a transistor group Q1, a first organic insulating film 16, a second organic insulating film 19, an emitter wiring 11, a first rewiring layer 18, and a bump 21.

[0012] In the following description, one direction in a plane parallel to the surface of the semiconductor substrate 1 is referred to as the X-axis direction Dx. Furthermore, a direction perpendicular to the X-axis direction Dx in a plane parallel to the surface of the semiconductor substrate 1 is referred to as the Y-axis direction Dy. Furthermore, a direction perpendicular to each of the X-axis direction Dx and the Y-axis direction Dy is referred to as the Z-axis direction Dz. The Z-axis direction Dz is a direction perpendicular to the surface of the semiconductor substrate 1. The Z-axis direction Dz is an example of a "first direction," and the X-axis direction Dx and the Y-axis direction Dy are examples of a "second direction." Furthermore, in this specification, "planar view" refers to the positional relationship when viewed from the Z-axis direction Dz.

[0013] The transistor group Q1 is provided on the surface of the semiconductor substrate 1. The transistor group Q1 includes a plurality of transistors BT. The transistors BT are heterojunction bipolar transistors (HBTs). The transistors BT are also called unit transistors, and a unit transistor is defined as the smallest transistor that constitutes the transistor group Q1. The transistors BT are electrically connected in parallel to constitute the transistor group Q1.

[0014] The plurality of transistors BT of the transistor group Q1 are arranged side by side in the X-axis direction Dx. The mesa structures including the base layers 4 of the plurality of transistors BT and the emitter electrodes 6 each extend in the Y-axis direction Dy.

[0015] In FIG. 1, the transistor group Q1 is configured to include three or more transistors BT. However, the number and arrangement of the transistors BT are merely an example and can be changed as appropriate. At least one transistor BT is required. Also, for ease of understanding, FIG. 1 shows one transistor group Q1, but two or more transistor groups may be provided on the same semiconductor substrate 1.

[0016] The first redistribution layer 18 and the bump 21 overlap with the plurality of transistors BT of the transistor group Q1 in plan view. The first redistribution layer 18 is electrically connected to the emitter wiring 11 through a first opening 17 provided in the first organic insulating film 16.

[0017] The bump 21 is electrically connected to the first redistribution layer 18 through a second opening 20 provided in the second organic insulating film 19. As a result, the bump 21 is electrically connected to the plurality of transistors BT through the first redistribution layer 18. The bump 21 has an oval shape in a plan view, extends in the X-axis direction Dx, and is provided along the arrangement direction of the plurality of transistors BT. The bump 21 is provided to cover the entire plurality of transistors BT arranged in the X-axis direction Dx. Furthermore, the width of the bump 21 in the Y-axis direction Dy is larger than the width of the mesa structure including the base layers 4 of the plurality of transistors BT and the emitter electrodes 6 in the Y-axis direction Dy.

[0018] The detailed relationship between the first rewiring layer 18, the bump 21, the first opening 17 provided in the first organic insulating film 16, and the second opening 20 provided in the second organic insulating film 19 will be described later.

[0019] Next, a detailed cross-sectional configuration of the semiconductor device 100 will be described. FIG. 2 is a cross-sectional view taken along line II-II' in FIG. 1. As shown in FIG. 2, in the semiconductor device 100, the transistor BT includes a sub-collector layer 2, a collector layer 3, a base layer 4, an emitter layer 5, an emitter electrode 6, a base electrode 7, and a collector electrode 8. In the transistor BT, the sub-collector layer 2, the collector layer 3, the base layer 4, the emitter layer 5, and the emitter electrode 6 are stacked in this order on a semiconductor substrate 1. The base electrode 7 is provided on the base layer 4, and the collector electrode 8 is provided on the sub-collector layer 2.

[0020] The mesa structure of this embodiment is composed of one or more semiconductor layers among the semiconductor layers of the transistor BT (subcollector layer 2, collector layer 3, base layer 4, and emitter layer 5). For example, the mesa structure is a collector mesa composed of the collector layer 3 and the base layer 4.

[0021] More specifically, the semiconductor substrate 1 is, for example, a semi-insulating GaAs (gallium arsenide) substrate. The subcollector layer 2 is provided on the semiconductor substrate 1. The subcollector layer 2 is a highly doped n-type GaAs layer and has a thickness of, for example, about 0.5 μm. The collector layer 3 is provided on the subcollector layer 2. The collector layer 3 is an n-type GaAs layer and has a thickness of, for example, about 1 μm. The base layer 4 is provided on the collector layer 3. The base layer 4 is a p-type GaAs layer and has a thickness of, for example, about 100 nm.

[0022] The emitter layer 5 is provided on the base layer 4. Although not shown, the emitter layer 5 includes, for example, an intrinsic emitter layer and an emitter mesa layer provided thereon from the base layer 4 side. The intrinsic emitter layer is an n-type InGaP (indium gallium phosphide) layer and has a thickness of, for example, 30 nm to 40 nm. The emitter mesa layer is formed of a high-concentration n-type GaAs layer and a high-concentration n-type InGaAs layer. The high-concentration n-type GaAs layer and the high-concentration n-type InGaAs layer each have a thickness of, for example, about 100 nm. The high-concentration n-type InGaAs layer of the emitter mesa layer is provided to make ohmic contact with the emitter electrode 6.

[0023] The base layer 4 and the collector layer 3 are epitaxially grown on the semiconductor substrate 1 and then etched to form a mesa structure. Alternatively, the lower part of the collector layer 3 may not be removed and the mesa structure may be formed by the base layer 4 and the upper part of the collector layer 3.

[0024] The collector electrode 8 is provided on the sub-collector layer 2 in contact with the sub-collector layer 2. The collector electrode 8 is disposed, for example, adjacent to the mesa structure (base layer 4 and collector layer 3) in the X-axis direction Dx. The collector electrode 8 has, for example, a stacked film formed by stacking an AuGe (gold germanium) film, a Ni (nickel) film, and an Au (gold) film in this order. The thickness of the AuGe film is, for example, 60 nm. The thickness of the Ni film is, for example, 10 nm. The thickness of the Au film is, for example, 200 nm.

[0025] The base electrode 7 is provided on the base layer 4 in contact with the base layer 4. The base electrode 7 is a laminated film in which a Ti film, a Pt film, and an Au film are laminated in this order. The thickness of the Ti film is, for example, 50 nm. The thickness of the Pt film is, for example, 50 nm. The thickness of the Au film is, for example, 200 nm.

[0026] The emitter electrode 6 is provided on the emitter layer 5 in contact with the emitter layer 5. The emitter electrode 6 is a Ti (titanium) film. The thickness of the Ti film is, for example, 50 nm.

[0027] An isolation region 2b is provided on the semiconductor substrate 1 adjacent to the sub-collector layer 2. The isolation region 2b is insulated by ion implantation technology. The isolation region 2b provides insulation between elements (between a plurality of transistors BT).

[0028] The inorganic insulating film 9 is provided on the sub-collector layer 2 and the isolation region 2b, covering the plurality of transistors BT except for a portion of the emitter electrode 6. The inorganic insulating film 9 is, for example, a SiN (silicon nitride) layer. The inorganic insulating film 9 may be a single layer, or may be a laminate of multiple nitride layers or oxide layers.

[0029] The emitter wiring 11 is provided on the inorganic insulating film 9, covering the plurality of transistors BT. An emitter opening 10 is provided in the inorganic insulating film 9 in a region that overlaps with the emitter electrode 6 in a plan view, and the emitter wiring 11 is electrically connected to the emitter electrode 6 through the emitter opening 10.

[0030] A first organic insulating film 16 is provided on the inorganic insulating film 9, covering a portion of the emitter wiring 11. The first organic insulating film 16 is an organic protective film made of an organic material such as polyimide or BCB. A first opening 17 is provided in the first organic insulating film 16 in a region overlapping with the plurality of transistors BT, the emitter electrode 6, and the emitter wiring 11 in plan view.

[0031] The first rewiring layer 18 is provided on the first organic insulating film 16, overlaps the plurality of transistors BT, and is electrically connected to the emitter wiring 11 through the first opening 17.

[0032] The second organic insulating film 19 is provided on the first organic insulating film 16, covering a portion of the first redistribution layer 18. A second opening 20 is provided in a region of the second organic insulating film 19 that overlaps with the first redistribution layer 18 in a plan view. The bump 21 is provided in a region that overlaps with the second opening 20, and is electrically connected to the first redistribution layer 18 through the second opening 20. With this configuration, the bump 21 is electrically connected to the emitter electrodes 6 of the multiple transistors BT through the first opening 17 and the second opening 20. The bump 21 is a pillar bump, and is made of, for example, copper (Cu). In addition to Cu, the bump 21 can also be made of a low-resistance metal material such as aluminum (Al) or gold (Au).

[0033] 2, a metal film such as a diffusion prevention layer or a plating seed layer may be provided between the bump 21 and the first redistribution layer 18. Materials such as nickel (Ni), titanium (Ti), tungsten (W), and chromium (Cr) are used as the diffusion prevention layer and the seed layer.

[0034] The width R1 of the first opening 17 of the first organic insulating film 16 in the X-axis direction Dx is larger than the width R2 of the second opening 20 of the second organic insulating film 19 in the X-axis direction Dx. In other words, in plan view, the inner circumferential surface of the second organic insulating film 19 that forms the second opening 20 is formed in a region that is more inward than the inner circumferential surface of the first organic insulating film 16 that forms the first opening 17 (see FIG. 1).

[0035] Here, the width R1 of the first opening 17 in the first organic insulating film 16 is the distance in the X-axis direction Dx between the position where the inner circumferential surface of the first organic insulating film 16 that forms the first opening 17 contacts the emitter wiring 11 on the semiconductor substrate 1 side. Similarly, the width R2 of the second opening 20 in the second organic insulating film 19 is the distance in the X-axis direction Dx between the position where the inner circumferential surface of the second organic insulating film 19 that forms the second opening 20 contacts the first redistribution layer 18 on the semiconductor substrate 1 side.

[0036] Furthermore, the width in the X-axis direction Dx of the bump 21 provided on the second organic insulating film 19 is larger than the width R1 of the first opening 17 and the width R2 of the second opening 20. The bump 21 contacts the first redistribution layer 18 at the bottom of the second opening 20. As described above, the width R1 of the first opening 17 is formed larger than the width R2 of the second opening 20. In other words, the width in the X-axis direction Dx of the portion where the bump 21 and the first redistribution layer 18 contact each other in the second opening 20 (the width R2 of the second opening 20) is smaller than the width R1 of the first opening 17.

[0037] The width of the bump 21 in the X-axis direction Dx on the second organic insulating film 19 is not particularly limited and can be changed as appropriate. For example, the width of the bump 21 in the X-axis direction Dx may be larger than the width R2 of the second opening 20 and smaller than the width R1 of the first opening 17.

[0038] As described above, the semiconductor device 100 of this embodiment includes a semiconductor substrate 1, at least one transistor BT provided on the semiconductor substrate 1 and including a plurality of semiconductor layers, an emitter wiring 11 (wiring) provided on the transistor BT, a first organic insulating film 16 (first insulating film) having a first opening 17 provided in a region overlapping with the transistor BT and the emitter wiring 11, a first rewiring layer 18 provided on the first organic insulating film 16, overlapping with at least one transistor BT in a planar view, and electrically connected to the emitter wiring 11 through the first opening 17, a second organic insulating film 19 (second insulating film) provided to cover the first rewiring layer 18 and the first organic insulating film 16, and having a second opening 20 provided in a region overlapping with at least a portion of the first rewiring layer 18, and a bump 21 electrically connected to the first rewiring layer 18 through the second opening 20. The width R1 of the first opening 17 of the first organic insulating film 16 in the X-axis direction Dx parallel to the semiconductor substrate 1 is larger than the width R2 of the second opening 20 of the second organic insulating film 19 in the X-axis direction Dx.

[0039] As a result, in the semiconductor device 100, the bumps 21 are provided to cover the entire area of ​​the mesa structures of the multiple transistors BT, thereby improving heat dissipation. Furthermore, thermal stress generated when the semiconductor device 100 is mounted on an external substrate such as a printed wiring board is applied to the mesa structures of the multiple transistors BT from the bumps 21. In this embodiment, the width R1 of the first opening 17 of the first organic insulating film 16 in the X-axis direction Dx is greater than the width R2 of the second opening 20 of the second organic insulating film 19 in the X-axis direction Dx. Therefore, even if stress is concentrated on the outer edge side of the bump 21 (the portion of the bump 21 in contact with the inner circumferential surface of the second organic insulating film 19), the stress transmitted from the bump 21 to the first redistribution layer 18 is dispersed in the region overlapping with the first opening 17 of the first redistribution layer 18. That is, stress concentration on the outer edge side of the first redistribution layer 18 (the portion of the first redistribution layer 18 in contact with the inner circumferential surface of the first organic insulating film 16) is suppressed. As a result, in this embodiment, the thermal stress applied from the bump 21 to the mesa structure of the transistor BT via the first redistribution layer 18 can be suppressed.

[0040] FIG. 3 is a table illustrating the relationship between opening width and the occurrence of defects in semiconductor devices according to the example and comparative example. As shown in FIG. 3, comparative examples 1 and 2 are semiconductor devices configured such that the width R1 of the first opening 17 is smaller than the width R2 of the second opening 20. Specifically, in the semiconductor device of comparative example 1, the width R1 of the first opening 17 is 49 μm and the width R2 of the second opening 20 is 69 μm. In the semiconductor device of comparative example 2, the width R1 of the first opening 17 is 61 μm and the width R2 of the second opening 20 is 69 μm. In the semiconductor device 100 of the example, the width R1 of the first opening 17 is 73 μm and the width R2 of the second opening 20 is 69 μm.

[0041] In both the semiconductor devices of Comparative Examples 1 and 2, cracks occurred in the mesa structure of the transistor BT. More specifically, in Comparative Examples 1 and 2, the width R1 of the first opening 17 was smaller than the width R2 of the second opening 20, i.e., the outer edge of the bump 21 provided in the second opening 20 (the portion of the bump 21 that contacts the inner circumferential surface of the second organic insulating film 19) was located outside the first opening 17. Stress from the bump 21 reaches the mesa structure of the transistor BT mainly through hard materials. That is, because the Young's modulus of the first organic insulating film 16 and the second organic insulating film 19 is smaller than that of the metal material such as the first redistribution layer 18, most of the thermal stress is concentrated at the wiring locations of the first redistribution layer 18 and the emitter wiring 11 and transmitted to the mesa structure of the transistor BT. For this reason, the stress from the bump 21 is concentrated on the outer edge side of the bump 21 (the portion of the bump 21 in contact with the inner circumferential surface of the second organic insulating film 19), and further concentrated on the outer edge side of the first redistribution layer 18 (the portion of the first redistribution layer 18 in contact with the inner circumferential surface of the first organic insulating film 16), and is transmitted to the transistor BT side. As a result, in Comparative Examples 1 and 2, thermal stress is concentrated on a part of the mesa structure of the transistor BT, causing cracks to occur in the mesa structure of the transistor BT.

[0042] In the semiconductor device 100 of the example, no cracks occur in the mesa structure of the transistor BT. The semiconductor device 100 of the example is configured such that the width R1 of the first opening 17 is larger than the width R2 of the second opening 20, and as described above, the stress transmitted from the bump 21 to the first redistribution layer 18 is dispersed in the region of the first redistribution layer 18 that overlaps with the first opening 17. In this way, the semiconductor device 100 of the example suppresses the concentration of stress as described in Comparative Examples 1 and 2, and it has been shown that the occurrence of cracks in the mesa structure of the transistor BT can be suppressed.

[0043] (Second embodiment) 4 is a cross-sectional view of a semiconductor device according to a second embodiment. As shown in FIG. 4, the second embodiment differs from the first embodiment in that it has a configuration having a superimposed organic insulating film 12 provided between a collector electrode 8, an emitter wiring 11, and a first redistribution layer 18 in a direction perpendicular to a semiconductor substrate 1. Note that the configurations of the plurality of transistors BT, the first opening 17 in the first organic insulating film 16, the second opening 20 in the second organic insulating film 19, and the like are the same as those in the first embodiment, and therefore repeated description will be omitted.

[0044] In the semiconductor device 100A according to the second embodiment, the superimposed organic insulating film 12 is provided so as to overlap the collector electrode 8 of the transistor BT. On the collector electrode 8, an inorganic insulating film 9, the superimposed organic insulating film 12, the emitter wiring 11, and the first rewiring layer 18 are stacked in this order. In this embodiment, the presence of the superimposed organic insulating film 12 ensures insulation between the collector and the emitter.

[0045] The overlaid organic insulating film 12 is provided in a region that does not overlap, in plan view, with the mesa structure formed by the collector layer 3, the base layer 4, and the emitter layer 5. In this case, focusing on the emitter wiring 11 and the overlaid organic insulating film 12, the overlaid organic insulating film 12 has a smaller Young's modulus than the emitter wiring 11, so most of the thermal stress is concentrated in the part of the emitter wiring 11 where the overlaid organic insulating film 12 is not provided, and there is a possibility that a larger stress will be transmitted to the mesa structure of the transistor BT.

[0046] In this embodiment as well, the width R1 of the first opening 17 of the first organic insulating film 16 in the X-axis direction Dx is larger than the width R2 of the second opening 20 of the second organic insulating film 19 in the X-axis direction Dx. This prevents the concentration of stress transmitted from the bump 21 to the emitter wiring 11 via the first redistribution layer 18. Therefore, even in a configuration in which the overlaid organic insulating film 12 is provided on the collector electrode 8, it is possible to prevent the concentration of stress in the mesa structure of the transistor BT and to prevent cracks from occurring.

[0047] The shape, thickness, etc. of the superposed organic insulating film 12 shown in FIG. 4 are merely shown schematically, and can be changed as appropriate depending on the configuration of the collector electrode 8 and the emitter wiring 11 and the required insulating properties.

[0048] (Third embodiment) Fig. 5 is a cross-sectional view of a semiconductor device according to the third embodiment. As shown in Fig. 5, the third embodiment differs from the first and second embodiments in that the semiconductor device 100B has a third organic insulating film 26 and a second redistribution layer 28.

[0049] In the semiconductor device 100B of the third embodiment, a third organic insulating film 26 (third insulating film) is provided between the first organic insulating film 16 and the second organic insulating film 19, and a third opening 27 is provided in a region overlapping at least a portion of the first redistribution layer 18. The second redistribution layer 28 is provided on the third organic insulating film 26. More specifically, the second redistribution layer 28 is provided between the first redistribution layer 18 and the bumps 21, and is electrically connected to the first redistribution layer 18 through the third opening 27. Furthermore, the second organic insulating film 19 is provided on the third organic insulating film 26, covering the second redistribution layer 28. A second opening 20 in the second organic insulating film 19 is provided in a region overlapping at least a portion of the second redistribution layer 28.

[0050] The width R3 of the third opening 27 of the third organic insulating film 26 in the X-axis direction Dx is larger than the width R2 of the second opening 20 of the second organic insulating film 19 in the X-axis direction Dx. Furthermore, the width R3 of the third opening 27 of the third organic insulating film 26 in the X-axis direction Dx is larger than the width R1 of the first opening 17 of the first organic insulating film 16 in the X-axis direction Dx. Furthermore, as in the first and second embodiments, the width R1 of the first opening 17 of the first organic insulating film 16 in the X-axis direction Dx is larger than the width R2 of the second opening 20 of the second organic insulating film 19 in the X-axis direction Dx.

[0051] That is, in the direction perpendicular to the semiconductor substrate 1, the third opening 27 is arranged between the second opening 20 and the first opening 17, and the width R3 of the third opening 27 is larger than the width R1 of the first opening 17 and the width R2 of the second opening 20.

[0052] In the present embodiment, the stress transmitted from the bump 21 to the second redistribution layer 28 is dispersed in the region of the second redistribution layer 28 that overlaps with the second opening 20. That is, stress concentration is suppressed on the outer edge side of the second redistribution layer 28 (the portion of the second redistribution layer 28 that contacts the inner circumferential surface of the third organic insulating film 26). Furthermore, since stress concentration is suppressed on the outer edge side of the second redistribution layer 28, stress transmitted from the second redistribution layer 28 to the first redistribution layer 18 is dispersed in the region that overlaps with the first opening 17. That is, stress concentration is suppressed on the outer edge side of the first redistribution layer 18 (the portion of the first redistribution layer 18 that contacts the inner circumferential surface of the first organic insulating film 16). As a result, in the third embodiment as well, thermal stress applied from the bump 21 to the mesa structure of the transistor BT via the second redistribution layer 28 and the first redistribution layer 18 can be suppressed.

[0053] Thus, even in a configuration in which three or more layers of organic insulating films are provided covering the transistor BT and an opening is formed in each of them, by making the width R1 of the first opening 17 in the first organic insulating film 16 provided at a position closest to the transistor BT larger than the width R2 of the second opening 20 in the second organic insulating film 19 provided at a position farthest from the transistor BT in the direction perpendicular to the semiconductor substrate 1, it is possible to suppress the thermal stress applied to the mesa structure of the transistor BT from the bump 21. In other words, the width R3 of the third opening 27 in the second redistribution layer 28 is not limited to a configuration in which it is larger than the width R1 of the first opening 17 and the width R2 of the second opening 20, and the degree of freedom of the third opening 27 can be increased.

[0054] (Modification of the third embodiment) Fig. 6 is an explanatory diagram of a semiconductor device according to a modification of the third embodiment. As shown in Fig. 6, in the semiconductor device 100C according to the modification of the third embodiment, unlike the third embodiment, the width R3 of the third opening 27 is smaller than the width R1 of the first opening 17 and the width R2 of the second opening 20.

[0055] The width R3 of the third opening 27 of the third organic insulating film 26 in the X-axis direction Dx is smaller than the width R2 of the second opening 20 of the second organic insulating film 19 in the X-axis direction Dx. The width R3 of the third opening 27 of the third organic insulating film 26 in the X-axis direction Dx is also smaller than the width R1 of the first opening 17 of the first organic insulating film 16 in the X-axis direction Dx. As in the first and second embodiments, the width R1 of the first opening 17 of the first organic insulating film 16 in the X-axis direction Dx is larger than the width R2 of the second opening 20 of the second organic insulating film 19 in the X-axis direction Dx.

[0056] That is, in the direction perpendicular to the semiconductor substrate 1, the third opening 27 is arranged between the second opening 20 and the first opening 17, and the width R3 of the third opening 27 is smaller than the width R1 of the first opening 17 and the width R2 of the second opening 20.

[0057] In this embodiment, the stress transmitted from the bump 21 to the second redistribution layer 28 is concentrated on the outer edge side of the second redistribution layer 28 (the portion of the second redistribution layer 28 in contact with the inner circumferential surface of the third organic insulating film 26). Even if stress is concentrated on the outer edge side of the second redistribution layer 28 (the portion of the second redistribution layer 28 in contact with the inner circumferential surface of the third organic insulating film 26), the stress transmitted from the second redistribution layer 28 to the first redistribution layer 18 is dispersed in the region overlapping with the first opening 17. That is, even if the width R3 of the third opening 27 is small, stress concentration on the outer edge side of the first redistribution layer 18 (the portion of the first redistribution layer 18 in contact with the inner circumferential surface of the first organic insulating film 16) is suppressed. As a result, in this modification as well, the thermal stress applied from the bump 21 to the mesa structure of the transistor BT via the second redistribution layer 28 and the first redistribution layer 18 can be suppressed.

[0058] The width R3 of the third opening 27 is not limited to being smaller than the width R1 of the first opening 17 and the width R2 of the second opening 20, and may be a size between the width R1 of the first opening 17 and the width R2 of the second opening 20. In other words, the width R3 of the third opening 27 may be larger than the width R2 of the second opening 20, and the width R1 of the first opening 17 may be larger than the width R3 of the third opening 27.

[0059] (Method of manufacturing a semiconductor device) 7 is an explanatory diagram illustrating a manufacturing process of a semiconductor device. As shown in FIG. 7, a plurality of transistors BT and their respective insulating films are provided on a semiconductor substrate 1, and emitter wiring 11 is formed to cover the plurality of transistors BT and their respective insulating films (step ST11). The emitter wiring 11 is provided to cover the inorganic insulating film 9 and emitter openings 10, and contacts the emitter electrodes 6 of the plurality of transistors BT at the emitter openings 10. The emitter wiring 11 is made of a metal material having good conductivity.

[0060] Next, a first organic insulating film 16 is formed to cover the emitter wiring 11, and a first opening 17 is provided in a region overlapping with the emitter wiring 11 (step ST12). The first opening 17 is formed by patterning the first organic insulating film 16 by photolithography, etching, or the like.

[0061] Next, a first redistribution layer 18 is provided on the first organic insulating film 16 so as to cover the first opening 17 of the first organic insulating film 16 (step ST13). The first redistribution layer 18 contacts the emitter wiring 11 at the bottom of the first opening 17.

[0062] Next, a second organic insulating film 19 is formed to cover the first redistribution layer 18 and the first organic insulating film 16, and a second opening 20 is formed in a region of the second organic insulating film 19 that overlaps with a part of the first redistribution layer 18 (step ST14). The width of the second opening 20 in the second organic insulating film 19 is formed to be smaller than the width of the first opening 17 in the first organic insulating film 16.

[0063] Next, bumps 21 are formed on the second organic insulating film 19 and the first rewiring layer 18 (step ST15). The bumps 21 may be formed by any process, for example, plating. In this case, a power supply film (not shown) is provided on the second organic insulating film 19 and the first rewiring layer 18 as a base layer for the bumps 21.

[0064] 7 is merely an example and can be modified as appropriate. For example, the rewiring layer and the organic insulating film may be formed in multiple layers by repeating steps ST12 and ST13.

[0065] In addition, in each of the above-described embodiments, a semiconductor device in which one bump 21 is provided overlapping a plurality of transistors BT has been described as an example, but the present invention is not limited to this. A semiconductor device in which one bump is formed overlapping a single transistor may also be used. In addition, pillar bumps have been described as an example of bumps, but in addition to pillar bumps, for example, solder bumps or stud bumps may also be used.

[0066] The materials, thicknesses, dimensions, etc. of the components shown in the above-described embodiments are merely examples and may be changed as appropriate. The materials and thicknesses of the subcollector layer 2, collector layer 3, base layer 4, emitter layer 5, and various wirings may also be changed as appropriate.

[0067] The above-described embodiments are intended to facilitate understanding of the present invention and are not intended to limit the present invention. The present invention may be modified or improved without departing from the spirit and scope of the present invention, and equivalents thereof are also included in the present invention. [Explanation of symbols]

[0068] 1. Semiconductor substrate 2 Subcollector layer 3 Collector layer 4 Base Layer 5 Emitter layer 6 Emitter electrode 7 Base Electrode 8 Collector electrode 11 Emitter wiring 12 Overlaid organic insulating film 16 First organic insulating film 17 First Opening 18 1st redistribution layer 19 Second organic insulating film 20 Second Opening 21 Bump 26 Third organic insulating film 27 Third Opening 28 2nd redistribution layer 100, 100A, 100B, 100C Semiconductor device R1, R2, R3 width BT transistor

Claims

1. a semiconductor substrate; At least one transistor provided on the semiconductor substrate and including a plurality of semiconductor layers; a wiring provided on the transistor; a first insulating film having a first opening in a region overlapping the transistor and the wiring when viewed in a plan view in a first direction perpendicular to the semiconductor substrate; a first redistribution layer provided on the first insulating film, overlapping with at least one of the transistors in a plan view in the first direction, and electrically connected to the wiring through the first opening; a second insulating film provided to cover the first redistribution layer and the first insulating film, the second insulating film having a second opening in a region overlapping at least a portion of the first redistribution layer in a plan view in the first direction; a bump electrically connected to the first redistribution layer through the second opening, The width of the first opening in the first insulating film in a second direction parallel to the semiconductor substrate is larger than the width of the second opening in the second insulating film in the second direction. Semiconductor device.

2. 2. The semiconductor device according to claim 1, the transistor has a collector electrode connected to a collector layer; a collector electrode, and a first rewiring layer provided on the transistor; and an organic insulating film provided between the collector electrode and the first rewiring layer in the first direction. Semiconductor device.

3. 3. The semiconductor device according to claim 1, a third insulating film provided between the first insulating film and the second insulating film, the third insulating film having a third opening in a region overlapping at least a portion of the first redistribution layer in a plan view in the first direction; a second redistribution layer provided between the first redistribution layer and the bump and electrically connected to the first redistribution layer through the third opening; Semiconductor device.

4. 3. The semiconductor device according to claim 1, a plurality of the transistors arranged side by side in the second direction; The bump and the first opening of the first insulating film are provided across a plurality of the transistors. Semiconductor device.

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