Semiconductor device, protection circuit, and method for manufacturing the semiconductor device

Abstract

To provide a semiconductor device having high dimensional controllability, a protection circuit and a manufacturing method of the protection circuit.SOLUTION: A semiconductor device comprises: a first semiconductor layer; a second semiconductor layer; a third semiconductor layer; a gate electrode; a fourth semiconductor layer; and an insulation layer. The first semiconductor layer has first impurity concentration, and has a first conductivity type. The second semiconductor layer is provided on the first semiconductor layer, has second impurity concentration, and has a second conductivity type being different from the first conductivity type. The third semiconductor layer is provided on the first semiconductor layer, is provided by being arranged with the second semiconductor layer in a first direction, and has the second conductivity type. The gate electrode is provided between the second semiconductor layer and the third semiconductor layer, and provided through a gate insulation film above the first semiconductor layer. The fourth semiconductor layer is provided on the first semiconductor layer, has one end contacting with the second semiconductor layer, has third impurity concentration being lower than the second impurity concentration of the second semiconductor layer, and has the second conductivity type. The insulation layer is provided on the fourth semiconductor layer, and has one end contacting with the second semiconductor layer.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device, a protection circuit, and a method for manufacturing a semiconductor device. [Background technology]

[0002] A protection circuit for protecting an electronic device from a surge such as electrostatic discharge may include a transistor that performs a switching operation to prevent the surge from being input to the electronic device, and a protective resistor that protects the transistor. A known method for forming such a protective resistor is to use a silicide block. However, this conventional method has the problem of making it difficult to control the dimensions of the protective resistor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-123742 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of embodiments of the present invention is to provide a protection circuit with high dimensional controllability and a method for manufacturing the protection circuit. [Means for solving the problem]

[0005] A semiconductor device according to one embodiment of the present invention includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a gate electrode, a fourth semiconductor layer, and an insulating layer. The first semiconductor layer has a first impurity concentration and is of a first conductivity type. The second semiconductor layer is provided on the first semiconductor layer, has a second impurity concentration, and is of a second conductivity type different from the first conductivity type. The third semiconductor layer is provided on the first semiconductor layer, is arranged alongside the second semiconductor layer in a first direction, and is of the second conductivity type. The gate electrode is provided between the second semiconductor layer and the third semiconductor layer, and is provided above the first semiconductor layer via a gate insulating film. The fourth semiconductor layer is provided on the first semiconductor layer, has one end in contact with the second semiconductor layer, has a third impurity concentration lower than the second impurity concentration of the second semiconductor layer, and is of the second conductivity type. The insulating layer is provided on the fourth semiconductor layer and has one end in contact with the second semiconductor layer. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 2 is a diagram showing an example of a usage form of a protection circuit according to an embodiment. [Figure 2] FIG. 2 is a top view illustrating an example of the configuration of a protection circuit according to the embodiment. [Figure 3] 3 is a cross-sectional view of the protection circuit of the embodiment taken along line AA in FIG. 2. [Figure 4] 3 is a cross-sectional view of the protection circuit of the embodiment taken along line BB in FIG. 2. [Figure 5] 3 is a cross-sectional view taken along the line BB in FIG. 2, illustrating an example of a manufacturing method for the protection circuit according to the embodiment. [Figure 6] 3 is a cross-sectional view taken along the line CC in FIG. 2, illustrating an example of a manufacturing method for the protection circuit according DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the present invention is not limited to the embodiments. Furthermore, components in the embodiments include those that can be easily imagined by a person skilled in the art or those that are substantially the same.

[0008] Fig. 1 is a diagram showing an example of a usage form of a protection circuit 1 according to an embodiment. The protection circuit 1 according to this embodiment protects a predetermined electronic device (e.g., a processor, a memory, etc.) from surges such as electrostatic discharge (ESD). In the configuration shown in Fig. 1, a plurality of protection circuits 1 (four in this example) are connected in parallel between a ground electrode and a conductor 10 through which an external current flows, which is connected to the electronic device to be protected.

[0009] Each protection circuit 1 includes a transistor 11 and a protective resistor 12. The transistor 11 is a switching element that operates in response to the magnitude of a surge voltage or surge current, and operates to guide the surge current to a ground electrode when the surge current or surge voltage exceeds a threshold. The protective resistor 12 is a resistor connected between the conductor 10 and the transistor 11, and has the effect of preventing damage to the transistor 11 due to the surge current. In addition, each of the multiple protection circuits 1 is provided with a protective resistor 12, and each protective resistor 12 exhibits a buffering effect that attenuates the surge current, thereby preventing the surge current from concentrating on one protection circuit 1 (transistor 11).

[0010] 1 illustrates an example in which transistor 11 is an N-channel MOSFET, but the configuration of transistor 11 is not limited to this. When transistor 11 is an N-channel MOSFET, the drain of transistor 11 is connected to protective resistor 12, the source is connected to a ground electrode, and a ground voltage is input to the gate. In the following, an example in which transistor 11 is an N-channel MOSFET will be described.

[0011] 2 is a top view showing an example of the configuration of a protection circuit 1 according to an embodiment. FIG. 3 is a cross-sectional view of the protection circuit 1 according to an embodiment taken along line AA in FIG. 2. FIG. 4 is a cross-sectional view of the protection circuit 1 according to an embodiment taken along line BB in FIG. 2. In the figure, the X direction corresponds to the left-right direction of the paper (the arrangement direction of the transistor 11 and the protective resistor 12), the Y direction corresponds to the direction perpendicular to the paper (the width direction of the transistor 11 or the protective resistor 12), and the Z direction corresponds to the direction perpendicular to the XY plane (the stacking direction). The X direction is an example of a first direction, the Y direction is an example of a second direction, and the Z direction is an example of a third direction.

[0012] 2 and 3, the protection circuit 1 includes a transistor 11, a protection resistor 12, a first contact 21, a second contact 22, a first insulating portion 25, and a second insulating portion 26. The first contact 21 is connected to the above-mentioned conductive wire 10, and the second contact 22 is connected to a ground electrode.

[0013] The transistor 11 illustrated here is an N-channel MOSFET, and includes, as shown in FIG. 3, a gate electrode 31, an oxide insulating film 32, insulating portions 33 and 34, a drain electrode 41, a source electrode 42 (an example of a first region), a P-type semiconductor layer 55 (an example of a first semiconductor layer), an N-type diffusion layer 56 (an example of a second semiconductor layer or diffusion layer), and an N-type diffusion layer 57 (an example of a third semiconductor layer).

[0014] The P-type semiconductor layer 55 is a region that becomes an inversion layer in response to the voltage input to the gate electrode 31, and contains impurities such as B at a predetermined concentration. The N-type diffusion layer 56 in contact with the drain electrode 41 is in contact with a resistance layer 63 of the protective resistor 12, which will be described later. The N-type diffusion layer 57 in contact with the source electrode 42 is connected to a ground electrode via a second contact 22.

[0015] As shown in FIGS. 2 to 4 , the protective resistor 12 includes a groove 61, an insulating layer 62, a resistive layer 63 (an example of a fourth semiconductor layer), a semiconductor layer 65 (an example of a fifth semiconductor layer), and a silicide layer 66. The silicide layer 66 (an example of a second region) is in contact with the first contact 21 and the semiconductor layer 65. The first contact 21, the silicide layer 66, and the semiconductor layer 65 form an input section 70 that guides an external current flowing through the conductive wire 10 ( FIG. 1 ) into the protection circuit 1. The semiconductor layer 65 may be the same semiconductor layer as the N-type diffusion layer 57, or may be a different semiconductor layer from the N-type diffusion layer 57. The semiconductor layer 65 may also be a conductive layer having a higher electrical conductivity than the N-type diffusion layer 57.

[0016] The trench 61 is formed in the N-type diffusion layer 56 so as to separate the input section 70 and the transistor 11. That is, the trench 61 forms a structure similar to so-called STI (Shallow Trench Isolation). An insulating layer 62 and a resistive layer 63 are formed inside the trench 61 of this embodiment. As shown in FIG. 4, the trench 61 of this embodiment has an inverted trapezoidal cross section along the YZ plane. That is, the width Wt of the opening of the trench 61 is larger than the width Wb of the bottom 71 of the trench 61.

[0017] The insulating layer 62 is made of an insulating material, and may be made of, for example, SiO2, SiN, or the like as a main component.

[0018] The resistive layer 63 is a region having a predetermined resistance value (electrical conductivity). The resistance value of the resistive layer 63 is set to a value that can protect the transistor 11 from a surge current input from the input unit 70. In this embodiment, the resistance value of the resistive layer 63 is higher than that of the N-type diffusion layer 56 and lower than that of the insulating layer 62.

[0019] In this embodiment, the resistance layer 63 and the N-type diffusion layer 56 contain impurities (e.g., B) contained in the P-type semiconductor layer 55, and the impurity concentration of the resistance layer 63 is lower than the impurity concentration of the N-type diffusion layer 56. Such adjustment of the impurity concentration can be performed with relatively high precision using a known ion implantation method or the like. The impurities contained in the resistance layer 63 are not limited to those described above, but vary depending on the configuration of the transistor 11. For example, if the transistor 11 is a P-channel MOSFET, impurities such as As and P contained in the N-type semiconductor layer will be contained in the resistance layer and diffusion layer.

[0020] Furthermore, the resistive layer 63 in this embodiment is formed on the bottom 71 of the groove 61. Forming the resistive layer 63 in such a position improves the manufacturability of the protective resistor 12 (protection circuit 1), but the position at which the resistive layer 63 is formed is not limited to this. For example, the resistive layer 63 may be formed on a side surface 72 of the groove 61 or in the center of the insulating layer 62.

[0021] As described above, by forming the protective resistor 12 using a structure similar to STI, the dimensional controllability of the protective resistor 12 can be improved compared to methods using silicide blocks, which require consideration of the amount of liquid seepage. This improved dimensional controllability also reduces excess design margins. Furthermore, since the protective resistor 12 has a structure including the resistive layer 63 with a lower impurity concentration than the N-type diffusion layer 56, a resistance value equivalent to that of a conventional protective resistor 12 can be achieved with a smaller capacitance (length in the X direction) than that of a conventional protective resistor. This allows the entire protection circuit 1 to be miniaturized.

[0022] A method for manufacturing the protection circuit 1 described above will now be described.

[0023] Fig. 5 is a cross-sectional view taken along line BB in Fig. 2, showing an example of a manufacturing method for the protection circuit 1 of the embodiment. Fig. 6 is a cross-sectional view taken along line CC in Fig. 2, showing an example of a manufacturing method for the protection circuit 1 of the embodiment. Figs. 5(A) to 5(E) illustrate changes in the YZ plane of the portion where the protective resistor 12 is formed as the manufacturing method of the embodiment progresses. Figs. 6(A) to 6(E) illustrate changes in the XZ plane of the portion where the protective resistor 12 is formed as the manufacturing method of the embodiment progresses.

[0024] First, as shown in Figures 5(A) and 6(A), an amorphous silicon layer 101 is formed on the upper surface of the P-type semiconductor layer 55, and a resist 102 is formed in a predetermined portion (a portion corresponding to the resist layer 63) on the amorphous silicon layer 101, after which RIE (Reactive Ion Etching) is performed. As a result, as shown in Figures 5(B) and 6(B), an amorphous silicon layer 101 having a thickness corresponding to the thickness of the resist 102 shown in Figures 5(A) and 6(B) remains on the P-type semiconductor layer 55. The amorphous silicon layer 101 is, for example, a first layer.

[0025] 5(B) and 6(B), a SiN layer 105 is formed on the P-type semiconductor layer 55 on which the amorphous silicon layer 101 remains, and a resist 103 is formed on the outer edge of the SiN layer 105, followed by RIE. At this time, the resist 102 shown in FIG. 5(B) corresponds to the outer region of the trench 61 in the Y direction, and the resist 102 shown in FIG. 6(B) corresponds to the outer region (the N-type diffusion layer 56 and the semiconductor layer 65) of the trench 61 in the X direction. As a result, as shown in FIGS. 5(C) and 6(C), a trench 61 having a depth corresponding to the thickness of the resist 102 shown in FIGS. 5(B) and 6(B) is formed. Due to the nature of the RIE process, the trench 61 is more difficult to etch as the distance (depth) from the top surface increases, so the trench 61 naturally assumes an inverted trapezoidal shape. 5(B) and 6(B), the P-type semiconductor layer 55 is not etched by the thickness of the amorphous silicon layer 101, and therefore a convex portion 110 formed by the P-type semiconductor layer 55 being pushed upward is formed at the bottom of the groove portion 61. The convex portion 111 has a structure formed by the first portion being protruded by a second portion that is located deeper than the first portion.

[0026] Thereafter, as shown in FIG. 5(C) and FIG. 6(C), the inside of the groove 61 is filled with NSG (Non-doped Silicate Glass) or the like to form an insulating layer 62.

[0027] 5(D) and 6(D), a resist 104 is formed on the outer edge of the insulating layer 62, and ion implantation is performed to implant an ionized substance (e.g., BF3 gas, etc.) obtained by ionizing an impurity (e.g., B, etc.) into the convex portion 110. At this time, the ion implantation is performed so that the impurity concentration in the convex portion 110 is lower than the impurity concentration in the N-type diffusion layer 56.

[0028] By the above process, a resistive layer 63 having a lower impurity concentration than the N-type diffusion layer 56 is formed at the bottom of the groove 61, as shown in FIGS. 5(E) and 6(E).

[0029] After the insulating layer 62 and the resistive layer 63 are formed as described above, a semiconductor layer 65 and a silicide layer 66 are formed using an appropriate semiconductor manufacturing process, thereby forming the protective resistor 12. Thereafter, a transistor 11 is formed using an appropriate semiconductor manufacturing process. The transistor 11 may be formed simultaneously with the semiconductor layer 65 and the silicide layer 66.

[0030] As described above, the manufacturing method of this embodiment includes the steps of forming a groove 61 in the N-type diffusion layer 56 that separates the input section 70 and the transistor 11, forming a convex portion 110 at the bottom of the groove 61, and forming a resistive layer 63 by implanting ions into the convex portion 110. This allows the dimensions of the protective resistor 12 to be controlled with high precision, thereby reducing excess design margins. Furthermore, because the protective resistor 12 can be formed to include the resistive layer 63 with a lower impurity concentration than the N-type diffusion layer 56, a resistance value equivalent to that of a conventional resistor can be achieved with a protective resistor 12 having a smaller capacitance (length in the X direction) than that of a conventional resistor. This allows the entire protection circuit 1 to be miniaturized.

[0031] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, or modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0032] 1...protection circuit, 10...conductor, 11...transistor, 12...protection resistor, 21...first contact, 22...second contact, 25...first insulating portion, 26...second insulating portion, 31...gate electrode, 32...oxide insulating film, 33, 34...insulating portion, 41...drain electrode, 42...source electrode, 55...p-type semiconductor layer, 56, 57...n-type diffusion layer, 61...groove portion, 62...insulating layer, 63...resist layer, 65...semiconductor layer, 66...silicide layer, 70...input portion, 71...bottom portion, 72...side portion, 101...amorphous silicon layer, 102 to 104...resist, 105...SiN layer, 110...convex portion

Claims

1. a first semiconductor layer of a first conductivity type having a first impurity concentration; a second semiconductor layer provided on the first semiconductor layer, having a second impurity concentration and of a second conductivity type different from the first conductivity type; a third semiconductor layer of the second conductivity type provided on the first semiconductor layer and arranged side by side with the second semiconductor layer in a first direction; a gate electrode provided between the second semiconductor layer and the third semiconductor layer and above the first semiconductor layer via a gate insulating film; a fourth semiconductor layer of the second conductivity type provided on the first semiconductor layer, having one end in contact with the second semiconductor layer, and having a third impurity concentration lower than the second impurity concentration of the second semiconductor layer; an insulating layer provided on the fourth semiconductor layer and having one end in contact with the second semiconductor layer; the gate electrode has a gate length extending in the first direction and a gate width extending in a second direction intersecting the first direction, a width of the insulating layer in the second direction that increases with increasing distance from a side closer to the fourth semiconductor layer in a third direction that intersects with the first direction and the second direction; Semiconductor device.

2. The semiconductor device according to claim 1 , further comprising a fifth semiconductor layer in contact with the other end of the fourth semiconductor layer and in contact with the other end of the insulating layer.

3. a first region provided on the third semiconductor layer; a first contact in contact with the first region; a second region provided on the fifth semiconductor layer; The semiconductor device according to claim 2 , further comprising a second contact in contact with the second region.

4. The semiconductor device according to claim 3 , wherein the other end of the insulating layer is in contact with the second region.

5. The gate electrode has a first surface including an interface between the first semiconductor layer and the gate insulating film, 2. The semiconductor device according to claim 1, wherein in a third direction intersecting the first direction and the second direction, a first distance from the fourth semiconductor layer to the first surface is greater than a second distance from the interface to the gate electrode.

6. The insulating layer has a first portion in contact with the fourth semiconductor layer and a second portion that is positioned differently from the fourth semiconductor layer in a third direction that intersects with the first direction and the second direction, The semiconductor device according to claim 1 , wherein the width of the first portion in the second direction is narrower than the width of the second portion in the second direction.

7. the insulating layer has a first portion in contact with the fourth semiconductor layer and a second portion that is positioned differently from the fourth semiconductor layer in a third direction that intersects with the first direction and the second direction, The semiconductor device according to claim 5 , wherein a distance from the first portion to the first surface in the third direction is greater than a distance from the second portion to the first surface in the third direction.

8. A transistor, a protective resistor connected between an input section to which an external current is input and the transistor; Equipped with The protective resistor is a groove formed in a diffusion layer of the transistor so as to separate the input section from the transistor; an insulating layer formed inside the groove; a resistive layer formed inside the groove and having a resistance higher than that of the diffusion layer and lower than that of the insulating layer; Including, protection circuit.

9. forming a first layer on the first semiconductor layer; forming a first resist on a portion of the first layer; Etching the exposed portion of the first layer; forming a second layer on the first semiconductor layer and the first layer; forming a second resist on a portion of the second layer; etching the exposed second layer, etching the exposed first semiconductor layer and the first layer; further etching the first semiconductor layer exposed by etching the first layer to form a first portion and a second portion deeper than the first portion in the first semiconductor layer; forming an insulating layer on the first portion and the second portion; forming a third resist on a portion of the insulating layer; Ion implantation is performed from the exposed insulating layer toward the first portion to form a second semiconductor layer. A method for manufacturing a semiconductor device.

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