Semiconductor Devices

Abstract

To provide a semiconductor device capable of appropriately adjusting the switching speed of an output stage element.SOLUTION: A semiconductor device according to an embodiment includes a first transistor, a first drive circuit including a second transistor, and a second drive circuit including a third transistor. The second transistor and the third transistor are connected in series, and the connection node is connected to a gate electrode of the first transistor. The first transistor, the second transistor, and the third transistor are normally-off MOS HEMTs formed on a first substrate containing GaN. The first drive circuit charges the parasitic capacitance of the first transistor. The second drive circuit discharges the parasitic capacitance of the first transistor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] Nitride semiconductor devices having heterojunctions of nitride semiconductors such as GaN can achieve higher breakdown voltage, lower resistance, and higher speed operation than semiconductor devices using Si.

[0003] It is desirable that the circuit that drives such a high-speed switching element be formed on the same chip as the output stage element in order to suppress the effects of parasitic inductance of wiring, etc. However, if the output stage element and the drive circuit are formed on the same chip, it may be difficult to apply the technology in practice if the turn-on and turn-off times of the output stage element cannot be adjusted. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 5285103 [Patent Document 2] Patent No. 5791193 [Patent Document 3] Patent No. 4954290 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the embodiments is to provide a semiconductor device capable of appropriately adjusting the switching speed of an output stage element. [Means for solving the problem]

[0006] A semiconductor device according to an embodiment includes: a first transistor including a first drain electrode connected to a drain electrode pad and a first source electrode connected to a source electrode pad; a first drive circuit including a second transistor connected between a first electrode pad connected to the first source electrode pad and receiving a first reference voltage; and a second electrode pad receiving a second voltage higher than the first voltage, the second transistor having a second drain electrode electrically connected to the second electrode pad and a second source electrode connected to a first gate electrode of the first transistor; and a second drive circuit including a third transistor connected between the second transistor and the first electrode, the third drain electrode connected to the first gate electrode, and a third source electrode connected to the source electrode pad. The first, second, and third transistors are formed on a first substrate including GaN. The first drive circuit charges parasitic capacitance of the first transistor. The second drive circuit discharges parasitic capacitance of the first transistor. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a circuit diagram illustrating a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a schematic view illustrating the semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a circuit diagram illustrating the semiconductor device according to the second embodiment. [Figure 4] FIG. 4 is a circuit diagram illustrating a semiconductor device according to the third embodiment. [Figure 5] FIG. 5 is a schematic view illustrating a semiconductor device according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In the present specification and the drawings, elements similar to those described above with reference to the previous drawings are given the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0009] (First embodiment) FIG. 1 is a circuit diagram illustrating a semiconductor device according to the first embodiment. 1, the semiconductor device 100 according to this embodiment includes a first transistor 10, a second transistor 20, a third transistor 30, a fourth transistor 40, and a fifth transistor 50. The third transistor 30 and the fifth transistor 50 form a current mirror. A resistor 72 having an adjustable resistance value is connected to the current mirror. The first transistor 10, the second transistor 20, the third transistor 30, the fourth transistor 40, and the fifth transistor 50 each include a nitride semiconductor and are n-channel.

[0010] The first transistor 10, the second transistor 20, the third transistor 30, the fourth transistor 40, and the fifth transistor 50 are all normally-off HEMTs. A normally-off HEMT has a threshold voltage that is a positive voltage value relative to the source electrode. In a normally-off HEMT, when a voltage exceeding the threshold is applied between the gate and source, a channel formed between the drain and source electrodes becomes conductive and current flows. In a normally-off HEMT, when a voltage equal to or less than the threshold voltage is applied between the gate and source, the channel between the drain and source electrodes disappears, and current flow between the drain and source electrodes is cut off.

[0011] The first transistor 10, the second transistor 20, the third transistor 30, the fourth transistor 40, and the fifth transistor 50 can be normally-off transistors by using a MOS (Metal-Oxide Semiconductor) structure. In a HEMT with a MOS structure, for example, a drain electrode and a source electrode are provided on an AlGaN layer formed on an undoped GaN layer. A portion of the AlGaN layer is removed, and an oxide film is provided on top of it, with a gate electrode provided via the oxide film. A channel is formed under the gate electrode.

[0012] The semiconductor device 100 includes a drain electrode pad 101 and a source electrode pad 102. A drain electrode (first drain electrode) 10d of the first transistor 10 is connected to the drain electrode pad 101. A source electrode (first source electrode) 10s of the first transistor 10 is connected to the source electrode pad 102. The source electrode pad 102 is electrically connected to a ground electrode pad (first electrode pad) 104. The ground electrode pad 104 is connected to ground, and a voltage (first voltage) applied to ground 1 is used as a reference voltage for the semiconductor device 100. In other words, the voltages of each component of the semiconductor device 100 are voltages based on the voltage of ground 1. The drain electrode 10d of the first transistor 10 is connected to an external circuit via the drain electrode pad 101. The source electrode 10s is connected to the external circuit via the source electrode pad 102. The external circuit is, for example, a load circuit of the first transistor 10. The load circuit of the first transistor 10 is, for example, a primary winding of a transformer.

[0013] The second transistor 20 is connected between the power supply electrode pad 103 and the source electrode pad 102. The source electrode (second source electrode) of the second transistor 20 is connected to the gate electrode 10g of the first transistor 10. The third transistor 30 is connected between the second transistor 20 and the source electrode pad 102. The drain electrode (third drain electrode) 30d of the third transistor 30 is connected to the gate electrode 10g of the first transistor 10. In other words, the connection node N1 between the second transistor 20 and the third transistor 30 is connected to the gate electrode 10g of the first transistor 10.

[0014] The second transistor 20 is turned on and the third transistor 30 is turned off, thereby turning on the first transistor 10. The second transistor 20 is turned off and the third transistor 30 is turned on, thereby turning off the first transistor 10.

[0015] The first transistor 10 is an output stage element of the semiconductor device 100. The second transistor 20 and the third transistor 30 are drive transistors that drive the first transistor 10.

[0016] The fourth transistor 40 is connected between the power supply electrode pad 103 and the ground electrode pad 104. A source electrode 40s of the fourth transistor 40 is connected to the ground electrode pad 104. A drain electrode 40d of the fourth transistor 40 is connected to the power supply electrode pad 103 via a resistor 65. A gate electrode 20g of the second transistor 20 is connected to a connection node N2 between the drain electrode 40d of the fourth transistor 40 and the resistor 65.

[0017] The gate of the fourth transistor 40 is connected to the output of the control circuit 82. When the signal D1 output from the control circuit 82 is at a high level, the fourth transistor 40 is turned on. When the signal D1 output from the control circuit 82 is at a low level, the fourth transistor 40 is turned off.

[0018] Resistor 65 is a pull-up resistor for second transistor 20. When fourth transistor 40 is turned on and the voltage at connection node N2 becomes lower than the threshold voltage of second transistor 20, second transistor 20 is turned off. When fourth transistor 40 is turned off and the voltage at connection node N2 becomes equal to or higher than the threshold voltage of second transistor 20, second transistor 20 is turned on.

[0019] The fifth transistor 50 is connected between the power supply electrode pad 103 and the source electrode pad 102. A series circuit of a sixth transistor 71 and a resistor 72 is connected between the power supply electrode pad 103 and the fifth transistor 50. A drain electrode 50d of the fifth transistor 50 is connected to the resistor 72, and a source electrode 50s of the fifth transistor 50 is connected to the source electrode pad 102.

[0020] The fifth transistor 50 and the third transistor 30 form a current mirror circuit. The source electrode and gate electrode of the fifth transistor 50 are connected to the source electrode and gate electrode of the third transistor 30, respectively. The gate electrode and drain electrode of the fifth transistor 50 are connected to each other.

[0021] By setting the ratio of the transistor sizes of the third transistor 30 and the fifth transistor 50, the current flowing between the drain and source of the third transistor 30 can be set to a current value obtained by multiplying the current flowing between the drain and source of the fifth transistor 50 by the ratio of the gate widths. The transistor size is expressed as the gate width W (W / L) of each transistor relative to the gate length L. When the gate length L is constant, the ratio of the transistor sizes of the two transistors is the ratio of the gate widths W of the two transistors.

[0022] The sixth transistor 71 is, for example, a PNP transistor formed by a Si bipolar process. The sixth transistor 71 is not limited to a bipolar transistor, and may be a pch MOSFET formed by a Si process.

[0023] The third transistor 30, the fifth transistor 50, the sixth transistor 71, and the resistor 72 constitute a gate discharge circuit (second drive circuit) 70. The gate discharge circuit 70 sets a gate discharge current (second drive current) Ig2 to be output to the gate electrode 10g of the first transistor 10. The gate discharge current Ig2 flows from the gate electrode 10g of the first transistor 10 to the drain electrode 30d of the third transistor 30. When the power supply voltage Vdd is constant, the current value of the gate discharge current Ig2 can be set by setting the resistance value of the resistor 72. The current value of the gate discharge current Ig2 can be adjusted by adjusting the resistance value of the resistor 72.

[0024] The seventh transistor 61 is connected between the power supply electrode pad 103 and the second transistor 20. The emitter electrode of the seventh transistor 61 is connected to the power supply electrode pad 103. The collector electrode of the seventh transistor 61 is connected to the drain electrode 20d of the second transistor 20.

[0025] The eighth transistor 62 is connected between the power supply electrode pad 103 and the ground electrode pad 104. A constant current source 63 is connected between the eighth transistor 62 and the ground electrode pad 104. The emitter electrode of the eighth transistor 62 is connected to the power supply electrode pad 103.

[0026] The seventh transistor 61 and the eighth transistor 62 are both PNP transistors formed by, for example, a Si bipolar process. The seventh transistor 61 and the eighth transistor 62 are not limited to bipolar transistors, and may be p-channel MOSFETs formed by a Si process. The constant current source 63 is also formed by the same Si process as the seventh transistor 61 and the eighth transistor 62.

[0027] The seventh transistor 61 and the eighth transistor 62 form a current mirror circuit. The emitter electrode and base electrode of the seventh transistor 61 are connected to the emitter electrode and base electrode of the eighth transistor 62, respectively. The emitter electrode of the eighth transistor 62 is connected to the base electrode. The constant current source 63 is connected between the collector electrode of the eighth transistor 62 and the source electrode pad 102. Therefore, the seventh transistor 61 outputs a current obtained by multiplying the ratio of the emitter area of ​​the seventh transistor 61 to the emitter area of ​​the eighth transistor 62 by the output current value of the constant current source 63. The current output from the seventh transistor 61 is output by the second transistor 20 as a gate charging current (first drive current) Ig1. The gate charging current Ig1 flows from the source electrode 20s of the second transistor 20 to the gate electrode 10g of the first transistor 10.

[0028] The constant current source 63 is, for example, a series circuit of a bandgap circuit and a resistor, and the output current value can be set by setting the resistance value of the resistor. The second transistor 20, the seventh transistor 61, the eighth transistor 62, and the constant current source 63 constitute a gate charging circuit (first drive circuit) 60. In the gate charging circuit 60, the current value of the gate charging current Ig1 output by the second transistor 20 can be adjusted by adjusting the current value output by the constant current source 63.

[0029] In this example, the input of the control circuit 82 is connected to one input electrode pad 105. In this example, the output of the control circuit 82 is connected to the gate electrode of the fourth transistor 40 and the input of the inverter circuit 81. The control circuit 82 may have any appropriate circuit function, such as a level shift function, as in this example. In this case, the control circuit 82 converts the voltage level between the input electrode pad 105 and the ground electrode pad 104 into a voltage level that drives the fourth transistor 40 and the sixth transistor 71, and outputs the converted voltage. The control circuit 82 may also be a PWM control circuit, etc.

[0030] The operation of the semiconductor device 100 according to this embodiment will be described. The first transistor 10 switches by turning on and off the second transistor 20 and the third transistor 30, which are drive transistors. A power supply voltage Vdd sufficiently higher than the thresholds of the first transistor 10, the second transistor 20, the third transistor 30, the fourth transistor 40, and the fifth transistor 50 is applied between the power supply electrode pad 103 and the ground electrode pad 104. The power supply voltage Vdd is, for example, +15 V. A signal D1, which is an output signal of the control circuit 82, has a high-level voltage value and a low-level voltage value. The high-level voltage value of the signal D1 is sufficiently higher than the threshold value of the fourth transistor 40, and the low-level voltage value is sufficiently lower than the threshold value of the fourth transistor 40.

[0031] First, the operation when the first transistor 10 is turned on will be described. The control circuit 82 outputs a low-level signal D1. The low-level voltage value of the signal D1 turns off the fourth transistor 40. With the fourth transistor 40 turned off, the connection node N2 is pulled up to the power supply voltage Vdd via the resistor 65.

[0032] When the connection node N2 is raised to the power supply voltage Vdd, which is higher than the threshold voltage of the second transistor 20, the second transistor 20 is turned on.

[0033] The drain electrode 20d of the second transistor 20 is connected to the collector electrode of the seventh transistor 61, which is the output of the current mirror. Therefore, the second transistor 20 outputs a gate charging current Ig1 having a current value obtained by multiplying the current value output by the constant current source 63 by the ratio of the emitter areas of the seventh transistor 61 and the eighth transistor 62.

[0034] The gate charging current Ig1 output by the second transistor 20 charges the parasitic capacitance, including the Miller capacitance, of the first transistor 10. Charging the parasitic capacitance turns on the first transistor 10. The current value of the gate charging current Ig1 determines the charging time of the parasitic capacitance of the first transistor 10, and therefore the turn-on time of the first transistor 10.

[0035] On the other hand, the sixth transistor 71 is turned off by the signal D1. Therefore, no current flows through the resistor 72, and the gate discharge circuit 70 is cut off. In other words, the gate discharge current Ig2 output by the third transistor 30 is almost zero. Therefore, the first transistor 10 is maintained in the on state.

[0036] Next, the operation when the first transistor 10 is turned off will be described. The control circuit 82 outputs a high-level signal D1. The high-level voltage of the signal D1 turns on the fourth transistor 40. With the fourth transistor 40 on, the voltage at the connection node N2 is approximately equal to the ground potential. Therefore, the second transistor 20 is off, and the gate charging current Ig1 output by the second transistor 20 is approximately zero.

[0037] The sixth transistor 71 is turned on by the high-level signal D1 from the control circuit 82. Therefore, the current flowing through the fifth transistor 50 is determined by the power supply voltage Vdd and the resistance value of the resistor 72, and the current output by the third transistor 30 that forms the current mirror is also determined. In other words, when the sixth transistor 71 is turned on, the gate discharge circuit 70 outputs a gate discharge current Ig2 having a current value proportional to the current value determined by the power supply voltage Vdd and the resistance value of the resistor 72.

[0038] The third transistor 30 outputs a gate discharge current Ig2 to discharge the parasitic capacitance including the Miller capacitance of the gate of the first transistor 10. Due to the discharge of the parasitic capacitance of the first transistor 10, the gate-source voltage decreases, and the first transistor 10 is turned off.

[0039] In this way, the first transistor 10 is turned on by the gate charging current Ig1 having a current value set by the gate charging circuit 60. The first transistor 10 is turned off by the gate discharging current Ig2 having a current value set by the gate discharging circuit 70.

[0040] A specific example of the configuration of the semiconductor device 100 according to this embodiment will be described. FIG. 2 is a schematic view illustrating the semiconductor device according to the first embodiment. 2, the semiconductor device 100 has an output circuit 110 and a control circuit 120. The output circuit 110 includes a first transistor 10, a second transistor 20, a third transistor 30, a fourth transistor 40, and a fifth transistor 50.

[0041] As described above, the first transistor 10, the second transistor 20, the third transistor 30, the fourth transistor 40 and the fifth transistor 50 include nitride semiconductors and are formed on, for example, the same GaN substrate.

[0042] The control circuit 120 includes a sixth transistor 71, a seventh transistor 61, an eighth transistor 62, a constant current source 63, a resistor 72, a resistor 65, an inverter circuit 81, and a control circuit 82. The sixth transistor 71, the seventh transistor 61, the eighth transistor 62, the constant current source 63, the resistor 72, the resistor 65, the inverter circuit 81, and the control circuit 82 are formed on, for example, the same Si substrate.

[0043] As described above, the semiconductor device 100 according to this embodiment includes an output circuit 110 formed on a GaN substrate and a control circuit 120 formed on a Si substrate. The output circuit 110 includes a drain electrode pad 101 and a source electrode pad 102 on the GaN substrate. The output circuit 110 also includes a first interconnect pad 111, a second interconnect pad 112, a third interconnect pad 113, and a fourth interconnect pad 114 on the GaN substrate.

[0044] The first interconnect pad 111 is connected to the drain of the second transistor 20 by wiring formed on the GaN substrate. The second interconnect pad 112 is connected to the gate of the second transistor 20 and the drain of the fourth transistor 40 by wiring formed on the GaN substrate. The third interconnect pad 113 is connected to the drain of the fifth transistor 50 by wiring formed on the GaN substrate. The fourth interconnect pad 114 is connected to the gate of the fourth transistor 40 by wiring formed on the GaN substrate.

[0045] The control circuit 120 has a power supply electrode pad 103, a ground electrode pad 104, an input electrode pad 105 formed on a Si substrate, as well as a fifth interconnect pad 121, a sixth interconnect pad 122, a seventh interconnect pad 123, and an eighth interconnect pad 124.

[0046] The fifth interconnection pad 121 is connected to the collector of the seventh transistor 61 by a wiring formed on the Si substrate. The sixth interconnection pad 122 is connected to the constant current source 63 by a wiring formed on the Si substrate. The seventh interconnection pad 123 is connected to the resistor 65 by a wiring formed on the Si substrate. The eighth interconnection pad 124 is connected to the output of the control circuit 82 and the input of the inverter circuit 81 by wiring formed on the Si substrate.

[0047] The first interconnect pad 111 and the fifth interconnect pad 121 are interconnected by a first interconnect wire (first connection wire) 131. The second interconnect pad 112 and the sixth interconnect pad 122 are interconnected by a second interconnect wire 132. The third interconnect pad 113 and the seventh interconnect pad 123 are interconnected by a third interconnect wire 133. The fourth interconnect pad 114 and the eighth interconnect pad 124 are interconnected by a fourth interconnect wire 134.

[0048] The first interconnect wire 131, the second interconnect wire 132, the third interconnect wire 133, and the fourth interconnect wire 134 are conductive members containing Au, Cu, or the like. The semiconductor device 100 is formed by interconnecting the output circuit 110 and the control circuit 120 with the first interconnect wire 131, the second interconnect wire 132, the third interconnect wire 133, and the fourth interconnect wire 134. The semiconductor device 100 has, for example, the output circuit 110 and the control circuit 120 housed in the same package.

[0049] The effects of the semiconductor device 100 according to this embodiment will be described. In the semiconductor device 100 according to this embodiment, the gate charging current Ig1 for turning on the first transistor 10 can be set by setting the current value of the gate charging circuit 60. The gate charging current Ig1 is a current that charges the parasitic capacitance between the gate and source of the first transistor 10. Therefore, by adjusting the current value of the gate charging current Ig1 in the gate charging circuit 60, the turn-on time of the first transistor 10 can be adjusted.

[0050] In the semiconductor device 100 according to this embodiment, the gate discharge current Ig2 for turning off the first transistor 10 can be set by setting the current value of the gate discharge circuit 70. The gate discharge current Ig2 is a current that discharges the parasitic capacitance between the gate and source of the first transistor 10. Therefore, by adjusting the current value of the gate discharge current Ig2 with the gate discharge circuit 70, the turn-off time of the first transistor 10 can be adjusted.

[0051] In semiconductor devices including an output stage, it is often desirable to have fast turn-on and turn-off times for the transistors constituting the output stage, as this reduces switching loss. However, fast turn-on and turn-off times can result in steep rises and falls in the drain-source voltage, potentially resulting in excessive surge voltages or reverse voltages being applied between the drain and source. Fast turn-on and turn-off times can also result in large temporal changes in the drain current, which can cause conduction noise, radiation noise, and other issues. Therefore, it is often desirable to adjust the turn-on and turn-off times of the transistors in the output stage while considering factors such as the magnitude of switching loss and the occurrence of surge voltages.

[0052] In the semiconductor device 100 according to this embodiment, the output current value of the drive circuit can be adjusted to adjust the turn-on time and turn-off time of the first transistor 10. This reduces the magnitude of switching loss in the semiconductor device 100 and suppresses the occurrence of surges, noise, and the like.

[0053] In the semiconductor device 100 of this embodiment, the first transistor 10 to the fifth transistor 50 are formed on the same substrate containing GaN. This allows the physical distance between the first transistor 10, which is the output stage element, and the second transistor 20 and the third transistor 30, which constitute the drive circuit, to be minimized. This allows for sufficiently fast turn-on and turn-off times to be achieved while suppressing waveform vibrations and oscillations caused by the parasitic inductance of the wiring connecting these elements.

[0054] (Second embodiment) FIG. 3 is a circuit diagram illustrating the semiconductor device according to the second embodiment. 3, the semiconductor device 200 according to this embodiment includes a first transistor 10, a first drive circuit 220, and a second drive circuit 230. The first transistor 10 has the same configuration as the first transistor 10 in the first embodiment, and is therefore denoted by the same reference numeral, with detailed description thereof being omitted where appropriate.

[0055] The drain electrode 10d of the first transistor 10 is connected to a drain electrode pad 201. The source electrode 10s of the first transistor 10 is connected to a source electrode pad 202. The source electrode pad 202 is connected to a ground electrode pad 204, and is connected to the ground together with the ground electrode pad 204. The drain electrode pad 201 and the source electrode pad 202 are connected to an external circuit such as a primary winding of a transformer.

[0056] The first drive circuit 220 includes a first drive transistor (second transistor) 221, a second drive transistor 222, and a third drive transistor 223. The first drive transistor 221, the second drive transistor 222, and the third drive transistor 223 are connected in parallel. That is, the drain electrodes 221d to 223d of these three drive transistors are connected to each other, and the source electrodes 221s to 223s of these three drive transistors are connected to each other.

[0057] The drain electrodes 221d to 223d of the three drive transistors are connected to the power supply electrode pad 203. The source electrodes 221s to 223s of the three drive transistors are connected to the gate electrode 10g of the first transistor 10. A power supply voltage Vdd is applied between the power supply electrode pad 203 and the ground electrode pad 204. The power supply voltage Vdd is a positive DC voltage based on the voltage applied to the ground 1 to which the ground electrode pad 204 is connected.

[0058] The second drive circuit 230 includes a fourth drive transistor 231, a fifth drive transistor 232, and a sixth drive transistor 233. The fourth drive transistor 231, the fifth drive transistor 232, and the sixth drive transistor 233 are connected in parallel. That is, the drain electrodes 231d to 233d of these three drive transistors are connected to each other, and the source electrodes 231s to 233s of these three drive transistors are connected to each other.

[0059] The drain electrodes 231d to 233d of the three drive transistors are connected to the gate electrode 10g of the first transistor 10. The source electrodes 231s to 233s of the three drive transistors are connected to the source electrode pad 202. That is, the first drive circuit 220 and the second drive circuit 230 are connected in series between the power supply electrode pad 203 and the ground electrode pad 204. A connection node N1 between the first drive circuit 220 and the second drive circuit 230 is connected to the gate electrode 10g of the first transistor 10.

[0060] For example, the first drive transistor 221, the second drive transistor 222, and the third drive transistor 223 have approximately the same transistor size, and therefore the drive capabilities of the first drive transistor 221, the second drive transistor 222, and the third drive transistor 223 are approximately the same.

[0061] For example, the fourth drive transistor 231, the fifth drive transistor 232, and the sixth drive transistor 233 have approximately the same transistor size, and therefore the drive capabilities of the fourth drive transistor 231, the fifth drive transistor 232, and the sixth drive transistor 233 are approximately the same.

[0062] "The driving capabilities of multiple driving transistors are the same" means that when the same drain-source voltage and the same gate-source voltage are applied to each of the multiple driving transistors, the magnitude of the current flowing between the drain and source is the same. The first driving transistor 221, the second driving transistor 222, and the third driving transistor 223 are connected in parallel. Therefore, when the same gate-source voltage is applied to each driving transistor, the current flowing between the drain and source of each driving transistor is approximately the same. Furthermore, the fourth driving transistor 231, the fifth driving transistor 232, and the sixth driving transistor 233 are connected in parallel. Therefore, when the same gate-source voltage is applied to each driving transistor, the current flowing between the drain and source of each driving transistor is approximately the same.

[0063] The transistor sizes of the first drive transistor 221 to the sixth drive transistor 233 can be approximately the same, but without being limited to this, for example, the transistor sizes of the plurality of drive transistors constituting the first drive circuit 220 and the transistor sizes of the plurality of drive transistors constituting the second drive circuit 230 may be different.

[0064] In the above description, the number of drive transistors constituting the first drive circuit 220 is three, but it may be one, two, or four or more. The number of drive transistors constituting the second drive circuit 230 is also not limited to three, and may be one, two, or four or more.

[0065] In the above description, the first drive circuit 220 includes three drive transistors, and the second drive circuit 230 includes three drive transistors, the same number as the number of drive transistors in the first drive circuit, but this is not limited to this. The number of drive transistors in the first drive circuit 220 and the number of drive transistors in the second drive circuit 230 may be different.

[0066] Furthermore, the transistor sizes of the multiple drive transistors in the first drive circuit 220 do not all have to be the same. For example, the ratio of the transistor sizes of the first drive transistor 221, the second drive transistor 222, and the third drive transistor 223 may be 1:2:4.

[0067] The transistor sizes of the plurality of driving transistors in the second driving circuit 230 may be different from one another.

[0068] Like the first transistor, the first driving transistor 221 to the sixth driving transistor 233 include a nitride semiconductor and are n-channel normally-off MOS HEMTs. For example, the first transistor 10 and the first driving transistor 221 to the sixth driving transistor 233 are formed on the same GaN substrate.

[0069] An input of the first control circuit 281 is connected to a first input electrode pad 205. A control signal is input to the first control circuit 281 via the first input electrode pad 205. In this example, the first control circuit 281 is connected to a ground electrode pad 204. The ground electrode pad 204 is connected to a ground 1 to which a reference voltage is applied, and is connected to the source electrode pad 202 via the ground 1. The ground electrode pad 204 is also connected to a ground 1 of the second control circuit 282.

[0070] The output of the first control circuit 281 is connected to the gate electrode 221g of the first drive transistor 221, the gate electrode 222g of the second drive transistor 222, and the gate electrode 223g of the third drive transistor 223. The first control circuit 281 drives the gate electrode of at least one of the first drive transistor 221, the second drive transistor 222, and the third drive transistor 223, for example, in response to a control signal.

[0071] The first control circuit 281 selectively drives the gate electrode 221g of the first drive transistor 221, the gate electrode 222g of the second drive transistor 222, and the gate electrode 223g of the third drive transistor 223. For example, the first control circuit 281 drives the gate electrode 221g of the first drive transistor 221, but does not drive the gate electrodes of the other drive transistors. For example, the first control circuit 281 simultaneously drives the gate electrode 221g of the first drive transistor 221 and the gate electrode 222g of the second drive transistor 222, but does not drive the gate electrodes of the other drive transistors. For example, the first control circuit 281 simultaneously drives the gate electrodes 221g to 223g of all the drive transistors.

[0072] The input of the second control circuit 282 is connected to the second input electrode pad 206. A control signal is input to the second control circuit 282 via the second input electrode pad 206.

[0073] The output of the second control circuit 282 is connected to the gate electrode 231g of the fourth drive transistor 231, the gate electrode 232g of the fifth drive transistor 232, and the gate electrode 233g of the sixth drive transistor 233. The second control circuit 282 selectively drives the gate electrode 231g of the fourth drive transistor 231, the gate electrode 232g of the fifth drive transistor 232, and the gate electrode 233g of the sixth drive transistor 233. For example, the second control circuit 282 drives the gate electrode 231g of the fourth drive transistor 231, but does not drive the gates of the other drive transistors. For example, the second control circuit 282 simultaneously drives the gate electrode 231g of the fourth drive transistor 231 and the gate electrode 232g of the fifth drive transistor 232, but does not drive the gates of the other drive transistors. For example, the second control circuit 282 simultaneously drives the gate electrodes 231g to 233g of all drive transistors.

[0074] For example, first control circuit 281 and second control circuit 282 generate complementary drive signals based on control signals input to first control circuit 281 and second control circuit 282, respectively. Generating complementary drive signals means, for example, that when first control circuit 281 generates a high-level drive signal, second control circuit 282 generates a low-level drive signal. Also, when second control circuit 282 generates a high-level drive signal, first control circuit 281 generates a low-level drive signal.

[0075] In the first drive circuit 220 and the second drive circuit 230, the gate electrode of the drive transistor to be driven is set in advance, for example. Alternatively, the gate electrode of the drive transistor to be driven in the first drive circuit 220 and the second drive circuit 230 can be selected and adjusted. In the first drive circuit 220 and the second drive circuit 230, the selection of the gate electrode of the drive transistor to be driven may be switched, for example, depending on the operation mode of the semiconductor device 200. The operation mode of the semiconductor device 200 refers to an operation mode when the load of the power conversion device including the semiconductor device 200 is light, an operation mode when the load is heavy, etc.

[0076] The operation of the semiconductor device 200 according to this embodiment will be described. First, the operation when the first transistor 10 is turned on will be described. The first control circuit 281 generates a high-level drive signal. The first control circuit 281 selects a required number of drive transistors from the plurality of drive transistors, and simultaneously drives the gate electrodes of the selected drive transistors.

[0077] The first drive circuit 220 outputs a gate charging current Ig1 according to the number of selected drive transistors, and the gate charging current Ig1 charges parasitic capacitance including the Miller capacitance between the gate and source of the first transistor 10. The output of the gate charging current Ig1 increases the gate-source voltage of the first transistor 10, and when this voltage exceeds the threshold value of the first transistor 10, the first transistor 10 turns on.

[0078] At this time, the second control circuit 282 generates a low-level drive signal. Therefore, the output of the second drive circuit 230 is at high impedance. Therefore, the voltage of the connection node N1 is determined by the output of the first drive circuit 220. The first transistor 10 continues to be on.

[0079] The operation when the first transistor 10 is turned off will be described. The second control circuit 282 generates a high-level drive signal. The second control circuit 282 selects a required number of drive transistors from the plurality of drive transistors and simultaneously drives the gate electrodes of the selected drive transistors.

[0080] The second drive circuit 230 outputs a gate discharge current Ig2 according to the number of selected drive transistors, and the gate discharge current Ig2 discharges parasitic capacitance including the Miller capacitance between the gate and source of the first transistor 10. The output of the gate discharge current Ig2 reduces the gate-source voltage of the first transistor 10 and makes it fall below the threshold value of the first transistor 10, turning the first transistor 10 off.

[0081] At this time, the first control circuit 281 generates a low-level drive signal. Therefore, the output of the first drive circuit 220 is at high impedance. Therefore, the voltage of the connection node N1 is determined by the output of the second drive circuit 230. The first transistor 10 continues to be off.

[0082] The first control circuit 281 selects necessary drive transistors from the multiple drive transistors of the first drive circuit 220, and sets the current value of the gate charging current Ig1 according to the number of selected drive transistors. By setting the current value of the gate charging current Ig1, the turn-on time of the first transistor 10 can be set appropriately.

[0083] The second control circuit 282 selects necessary drive transistors from the multiple drive transistors of the second drive circuit 230, and sets the current value of the gate discharge current Ig2 according to the number of selected drive transistors. By setting the current value of the gate discharge current Ig2, the turn-off time of the second transistor 10 can be set appropriately.

[0084] The effects of the semiconductor device 200 according to this embodiment will be described. The semiconductor device 200 according to this embodiment includes a first drive circuit 220 that turns on the first transistor 10. The first drive circuit 220 includes multiple drive transistors connected in parallel. A first control circuit 281 selectively drives one or more of the multiple drive transistors simultaneously. The gate charging current Ig1 can be adjusted based on the total drive capacity of the selected drive transistors. The gate charging current Ig1 serves as a charging current for the parasitic capacitance required to turn on the first transistor 10. The larger the gate charging current Ig1, the shorter the turn-on time of the first transistor 10. The smaller the gate charging current Ig1, the longer the turn-on time of the first transistor 10. Therefore, the first control circuit 281 can adjust the value of the output gate charging current Ig1 by selecting drive transistors to be simultaneously driven from the multiple drive transistors. Therefore, the first transistor 10 turns on at the desired turn-on time.

[0085] The semiconductor device 200 according to this embodiment includes a second drive circuit 230 that turns off the first transistor 10. The second drive circuit 230 includes multiple drive transistors connected in parallel. The second control circuit 282 selectively drives one or more of the multiple drive transistors simultaneously. The current value of the gate discharge current Ig2 can be adjusted based on the drive capability of the selected drive transistor. The gate discharge current Ig2 is a discharge current for turning off the first transistor 10. The larger the current value of the gate discharge current Ig2, the shorter the turn-off time of the first transistor 10. The smaller the current value of the gate discharge current Ig2, the longer the turn-off time of the first transistor 10. Therefore, the second control circuit 282 can adjust the current value of the output gate discharge current Ig2 by selecting drive transistors to be driven simultaneously from the multiple drive transistors. Therefore, the first transistor 10 turns off at the desired turn-off time.

[0086] Although shortening both the turn-on time and the turn-off time of the first transistor 10 can reduce switching loss, this can also cause surge voltages, noise, etc., as explained in the first embodiment. In the semiconductor device 200 according to this embodiment, too, by adjusting the gate charge current Ig1 and the gate discharge current Ig2, it is possible to appropriately achieve both reduced switching loss and improvements to problems such as surge voltage generation.

[0087] In the semiconductor device 200 according to this embodiment, if it is possible to change the selection state of the drive transistor during operation of the semiconductor device 200, it is possible to change the gate charge current Ig1 and the gate discharge current Ig2, for example, according to the operation mode of the power conversion circuit to which the semiconductor device 200 is applied. Therefore, in each operation mode, it is possible to realize operation under optimal conditions that achieve both reduced switching loss and improvements to problems such as surge voltage generation.

[0088] In the semiconductor device 200 according to this embodiment, the first transistor 10, the first drive circuit 220, and the third drive circuit 230 can all have a transistor structure including nitride semiconductors. For example, the first transistor 10, the first drive circuit 220, and the third drive circuit 230 can be formed on the same GaN substrate, allowing the electrical connections between the transistors to be minimized. Therefore, the first drive circuit 220 and the second drive circuit 230 can output a sufficiently large gate charge current Ig1 and a gate discharge current Ig2 to the first transistor 10 while minimizing the effects of parasitic inductance of wiring and the like.

[0089] (Third embodiment) FIG. 4 is a circuit diagram illustrating a semiconductor device according to the third embodiment. As shown in FIG. 4, the semiconductor device 300 according to this embodiment includes a first transistor 10, a second transistor 20, a third transistor 30, a fourth transistor 40, and a resistor 360.

[0090] The first transistor 10 to the fourth transistor 40 can have the same configuration as in the first embodiment, and are formed on the same GaN substrate, for example. A drain electrode 10d of the first transistor 10 is connected to a drain electrode pad 301. A source electrode 10s of the first transistor 10 is connected to a source electrode pad 302. The drain electrode pad 301 and the source electrode pad 302 are connected to an external circuit such as a primary winding of a transformer.

[0091] In the semiconductor device 300 according to this embodiment, a first power supply electrode pad 303 is connected to the drain electrode 20d of the second transistor 20. A source electrode 20s of the second transistor 20 is connected to the gate electrode 10g of the first transistor 10.

[0092] The drain electrode 30d of the third transistor 30 is connected to the source electrode 20s of the second transistor 20 and the gate electrode 10g of the first transistor 10. In other words, the connection node N1 between the second transistor 20 and the third transistor 30 is connected to the gate electrode 10g of the first transistor 10.

[0093] A drain electrode 40d of the fourth transistor 40 is connected to the second power supply electrode pad 304 via a resistor 365. A source electrode 40s of the fourth transistor 40 is connected to the source electrode pad 302. A gate electrode 40g of the fourth transistor 40 and a gate electrode 30g of the third transistor 30 are connected to a gate electrode pad 305.

[0094] The semiconductor device 300 includes a third power supply electrode pad 306, and the resistor 360 is connected between the first power supply electrode pad 303 and the third power supply electrode pad 306. The semiconductor device 300 is provided with a wiring 371 that connects the second power supply electrode pad 304 and the third power supply electrode pad 306. The wiring 371 is connected to a power supply line 372. A power supply voltage Vdd, which is a positive DC voltage with respect to the voltage applied to the source electrode pad 302, is applied between the power supply line 372 and the source electrode pad 302.

[0095] FIG. 5 is a schematic view illustrating a semiconductor device according to the third embodiment. As shown in FIG. 5, the semiconductor device 300 according to this embodiment is formed on a substrate 311, for example. The output circuit 310 includes a first transistor 10, a second transistor 20, a third transistor 30, a fourth transistor 40, and a resistor 365. The output circuit 310 is disposed on a substrate 311 that has good heat dissipation properties and contains, for example, AlN. On the substrate 311, a drain external connection pad 321, a source external connection pad 322, a first power supply external connection pad 323, a second power supply external connection pad 324, and a gate external connection pad 325 are formed.

[0096] In the output circuit 310, the drain electrode pad 301 and the drain external connection pad 321 are connected to each other by a drain connection wire 341. The source electrode pad 302 and the source external connection pad 322 are connected to each other by a source connection wire 342. The first power supply electrode pad 303 and the first power supply external connection pad 323 are connected to each other by a first power supply connection wire 343. The second power supply electrode pad 304 and the second power supply external connection pad 324 are connected to each other by a second power supply connection wire 344. The gate electrode pad 305 and the gate external connection pad 325 are connected to each other by a gate connection wire 345. Each connection wire is made of a conductive material including Au, Cu, etc.

[0097] The output circuit 310 is disposed on a substrate 312, which is separate from the substrate 311, via the substrate 311, for example. A wiring 371 is formed on the substrate 312, and a third power supply electrode pad 306 is formed on a part of the wiring 371. The resistor 360 is disposed between the first power supply external connection pad 323 and the third power supply electrode pad 306 and is electrically connected to them. Although not shown, the wiring 371 is connected to a power supply line on the substrate 312. A power supply voltage Vdd is applied between the power supply line and the source electrode pad 302.

[0098] The resistor 360 may be, for example, a chip resistor, which may be detachable. The resistor 360 may be, for example, a chip resistor having an appropriate resistance value, which may be connected while checking the operation of the semiconductor device 300.

[0099] The operation of the semiconductor device 300 according to this embodiment will be described. As in the first embodiment, the first transistor 10 is an output stage element, and the second transistor 20 and the third transistor 30 form a drive circuit that drives the first transistor 10.

[0100] The operation when the first transistor 10 is turned on will be described. A drive signal is input between the gate electrode pad 305 and the source electrode pad 302. The drive signal has a high-level voltage and a low-level voltage. When the low-level voltage of the drive signal is input to the gate electrode pad 305, the fourth transistor 40 is turned off. With the fourth transistor 40 turned off, the gate electrode 20g of the second transistor 20 is pulled up to the power supply voltage Vdd via the resistor 365, the second power supply electrode pad 304, the wiring 371, and the power supply line 372. As a result, the second transistor 20 is turned on.

[0101] When the second transistor 20 is turned on, a gate charging current Ig1 flows through the second transistor 20 via the power supply line 372, the third power supply electrode pad 306, the resistor 360, and the first power supply electrode pad 303. The magnitude of the gate charging current Ig1 is determined by the voltage across the resistor 360 and the resistance value of the resistor 360. Therefore, when the power supply voltage Vdd is kept constant, the gate charging current Ig1 can be adjusted by adjusting the resistance value of the resistor 360. As in the other embodiments described above, the turn-on time of the first transistor 10 can be adjusted by adjusting the gate charging current Ig1.

[0102] In the above state, the third transistor 30 is off, and the voltage of the connection node N1 is determined by the voltage of the source of the second transistor 20.

[0103] Next, the operation when the first transistor 10 is off will be described. When a high-level voltage of the drive signal is input to the gate electrode pad 305, the fourth transistor 40 turns on. When the fourth transistor 40 turns on, the voltage at the connection node N2 between the resistor 365 and the drain electrode 40d of the fourth transistor 40 drops, and the voltage at the gate of the second transistor 20 is pulled down. As a result, the second transistor 20 turns off.

[0104] When the third transistor 30 is turned on by the high-level voltage of the drive signal, the third transistor 30 discharges the gate-source capacitance and the Miller capacitance of the first transistor 10. At this time, the discharge current is determined by the drive capability of the third transistor 30.

[0105] In this way, the first transistor 10 can perform a switching operation.

[0106] The effects of the semiconductor device 300 according to this embodiment will be described. The semiconductor device 300 of this embodiment can adjust the gate charging current Ig1 when the second transistor 20, which turns on the first transistor 10, is turned on by adjusting the voltage across the resistor 360 and the resistance value of the resistor 360.

[0107] According to the embodiment described above, it is possible to realize a semiconductor device that can appropriately adjust the switching speed of the nitride semiconductor output stage element.

[0108] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other. [Explanation of symbols]

[0109] 100, 200, 300...semiconductor device, 10...first transistor, 20...second transistor, 30...third transistor, 40...fourth transistor, 50...fifth transistor, 60...gate charging circuit, 70...gate discharging circuit, 72...resistor, 82...control circuit, 220...first driving circuit, 230...second driving circuit, 281...first control circuit, 282...second control circuit, 360, 365...resistor

Claims

1. a first transistor including a first drain electrode connected to the drain electrode pad and a first source electrode connected to the source electrode pad; a first driving circuit including a second transistor connected between a first electrode pad connected to the source electrode pad and receiving a first reference voltage and a second electrode pad receiving a second voltage higher than the first voltage, the second transistor having a second drain electrode electrically connected to the second electrode pad and a second source electrode connected to a first gate electrode of the first transistor; a second driving circuit including a third transistor connected between the second transistor and the source electrode pad, the third transistor having a third drain electrode connected to the first gate electrode and a third source electrode connected to the source electrode pad; Equipped with the first transistor, the second transistor, and the third transistor are formed on a first substrate including GaN; the first driving circuit charges a parasitic capacitance of the first transistor and outputs a first driving current, the current value of which is settable, to the first gate electrode; The second drive circuit discharges a parasitic capacitance of the first transistor and outputs a second drive current, the current value of which is settable, to the first gate electrode.

2. the first driving circuit includes a fourth transistor connected between a second gate electrode of the second transistor and the first electrode pad; The second drive circuit a fifth transistor provided to form a current mirror with the third transistor; a constant current source that outputs a current having a variably set current value to the fifth transistor; The semiconductor device according to claim 1 , comprising:

3. The first drive circuit a sixth transistor connected to the second drain electrode; a seventh transistor provided to form a current mirror with the sixth transistor; a constant current circuit that outputs a current having a variably set current value to the seventh transistor; 3. The semiconductor device according to claim 2, comprising:

4. the fifth transistor is formed on the first substrate; The semiconductor device according to claim 3 , wherein the sixth transistor and the seventh transistor are formed on a second substrate containing Si.

5. the first drive circuit includes a plurality of the second transistors connected in parallel; 2. The semiconductor device according to claim 1, further comprising a first control circuit that selectively drives one or more of the second transistors.

6. the second driving circuit includes a plurality of the third transistors connected in parallel, 2. The semiconductor device according to claim 1, further comprising a second control circuit that selectively drives one or more of the third transistors.

7. 7. The semiconductor device according to claim 1, wherein the first transistor, the second transistor, and the third transistor are normally-off MOS type HEMTs.

8. 5. The semiconductor device according to claim 4, wherein the second transistor is connected to the sixth transistor via a first connecting wire.

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