Indication device

Abstract

To provide a display device capable of suppressing a decrease in reliability.SOLUTION: A display device includes: an organic insulating layer; a barrier layer formed of an inorganic insulating material and disposed on the organic insulating layer; a rib formed of an inorganic insulating material and disposed on the barrier layer; a partition including a lower portion located directly above the barrier layer and disposed on the rib and an upper portion disposed on the lower portion and protruding from a side surface of the lower portion; a lower electrode having an end portion between the organic insulating layer and the rib; an organic layer including a light-emitting layer that has a first portion disposed on the lower electrode in an aperture of the rib and separated from the lower portion of the partition and a second portion disposed on the upper portion, the first portion and the second portion being formed of the same material; and an upper electrode disposed on the first portion of the organic layer and having a first portion in contact with the lower portion of the partition and a second portion disposed on the second portion of the organic layer.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device.

Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. Such a display element includes a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. The organic layer includes functional layers such as a hole transport layer and an electron transport layer in addition to a light-emitting layer. In the process of manufacturing such a display element, a technique for suppressing a decrease in reliability is required.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

[0006] [Figure 1] Figure 1 shows an example of the configuration of a display device DSP. [Figure 2] Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3. [Figure 3] Figure 3 is a schematic cross-sectional view of the DSP display device along the line III-III in Figure 2. [Figure 4] Figure 4 is a plan view showing one example of the configuration of the barrier layer BL. [Figure 5] Figure 5 shows an example of the configuration of the display element 20. [Figure 6] Figure 6 is a flowchart illustrating an example of a manufacturing method for a display device DSP. [Figure 7] Figure 7 is a diagram illustrating step ST1. [Figure 8] Figure 8 is a diagram illustrating step ST21. [Figure 9] FIG. 9 is a diagram for explaining step ST22. [Figure 10] FIG. 10 is a diagram for explaining step ST23. [Figure 11] FIG. 11 is a diagram for explaining step ST23. [Figure 12] FIG. 12 is a diagram for explaining step ST24. [Figure 13] FIG. 13 is a plan view showing another configuration example of the barrier layer BL. [Figure 14] FIG. 14 is a cross-sectional view showing another configuration example of the display device. [Figure 15] FIG. 15 is a cross-sectional view showing another configuration example of the display device. [Figure 16] FIG. 16 is a cross-sectional view showing another configuration example of the display device.

MODE FOR CARRYING OUT THE INVENTION

[0007] An embodiment will be described with reference to the drawings. The disclosure is merely an example, and for those that can be easily conceived by those skilled in the art for appropriate modifications while maintaining the gist of the invention, they are naturally included in the scope of the present invention. Also, for the purpose of making the description clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual aspect, but it is merely an example and does not limit the interpretation of the present invention. Further, in this specification and each drawing, components that exhibit the same or similar functions as those described above with respect to the already presented drawings may be assigned the same reference numerals, and detailed descriptions may be appropriately omitted as needed.

[0008] Note that in the drawings, for ease of understanding as necessary, the X-axis, Y-axis, and Z-axis orthogonal to each other are described. The direction along the X-axis is referred to as the first direction, the direction along the Y-axis is referred to as the second direction, and the direction along the Z-axis is referred to as the third direction. Looking at various elements parallel to the third direction Z is called a plan view.

[0009] The display device according to this embodiment is an organic electroluminescence display device including an organic light emitting diode (OLED) as a display element, and can be mounted on a television, a personal computer, an in-vehicle device, a tablet terminal, a smartphone, a mobile phone terminal, or the like.

[0010] FIG. 1 is a diagram showing a configuration example of the display device DSP. The display device DSP has a display area DA for displaying an image and a peripheral area SA around the display area DA on an insulating substrate 10. The substrate 10 may be glass or a resin film having flexibility.

[0011] In this embodiment, the shape of the substrate 10 in a plan view is rectangular. However, the shape of the substrate 10 in a plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0012] The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. The pixel PX includes a plurality of sub-pixels SP. In one example, the pixel PX includes a red sub-pixel SP1, a green sub-pixel SP2, and a blue sub-pixel SP3. Note that the pixel PX may include sub-pixels SP of other colors such as white, together with or in place of the sub-pixels SP1, SP2, and SP3.

[0013] The sub-pixel SP includes a pixel circuit 1 and a display element 20 driven by the pixel circuit ｡ The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements formed of, for example, thin film transistors.

[0014] The gate electrode of the pixel switch 2 is connected to the scan line GL. One of the source and drain electrodes of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source and drain electrodes is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element 20.

[0015] Note that the configuration of the pixel circuit 1 is not limited to the example shown. For example, the pixel circuit 1 may include more thin-film transistors and capacitors.

[0016] The display element 20 is an organic light-emitting diode (OLED) as a light-emitting element, and is sometimes referred to as an organic EL element. For example, sub-pixel SP1 is equipped with a display element 20 that emits light in the red wavelength range, sub-pixel SP2 is equipped with a display element 20 that emits light in the green wavelength range, and sub-pixel SP3 is equipped with a display element 20 that emits light in the blue wavelength range.

[0017] Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3. In the example in Figure 2, sub-pixels SP1 and SP2 are aligned in the second direction Y. Furthermore, sub-pixels SP1 and SP2 are aligned with sub-pixel SP3 in the first direction X.

[0018] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP1 and SP2 are alternately arranged in the second direction Y, and columns in which multiple sub-pixels SP3 are repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0019] Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2. Another example is that the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged sequentially in the first direction X.

[0020] The display area DA has ribs 5 and partition walls 6. Ribs 5 have apertures AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively. In the example in Figure 2, aperture AP2 is larger than aperture AP1, and aperture AP3 is larger than aperture AP2.

[0021] The partition wall 6 overlaps with the rib 5 in a plan view. The partition wall 6 has a plurality of first partition walls 6x extending in the first direction X and a plurality of second partition walls 6y extending in the second direction Y. The plurality of first partition walls 6x are arranged between adjacent openings AP1 and AP2 in the second direction Y, and between two adjacent openings AP3 in the second direction Y. The second partition walls 6y are arranged between adjacent openings AP1 and AP3 in the first direction X, and between adjacent openings AP2 and AP3 in the first direction X.

[0022] In the example shown in Figure 2, the first partition wall 6x and the second partition wall 6y are connected to each other. As a result, the partition wall 6 as a whole is formed in a grid shape that surrounds the openings AP1, AP2, and AP3. The partition wall 6 can also be said to have openings in the sub-pixels SP1, SP2, and SP3, similar to the rib 5.

[0023] Sub-pixel SP1 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with aperture AP1. Sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with aperture AP2. Sub-pixel SP3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with aperture AP3.

[0024] In the example in Figure 2, the outlines of the lower electrodes LE1, LE2, and LE3 are shown by dotted lines, and the outlines of the organic layers OR1, OR2, OR3, and the upper electrodes UE1, UE2, and UE3 are shown by dashed lines. The periphery of each of the lower electrodes LE1, LE2, and LE3 overlaps with the rib 5. The outline of the upper electrode UE1 is almost identical to the outline of the organic layer OR1, and the periphery of both the upper electrode UE1 and the organic layer OR1 overlaps with the partition wall 6. The outline of the upper electrode UE2 is almost identical to the outline of the organic layer OR2, and the periphery of both the upper electrode UE2 and the organic layer OR2 overlaps with the partition wall 6. The outline of the upper electrode UE3 is almost identical to the outline of the organic layer OR3, and the periphery of both the upper electrode UE3 and the organic layer OR3 overlaps with the partition wall 6.

[0025] The lower electrode LE1, upper electrode UE1, and organic layer OR1 constitute the display element 20 of the sub-pixel SP1. The lower electrode LE2, upper electrode UE2, and organic layer OR2 constitute the display element 20 of the sub-pixel SP2. The lower electrode LE3, upper electrode UE3, and organic layer OR3 constitute the display element 20 of the sub-pixel SP3. The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anodes of the display element 20. The upper electrodes UE1, UE2, and UE3 correspond to the cathodes or common electrodes of the display element 20.

[0026] The lower electrode LE1 is connected to the pixel circuit 1 of the sub-pixel SP1 (see Figure 1) through the contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 of the sub-pixel SP2 through the contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the sub-pixel SP3 through the contact hole CH3.

[0027] Figure 3 is a schematic cross-sectional view of the DSP display device along the line III-III in Figure 2. A circuit layer 11 is placed on the substrate 10 described above. The circuit layer 11 includes various circuits and wiring, such as the pixel circuit 1, scan line GL, signal line SL, and power line PL shown in Figure 1. The circuit layer 11 is covered by an insulating layer 12. The insulating layer 12 functions as a planarizing film that flattens the irregularities caused by the circuit layer 11. A barrier layer BL is placed on top of the insulating layer 12. In the illustrated example, the barrier layer BL is in contact with the insulating layer 12 and covers almost the entire surface of the insulating layer 12.

[0028] The lower electrodes LE1, LE2, and LE3 are positioned on top of the barrier layer BL. The rib 5 is positioned on top of the barrier layer BL and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib 5. In other words, the ends of the lower electrodes LE1, LE2, and LE3 are positioned between the insulating layer 12 and the rib 5, and in the illustrated example, between the barrier layer BL and the rib 5. Between the lower electrodes LE1, LE2, and LE3 that are adjacent to each other, the barrier layer BL is covered by the rib 5. At positions overlapping with the openings AP1, AP2, and AP3 of the rib 5, the lower electrodes LE1, LE2, and LE3 are positioned on top of the barrier layer BL.

[0029] The partition wall 6 includes a lower part (stem) 61 located directly above the barrier layer BL and positioned on top of the rib 5, and an upper part (cap) 62 positioned on top of the lower part 61. The upper part 62 has a greater width than the lower part 61. As a result, in Figure 3, both ends of the upper part 62 protrude beyond the sides of the lower part 61. This shape of the partition wall 6 can also be described as overhanging.

[0030] Directly below the partition wall 6, the barrier layer BL is positioned between the insulating layer 12 and the rib 5. Furthermore, the barrier layer BL is positioned between the insulating layer 12 and the rib 5 between the side surface of the lower part 61 of the partition wall 6 and the respective ends of the lower electrodes LE1, LE2, and LE3.

[0031] The organic layer OR1 shown in Figure 2 includes a first portion OR1a and a second portion OR1b that are spaced apart from each other, as shown in Figure 3. The first portion OR1a contacts the lower electrode LE1 through the opening AP1, covers the lower electrode LE1, and overlaps a portion of the rib 5. The second portion OR1b is positioned on top of the upper portion 62. Furthermore, the upper electrode UE1 shown in Figure 2 includes a first portion UE1a and a second portion UE1b that are spaced apart from each other, as shown in Figure 3. The first portion UE1a faces the lower electrode LE1 and is positioned above the first portion OR1a. In addition, the first portion UE1a is in contact with the side surface of the lower part 61. The second portion UE1b is located above the partition wall 6 and is positioned above the second portion OR1b.

[0032] The organic layer OR2 shown in Figure 2 includes a first portion OR2a and a second portion OR2b that are spaced apart from each other, as shown in Figure 3. The first portion OR2a contacts the lower electrode LE2 through the opening AP2, covers the lower electrode LE2, and overlaps a portion of the rib 5. The second portion OR2b is positioned on top of the upper portion 62. Furthermore, the upper electrode UE2 shown in Figure 2 includes a first portion UE2a and a second portion UE2b that are spaced apart from each other, as shown in Figure 3. The first portion UE2a faces the lower electrode LE2 and is positioned above the first portion OR2a. In addition, the first portion UE2a is in contact with the side surface of the lower part 61. The second portion UE2b is located above the partition wall 6 and is positioned above the second portion OR2b.

[0033] The organic layer OR3 shown in Figure 2 includes a first portion OR3a and a second portion OR3b that are spaced apart from each other, as shown in Figure 3. The first portion OR3a contacts the lower electrode LE3 through the opening AP3, covers the lower electrode LE3, and overlaps a portion of the rib 5. The second portion OR3b is positioned on top of the upper portion 62. Furthermore, the upper electrode UE3 shown in Figure 2 includes a first portion UE3a and a second portion UE3b that are spaced apart from each other, as shown in Figure 3. The first portion UE3a faces the lower electrode LE3 and is positioned above the first portion OR3a. In addition, the first portion UE3a is in contact with the side surface of the lower part 61. The second portion UE3b is located above the partition wall 6 and is positioned above the second portion OR3b.

[0034] In the example shown in Figure 3, the sub-pixels SP1, SP2, and SP3 include cap layers (optical adjustment layers) CP1, CP2, and CP3 for adjusting the optical properties of the light emitted by the light-emitting layers of the organic layers OR1, OR2, and OR3.

[0035] The cap layer CP1 includes a first portion CP1a and a second portion CP1b that are spaced apart from each other. The first portion CP1a is located at the opening AP1 and is positioned above the first portion UE1a. The second portion CP1b is located above the partition wall 6 and is positioned above the second portion UE1b.

[0036] The cap layer CP2 includes a first portion CP2a and a second portion CP2b that are spaced apart from each other. The first portion CP2a is located at the opening AP2 and is positioned above the first portion UE2a. The second portion CP2b is located above the partition wall 6 and is positioned above the second portion UE2b.

[0037] The cap layer CP3 includes a first portion CP3a and a second portion CP3b that are spaced apart from each other. The first portion CP3a is located at the opening AP3 and is positioned above the first portion UE3a. The second portion CP3b is located above the partition wall 6 and is positioned above the second portion UE3b.

[0038] Sub-pixels SP1, SP2, and SP3 are each covered by sealing layers SE1, SE2, and SE3, respectively. Sealing layer SE1 continuously covers each component of sub-pixel SP1, including the first portion CP1a, the partition wall 6, and the second portion CP1b. Sealing layer SE2 continuously covers each component of sub-pixel SP2, including the first portion CP2a, the partition wall 6, and the second portion CP2b. Sealing layer SE3 continuously covers each component of sub-pixel SP3, including the first portion CP3a, the partition wall 6, and the second portion CP3b.

[0039] In the example shown in Figure 3, the second portion OR1b, second portion UE1b, second portion CP1b, and sealing layer SE1 on the partition wall 6 between sub-pixels SP1 and SP3 are separated from the second portion OR3b, second portion UE3b, second portion CP3b, and sealing layer SE3 on the same partition wall 6. Similarly, the second portion OR2b, second portion UE2b, second portion CP2b, and sealing layer SE2 on the partition wall 6 between sub-pixels SP2 and SP3 are separated from the second portion OR3b, second portion UE3b, second portion CP3b, and sealing layer SE3 on the same partition wall 6.

[0040] The sealing layers SE1, SE2, and SE3 are covered by a resin layer 13. The resin layer 13 is covered by a sealing layer 14. Furthermore, the sealing layer 14 is covered by a resin layer 15.

[0041] The insulating layer 12 is an organic insulating layer. The barrier layer BL, ribs 5, sealing layers SE1, SE2, SE3, and sealing layer 14 are inorganic insulating layers. The barrier layer BL has the function of blocking moisture paths from the insulating layer 12 to the organic layers OR1, OR2, OR3, or from the insulating layer 12 to the upper electrodes UE1, UE2, UE3. By placing the barrier layer BL, deterioration of the organic layers OR1, OR2, OR3 and the upper electrodes UE1, UE2, UE3 due to moisture is suppressed.

[0042] The barrier layer BL and the rib 5 are formed from different inorganic insulating materials. Rib 5 and sealing layers SE1, SE2, and SE3 are formed from the same inorganic insulating material. The barrier layer BL and the sealing layers SE1, SE2, and SE3 are formed from different inorganic insulating materials. For example, the barrier layer BL is formed of silicon oxide (SiOx) or silicon oxynitride (SiON). The rib 5 is formed of silicon nitride (SiNx), for example. The sealing layers 14, SE1, SE2, SE3 are formed of silicon nitride (SiNx), for example.

[0043] The thickness of rib 5 is sufficiently small compared to the thickness of the partition wall 6 and the insulating layer 12. In one example, the thickness of rib 5 is between 200 nm and 400 nm. The thickness of barrier layer BL is equal to or less than the thickness of rib 5.

[0044] The lower part 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the first portions UE1a, UE2a, and UE3a of each upper electrode. Both the lower part 61 and the upper part 62 of the partition wall 6 may be conductive.

[0045] The lower electrodes LE1, LE2, and LE3 may be formed from a transparent conductive material such as ITO, or they may have a laminated structure of a metallic material such as silver (Ag) and a transparent conductive material. The upper electrodes UE1, UE2, and UE3 are formed from a metallic material such as a magnesium-silver alloy (MgAg). The upper electrodes UE1, UE2, and UE3 may also be formed from a transparent conductive material such as ITO.

[0046] When the potentials of the lower electrodes LE1, LE2, and LE3 are relatively higher than the potentials of the upper electrodes UE1, UE2, and UE3, the lower electrodes LE1, LE2, and LE3 correspond to the anodes, and the upper electrodes UE1, UE2, and UE3 correspond to the cathodes. Also, when the potentials of the upper electrodes UE1, UE2, and UE3 are relatively higher than the potentials of the lower electrodes LE1, LE2, and LE3, the upper electrodes UE1, UE2, and UE3 correspond to the anodes, and the lower electrodes LE1, LE2, and LE3 correspond to the cathodes.

[0047] The organic layers OR1, OR2, and OR3 contain multiple functional layers. Furthermore, the first portion OR1a and the second portion OR1b of organic layer OR1 contain an emissive layer EM1 formed from the same material. The first portion OR2a and the second portion OR2b of organic layer OR2 contain an emissive layer EM2 formed from the same material. The first portion OR3a and the second portion OR3b of organic layer OR3 contain an emissive layer EM3 formed from the same material. The emissive layers EM1, EM2, and EM3 are formed from materials that emit light in different wavelength ranges.

[0048] The cap layers CP1, CP2, and CP3 are formed, for example, by a multilayer structure of transparent thin films. The multilayer structure may include thin films formed of inorganic materials and thin films formed of organic materials. Furthermore, these multiple thin films have different refractive indices. The materials of the thin films constituting the multilayer structure are different from the materials of the upper electrodes UE1, UE2, and UE3, and also different from the materials of the sealing layers SE1, SE2, and SE3. Note that the cap layers CP1, CP2, and CP3 may be omitted.

[0049] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the first portions UE1a, UE2a, and UE3a of each upper electrode that are in contact with the side surface of the lower part 61. Pixel voltages are supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0050] When a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer EM1 of the first portion OR1a of the organic layer OR1 emits light in the red wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer EM2 of the first portion OR2a of the organic layer OR2 emits light in the green wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer EM3 of the first portion OR3a of the organic layer OR3 emits light in the blue wavelength range.

[0051] As another example, the light-emitting layers of organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layers into light of the color corresponding to the sub-pixels SP1, SP2, and SP3. Alternatively, the display device DSP may include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the color corresponding to the sub-pixels SP1, SP2, and SP3.

[0052] Figure 4 is a plan view showing one example configuration of the barrier layer BL. Note that in Figure 4, only the barrier layer BL and the lower electrodes LE1, LE2, and LE3 are shown, and the other components are not shown.

[0053] In a plan view, the lower electrodes LE1, LE2, and LE3 overlap the barrier layer BL. The barrier layer BL has an opening AP11 that overlaps the contact hole CH1, an opening AP12 that overlaps the contact hole CH2, and an opening AP13 that overlaps the contact hole CH3.

[0054] In other words, the lower electrode LE1 is connected to the pixel circuit 1 of the sub-pixel SP1 shown in Figure 1 through the aperture AP11 and the contact hole CH1. Similarly, the lower electrode LE2 is connected to the pixel circuit 1 of the sub-pixel SP2 through the aperture AP12 and the contact hole CH2. Furthermore, the lower electrode LE3 is connected to the pixel circuit 1 of the sub-pixel SP3 through the aperture AP13 and the contact hole CH3.

[0055] Furthermore, in the peripheral region SA shown in Figure 1, through holes may be provided in the barrier layer BL for the purpose of removing moisture from the insulating layer 12.

[0056] Figure 5 shows an example of the configuration of the display element 20. The lower electrode LE shown in Figure 5 corresponds to the lower electrodes LE1, LE2, and LE3 in Figure 3, respectively. The organic layer OR shown in Figure 5 corresponds to the organic layers OR1, OR2, and OR3 in Figure 3, respectively. The upper electrode UE shown in Figure 5 corresponds to the upper electrodes UE1, UE2, and UE3 in Figure 3, respectively.

[0057] The organic layer OR comprises a carrier adjustment layer CA1, an emissive layer EM, and a carrier adjustment layer CA2. Carrier adjustment layer CA1 is located between the lower electrode LE and the emissive layer EM, and carrier adjustment layer CA2 is located between the emissive layer EM and the upper electrode UE. Carrier adjustment layers CA1 and CA2 contain multiple functional layers. The following explanation will use the case where the lower electrode LE corresponds to the anode and the upper electrode UE corresponds to the cathode as an example.

[0058] The carrier adjustment layer CA1 includes functional layers such as a hole injection layer F11, a hole transport layer F12, and an electron blocking layer F13. The hole injection layer F11 is placed on the lower electrode LE, the hole transport layer F12 is placed on top of the hole injection layer F11, the electron blocking layer F13 is placed on top of the hole transport layer F12, and the light emission layer EM is placed on top of the electron blocking layer F13.

[0059] The carrier adjustment layer CA2 includes, as functional layers, a hole blocking layer F21, an electron transport layer F22, and an electron injection layer F23. The hole blocking layer F21 is located on top of the light-emitting layer EM, the electron transport layer F22 is located on top of the hole blocking layer F21, the electron injection layer F23 is located on top of the electron transport layer F22, and the upper electrode UE is located on top of the electron injection layer F23.

[0060] Furthermore, the carrier adjustment layers CA1 and CA2 may include other functional layers, such as a carrier generation layer, as needed, in addition to the functional layers described above, or at least one of the functional layers may be omitted.

[0061] Next, we will describe an example of a manufacturing method for a display device DSP.

[0062] Figure 6 is a flowchart illustrating an example of a manufacturing method for a display device DSP. The manufacturing method described herein broadly includes the steps of preparing a processing substrate SUB to serve as the base for sub-pixels SPα, SPβ, and SPγ (step ST1), forming sub-pixel SPα (step ST2), forming sub-pixel SPβ (step ST3), and forming sub-pixel SPγ (step ST4). Note that sub-pixels SPα, SPβ, and SPγ here refer to any of the sub-pixels SP1, SP2, and SP3 described above.

[0063] In step ST1, a processing substrate SUB is first prepared on the substrate 10, with a barrier layer BL, lower electrodes LEα, LEβ, LEγ, ribs 5, and partition walls 6 formed on top of it. As shown in Figure 3, a circuit layer 11 and an insulating layer 12 are also formed between the substrate 10 and the barrier layer BL. Further details will be described later.

[0064] In step ST2, first, a first thin film 31 including a first light-emitting layer EMα is formed on the processing substrate SUB (step ST21). Then, a first resist 41 patterned in a predetermined shape is formed on the first thin film 31 (step ST22). Subsequently, a portion of the first thin film 31 is removed by etching using the first resist 41 as a mask (step ST23). After that, the first resist 41 is removed (step ST24). This forms a sub-pixel SPα. The sub-pixel SPα comprises a display element 21 having the first thin film 31 of a predetermined shape.

[0065] In step ST3, a second thin film 32 including a second light-emitting layer EMβ is formed on the processing substrate SUB (step ST31). Then, a second resist 42 patterned in a predetermined shape is formed on the second thin film 32 (step ST32). Subsequently, a portion of the second thin film 32 is removed by etching using the second resist 42 as a mask (step ST33). Then, the second resist 42 is removed (step ST34). This forms a sub-pixel SPβ. The sub-pixel SPβ comprises a display element 22 having a second thin film 32 of a predetermined shape.

[0066] In step ST4, a third thin film 33 including a third light-emitting layer EMγ is formed on the processing substrate SUB (step ST41). Then, a third resist 43 patterned in a predetermined shape is formed on the third thin film 33 (step ST42). Subsequently, a portion of the third thin film 33 is removed by etching using the third resist 43 as a mask (step ST43). Then, the third resist 43 is removed (step ST44). This forms a sub-pixel SPγ. The sub-pixel SPγ comprises a display element 23 having a third thin film 33 of a predetermined shape.

[0067] The first light-emitting layer EMα, the second light-emitting layer EMβ, and the third light-emitting layer EMγ are formed from materials that emit light in different wavelength ranges.

[0068] Detailed illustrations of the second thin film 32, the second light-emitting layer EMβ, the display element 22, the third thin film 33, the third light-emitting layer EMγ, and the display element 23 are omitted.

[0069] Steps ST1 and ST2 will be explained below with reference to Figures 7 through 12.

[0070] First, in step ST1, a processing substrate SUB is prepared as shown in Figure 7. The steps for preparing the processing substrate SUB include: forming a circuit layer 11 on a substrate 10; forming an insulating layer 12 on the circuit layer 11; forming a barrier layer BL on the insulating layer 12; forming the lower electrode LEα of the sub-pixel SPα, the lower electrode LEβ of the sub-pixel SPβ, and the lower electrode LEγ of the sub-pixel SPγ on the barrier layer BL; forming ribs 5 having openings APα, APβ, and APγ that overlap with the lower electrodes LEα, LEβ, and LEγ, respectively; and forming a partition wall 6 including a lower part 61 placed on the ribs 5 and an upper part 62 placed on the lower part 61 and protruding from the side surface of the lower part 61. Note that in Figures 8 to 12, the substrate 10 and circuit layer 11 below the insulating layer 12 are not shown.

[0071] Next, in step ST21, as shown in Figure 8, a first thin film 31 is formed over sub-pixels SPα, SPβ, and SPγ. The step of forming the first thin film 31 includes the steps of forming an organic layer OR10 containing a first light-emitting layer EMα on a processing substrate SUB, forming an upper electrode UE10 on the organic layer OR10, forming a cap layer CP10 on the upper electrode UE10, and forming a sealing layer SE10 on the cap layer CP10. In other words, in the illustrated example, the first thin film 31 includes the organic layer OR10, the upper electrode UE10, the cap layer CP10, and the sealing layer SE10.

[0072] The organic layer OR10 includes the first organic layer OR11, the second organic layer OR12, the third organic layer OR13, the fourth organic layer OR14, and the fifth organic layer OR15. The first organic layer OR11, the second organic layer OR12, the third organic layer OR13, the fourth organic layer OR14, and the fifth organic layer OR15 all contain the first light-emitting layer EMα. The first organic layer OR11 is formed to cover the lower electrode LEα. The second organic layer OR12 is spaced apart from the first organic layer OR11 and is located above the upper part 62 of the partition wall 6 between the lower electrodes LEα and LEβ. The third organic layer OR13 is spaced apart from the second organic layer OR12 and is formed to cover the lower electrode LEβ. The fourth organic layer OR14 is spaced apart from the third organic layer OR13 and is located above the upper part 62 of the partition wall 6 between the lower electrodes LEβ and LEγ. The fifth organic layer OR15 is spaced apart from the fourth organic layer OR14 and is formed to cover the lower electrode LEγ.

[0073] The upper electrode UE10 includes a first upper electrode UE11, a second upper electrode UE12, a third upper electrode UE13, a fourth upper electrode UE14, and a fifth upper electrode UE15. The first upper electrode UE11 is located on the first organic layer OR11 and is in contact with the lower part 61 of the partition wall 6 between the lower electrodes LEα and LEβ. The second upper electrode UE12 is spaced apart from the first upper electrode UE11 and is located on the second organic layer OR12 between the lower electrodes LEα and LEβ. The third upper electrode UE13 is spaced apart from the second upper electrode UE12 and is located on the third organic layer OR13. In the illustrated example, the third upper electrode UE13 is in contact with the lower part 61 of the partition wall 6 between the lower electrodes LEα and LEβ, and between the lower electrodes LEβ and LEγ, but it may be in contact with either one of the lower parts 61. The fourth upper electrode UE14 is spaced apart from the third upper electrode UE13 and is located on the fourth organic layer OR14 between the lower electrodes LEβ and LEγ. The fifth upper electrode UE15 is spaced apart from the fourth upper electrode UE14, located on the fifth organic layer OR15, and is in contact with the lower part 61 of the partition wall 6 between the lower electrodes LEβ and LEγ.

[0074] The cap layer CP10 includes a first cap layer CP11, a second cap layer CP12, a third cap layer CP13, a fourth cap layer CP14, and a fifth cap layer CP15. The first cap layer CP11 is located on the first upper electrode UE11. The second cap layer CP12 is spaced apart from the first cap layer CP11 and located on the second upper electrode UE12. The third cap layer CP13 is spaced apart from the second cap layer CP12 and located on the third upper electrode UE13. The fourth cap layer CP14 is spaced apart from the third cap layer CP13 and located on the fourth upper electrode UE14. The fifth cap layer CP15 is spaced apart from the fourth cap layer CP14 and located on the fifth upper electrode UE15.

[0075] The sealing layer SE10 is formed to cover the first cap layer CP11, the second cap layer CP12, the third cap layer CP13, the fourth cap layer CP14, the fifth cap layer CP15, and the partition wall 6. The sealing layer SE10 covering the partition wall 6 is in contact with the lower part of the upper part 62 and with the side surface of the lower part 61.

[0076] In the example shown in Figure 8, the rib 5 is covered by the organic layer OR10 and the upper electrode UE10. Therefore, the rib 5 and the sealing layer SE10 do not come into contact with each other. However, if none of the organic layer OR10, the upper electrode UE10, and the cap layer CP10 extend to the lower part 61 of the partition wall 6, then the area of ​​the upper surface of the rib 5 near the partition wall 6 may come into contact with the sealing layer SE10.

[0077] Subsequently, in step ST22, as shown in Figure 9, a resist is applied to the sealing layer SE10 and this resist is patterned. The first resist 41 formed by this patterning covers the subpixel SPα. That is, the first resist 41 is located directly above the lower electrode LEα, the first organic layer OR11, the first upper electrode UE11, and the first cap layer CP11. The first resist 41 also extends upward from the subpixel SPα to the partition wall 6. Between the subpixel SPα and the subpixel SPβ, the first resist 41 is located on the subpixel SPα side (left side in the figure) and exposes the sealing layer SE10 on the subpixel SPβ side (right side in the figure). In the illustrated example, the first resist 41 exposes the sealing layer SE10 at subpixels SPβ and SPγ.

[0078] Subsequently, in step ST23, etching is performed using the first resist 41 as a mask to remove the first thin film 31 exposed from the first resist 41. The step of removing the first thin film 31 includes removing a portion of the sealing layer SE10, removing a portion of the cap layer CP10, removing a portion of the upper electrode UE10, and removing a portion of the organic layer OR10.

[0079] First, as shown in Figure 10, dry etching is performed using the first resist 41 as a mask to remove a portion of the encapsulation layer SE10 exposed from the first resist 41. In the illustrated example, the portion of the encapsulation layer SE10 that covers the subpixel SPα (the portion that covers the first cap layer CP11) and the portion on the subpixel SPα side (left side of the figure) directly above the partition wall 6 (the portion of the second cap layer CP12 that covers the subpixel SPα side) remain. On the other hand, the portion of the encapsulation layer SE10 on the subpixel SPβ side (right side of the figure) directly above the partition wall 6 (the portion that covers the subpixel SPβ side of the second cap layer CP12), the portion that covers the subpixel SPβ (the portion that covers the third cap layer CP13), the portion that covers the partition wall 6 between subpixel SPβ and subpixel SPγ (the portion that covers the fourth cap layer CP14), and the portion that covers subpixel SPγ (the portion that covers the fifth cap layer CP15) are removed. As a result, a portion of the second cap layer CP12, the third cap layer CP13, the fourth cap layer CP14, and the fifth cap layer CP15 are exposed from the sealing layer SE10.

[0080] As explained with reference to Figure 8, for example, if the sealing layer SE10 and the rib 5 are in contact near the partition wall 6 of the sub-pixels SPβ and SPγ, the rib 5 may also be damaged when the sealing layer SE10 is removed. However, even if the rib 5 is damaged, the barrier layer BL prevents the insulating layer 12 from being exposed.

[0081] Then, as shown in Figure 11, etching is performed using the first resist 41 as a mask to remove the first resist 41 and a portion of the cap layer CP10 exposed from the sealing layer SE10. In the illustrated example, a portion of the second cap layer CP12, all of the third cap layer CP13, all of the fourth cap layer CP14, and all of the fifth cap layer CP15 are removed. Then, etching is performed using the first resist 41 as a mask to remove the first resist 41, the sealing layer SE10, and a portion of the upper electrode UE10 exposed from the cap layer CP10. In the illustrated example, a portion of the second upper electrode UE12, all of the third upper electrode UE13, all of the fourth upper electrode UE14, and all of the fifth upper electrode UE15 are removed. Then, etching is performed using the first resist 41 as a mask to remove the first resist 41, the sealing layer SE10, the cap layer CP10, and a portion of the organic layer OR10 exposed from the upper electrode UE10. In the illustrated example, a portion of the second organic layer OR12, all of the third organic layer OR13, all of the fourth organic layer OR14, and all of the fifth organic layer OR15 are removed.

[0082] As a result, the lower electrode LEβ is exposed in the sub-pixel SPβ, and the lower electrode LEγ is exposed in the sub-pixel SPγ.

[0083] Regarding the partition wall 6 between sub-pixels SPα and SPβ, directly above the upper part 62, the second organic layer OR12, second upper electrode UE12, second cap layer CP12, and sealing layer SE10 remain on the sub-pixel SPα side, while on the sub-pixel SPβ side, the second organic layer OR12, second upper electrode UE12, second cap layer CP12, and sealing layer SE10 are removed. As a result, the sub-pixel SPβ side of the partition wall 6 is exposed. Furthermore, the partition wall 6 between sub-pixels SPβ and SPγ is also exposed.

[0084] Subsequently, in step ST24, the first resist 41 is removed as shown in Figure 12. This exposes the sealing layer SE10 of the sub-pixel SPα. Through these steps ST21 to ST24, the display element 21 is formed in the sub-pixel SPα. The display element 21 consists of a lower electrode LEα, a first organic layer OR11 including a first light-emitting layer EMα, a first upper electrode UE11, and a first cap layer CP11. The display element 21 is also covered by the sealing layer SE10.

[0085] A laminate is formed on the partition wall 6 between the sub-pixels SPα and SPβ, comprising a second organic layer OR12 containing a first light-emitting layer EMα, a second upper electrode UE12, and a second cap layer CP12. This laminate is covered with a sealing layer SE10. Furthermore, the portion of the partition wall 6 on the side of the sub-pixels SPα is covered with the sealing layer SE10.

[0086] In the example described above, the sub-pixel SPα is one of the sub-pixels SP1, SP2, or SP3 shown in Figure 2. For example, if sub-pixel SPα corresponds to sub-pixel SP1, then the lower electrode LEα corresponds to the lower electrode LE1, the first organic layer OR11 corresponds to the first part OR1a, the second organic layer OR12 corresponds to the second part OR1b, the first light-emitting layer EMα corresponds to the light-emitting layer EM1, the first upper electrode UE11 corresponds to the first part UE1a, the second upper electrode UE12 corresponds to the second part UE1b, the first cap layer CP11 corresponds to the first part CP1a, the second cap layer CP12 corresponds to the second part CP1b, and the sealing layer SE10 corresponds to the sealing layer SE1.

[0087] According to this embodiment, an inorganic insulating layer, a barrier layer BL, is placed between the inorganic insulating layer, the rib 5, and the organic insulating layer, the insulating layer 12. The barrier layer BL is made of a different inorganic insulating material than the rib 5 and the sealing layer SE10. For example, while the rib 5 and the sealing layer SE10 are made of silicon nitride, the barrier layer BL is made of silicon oxide (SiO) or silicon oxynitride (SiON), which have higher resistance to dry etching compared to silicon nitride (SiN).

[0088] Therefore, even if the sealing layer SE10 is positioned in contact with the rib 5 and the rib 5 is damaged during dry etching of the sealing layer SE10, the barrier layer BL directly beneath the rib 5 prevents exposure of the insulating layer 12. This suppresses the formation of unwanted holes (moisture intrusion paths) from the rib 5 to the insulating layer 12. Consequently, moisture paths from the insulating layer 12 to the organic layer OR10, or from the insulating layer 12 to the upper electrode UE10, are blocked, and deterioration of the organic layer OR10 and the upper electrode UE10 due to moisture is suppressed. Therefore, a decrease in reliability can be suppressed.

[0089] Next, we will describe other examples of display device configurations.

[0090] Figure 13 is a plan view showing another example of the barrier layer BL configuration. Note that in Figure 13, only the barrier layer BL and the lower electrodes LE1, LE2, and LE3 are shown, and the other components are not shown.

[0091] In a plan view, the ends of the lower electrodes LE1, LE2, and LE3 overlap the barrier layer BL. The barrier layer BL has an opening AP11 that overlaps the contact hole CH1, an opening AP12 that overlaps the contact hole CH2, and an opening AP13 that overlaps the contact hole CH3.

[0092] The configuration example shown in Figure 13 differs from the configuration example shown in Figure 4 in that each of the openings AP11, AP12, and AP13 is expanded. Opening AP11 is expanded to overlap the contact hole CH1 and the center of the lower electrode LE1. Similarly, opening AP12 is expanded to overlap the contact hole CH2 and the center of the lower electrode LE2, and opening AP13 is expanded to overlap the contact hole CH3 and the center of the lower electrode LE3.

[0093] Figure 14 is a cross-sectional view showing another example of the display device configuration. Figure 14 shows a cross-section of the main part along line A and B in Figure 13, and the cap layer and sealing layer are not shown.

[0094] The barrier layer BL is positioned on top of the insulating layer 12. The opening AP11 of the barrier layer BL overlaps with the opening AP1 of the rib 5, and the opening AP12 overlaps with the opening AP2 of the rib 5. The lower electrodes LE1 and LE2 are positioned on top of the insulating layer 12. The ends of the lower electrode LE1 and the lower electrode LE2 are positioned between the barrier layer BL and the rib 5, respectively. The barrier layer BL is positioned between the partition wall 6 and the lower electrode LE1, between the partition wall 6 and the lower electrode LE2, and between the insulating layer 12 and the rib 5. Furthermore, the barrier layer BL is located directly below the partition wall 6 and covers the insulating layer 12 between the lower electrodes LE1 and LE2.

[0095] At the position where it overlaps with the opening AP1 of rib 5, the lower electrode LE1 is positioned on the insulating layer 12 without passing through the barrier layer BL. Similarly, at the position where it overlaps with the opening AP2 of rib 5, the lower electrode LE2 is positioned on the insulating layer 12 without passing through the barrier layer BL. The lower electrode LE3 (not shown) is similarly positioned on the insulating layer 12 without passing through the barrier layer BL at the position where it overlaps with the opening AP3 of rib 5.

[0096] The same effects as described above can be obtained even in this configuration example.

[0097] Figure 15 is a cross-sectional view showing another example of the display device configuration. Figure 15 shows a cross-section of the main part along line A and B in Figure 13, and the cap layer and sealing layer are not shown.

[0098] The configuration example shown in Figure 15 differs from the configuration example shown in Figure 14 in that the ends of the lower electrode LE1 and the lower electrode LE2 are positioned between the insulating layer 12 and the barrier layer BL, respectively. Similarly, the end of the lower electrode LE3 (not shown) is also positioned between the insulating layer 12 and the barrier layer BL. The entire barrier layer BL is covered with ribs 5.

[0099] Similar to the configuration example in Figure 14, the barrier layer BL is positioned between the partition wall 6 and the lower electrode LE1, and between the partition wall 6 and the lower electrode LE2, and between the insulating layer 12 and the rib 5. Furthermore, the barrier layer BL is located directly below the partition wall 6 and covers the insulating layer 12 between the lower electrodes LE1 and LE2.

[0100] The same effects as described above can be obtained even in this configuration example.

[0101] Figure 16 is a cross-sectional view showing another example of the display device configuration. Note that the cap layer and sealing layer are omitted from the illustration in Figure 16.

[0102] The configuration example shown in Figure 16 differs from the configuration example shown in Figure 14 in that the ends of the lower electrode LE1 and the lower electrode LE2 are spaced apart from the barrier layer BL. The lower electrodes LE1 and LE2 are each placed on the insulating layer 12. The ends of the lower electrode LE1 and the lower electrode LE2 are each covered with ribs 5. The entire barrier layer BL is covered with ribs 5. Between the lower electrode LE1 and the barrier layer BL, and between the lower electrode LE2 and the barrier layer BL, the ribs 5 cover the insulating layer 12.

[0103] The same effects as described above can be obtained even in this configuration example.

[0104] As described above, this embodiment provides a display device that can suppress a decrease in reliability and improve manufacturing yield.

[0105] All display devices that a person skilled in the art can implement by appropriately modifying the design based on the display devices described above as embodiments of the present invention also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0106] Within the scope of the spirit of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, modifications made by a person skilled in the art to the above-described embodiments, such as adding, deleting, or changing the design of components, or adding, omitting, or changing the conditions of processes, are also included within the scope of the present invention, as long as they retain the gist of the present invention.

[0107] Furthermore, any other effects and benefits brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of symbols]

[0108] DSP…display device 10...Substrate 12...Insulating layer 5...Rib (insulating layer) BL...Barrier layer 6...Bulkhead 61...Lower 62...Upper SP1, SP2, SP3, SPα, SPβ, SPγ... Sub-pixels 20, 21, 22, 23… Display elements (organic EL elements) LE, LE1, LE2, LE3, LEα, LEβ, LEγ... Lower electrode (anode) UE, UE1, UE2, UE3, UE10... Upper electrode (cathode) OR,OR1,OR2,OR3,OR10…Organic layer CP, CP1, CP2, CP3, CP10… Cap layers SE, SE1, SE2, SE3, SE10…Sealing layer

Claims

1. circuit board and An organic insulating layer disposed above the substrate, A barrier layer formed of an inorganic insulating material and placed in direct contact with the organic insulating layer, Ribs formed of an inorganic insulating material and positioned in direct contact with the barrier layer, A partition wall having a lower part located directly above the barrier layer and positioned on the rib, and an upper part positioned above the lower part and protruding from the side surface of the lower part, A lower electrode having an end between the organic insulating layer and the rib, An organic layer comprising a light-emitting layer having a first portion positioned above the lower electrode in the opening of the rib and spaced apart from the lower part of the partition wall, and a second portion positioned above the upper part, wherein the first and second portions are formed of the same material, An upper electrode having a first portion disposed on the first portion of the organic layer and in contact with the lower part of the partition wall, and a second portion disposed on the second portion of the organic layer, A cap layer having a first portion disposed on the first portion of the upper electrode and a second portion disposed on the second portion of the upper electrode, A sealing layer covering the first and second portions of the cap layer, Equipped with, The barrier layer is positioned between the side surface of the partition wall and the end of the lower electrode, between the organic insulating layer and the rib. The end of the lower electrode is positioned between the barrier layer and the rib. A display device in which the lower electrode is positioned on the organic insulating layer without the barrier layer, at a position overlapping the opening of the rib.

2. A substrate and An organic insulating layer disposed above the substrate, A barrier layer formed of an inorganic insulating material and placed in direct contact with the organic insulating layer, Ribs formed of an inorganic insulating material and positioned in direct contact with the barrier layer, A partition wall having a lower part located directly above the barrier layer and positioned on the rib, and an upper part positioned above the lower part and protruding from the side surface of the lower part, A lower electrode having an end between the organic insulating layer and the rib, An organic layer comprising a light-emitting layer having a first portion positioned above the lower electrode in the opening of the rib and spaced apart from the lower part of the partition wall, and a second portion positioned above the upper part, wherein the first and second portions are formed of the same material, An upper electrode having a first portion disposed on the first portion of the organic layer and in contact with the lower part of the partition wall, and a second portion disposed on the second portion of the organic layer, A cap layer having a first portion disposed on the first portion of the upper electrode and a second portion disposed on the second portion of the upper electrode, A sealing layer covering the first and second portions of the cap layer, Equipped with, The barrier layer is positioned between the side surface of the partition wall and the end of the lower electrode, between the organic insulating layer and the rib. The end of the lower electrode is positioned between the organic insulating layer and the barrier layer, in a display device.

3. The display device according to claim 1, wherein the barrier layer and the ribs are formed of different inorganic insulating materials.

4. The barrier layer is formed of silicon oxide or silicon oxynitride, The display device according to claim 1, wherein the ribs are formed of silicon nitride.

5. The display device according to claim 1, wherein the ribs and the sealing layer are formed of the same inorganic insulating material.

6. The display device according to claim 1, wherein the ribs and the sealing layer are formed of silicon nitride.

7. The display device according to claim 1, wherein the barrier layer and the sealing layer are formed of different inorganic insulating materials.

8. The barrier layer is formed of silicon oxide or silicon oxynitride, The display device according to claim 1, wherein the sealing layer is formed of silicon nitride.

9. The display device according to claim 1, wherein the lower part of the partition wall is formed of a conductive material and is electrically connected to the first portion of the upper electrode.

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