Method for manufacturing silicon wafer and silicon wafer

Abstract

A method for manufacturing a silicon wafer that can suppress BMD precipitation while avoiding the risk of metal contamination is provided. A method for manufacturing a silicon wafer according to the present invention comprises a first RTO, in which a flattened silicon wafer (W) produced from a single-crystal silicon ingot grown by the CZ method is heated to a first maximum temperature of 1300°C or higher and 1380°C or lower under an oxidizing atmosphere with an oxygen partial pressure of 25% to 100% and maintained at the first maximum temperature for 5 seconds or more; an oxide film stripping process in which the silicon wafer (W) obtained by the first RTO is cleaned with hydrofluoric acid; and a second RTO, in which the silicon wafer (W) obtained by the oxide film stripping process is heated to a second maximum temperature of 1050°C or higher and less than 1300°C under an oxidizing atmosphere with an oxygen partial pressure of 25% to 100% and maintained at the second maximum temperature for 5 seconds or more.

Description

Technology Field

[0001] The present invention relates to a method for manufacturing a silicon wafer suitable for use as a substrate for a semiconductor device, etc., and to a silicon wafer. Background Technology

[0002] Silicon wafers used as substrates for semiconductor devices contain defects called atomic vacancies (V). There is a correlation between the concentration of these atomic vacancies and the density of oxygen precipitates (BMD: Bulk Micro Defect) that precipitate when heat treatment is performed, and it is believed that atomic vacancies contribute to the nucleation of BMDs.

[0003] Atomic vacancies in silicon wafers do not exist as individual entities, but are vacancy-oxygen complexes (VO₂) formed by combining with oxygen dissolved from a quartz crucible during growth by the Czochralski method (CZ method). x ) or atomic vacancies form void defects by bonding with each other. BMDs precipitated from atomic vacancies are prone to bonding with metals and function as gettering sites for metal impurities that have intruded into the silicon wafer.

[0004] Meanwhile, BMD can be a cause of dislocation generation, and in such cases, suppression of BMD precipitation is required as a countermeasure against dislocation generation. As a technique for suppressing BMD precipitation, Patent Document 1 discloses a heat treatment method in which two stages of RTO (Rapid Thermal Oxidation) are performed on a silicon wafer.

[0005] Specifically, this heat treatment method comprises a first heat treatment process (a first RTO (Rapid Thermal Process in an oxidizing atmosphere)) in which a silicon wafer is heated from 1300°C to 1380°C under an oxidizing atmosphere in which the oxygen partial pressure is 25% or more and 100% or less, maintained for 5 seconds or more, and cooled to 800°C or less at a rate not exceeding 120°C / s, and a second heat treatment process (a second RTO) in which a silicon wafer is heated from 1150°C to 1220°C under an oxidizing atmosphere in which the oxygen partial pressure is 25% or more and 100% or less, maintained for 5 seconds or more, and cooled at a rate not exceeding 120°C / s, and the second RTO is performed continuously after the first RTO. Accordingly, atomic vacancies in the surface layer of the silicon wafer are eliminated in the first RTO, and atomic vacancies present in the bulk are eliminated in the second RTO. Prior art literature

[0006] Japanese Patent Publication No. 2019-192831 The problem to be solved

[0007] However, in the heat treatment method described in Patent Document 1, since a second RTO is performed continuously after the first RTO, if metal contamination by the RTP device occurs on the silicon wafer during the first RTO, there is a risk that the metal contamination will spread into the silicon wafer by the second RTO.

[0008] That is, in the heat treatment method described in Patent Document 1, since the atomic vacancies are reduced by the two-stage RTO to suppress BMD precipitation, there was a concern that the effect of BMD, which functions as a gettering site for metal impurities, would be limited even if metal contamination occurred.

[0009] The present invention has been made in consideration of the above problem and aims to provide a method for manufacturing a silicon wafer capable of suppressing BMD precipitation while avoiding the risk of metal contamination, and a silicon wafer. means of solving the problem

[0010] A method for manufacturing a silicon wafer according to the present invention comprises: a first heat treatment process in which a silicon wafer, obtained by slicing and flattening a single-crystal silicon ingot grown by the CZ method, is heated to a first maximum temperature of 1300°C or higher and 1380°C or lower under an oxidizing atmosphere having an oxygen partial pressure of 25% to 100%, and maintained at the first maximum temperature for 5 seconds or more; an oxide film stripping process in which the silicon wafer obtained by the first heat treatment process is cleaned with hydrofluoric acid; and a second heat treatment process in which the silicon wafer obtained by the oxide film stripping process is heated to a second maximum temperature of 1050°C or higher and less than 1300°C under an oxidizing atmosphere having an oxygen partial pressure of 25% to 100%, and maintained at the second maximum temperature for 5 seconds or more.

[0011] According to the method for manufacturing a silicon wafer according to the present invention, the vacancy-oxygen complex (VO₂) x A first heat treatment process is performed to eliminate voids or atomic voids to enhance the atomic void elimination effect, and an oxide film stripping process is performed to remove metal contamination from the wafer (W) by the RTP device, and a second heat treatment process is performed to eliminate atomic voids remaining in the bulk region, so a silicon wafer with effectively suppressed BMD precipitation can be obtained while avoiding the risk of metal contamination.

[0012] Furthermore, in the method for manufacturing a silicon wafer according to the present invention, it is preferable to further include a polishing process for polishing the surface and surface layer of the silicon wafer obtained by the second heat treatment process. Additionally, in the first heat treatment process and the second heat treatment process, it is more preferable that the oxygen partial pressure in the oxidizing atmosphere is 100%. Additionally, in the oxide film stripping process, it is preferable to clean the surface of the silicon wafer obtained by the first heat treatment process with an aqueous hydrofluoric acid solution of 10% or more for at least 10 seconds. Additionally, the oxygen concentration of the silicon wafer prior to the first heat treatment process is 1.0 × 10⁻⁶ 18 / cm 3 ~1.5×10 18 / cm 3 It is desirable that it is.

[0013] The silicon wafer according to the present invention is a silicon wafer obtained by performing a two-stage RTO on a silicon wafer obtained by slicing and planarizing a single-crystal silicon ingot grown by the CZ method, wherein, when maintained at 780°C for 3 hours in an oxidizing atmosphere followed by maintaining at 1000°C for 16 hours, the defect density of 20 nm or more observed by IR tomography is 1×10⁻⁶ 8 / cm 3 It is characterized by being lower. Effects of the invention

[0014] According to the method for manufacturing a silicon wafer according to the present invention, BMD precipitation can be suppressed while avoiding the risk of metal contamination. Brief explanation of the drawing

[0015] FIG. 1 is a cross-sectional conceptual diagram showing an example of a single-wafer RTP device used for heat treatment in a method for manufacturing a silicon wafer according to the present invention. FIG. 2 is a flowchart illustrating an example of a method for manufacturing a silicon wafer according to the present invention. Figure 3 is a conceptual diagram showing a heat treatment sequence. Figure 4 is a schematic diagram showing the behavior of point defects due to heat treatment. Figure 5 is a diagram showing a defect density of 20 nm or more observed by IR tomography. Figure 6 is a drawing showing an image of a wafer cross-section at a depth of 350 μm from the wafer surface. Specific details for implementing the invention

[0016] Hereinafter, a method for manufacturing a silicon wafer and an embodiment of a silicon wafer according to the present invention will be described in detail based on the drawings. Furthermore, the present invention is not limited by these embodiments. Additionally, elements that can be described identically in this specification and drawings may be given the same reference numerals to omit redundant descriptions.

[0017] <Overview of Manufacturing Method>

[0018] The method for manufacturing a silicon wafer in the present embodiment comprises a first heat treatment process (first RTO) in which a silicon wafer, obtained by slicing and flattening a single-crystal silicon ingot grown by the CZ method, is heated to a first maximum temperature of 1300°C or higher and 1380°C or lower under an oxidizing atmosphere with an oxygen partial pressure of 25% to 100%, and maintained at the first maximum temperature for 5 seconds or more; an oxide film stripping process in which the silicon wafer obtained by the first heat treatment process is cleaned with hydrofluoric acid; and a second heat treatment process (second RTO) in which the silicon wafer obtained by the oxide film stripping process is heated to a second maximum temperature of 1050°C or higher and less than 1300°C under an oxidizing atmosphere with an oxygen partial pressure of 25% to 100%, and maintained at the second maximum temperature for 5 seconds or more. Additionally, in subsequent embodiments, the silicon wafer may be simply referred to as a "wafer."

[0019] Atomic vacancies contained in silicon single crystals grown by the CZ method are vacancies-oxygen complexes (VO₂) bonded with oxygen atoms. x) or forms voids where atomic vacancies are bonded together. Since a correlation is observed between the atomic vacancy concentration and the precipitated BMD density, the vacancy-oxygen complex (VO) in the wafer x It is believed that ) or voids become BMD precipitation nuclei.

[0020] Accordingly, in the method for manufacturing a silicon wafer in the present embodiment, defects caused by atomic vacancies contained in a wafer (W) in which atomic vacancies are predominantly present, namely vacancies-oxygen complexes (VO2), are removed by carrying out RTP (RTO) in an oxidizing atmosphere. x ) or void defects are eliminated. Since it is known that voids formed during crystal growth are eliminated by RTO at 1300°C or higher, in this embodiment, a wafer (W) is heated to a first maximum temperature of 1300°C or higher and 1380°C or lower under an oxidizing atmosphere, and a first RTO is performed by maintaining the first maximum temperature for 5 seconds or more. In addition, when RTO at 1300°C or higher is performed, the thermal equilibrium concentration of atomic vacancies becomes higher than the thermal equilibrium concentration of interstitial silicon, so new atomic vacancies are introduced in the bulk region and VO4 combined with 4 oxygen atoms is formed. Therefore, in the first RTO, BMD precipitation in the wafer surface layer is suppressed, but BMD precipitation in the bulk region is not suppressed.

[0021] After that, the wafer (W) is heated to a second maximum temperature of 1050°C or higher and less than 1300°C under an oxidizing atmosphere, and a second RTO is performed by maintaining the second maximum temperature for 5 seconds or more, thereby injecting interstitial silicon from the oxide film formed on the wafer surface and eliminating the atomic vacancies introduced in the first RTO.

[0022] By doing so, a wafer (W) can be manufactured from a single-crystal silicon ingot in which atomic vacancies are predominantly present, in which defects caused by atomic vacancies are not included in the wafer surface layer and bulk region.

[0023] In addition, as described above, when eliminating atomic vacancies introduced in the first RTO, if the second RTO is performed while the oxide film formed in the first RTO is attached to the wafer surface, there is a concern that the effect of eliminating atomic vacancies by the second RTO may be reduced because the distortion of the oxide film interface has already been alleviated. Accordingly, in this embodiment, in order to improve the effect of eliminating atomic vacancies by the second RTO, it is preferable to perform an oxide film stripping process in which the wafer surface is cleaned with hydrofluoric acid (hydrofluoric acid: HF) after the first RTO (before the second RTO).

[0024] If the wafer surface is cleaned with hydrofluoric acid before the second RTO, the oxide film on the wafer surface can be removed, and hydrogen termination of the dangling bonds on the surface can be suppressed, thereby preventing the formation of a new natural oxide film. In addition, by stripping the oxide film with hydrofluoric acid before the second RTO, BMD precipitation can be suppressed at a lower temperature than conventional methods.

[0025] In addition, by performing an oxide film stripping process, even if metal contamination by the RTP device occurs on the wafer (W) during the first RTO, the metal contamination can be removed, thereby reducing the risk of metal contamination spreading into the wafer when the second RTO is performed.

[0026] <RTP 장치>

[0027] FIG. 1 is a cross-sectional conceptual diagram showing an example of a single-wafer RTP device used for heat treatment (RTP) in a method for manufacturing a silicon wafer according to the present invention.

[0028] The RTP device (10) shown in FIG. 1 comprises a reaction chamber (20) for receiving a wafer (W) and performing heat treatment, a wafer holding unit (30) installed within the reaction chamber (20) to hold the wafer (W), and a heating unit (40) for heating the wafer (W). When the wafer (W) is held in the wafer holding unit (30), a first space (20a) is formed, which is a space enclosed by the inner wall of the reaction chamber (20) and the surface (front side: device forming surface) (W1) of the wafer (W), and a second space (20b) is formed, which is a space enclosed by the inner wall of the reaction chamber (20) and the back side (W2) of the wafer (W) facing the surface (W1).

[0029] The reaction chamber (20) contains an atmosphere gas (F) in the first space (20a) and the second space (20b). A A supply port (22) that supplies )(solid arrow), and supplied atmosphere gas (F A It has an outlet (26) that discharges ) from the first space (20a) and the second space (20b). The reaction chamber (20) is, for example, made of quartz.

[0030] The wafer holding portion (30) comprises a ring-shaped susceptor (32) that holds the outer periphery of the back surface (W2) of the wafer (W), and a rotating body (34) that holds the susceptor (32) and rotates the susceptor (32) around the center of the wafer (W) as an axis. The susceptor (32) is, for example, composed of SiC, and its surface is covered with an oxide film.

[0031] The heating unit (40) heats the wafer (W) from both sides by lamp heating through light irradiation from a plurality of halogen lamps (50) placed outside the reaction chamber (20), above the surface (W1) and below the back surface (W2) of the wafer (W) held in the wafer holding unit (30).

[0032] When performing heat treatment using the RTP device (10) shown in FIG. 1, a wafer (W) is introduced into the reaction chamber (20) from a wafer introduction port not shown installed in the reaction chamber (20), and the outer periphery of the back surface (W2) of the wafer (W) is held on a ring-shaped susceptor (32) in the wafer holding part (30). Then, an atmosphere gas (F A While supplying ), the wafer (W) is rotated, and the wafer (W) is heated by the heating unit (40).

[0033] Specific examples of manufacturing methods

[0034] Next, an embodiment of the method for manufacturing a silicon wafer according to the present invention will be described in detail using the drawings. FIG. 2 is a flowchart showing an example of the method for manufacturing a silicon wafer according to the present invention, FIG. 3 is a conceptual diagram showing a heat treatment sequence, and FIG. 4 is a schematic diagram showing the behavior of point defects due to heat treatment.

[0035] As shown in FIG. 2, the method for manufacturing a silicon wafer in the present embodiment comprises a growth process (step S1) for growing a single-crystal silicon ingot by the CZ method, a slicing process (step S2) for slicing the grown single-crystal silicon ingot to produce a disc-shaped wafer (W), a processing process (step S3) for performing a planarization treatment on the surface of the disc-shaped wafer (W), the first heat treatment process (first RTO: step S4), the oxide film peeling process (step S5), the second heat treatment process (second RTO: step S6), a polishing process (step S7) for polishing the surface and surface layer of the wafer (W) obtained by the second RTO, and a cleaning process (step S8) for performing single-wafer spin cleaning on the wafer (W) after polishing.

[0036] Thus, in the method for manufacturing a silicon wafer according to the present embodiment, a single-crystal silicon ingot grown by the CZ method is sliced, and then a two-stage RTO is performed on the flattened wafer (W).

[0037] In FIG. 2, the growth of a single-crystal silicon ingot by the CZ method (step S1) is performed in a well-known manner. That is, polycrystalline silicon filled in a quartz crucible is heated to form molten silicon, a seed crystal is brought into contact with the surface of the molten silicon, and the seed crystal and the quartz crucible are rotated and pulled upward, and the linear portion is grown by expanding to a desired diameter to produce a single-crystal silicon ingot.

[0038] The obtained single-crystal silicon ingot is processed into a flattened wafer (W) by a known method (step S2, step S3). That is, the single-crystal silicon ingot is sliced ​​into a wafer shape using an inner blade or a wire saw (step S2), and then, on the wafer (W) after slicing, processing such as chamfering of the outer edge, lapping to roughly polish to a certain thickness while removing cutting damage formed during slicing, etching to remove fine distortion or scratches introduced by lapping through chemical etching, and polishing is performed (step S3) to obtain a flattened wafer (W). Furthermore, the processing process described herein is exemplary, and the present embodiment is not limited to this processing process.

[0039] In steps S1 to S3, the atomic vacancies contained in the silicon single crystal grown by the CZ method are, as described above, vacancies-oxygen complexes (VO₂). x It forms ) or voids. And, as shown in FIG. 4(a), these void-oxygen complexes (VO) x ) or voids (61) exist in the flattened wafer (W) after the processing process (in FIG. 4, only voids (61) are described for convenience).

[0040] Next, for the planarized wafer (W), a first RTO (step S4), an oxide film stripping process (step S5), and a second RTO (step S6) are performed in sequence according to predetermined conditions. Additionally, in this embodiment, the oxygen concentration (oxygen concentration of the crystal) of the wafer (W) before performing the first RTO is 1.5 × 10⁻⁶ 18 / cm 3 It must be less than or equal to, for example, 0.8 × 10⁻⁶ 18 / cm 3 ~1.5×10 18 / cm 3 If so, it is more desirable, and 1.0×10 18 / cm 3 ~1.5×10 18 / cm 3 This is the most desirable.

[0041] As shown in FIG. 3, in the heat treatment sequence applied to the method for manufacturing a silicon wafer of the present embodiment, a wafer (W) is first placed in a susceptor (32) in a reaction chamber (20) of an RTP device (10) maintained at a desired temperature (T0).

[0042] Then, a first RTO is performed on this wafer (W) (step S4). Specifically, under an oxidizing atmosphere, the temperature is rapidly increased to a first maximum temperature (T1) at a first heating rate (△Tu1), and after maintaining the first maximum temperature (T1) for a first holding time (t1), the temperature is lowered to a desired temperature at a first cooling rate (△Td1). When the first RTO is performed, an oxide film (62a) of, for example, 10 to 50 nm is formed on the wafer surface, and interstitial silicon (I) is injected from the interface of the oxide film (62a), and a vacancy-oxygen complex (VO) x) or aggregated voids (61) disappear, and atomic vacancies (V) diffuse (see FIG. 4(b)). Then, after the first RTO operation, the interstitial silicon (I) and atomic vacancies (V) present on the surface layer of the wafer (W) disappear through recombination, and on the other hand, because the thermal equilibrium concentration of atomic vacancies (V) becomes higher than the thermal equilibrium concentration of interstitial silicon (I), atomic vacancies (V) remain in the bulk region (see FIG. 4(c)).

[0043] After performing the first RTO, in the oxide film stripping process (step S5), the oxide film (62a) formed on the wafer surface is removed (striped). At this time, the oxide film (62a) is removed by performing hydrofluoric acid cleaning on the wafer surface. Specifically, after removing the wafer (W) after RTO from the RTP device (10), the oxide film (62a) is removed by supplying an aqueous hydrofluoric acid solution with a hydrofluoric acid concentration of 10% or more to the wafer surface for 10 seconds or more by single-wafer spin cleaning (cleaning using a spin cleaning device) (see FIG. 4(d)).

[0044] Next, before performing the second RTO, the wafer (W) after oxide film removal is placed in the susceptor (32) inside the reaction chamber (20) of the RTP device (10) maintained at the desired temperature (T0) (see the heat treatment sequence shown in FIG. 3).

[0045] Then, a second RTO is performed on the wafer (W) after the oxide film removal (step S6). Specifically, under an oxidizing atmosphere, the temperature is rapidly increased to a second maximum temperature (T2) at a second heating rate (△Tu2), and after maintaining the second maximum temperature (T2) for a second holding time (t2), the temperature is lowered to a desired temperature at a second cooling rate (△Td2). When the second RTO is performed, an oxide film (62b) of, for example, 10 to 50 nm is formed on the wafer surface, and interstitial silicon (I) is injected from the interface of the oxide film (62b) (see FIG. 4(e)). Then, after the second RTO is performed, the injected interstitial silicon (I) and the atomic vacancies (V) remaining in the bulk region are eliminated by recombination (see FIG. 4(f)).

[0046] As described above, in the method for manufacturing a silicon wafer according to the present embodiment, a two-stage RTO is performed on a flattened wafer (W) with an oxide film peeling process in between, and in the first RTO, a vacancy-oxygen complex (VO₂) x After eliminating the ) or aggregated voids (61) and removing the oxide film (62a) formed in the first RTO, the atomic voids (V) remaining in the bulk region are eliminated again in the second RTO.

[0047] Specifically, in the first RTO, the wafer (W) flattened by the processing of steps S1 to S3 is heated to a first maximum temperature (T1) of 1300°C or higher and 1380°C or lower at a first heating rate (△Tu1) of 10°C / s or higher under an oxidizing atmosphere with an oxygen partial pressure of 25% to 100%, maintained at the first maximum temperature (T1) for a first holding time (t1) of 5 seconds or more, and then lowered to a desired temperature at a first cooling rate (△Td1) of 25°C / s or higher and 120°C / s or lower.

[0048] In the second RTO, the wafer (W) after removing the oxide film by the treatment of step S5 is heated to a second maximum temperature (T2) of 1050°C or higher and less than 1300°C at a second heating rate (△Tu2) of 10°C / s or higher under an oxidizing atmosphere with an oxygen partial pressure of 25°C to 100°C, maintained at the second maximum temperature (T2) for a second holding time (t2) of 5 seconds or more, and then lowered to a desired temperature at a second cooling rate (△Td2) of 25°C / s or higher and less than 120°C / s.

[0049] As described above, after performing the first RTO (step S4), the oxide film stripping process (step S5), and the second RTO (step S6) in sequence, in this embodiment, a polishing process (step S7) for polishing the surface and surface layer of the wafer (W) from which atomic vacancies have been eliminated, and a cleaning process (step S8) for performing single-wafer spin cleaning on the wafer (W) after polishing are performed.

[0050] In this embodiment, by carrying out the above-described method for manufacturing a silicon wafer (steps S1 to S8), a wafer (W) with suppressed BMD precipitation can be obtained from a single-crystal silicon ingot in which atomic vacancies are predominantly present.

[0051] In addition, the single-crystal silicon ingot is not limited to those grown by the CZ method; for example, it is also possible to use a single-crystal ingot grown by the FZ method. Furthermore, the dissolved oxygen concentration of the wafer (W) before the first RTO is 1.0 × 10⁻⁶ to maintain a high dissolved oxygen concentration after RTO. 18 / cm 3 At least 1.5×10 18 / cm 3 It is desirable that it be less than or equal to this range, but it is not specifically limited to this range.

[0052] <Detailed Explanation of Stage 2 RTO>

[0053] Below, the first and second RTOs will be explained in more detail.

[0054] <1st RTO>

[0055] By performing RTP (RTO) in an oxidizing atmosphere, interstitial silicon is injected into the wafer surface layer due to oxidation of the wafer surface, and since the interstitial silicon becomes supersaturated, the vacancy-oxygen complex (VO) on the wafer surface layer x ) or voids (61) are eliminated. Also, because the oxygen concentration on the wafer surface increases, the oxygen contained in the inner wall oxide film formed on the inner wall of the COP or voids present on the wafer surface becomes difficult to dissolve into the wafer, making it difficult to reduce the grown-in defects on the wafer surface, but this area is removed by polishing, etc., that is done later.

[0056] It is preferable that the oxygen partial pressure in an oxidizing atmosphere be 25% or higher and 100%. Furthermore, to further promote oxidation of the wafer surface, it is particularly preferable to have an oxidizing atmosphere with an oxygen partial pressure of 100%. Additionally, oxygen gas is suitably used as the oxidizing atmosphere, and it is preferable to use an inert gas such as argon gas to adjust the partial pressure of this oxygen.

[0057] <1st heating rate, 1st maximum temperature reached, 1st holding time, 1st cooling rate>

[0058] As shown in FIG. 3, a wafer (W) maintained at a desired temperature (T0) (e.g., 500°C) is heated to a first maximum temperature (T1). At this time, the first heating rate (△Tu1) is, It is preferable that the first heating rate (△Tu1) be between 10℃ / s and 150℃ / s. If the first heating rate (△Tu1) is less than 10℃ / s, it is not desirable because there is a possibility that oxygen precipitation nuclei, which are glow defects (voids (61), etc.), will grow into BMDs before they are extinguished. In addition, if the first heating rate (△Tu1) exceeds 150℃ / s, it is not desirable because there is a risk that slip will occur on the wafer (W) due to the inability to withstand the rapid temperature change.

[0059] The first maximum reached temperature (T1) is, It is preferable that the temperature be between 1300℃ and 1380℃. If the first maximum reached temperature (T1) is less than 1300℃, the vacancy-oxygen complex (VO₂) x ) or voids (61) are difficult to eliminate, and if the temperature is higher than 1380℃, the wafer surface sublimes, so it is not desirable. Also, the first maximum reachable temperature (T1) mentioned here is, In the case where a wafer (W) is installed in the RTP device (10), the average temperature of multiple points on the wafer surface in the wafer diameter direction at the bottom of the wafer (e.g., the average temperature of 9 points) is measured by a radiation thermometer (not shown) placed around the wafer holding part (30) that holds the wafer (W).

[0060] The first retention time (t1) is, It is desirable that it be 5 seconds or longer. If the first maintenance time (t1) is less than 5 seconds, the vacancy-oxygen complex (VO₂) x It is undesirable because there is a possibility that ) or voids (61) may remain. Also, it is undesirable if it exceeds 40 seconds because there is a risk of slipping. The first holding time (t1) is, It is particularly desirable that it be between 10 and 30 seconds.

[0061] The first cooling rate (△Td1) is, It is preferable that the first cooling rate (△Td1) be 25℃ / s or higher and 120℃ / s or lower. If the first cooling rate (△Td1) exceeds 120℃ / s, it is not desirable because slip is likely to occur on the wafer (W) due to thermal stress. In addition, if the first cooling rate (△Td1) is less than 25℃ / s, it is not desirable because there is a possibility that metal impurities (e.g., Ni) that are mixed into the wafer, even in small amounts, may precipitate as silicide near the surface.

[0062] <2nd RTO>

[0063] By performing RTP (RTO) in an oxidizing atmosphere, interstitial silicon is injected into the wafer surface layer through oxidation of the wafer surface, and the dominant point defect species becomes interstitial silicon.

[0064] It is preferable that the oxygen partial pressure in an oxidizing atmosphere be 25% or higher and 100%. Furthermore, to further promote oxidation of the wafer surface, it is particularly preferable to have an oxidizing atmosphere with an oxygen partial pressure of 100%. Additionally, oxygen gas is suitably used as the oxidizing atmosphere, and it is preferable to use an inert gas such as argon gas to adjust the partial pressure of this oxygen.

[0065] <Second heating rate, second maximum temperature reached, second holding time, second heating rate>

[0066] As shown in FIG. 3, a wafer (W) maintained at a desired temperature (T0) (e.g., 500°C) is heated to a second maximum temperature (T2). At this time, the second heating rate (△Tu2) is, It is preferable that the second heating rate (△Tu2) be between 10℃ / s and 150℃ / s. If the second heating rate (△Tu2) is less than 10℃ / s, it is not desirable because there is a possibility that voids formed by aggregated atomic vacancies will promote the formation of oxygen precipitation nuclei and grow into BMDs before the remaining atomic vacancies are eliminated. In addition, if the second heating rate (△Tu2) exceeds 150℃ / s, it is not desirable because there is a risk that slip will occur on the wafer (W) due to the inability to withstand the rapid temperature change.

[0067] The second highest temperature reached (T2) is, It is preferable that the temperature be 1050°C or higher and less than 1300°C. If the second maximum temperature reached (T2) is less than 1050°C, it is difficult for atomic vacancies remaining in the bulk region to disappear, and if it is 1300°C or higher, it is not desirable because vacancies become more dominant and the vacancies increase. In addition, the second maximum temperature reached (T2) mentioned here is the average temperature of multiple points within the wafer surface in the wafer diameter direction at the bottom of the wafer (e.g., the average temperature of 9 points) measured by a radiation thermometer (not shown), just like the first RTO.

[0068] The second retention time (t2) is, It is desirable that the second holding time (t2) be between 5 seconds and 30 seconds. If the second holding time (t2) is less than 5 seconds, it is not desirable because there is a possibility that atomic vacancies will remain. Also, if it exceeds 30 seconds, it is not desirable because it becomes susceptible to metal contamination by the RTP device (10).

[0069] The second cooling rate (△Td2) is, It is preferable that the second cooling rate (△Td2) be 25℃ / s or higher and 120℃ / s or lower. If the second cooling rate (△Td2) exceeds 120℃ / s, it is not desirable because slip is likely to occur on the wafer (W) due to thermal stress. In addition, if the second cooling rate (△Td2) is less than 25℃ / s, it is not desirable because there is a possibility that metal impurities (e.g., Ni) that are mixed into the wafer, even in small amounts, may precipitate as silicide near the surface.

[0070] In addition, when performing the second stage of RTO, the oxygen concentration near the surface of the wafer (W) rises to the thermal equilibrium concentration, so there is a possibility that glow defects may remain. For this reason, after the second stage of RTO, polishing (step S7) of, for example, 1 μm to 10 μm is performed from the surface of the wafer (W).

[0071] Silicon Wafer

[0072] In the method for manufacturing a silicon wafer according to the present embodiment, atomic vacancies in the surface layer and bulk region of the wafer (W) are eliminated by performing a two-stage RTO with an oxide film peeling process in between. As a result, the wafer (W) produced by the method for manufacturing a silicon wafer according to the present embodiment (steps S1 to S8) has a defect density of 20 nm or more observed by IR tomography of 1×10⁻⁶ when maintained at 780°C for 3 hours in an oxidizing atmosphere and then maintained at 1000°C for 16 hours. 8 / cm 3 You can do it less.

[0073] In addition, in IR tomography, laser light is irradiated from the wafer surface to collide with defects contained in the wafer (W), and defects contained in the wafer (W) can be detected by detecting the scattered light. The defects detected by this method are not limited to BMDs, and it is possible to detect void defects, etc., as long as they are larger than a threshold size.

[0074] <Effects, etc.>

[0075] As described above, the method for manufacturing a silicon wafer according to the present embodiment comprises a silicon wafer (W) grown by the CZ method, which is sliced ​​and flattened, and a first RTO (first heat treatment process) in which the silicon wafer (W) is heated to a first maximum temperature of 1300°C or higher and 1380°C or lower under an oxidizing atmosphere with an oxygen partial pressure of 25% to 100%, and maintained at the first maximum temperature for 5 seconds or more; an oxide film stripping process in which the silicon wafer (W) obtained by the first RTO is cleaned with hydrofluoric acid; and a second RTO (second heat treatment process) in which the silicon wafer (W) obtained by the oxide film stripping process is heated to a second maximum temperature of 1050°C or higher and less than 1300°C under an oxidizing atmosphere with an oxygen partial pressure of 25% to 100%, and maintained at the second maximum temperature for 5 seconds or more.

[0076] According to the method for manufacturing a silicon wafer of the present embodiment, the vacancy-oxygen complex (VO₂) x By performing a first RTO to eliminate ) or voids (61) and increasing the atomic void elimination effect, and by performing an oxide film peeling process to remove metal contamination from the silicon wafer (W) by the RTP device (10), and by performing a second RTO to eliminate atomic voids remaining in the bulk region, a silicon wafer (W) with BMD precipitation effectively suppressed can be obtained while avoiding the risk of metal contamination.

[0077] In addition, in the method for manufacturing a silicon wafer according to the present embodiment, it is preferable to further perform a polishing process to polish the surface and surface layer of the silicon wafer (W) obtained by the second RTO. In addition, it is particularly preferable that the oxygen partial pressure in an oxidizing atmosphere is 100% in the first and second RTOs. In addition, in the oxide film stripping process, it is preferable to clean the surface of the silicon wafer (W) obtained by the first RTO with an aqueous solution of hydrofluoric acid at a concentration of 10% or more for at least 10 seconds. In addition, the oxygen concentration of the silicon wafer (W) prior to the first RTO is 1.0 × 10⁻⁶. 18 / cm 3 ~1.5×10 18 / cm 3 It is desirable that it is.

[0078] Furthermore, the present invention is not limited to the embodiments described above. The above embodiments are examples, and all having substantially the same configuration as the technical concept described in the claims and exhibiting the same functional effects are included within the technical scope of the present invention.

[0079] [Example]

[0080] Next, a method for manufacturing a silicon wafer according to the present invention will be further explained based on examples. Furthermore, the present invention is not limited by the following examples.

[0081] <Reference Examples, Comparative Examples, Examples>

[0082] The method for manufacturing a silicon wafer according to the present invention shown in FIG. 2 (steps S1 to S8) was carried out, that is, after performing a slicing process and a processing process by a known method, the manufacturing process shown in Table 1 below was carried out according to the following manufacturing conditions, and also a polishing process and a cleaning process were carried out by a known method, and a wafer with a diameter of 300 mm was prepared for each comparative example and example. In addition, the RTO of Reference Example 2 was carried out under the same conditions as the first RTO heat treatment, except that the maximum temperature reached was 1350°C.

[0083]

[0084] In addition, the manufacturing conditions are shown below.

[0085] (Decision condition)

[0086] · Oxygen concentration: 1.08–1.25 × 10⁻⁶ 18 / cm 3

[0087] · Nitrogen concentration: 3.84–5.16 × 10⁻⁶ 14 / cm 3

[0088] · N-type determination

[0089] · Atomic public dominance

[0090] (Heat treatment conditions for the 1st RTO)

[0091] Oxidizing atmosphere with 100% oxygen partial pressure

[0092] · 1st maximum reachable temperature (T1): 1300℃

[0093] · First heating rate (△Tu1): 50℃ / s

[0094] · First hold time (t1): 30 seconds

[0095] · First cooling rate (△Td1): 120℃ / s

[0096] (Oxide film peeling conditions)

[0097] · Clean the wafer surface with 15% HF for 12 seconds before the 2nd RTO (after the 1st RTO).

[0098] (Heat treatment conditions for the 2nd RTO)

[0099] Oxidizing atmosphere with 100% oxygen partial pressure

[0100] · Second maximum reached temperature (T2): 1090–1250°C (see Table 1)

[0101] · Second heating rate (△Tu2): 50℃ / s

[0102] · Second hold time (t2): 30 seconds

[0103] · Second cooling rate (△Td2): 120℃ / s

[0104] <Evaluation>

[0105] Wafers manufactured according to reference examples, comparative examples, and examples were evaluated under the following evaluation conditions. Specifically, BMD precipitation heat treatment was performed twice according to the following BMD precipitation heat treatment conditions, and a defect density of 20 nm or more was evaluated using IR tomography, which is an evaluation device.

[0106] (BMD precipitation heat treatment conditions)

[0107] Oxidizing atmosphere with 100% oxygen partial pressure

[0108] · Heating temperature: 780℃ and holding time: 3 hours

[0109] · Heating temperature: 1000℃ and holding time: 16 hours

[0110] (Evaluation device)

[0111] ·IR Tomography: LST2500HD

[0112] · Laser output: 10mW

[0113] Figure 5 shows a defect density of 20 nm or more observed by IR tomography. In addition, Figure 6 shows an image of a wafer cross-section at a depth of 350 μm from the wafer surface.

[0114] According to FIG. 5, the defect density of Reference Examples 1 and 2 is the highest, and the defect density is approximately 7×10 9 / cm 3 In addition, according to the image in Fig. 6, in Reference Example 1, defect points are evenly distributed from directly below the wafer surface (see dotted line). Also, looking at the image of Reference Example 2, no defects are visible near the wafer surface (see dotted line), but many defects are visible in the bulk region. This captures BMD precipitates during crystal growth, or BMD precipitates of atomic vacancy origin introduced by RTO performed only once.

[0115] Next, looking at the results of Comparative Example 1 (2nd maximum reached temperature (T2): 1090°C), Comparative Example 2 (2nd maximum reached temperature (T2): 1150°C), Comparative Example 3 (2nd maximum reached temperature (T2): 1250°C) in which the 2nd RTO was performed, as well as Example 1 (2nd maximum reached temperature (T2): 1090°C), Example 2 (2nd maximum reached temperature (T2): 1150°C), and Example 3 (2nd maximum reached temperature (T2): 1250°C), Examples 1 to 3, in which the oxide film stripping process was performed, tend to have lower defect densities compared to Comparative Examples 1 to 3, and all are 1×10⁻⁶ 8 / cm 3 It was found that it was lower. In addition, looking at the defect images, the defects shown in Comparative Examples 1 to 3 were significantly reduced, indicating that BMD precipitation was effectively suppressed by the first RTO and oxide film stripping process and the second RTO process. Explanation of the symbols

[0116] 10 RTP devices 20 reaction chambers 20a First space 20b Second space 22 supply port 26 outlets 30 wafer holding section 32 susceptors 34 rotational bodies 40 heating section 50 halogen lamps 61 Void 62a, 62b oxide film W wafer (silicon wafer)

Claims

Claim 1 A method for manufacturing a silicon wafer, characterized by comprising: a first heat treatment process in which a silicon wafer, obtained by slicing and flattening a single-crystal silicon ingot grown by the CZ method, is heated to a first maximum temperature of 1300°C or higher and 1380°C or lower under an oxidizing atmosphere having an oxygen partial pressure of 25% to 100%, and maintained at the first maximum temperature for 5 seconds or more; an oxide film stripping process in which the silicon wafer obtained by the first heat treatment process is cleaned with hydrofluoric acid; and a second heat treatment process in which the silicon wafer obtained by the oxide film stripping process is heated to a second maximum temperature of 1050°C or higher and less than 1300°C under an oxidizing atmosphere having an oxygen partial pressure of 25% to 100%, and maintained at the second maximum temperature for 5 seconds or more. Claim 2 A method for manufacturing a silicon wafer according to claim 1, further comprising a polishing process for polishing the surface and surface layer of the silicon wafer obtained by the second heat treatment process. Claim 3 A method for manufacturing a silicon wafer according to claim 1, characterized in that, in the first heat treatment process and the second heat treatment process, the oxygen partial pressure in the oxidizing atmosphere is 100%. Claim 4 A method for manufacturing a silicon wafer according to claim 1, wherein in the oxide film peeling process, the surface of the silicon wafer obtained by the first heat treatment process is cleaned with an aqueous solution of hydrofluoric acid at a concentration of 10% or more for 10 seconds or more. Claim 5 In claim 1, the oxygen concentration of the silicon wafer prior to the first heat treatment process is 1.0 × 10⁻⁶ 18 / cm 3 ~1.5×10 18 / cm 3 A method for manufacturing a silicon wafer characterized by being Claim 6 A silicon wafer subjected to two stages of Rapid Thermal Oxidation (RTO) with an intermediate process for peeling off the oxide film formed on the surface, wherein when maintained at 780°C for 3 hours in an oxidizing atmosphere followed by maintaining at 1000°C for 16 hours, the defect density of 20 nm or larger observed by IR tomography is 1×10⁻⁶ 8 / cm 3 Silicon wafer characterized by being lower.

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