Processor for in-memory computing

Abstract

In-memory computing, IMC, processor, comprising a set of IMC banks that is grouped into a plurality of IMC processing stages, each of the IMC processing stages including either one IMC bank or two or more IMC banks in a parallel configuration. The IMC processing stages are each configured, in a given processing cycle of a temporal sequence of processing cycles, to receive a digital input data vector, and to process, using a respective set of weight data stored in the IMC banks of the respective IMC processing stage, the currently received input data vector to generate and pro-vide a respective fraction of an output data vector. The IMC pro-cessor is configured to process any given input data vector using the set of IMC processing stages in a sequential processing order, the sequential processing order for the given input data vector advancing within the set of IMC banks one IMC processing stage per processing cycle of the temporal sequence of processing cycles.