Semiconductor circuit structure

Abstract

A semiconductor circuit structure is provided. The semiconductor circuit structure includes a semiconductor substrate having a raw semiconductor surface, a set of transistors formed on the semiconductor substrate, a first STI region adjacent to the set of transistors and extending along a first direction, a large STI region away from the set of transistors, a first under-surface interconnect within the first STI region and located below the raw semiconductor surface, and a first under-surface interconnect pad electrically coupled to the first under-surface interconnect. Each transistor includes a gate structure, a first conductive region, and a second conductive region. The first under-surface interconnect extends along the first direction. The first under-surface interconnect pad is located within the large STI region and below the raw semiconductor surface. The width of the first under-surface interconnect pad is greater than the width of the first under-surface interconnect.

Description

Semiconductor circuit structure This disclosure relates to semiconductor structures, and more particularly to semiconductor circuit structures. In state-of-the-art integrated circuits, numerous transistors are interconnected via conductive interconnects to facilitate signal transmission between their gate, source, and drain (GSD) regions. These interconnects, such as metal wires and polysilicon wires, connect the gate, source, and drain regions of multiple transistors through numerous vias and connectors. This presents significant challenges and difficulties for chip design goals such as minimizing area, reducing power consumption, lowering noise, and improving integrated circuit performance. For example, regarding area loss: the size of the source or drain diffusion region must be designed to be larger than the size of the vias used to connect the conductive interconnects to the source or drain region to avoid unavoidable lithography misalignment due to limitations of lithography equipment, which would cause the vias to form outside the lower edge of the source or drain region. This inevitably increases the transistor diffusion area, thus increasing the chip area and resulting in large capacitance. Large capacitance severely impacts the circuit's AC performance, consumes more power, and increases noise. Therefore, introducing better self-aligned contact structures and technologies to connect transistors to a first interconnect (metal) layer with a smaller surface area for transmitting and receiving signals is a key challenge for effectively reducing the size of integrated circuits and improving their performance. Furthermore, the single-crystal integration capability of silicon wafers has evolved from GSI (gigabit integration: over a billion transistors integrated on a single chip) to TSI (trillion-bit integration: trillions of transistors integrated on a single chip). Operating such a large number of transistors leads to a sharp increase in power consumption. Due to the limited existing heat dissipation capabilities, the increased power consumption adversely raises the junction temperature of the transistors, thereby increasing the overall temperature of the wafer. Silicon dioxide has a very low thermal conductivity, and silicon itself does not have a very high thermal conductivity. This material and device structure problem creates a negative cycle effect; that is, increasing the wafer temperature reduces the speed of the transistors, which inevitably necessitates designs that increase the circuitry to higher power to accelerate transistor performance. However, this mechanism leads to a significant increase in wafer temperature, thus exacerbating the heat dissipation problem. The problem of insufficient heat dissipation leading to high wafer operating temperatures is considered one of the worst problems that the entire chip industry needs to solve, a major obstacle to avoiding the integration of a large number of devices on a single chip. However, the cooling of GSI wafers has not been adequately improved. In fact, as technology nodes shrink further, transistor sizes must become smaller (e.g., the minimum feature size shrinks from 7nm to 5nm, then to 3nm, etc.), the proportion of oxide coverage relative to the total transistor size is increasing, and the heat dissipation capacity of the device junction is becoming more concentrated. Although many heat dissipation methods exist, such as covering the entire wafer with a thermally removed pad for better heat dissipation or using liquid cooling circulation outside the packaged wafer, these methods are very expensive and inefficient and cannot effectively reduce the transistor junction temperature. The embodiments disclosed herein provide a semiconductor circuit structure. The semiconductor circuit structure includes a semiconductor substrate having a pristine semiconductor surface, a set of transistors formed on the semiconductor substrate, a first shallow trench isolation (STI) region adjacent to the set of transistors and extending along a first direction, a large shallow trench isolation (STI) region distant from the set of transistors, a first underground interconnection line within the first STI region and located below the pristine semiconductor surface, and a first underground interconnection pad electrically coupled to the first underground interconnection line. Each transistor includes a gate structure, a first conductive region, and a second conductive region. The first underground interconnection line extends along the first direction. The first underground interconnection pad is located within the large STI region and below the pristine semiconductor surface. The width of the first underground interconnection pad is greater than the width of the first underground interconnection line. According to one aspect of this disclosure, the first under-surface interconnect pad is directly connected to the first under-surface interconnect line. According to one aspect of this disclosure, the semiconductor circuit structure further includes a through semiconductor via (TSV) extending from the bottom surface of the first under-surface interconnect pad to the backside surface of the semiconductor substrate, wherein the TSV is electrically connected to the first under-surface interconnect pad and is configured to transmit a power signal or a data signal from the backside surface of the semiconductor substrate to the first under-surface interconnect pad, the backside surface being relative to the original semiconductor surface. According to one aspect of this disclosure, the first conductive region of the first transistor in the group of transistors is electrically connected to the first under-surface interconnect via a connecting plug. The connecting plug is located in the active area that houses the first transistor. Power signals or data signals are transmitted to the first transistor via the first under-surface interconnect pad, the first under-surface interconnect, and the corresponding connecting plug. According to one aspect of this disclosure, the connecting plug contacts the sidewall of the interconnect below the first surface. According to one aspect of this disclosure, both the first under-surface interconnect pad and the first under-surface interconnect line contain tungsten (W) and titanium nitride (TiN). According to one aspect of this disclosure, the TSV comprises a copper pillar. According to one aspect of this disclosure, the semiconductor circuit structure further includes a conducting pad located near the back side of the semiconductor substrate and connected to the TSV. According to one aspect of this disclosure, the semiconductor circuit structure further includes a second shallow trench isolation (STI) region remote from the set of transistors, and a second under-surface interconnect within the second STI region and located below the original semiconductor surface, wherein the second under-surface interconnect extends along a second direction different from the first direction, and the second under-surface interconnect connects to the first under-surface interconnect. According to one aspect of this disclosure, the semiconductor circuit structure further includes a second shallow trench isolation (STI) region remote from the set of transistors, and a second under-surface interconnect within the second STI region and located below the original semiconductor surface, wherein the second under-surface interconnect extends along a second direction different from the first direction, and the second under-surface interconnect connects to the first under-surface interconnect pad. According to one aspect of this disclosure, the semiconductor circuit structure further includes a plurality of metal layers located above the original semiconductor surface and vertically separated from each other, and a plurality of connecting vias above the original semiconductor surface and electrically connected to the plurality of metal layers, wherein a first conductive region of a first transistor in the group of transistors is electrically connected to a first under-surface interconnect pad through the plurality of metal layers and the plurality of connecting vias. According to one aspect of this disclosure, the semiconductor circuit structure further includes a plurality of metal layers located above the original semiconductor surface and vertically separated from each other, a plurality of vias electrically connected to the plurality of metal layers above the original semiconductor surface, and a second under-surface interconnect pad located below the original semiconductor surface, wherein the width of the second under-surface interconnect pad is greater than the width of the first under-surface interconnect line, and the first under-surface interconnect pad is electrically connected to the second under-surface interconnect pad through the plurality of metal layers and the plurality of vias. Another embodiment of this disclosure provides a semiconductor circuit structure. The semiconductor circuit structure includes: a semiconductor substrate having a pristine semiconductor surface; a set of transistors formed on the semiconductor substrate; a first shallow trench isolation (STI) region adjacent to the set of transistors and extending along a first direction; a second shallow trench isolation (STI) region away from the set of transistors; a large shallow trench isolation (STI) region away from the set of transistors; a first under-surface interconnect within the first STI region and located below the pristine semiconductor surface; a second under-surface interconnect within the second STI region and located below the pristine semiconductor surface; and a first under-surface interconnect pad located within the large STI region and located below the pristine semiconductor surface. The first under-surface interconnect extends along the first direction. The second under-surface interconnect extends along a second direction different from the first direction. The second under-surface interconnect connects to the first under-surface interconnect or the first under-surface interconnect pad. According to one aspect of this disclosure, the width of the first surface under interconnect pad is greater than the width of the first surface under interconnect line. According to one aspect of this disclosure, a first under-surface interconnect pad connects to a first under-surface interconnect line. According to one aspect of this disclosure, the semiconductor circuit structure further includes a third shallow trench isolation (STI) region remote from the set of transistors, and a third under-surface interconnect within the third STI region and located below the original semiconductor surface, wherein the third under-surface interconnect extends along a first direction, and a second under-surface interconnect is located between the first under-surface interconnect and the third under-surface interconnect and connects the first under-surface interconnect and the third under-surface interconnect. Another embodiment of this disclosure provides a semiconductor circuit structure. The semiconductor circuit structure includes a semiconductor substrate having a pristine semiconductor surface, a set of transistors formed on the semiconductor substrate, a first shallow trench isolation (STI) region adjacent to the set of transistors and extending along a first direction, a large shallow trench isolation (STI) region away from the set of transistors, a first under-surface interconnect within the first STI region and located below the pristine semiconductor surface, a first under-surface interconnect pad electrically coupled to the first under-surface interconnect, and a semiconductor via (TSV) within the large STI region and connecting the first under-surface interconnect pad. Each transistor includes a gate structure, a first conductive region, and a second conductive region. The first under-surface interconnect extends along the first direction. The first under-surface interconnect pad is located within the large STI region and below the pristine semiconductor surface. According to one aspect of this disclosure, a large STI region extends from the edge of the first STI region, and a first under-surface interconnect pad is directly connected to the first under-surface interconnect. According to one aspect of this disclosure, the TSV extends from the bottom surface of the first under-surface interconnect pad to the back surface of the semiconductor substrate. The TSV is assembled to transmit power signals or data signals from the back surface of the semiconductor substrate to the first under-surface interconnect pad, with the back surface relative to the original semiconductor surface. According to one aspect of this disclosure, the first conductive region of the first transistor in the group of transistors is electrically connected to the first under-surface interconnect via a connecting plug. The connecting plug is located in the active region accommodating the first transistor, and power signals or data signals are transmitted to the first transistor via the first under-surface interconnect pad, the first under-surface interconnect, and the corresponding connecting plug. According to one aspect of this disclosure, the connecting plug contacts the sidewall of the interconnect below the first surface. According to one aspect of this disclosure, the semiconductor circuit structure further includes a conductive pad located near the back side of the semiconductor substrate and connected to the TSV. The above-described embodiments and other embodiments disclosed herein will be better understood through the following detailed description of non-limiting embodiments. The description is based on the accompanying drawings. Various embodiments will be described more fully below with reference to the accompanying drawings, and this description is for illustrative purposes only and not as limiting. For clarity, elements may not be drawn to scale. Furthermore, some elements and / or element symbols may be omitted in certain drawings. It is contemplated that elements and features of one embodiment may be advantageously incorporated into another embodiment without further explanation. In the methods for manufacturing a semiconductor device described below, one or more additional operations may exist between the described operations, and the order of operations may be changed. The same / similar element symbols are used in the drawings to denote the same / similar elements. The ordinal numbers used to modify elements in the specification and claims, such as "first," "second," etc., do not imply or represent a specific position, arrangement, or manufacturing order within the structure. These ordinal numbers are merely used to clearly distinguish multiple elements with the same name. Spatial terms used in the specification and claims, such as "above," "over," "above," "higher than," "top," "below," "below," "below," "lower than," "bottom," etc., describe the relative spatial or positional relationship between one element and another in the drawings, and unless otherwise specified, these spatial or positional relationships may be direct or indirect (there may be no or other elements disposed between the two elements). Spatial terms may cover structures shown in other orientations, not limited to the orientation shown in the drawings. Structures may be flipped or rotated at various angles, and the spatial terms used herein may be interpreted accordingly. Furthermore, the terms "electrical connection" and "electrical coupling" used in the specification and claims can represent multiple components forming an ohmic contact, or current flowing between multiple components, or multiple components having an operational relationship. An operational relationship can be, for example, one component driving another component, but current may not flow directly between the two components. This disclosure focuses on semiconductor circuit structures including underground interconnection (UGI) structures within a semiconductor substrate. UGI structures are used for signal transmission and / or heat dissipation. UGI structures can be fabricated in monolithic integrated circuit processes. The UGI structure may include underground interconnect lines (UGI lines), underground interconnect pads (UGI pads), etc. The underground interconnect structure within the semiconductor substrate forms a mid-side signal network and / or heat dissipation network, which can improve the performance of the integrated circuit. Traditional semiconductor circuit structures on semiconductor substrates have numerous active regions (AA) and shallow trench isolation (STI) regions surrounding these active regions, with multiple transistors or circuit elements located within the active regions, as shown in Figure 1. However, the STI regions in a semiconductor substrate may occupy 40% or more of the total area of ​​the semiconductor substrate, and these STI regions do not provide any special function other than isolation. On the other hand, Figure 2A illustrates a schematic top view of a semiconductor circuit structure 10 according to some embodiments of the present disclosure. Figure 2B is a schematic cross-sectional view of the semiconductor circuit structure 10 drawn along section line BB' of Figure 2A. Figure 2C is a schematic cross-sectional view of the semiconductor circuit structure 10 drawn along section line CC' of Figure 2A. As shown in Figures 2A to 2C, the semiconductor circuit structure 10 of the present invention includes a semiconductor substrate 100 having a pristine semiconductor surface 100S. The semiconductor substrate 100 includes one or more active regions 10A and one or more shallow trench isolation (STI) regions 114. The plurality of STI regions 114 surround the plurality of active regions 10A, and the active regions 10A are separable from each other by the plurality of STI regions 114. Before forming a transistor, a pad oxide layer 104 and a pad nitride layer 106 are formed to define or protect the active regions 10A. According to the present invention, one or more subsurface interconnect structures are provided in a plurality of STI regions 114 to replace a portion of the original isolation material (e.g., oxide) in the STI region 114. These subsurface interconnect structures can provide a predetermined function that differs from the isolation function of the original STI region 114. This UGI structure is essentially an "intermediate connector" in the substrate, and the aforementioned composite STI region containing the original isolation material and the UGI structure can be considered as heterogeneous STI (HSTI). In one embodiment, the UGI structure includes a UGI element 105 (e.g., a conductive material or other suitable material) and a barrier layer 107. The barrier layer 107 covers the bottom surface and / or sidewalls of the UGI element 105. In some embodiments, the barrier layer 107 shown in Figures 2A to 2C may be omitted; that is, the UGI structure may not include the barrier layer 107. The UGI structure is located below the original semiconductor surface 100S. Moreover, the UGI structure is formed within an STI region 114. For example, as shown in Figure 2B, the UGI element 105 is sandwiched between the materials of the STI region 114. In this embodiment, the UGI structure extends along the X direction, and the STI region 114 also extends along the X direction. In this case, the UGI structure or UGI element may be a UGI line. In one example, a UGI structure or UGI element within and extending along the STI region 114 can be connected to the source or drain terminals of a transistor via a self-aligned or self-constructed method and a connector plug within the active region 10A. The connector plug connects to the sidewalls of the UGI structure. The UGI structure within STI region 114 can be used for signal transmission (including power signals and data signals) and / or heat dissipation. For signal transmission, UGI element 105 may contain metal (or may be made of metal), such as tungsten, and barrier layer 107 may contain titanium nitride (or may be made of titanium nitride). UGI element 105 is not limited to a specific type of metal material; there are other suitable metal layers that can be used for UGI element 105. For heat dissipation, UGI element 105 may contain materials with a higher thermal conductivity than the original insulating material (e.g., oxide) in STI region 114, such as aluminum nitride (AlN), boron nitride (BN), silicon carbide (SiC), metals, etc. Figure 2D illustrates a schematic top view of a semiconductor circuit structure 20 according to an embodiment of the present disclosure. The semiconductor circuit structure 20 may be formed within a semiconductor wafer or substrate. Figure 2D shows additional active regions 20A, STI regions 20B, and a pad open layer 20C for accommodating contact pads of the semiconductor circuit structure 20. Some large STI regions 224-1 to 224-4 in the STI regions 20B may be located in corner regions adjacent to the periphery / edge region of the semiconductor wafer, or in a central spare region of the wafer. Large UGI structures (e.g., UGI pads) 209 are located within the large STI regions 224-1 to 224-4 and below the original semiconductor surface of the semiconductor substrate. Furthermore, other thin or long UGI structures (e.g., UGI lines) 204 are located below the original semiconductor surface of the semiconductor substrate and are formed within those thin or long STI regions 214-1 to 214-4 in the STI regions 20B. UGI structure 205 and STI regions 214-1 to 214-4 may extend along the X direction (or along the length of the active region). Furthermore, UGI structure 205 may extend beyond two or more active regions 20A. For example, UGI structure 205 located in the upper right portion of Figure 2D extends from a predetermined point in STI region 214-1 adjacent to active region 20A-1 to large STI region 224-1. In Figure 3, on one side of the STI region 214-1, there is a first set of active regions extending along the X direction; on the other side of the STI region 214-1, there is a second set of active regions extending along the X direction. Thus, the STI region 214-1 is situated between the first and second sets of active regions and extends along the X direction. Furthermore, the VHDC structure 205 within the STI region 214-1 is also situated between the first and second sets of active regions and extends along the X direction. In one embodiment, the minimum size and / or maximum width (e.g., along the Y direction) of the VHDC structure 205 situated between the first and second sets of active regions is smaller than the width of the VHDC structure 209 connecting the VHDC structure 205. Each of STI regions 214-1 to 214-4 may be adjacent to a group of transistors in active region 20A, and the large STI region 224-1 may be located away from this group of transistors. UGI structure 205 is electrically coupled to or directly connected to UGI structure 209. Each of UGI structures 205 and 209 may include a UGI element and a barrier layer, as shown in Figures 2A to 2C. In some embodiments, UGI structures 205 and 209 may not include a barrier layer. The width of the large STI region 224-1 along the Y direction is greater than the width of the STI region 214-1 along the Y direction. The width of the UGI structure 209 along the Y direction is greater than the width of the UGI structure 205 along the Y direction. For example, the width of the UGI structure 209 along the Y direction can be approximately 2. m (micrometers) to approximately 8 The width of the UGI structure 205 along the Y direction can be between approximately 10 nm and approximately 100 nm. The area of ​​the UGI structure 209 can be between approximately 4 nm. m 2 To approximately 50 m 2 Between. For signal transmission, UGI structures 205 and 209 may contain metal (or may be made of metal), such as tungsten. The materials of UGI structures 205 and 209 may be the same or different. Large STI areas 224 can form additional alignment marks for the rear signal / power delivery network and the rear TSV (Through Silicon Via), that is, signal / power is delivered from the rear of the active area to the active area, as shown in Figure 2E. Those large STI areas 224 can also form additional alignment marks for the front signal / power delivery network and the front TSV, that is, signal / power is delivered from the front of the active area to the active area. In other embodiments, the UGI structure may extend in a direction other than the X direction, as shown in Figure 3. Figure 3 is a schematic top view illustrating a semiconductor circuit structure 30 according to some embodiments of the present disclosure. Compared to the semiconductor circuit structure 20 shown in Figure 2D, the semiconductor circuit structure 30 shown in Figure 3 further includes STI regions 314-1, 314-2, and 314-3, and UGI structures 305-1, 305-2, and 305-3 extending along the Y direction. The UGI structures 305-1, 305-2, and 305-3 are located below the original semiconductor surface of the semiconductor substrate and are formed within the STI regions 314-1, 314-2, and 314-3, respectively. The UGI structures 305-1, 305-2, and 305-3 may be UGI lines. UGI structures 305-1, 305-2, and 305-3, and STI regions 314-1, 314-2, and 314-3 may extend along the Y direction (or along the width direction of the active region). Furthermore, UGI structures 305-1, 305-2, and 305-3 may extend beyond two or more active regions 20A. For example, UGI structure 305-1, located in the upper left portion of Figure 3, extends from a predetermined point of STI region 314-1 adjacent to active region 20A-2 to horizontal STI region 214. Each of STI regions 314-1, 314-2, and 314-3 may be adjacent to a set of transistors in the active regions 20A. In Figure 3, UGI structures extending in directions other than the X direction may be connected (or electrically coupled) to UGI structures extending in the X direction and / or to UGI pads within the large STI region. For example, UGI structure 305-1 is connected (or electrically coupled) to UGI structure 205; UGI structure 305-2 is connected (or electrically coupled) to multiple UGI structures 205 and is located between these two UGI structures 205; UGI structure 305-3 is connected (or electrically coupled) to UGI pads 209 within the large STI region 224. The dimensions and materials of UGI structures 305-1, 305-2, and 305-3 may be similar to those of UGI structure 205. Each of UGI structures 305-1, 305-2, and 305-3 may contain UGI elements (or further contain barrier layers), as shown in Figure 1. By configuring UGI structures / lines extending along the X direction, UGI structures / lines extending along the Y direction (or directions other than the X direction), and UGI pads in the large STI region, a UGI network (or Mid-Side Signal Network) can be provided within a wafer or semiconductor substrate and located below the original semiconductor surface of the semiconductor substrate. UGI structures extending along the X direction (i.e., horizontal UGI lines) can be used to connect UGI structures (i.e., UGI pads) in the large STI region or the source / drain of transistors in the active region, while UGI structures extending along the Y direction (i.e., vertical UGI lines) can be used to connect UGI pads or horizontal UGI lines. 1. based on UGI intermediate signal power network Figures 4 through 6 relate to intermediate signal / power networks based on UGI structures. For the configuration of UGI structures in the XY plane, please refer to the descriptions related to Figures 2 and 3. The location, size, and number of UGI structures are not limited to those shown in Figures 2 and 3. In some embodiments, a large STI region (as shown in Figures 2 and 3) may be aligned with one or more TSVs (as shown in Figure 4). Figure 4 is a schematic cross-sectional view illustrating a semiconductor circuit structure 40 according to some embodiments of the present disclosure. The semiconductor circuit structure 40 includes a semiconductor substrate 400 having a raw semiconductor surface 400S, a plurality of active regions 40A in the semiconductor substrate 400, a plurality of transistors TS formed on the semiconductor substrate 400 and in the plurality of active regions 40A, a plurality of STI regions 414, a large STI region 424, a plurality of first UGI structures within the plurality of STI regions 414, and a second UGI structure within the large STI region 424. Each transistor TS includes a first conductive region (e.g., a source) T1, a second conductive region (e.g., a drain) T2, and a gate structure T3. The first UGI structure (e.g., a UGI line) within the STI region 414 and the second UGI structure (e.g., a UGI pad) within the large STI region 424 are located below the original semiconductor surface 400S of the semiconductor substrate 400, with the first UGI structure extending along the X direction. Each first UGI structure may include a UGI element 405 and a barrier layer 407 on the bottom surface and / or sidewalls of the UGI element 405. Each second UGI structure may include a UGI element 409 and a barrier layer 407 on the bottom surface and / or sidewalls of the UGI element 409. The semiconductor circuit structure 40 further includes a plurality of connection plugs 431, which contact the sidewalls of the UGI element 405 of the first UGI structure and electrically couple the transistor TS to the first UGI structure. Power signals or data signals can be transmitted to the transistor TS through the second UGI structure, the first UGI structure, and the corresponding connection plugs 431. The connection plugs 431 are located within the active region accommodating the transistor TS. The semiconductor circuit structure 40 further includes a TSV 433 directly beneath the second UGI structure (i.e., the UGI pad), and a barrier film or isolation film 435 on the sidewall of the TSV 433. The TSV 433 is connected to the second UGI structure, which is located within the large STI region 424. The TSV 433 extends from the bottom surface of the second UGI structure to the back surface 400B of the semiconductor substrate 400. The back surface 400B is relative to the original semiconductor surface 400S. The TSV 433 can be understood as a back TSV. The TSV can be electrically connected to the second UGI structure. Power signals or data signals can be transmitted from the back surface 400B of the semiconductor substrate 400 to the second UGI structure. The TSV 433 can be connected to a back surface conductive pad 437 located on or near the back surface 400B of the semiconductor substrate 400 (or on the back surface of the wafer). The back surface conductive pad 437 can be a power signal or data signal input terminal. Thus, this disclosure provides a convenient and effective method for implementing a back surface signal transmission network. TSV 433 may contain a conductive material such as copper. TSV 433 may be or may contain copper pillars. Barrier film 435 may contain a dielectric material such as oxide. The semiconductor circuit structure 40 further includes an upper interconnect structure 440 on the semiconductor substrate 400 and a bonding layer 450 on the upper interconnect structure 440. The upper interconnect structure 440 includes a contact structure 441, metal layers M1 to M3, vias V1 and V2, and a dielectric layer 442. The contact structure 441, metal layers M1 to M3, and vias V1 and V2 are located within the dielectric layer 442, which may contain multiple dielectric layers. The contact structure 441 is located between a transistor TS and metal layer M1. Metal layers M1 to M3 are sequentially disposed above the original semiconductor surface 400S of the semiconductor substrate 400 along the Z-direction. Metal layers M1 to M3 are perpendicularly separated from each other. Vias V1 and V2 are located above the original semiconductor surface 400S of the semiconductor substrate 400. Via V1 is located between metal layers M1 and M2. Via V2 is located between metal layers M2 and M3. Metal layers M1 to M3, and connecting vias V1 and V2 are electrically connected to each other. Transistor TS is electrically coupled to metal layer M1 via contact structure 441. Power signals or data signals can be transmitted between back conductive pad 437, TSV 433, second UGI structure, first UGI structure, transistor TS, contact structure 441, metal layers M1 to M3, and connecting vias V1 and V2. Traditional semiconductor circuit structures lack the UGI structure disclosed herein, which can lead to TSV misalignment issues. Furthermore, the TSV requires greater depth to connect to the transistor via the metal layer in the upper interconnect structure 440. On the other hand, as shown in Figure 4, by using the UGI structure (including UGI lines and / or UGI pads), this disclosure provides greater misalignment tolerance because the STI region accommodating the UGI pads is larger. Moreover, this disclosure allows the back-side TSV to connect to the transistor via the UGI structure through a shorter path, without needing to pass through the metal layer in the upper interconnect structure 440. Therefore, the voltage drop (IR drop) between the TSV and the transistor can be significantly improved. Figure 5 is a schematic cross-sectional view of a semiconductor circuit structure 50 according to another embodiment of this disclosure. The semiconductor circuit structure 50 shown in Figure 5 differs from the semiconductor circuit structure 40 shown in Figure 4 in that the semiconductor circuit structure 50 does not include a backside TSV. Without using backside signal transmission via a backside TSV, power / data signals can be transmitted from the front side of the wafer to the second UGI structure or the first UGI structure via metal layers M1 to M3 and / or vias V1 and V2 in a conventional wafer fabrication process. Furthermore, if necessary, the second UGI structure or the first UGI structure can also be connected to a transistor (or other UGI structure) via metal layers M1 to M3 and vias V1 and V2. The first or second conductive region of the transistor TS can be electrically connected to the second UGI structure via metal layers M1 to M3 and vias V1 and V2. Figure 6 is a schematic cross-sectional view of a semiconductor circuit structure 60 according to some embodiments of the present disclosure. As shown in Figure 6, a second UGI structure (i.e., UGI pad, not shown in Figure 6) within a large STI region 424 connects to a backside TSV 433 to form a backside signal transmission, and another second UGI structure (i.e., UGI pad, not shown in Figure 6) within another large STI region 424 connects to a connection via 661 (front-side down via) above the top of the wafer / semiconductor substrate 400 to form a frontside signal transmission. Some first UGI structures (i.e., UGI lines, not shown in Figure 6) may extend along the X direction and within the STI region 414. Furthermore, the semiconductor circuit structure 60 may include one or more first UGI structures 662 (i.e., UGI lines, indicated by dashed lines in Figure 6) extending along the Y direction. UGI lines 662 may connect UGI lines in the STI region 414 and / or UGI pads in the large STI region 424. Thus, UGI pads and UGI lines extending in different directions can be connected to each other to form a UGI network, and the source terminals of transistor TS can be connected to some UGI lines. 2. based on UGI Heat dissipation network Figures 7 through 10 relate to a UGI-based heat dissipation network in the middle of a wafer or semiconductor substrate according to this disclosure. The configuration of the UGI structure on the XY plane is described in relation to Figures 2 and 3. The location, size, and number of the UGI structures are not limited to those shown in Figures 2 and 3. For heat dissipation applications, the UGI structure may contain (or be made of) a high thermal conductivity material, such as tungsten (with a thermal conductivity of approximately 170 kJ / m²). (thermal conductivity), boron nitride (with a thermal conductivity of approximately 600 W / m∙K), aluminum nitride (with a thermal conductivity of approximately 321 W / m∙K), and boron nitride (with a thermal conductivity of approximately 321 W / m∙K). The thermal conductivity of the material can be higher than that of the original material of the STI region (e.g., silicon dioxide), such as silicon carbide, silicon germanium (SiGe), undoped silicon, etc. In some embodiments, the UGI structure may comprise (or be made of) a composite material containing two or more highly thermally conductive materials. A portion of the silicon dioxide in the original STI region can be replaced by the UGI structure, thereby improving heat dissipation capacity because the thermal conductivity of the material in the UGI structure is higher than that of silicon dioxide and / or silicon. Similar to the UGI structure used for signal / power transfer, the UGI structure for heat dissipation extends from some STI areas next to the active region where the transistor is located to the UGI pad (e.g., the area of ​​the UGI pad may be between approximately 4...). m 2 To approximately 50 m 2 The large STI region (between the two areas) is almost identical to that shown in Figures 2 and 3. Multiple UGI structures can be thermally coupled to each other. For example, a UGI structure (i.e., a UGI pad) in the large STI region can be thermally coupled to a UGI structure (i.e., a UGI line) in the STI region. Furthermore, the large STI region can be aligned with one or more TSVs (as shown in Figure 4), which can be used for heat dissipation; TSVs can be understood as thermal vias. Moreover, compared to signal / power transfer, all or most of the STI regions in a semiconductor wafer (e.g., more than 60%, or even 70% to 90%) can be filled with the UGI structures proposed in this disclosure for heat dissipation purposes. Figure 7 is a schematic cross-sectional view illustrating a semiconductor circuit structure 70 according to some embodiments of the present disclosure. The main difference between the semiconductor circuit structure 70 shown in Figure 7 and the semiconductor circuit structure 40 shown in Figure 4 is that the semiconductor circuit structure 70 includes a TSV 733, a heat dissipation film 734 on the sidewall of the TSV 733, a barrier film 735 on the sidewall of the heat dissipation film 734, a heat sink 737, and a top heat sink 739 above the upper interconnect structure 440. The TSV 733 is directly below and connected to the second UGI structure (i.e., UGI pad) within the large STI region 424. The heat sink 737 is located on or near the back surface 400B of the semiconductor substrate 400 (or on the back surface of the wafer). The TSV 733 is used for heat dissipation and can be understood as a (back surface) thermal via. The heat sink 737 can be a heat radiator, and the material of the heat sink 737 can be the same as the material of the heat dissipation film 734 or the TSV 733. The TSV 733 extends from the bottom surface of the second UGI structure to the back surface 400B of the semiconductor substrate 400. The TSV 733 connects the second UGI structure and the heat sink 737 to form a heat dissipation path, which includes the second UGI structure close to the transistor, the TSV 733, and the heat sink 737. In some embodiments, the barrier film 735 and / or the heat dissipation film 734 may be omitted. For heat dissipation, the UGI structure in this embodiment may include a material with a higher thermal conductivity than silicon dioxide and / or silicon, or may be made of a material with a higher thermal conductivity than silicon dioxide and / or silicon. For example, the UGI structure may include tungsten, copper, boron nitride, aluminum nitride, silicon carbide, germanium silicon, undoped silicon, or combinations thereof. In some embodiments, the UGI structure includes an insulating material having a higher thermal conductivity than silicon dioxide and / or silicon. TSV 733 may include copper, and the heat dissipation film 734 may be boron nitride or aluminum nitride. Furthermore, TSV 733 is directly connected to a second UGI structure (e.g., the UGI pad in STI region 424), which in turn connects to a first UGI structure (e.g., the UGI line in STI region 414). The first UGI structure is connected to a transistor (e.g., the source / drain region of the transistor) via a corresponding connector 431. In this way, heat generated by the transistor can dissipate to TSV 733 through connector 431, the first UGI structure, and the second UGI structure. This provides a UGI heat dissipation network with high heat dissipation efficiency. In another embodiment, the UGI structure can be isolated from the transistor, but heat dissipation can still be achieved through the UGI line, UGI pad, and TSV 733. Conventional semiconductor circuit structures may only include upper thermal vias in the upper interconnect structure 440, without UGI structures, particularly UGI pads. Therefore, the alignment of the upper thermal vias is a critical issue. Furthermore, in conventional semiconductor circuit structures, the upper thermal vias are located only within and isolated by the dielectric layer 442 of the upper interconnect structure 440, far from the transistor. Consequently, heat generated by the transistor is difficult to dissipate effectively. However, UGI pads allow the semiconductor circuit structure according to this disclosure to provide a larger misalignment window for the thermal vias. In addition, the UGI structure allows for a shorter thermal coupling path between the thermal vias and the source / drain terminals of the transistor. Therefore, heat generated by the transistor can be effectively dissipated through the configuration disclosed herein. Figure 8 is a schematic cross-sectional view of a semiconductor circuit structure 80 according to some embodiments of the present disclosure. The semiconductor circuit structure 80 includes an upper thermal via 833 in the dielectric layer 442 of the upper interconnect structure 440. The upper thermal via extends upward from the upper surface of the second UGI structure to the top heat sink 739 and penetrates the dielectric layer 442 of the upper interconnect structure 440. Thus, the upper heatsink 833 connects the second UGI structure (e.g., the UGI pad in STI area 424) to the top heatsink 739. The second UGI structure then connects to the first UGI structure (e.g., the UGI line in STI area 414), and the first UGI structure holds the corresponding connector plug 431 connected to the transistor (e.g., the source / drain region of the transistor). Therefore, the top heatsink 739, the upper heatsink 833, the first UGI structure, and the second UGI structure form a heat dissipation path for the heat generated by the transistor. In this way, the heat generated by the transistor can dissipate to the upper heatsink 833 through the connector plug 431, the first UGI structure, and the second UGI structure. A UGI heat dissipation network with high heat dissipation efficiency can be provided. In another embodiment, the UGI structure (e.g., the UGI line in STI region 414) can be isolated from the transistor but still achieve heat dissipation. In other embodiments, the upper thermal via 833 can extend from the upper surface of the upper interconnect structure 440 to the first UGI structure. The upper thermal via 833 can contain a material with a higher thermal conductivity than silicon or silicon dioxide (or can be made of a material with a higher thermal conductivity than silicon or silicon dioxide), such as copper. Figure 9 is a schematic cross-sectional view illustrating a semiconductor circuit structure 90 according to some embodiments of the present disclosure. The semiconductor circuit structure 90 shown in Figure 9 differs from the semiconductor circuit structure 80 shown in Figure 8 in that the semiconductor circuit structure 90 includes an upper heat dissipation film 934 on the sidewall of the upper thermal via 833. The upper heat dissipation film 934 may comprise a material having a higher thermal conductivity than silicon or silicon dioxide (or may be made of a material having a higher thermal conductivity than silicon or silicon dioxide), such as boron nitride or aluminum nitride. Distributing the upper heat dissipation film 934 on the upper thermal via 833 improves heat dissipation efficiency. In some embodiments, the TSV 733 shown in Figure 7 and the upper thermal via 833 shown in Figure 8 (or the upper heat dissipation film 934 and the upper thermal via 833 shown in Figure 9) can be combined together, as shown in Figure 10. In the semiconductor circuit structure 91 shown in Figure 10, some upper thermal vias 833 extend from the upper surface of the upper interconnect structure 440 to the second UGI structure and connect to the top heat sink 739. The TSV 733 (an additional thermal via) extends from the back surface 400B of the semiconductor substrate 400 to the second UGI structure (or other UGI structure) and connects to the heat sink 737 located on or near the back surface 400B of the semiconductor substrate 400. Such a sandwich structure (containing an intermediate UGI structure in the wafer, a top heat sink connecting the intermediate UGI structure, and a heat sink on the back surface of the semiconductor substrate and connected to the intermediate UGI structure) can significantly enhance the heat dissipation capability of the IC wafer. In some embodiments, the barrier film 735 and / or the heat dissipation film 734 can be omitted. Figure 11A illustrates a semiconductor circuit structure containing a FinFET and an STI region adjacent to (or surrounding) the FinFET, where a portion of the STI region (indicated by diagonal lines) is replaced by a UGI structure made of tungsten. Figure 11A further shows a temperature distribution map of the FinFET generated by the TCAD Sentaurus simulation software. When a portion of the STI region is replaced by tungsten, the temperature difference (∆T) between the peak temperature of the transistor (hot spot region) and the ambient temperature (40 °C) is calculated, as shown in Figure 11B. In Figure 11B, the term "Full" indicates that no STI region is replaced by tungsten. The terms "1 nm" to "15 nm" represent the remaining thickness of the unreplaced STI region. Obviously, the smaller the remaining thickness of the STI region, the smaller the temperature difference between the peak temperature of the transistor and the ambient temperature (better heat dissipation performance). Thus, this disclosure can effectively reduce the peak temperature of the transistor. 3. Based on the same chip UGI Signal network and heat dissipation network According to this disclosure, signal transmission and heat dissipation based on a UGI structure can be combined in the same IC chip, as shown in Figure 12. In the semiconductor circuit structure 92 shown in Figure 12, some upper thermal vias 833 extend from the upper surface of the upper interconnect structure 440 to the second UGI structure (e.g., UGI pad) in the large STI region 424 and are connected to the top heat sink 739. An upper heat dissipation film 934 is on the sidewall of the upper thermal via 833. A TSV 433 is located directly below and connected to the second UGI structure (e.g., UGI pad) in the large STI region 424. The TSV 433 extends from the bottom of the second UGI structure (e.g., UGI pad) to the back surface 400B of the semiconductor substrate 400 and is connected to one or more back surface conductive pads 437 on the back surface 400B of the semiconductor substrate 400 (or on the back surface of the chip) for power signal or data signal transmission. The bottom heat sink 737 located on the back side 400B of the semiconductor substrate 400 may surround or couple to the back conductive pad 437. A heat dissipation film 4331 may be located on the sidewall of the TSV 433, and a barrier film 4332 may be located on the sidewall of the heat dissipation film 4331. The TSV 433 may contain a conductive material (or may be made of a conductive material), such as copper. The heat dissipation film 4331 may contain a material with a higher thermal conductivity than silicon or silicon dioxide, or may be made of a material with a higher thermal conductivity than silicon or silicon dioxide, such as boron nitride or aluminum nitride, to aid in heat dissipation. The barrier film 4332 may contain a dielectric material, such as an oxide. In some embodiments, within the same wafer / semiconductor substrate, some UGI pads are used for signal transmission, while others are used for heat dissipation. Figures 13A through 21 illustrate exemplary methods for manufacturing UGI structures according to some embodiments of this disclosure. Figure 13A is a schematic top view illustrating the structure of one stage in the manufacturing process. Figure 13B is a schematic cross-sectional view of this stage drawn along section line BB' in Figure 13A. Figure 13C is a schematic cross-sectional view of this stage drawn along section line CC' in Figure 13A. Referring to Figures 13A to 13C, a pad oxide layer 1204 and a pad nitride layer 1206 are deposited to define multiple active regions. The portion of the semiconductor substrate 1202 outside the multiple active regions is removed. The semiconductor substrate 1202 may contain or be made of a semiconductor material, such as silicon. Next, an oxide layer is deposited and etched back to form a partial shallow trench isolation (STI) region 1214. Figure 14A is a schematic top view of the structure of one stage in the manufacturing process. Figure 14B is a schematic cross-sectional view of this stage of the structure drawn along section line BB' of Figure 14A. Figure 14C is a schematic cross-sectional view of this stage of the structure drawn along section line CC' of Figure 14A. Referring to Figures 14A to 14C, a thermal oxide layer 1205 is grown along the exposed sidewalls of the active region. The length of the thermal oxide layer 1205 along the Z direction can be approximately 89 to 200 nm. The thickness of the thermal oxide layer 1205 along the Y direction can be approximately 2.5 nm. Depending on the pitch of the active regions, the distance between the thermal oxide layers 1205 on different active regions (along the Y direction) can be approximately 13 nm. The upper surface of the thermal oxide layer 1205 can be lower in the Z direction than the upper surface of the pad oxide layer 1204 and the lower surface of the pad nitride layer 1206. A portion of the STI region 1214 may be exposed, or the bottom of the STI region 1214 may be covered by the thermal oxide layer 1205. Figure 15A shows a schematic top view of the structure of one stage in the manufacturing process, Figure 15B is a schematic cross-sectional view of this stage of the structure drawn along section line BB' of Figure 15A, and Figure 15C is a schematic cross-sectional view of this stage of the structure drawn along section line CC' of Figure 15A. Referring to Figures 15A to 15C, SOD material 1207 is deposited to fill the space between the multiple active regions. Planarization (e.g., chemical mechanical planarization (CMP)) can be performed to remove the portion of SOD material 1207 above the pad nitride layer 1206 and to make the upper surface of SOD material 1207 coplanar with the upper surface of pad nitride layer 1206. Figure 16A is a schematic top view illustrating a stage of the structure in the manufacturing process. Figure 16B is a schematic cross-sectional view of this stage of the structure drawn along section line BB' in Figure 16A. Figure 16C is a schematic cross-sectional view of this stage of the structure drawn along section line CC' in Figure 16A. Referring to Figures 16A to 16C, a photoresist layer 1306 is formed and patterned to cover a portion of the active area and expose a portion of the SOD material 1207. For example, half or more than half of the active area may be covered by the photoresist layer 1306. Figure 17A is a schematic top view illustrating a stage of the manufacturing process. Figure 17B is a schematic cross-sectional view of this stage of the structure drawn along section line BB' in Figure 17A. Figure 17C is a schematic cross-sectional view of this stage of the structure drawn along section line CC' in Figure 17A. Referring to Figures 17A to 17C, the portion of SOD material 1207 not covered by photoresist layer 1306, and the thermal oxide layer 1205 covering this portion of SOD material 1207, are removed to form a narrow groove between the remaining SOD material 1207 and the active region. The narrow groove may have a width of 2 to 5 nm along the Y direction, for example, 3 nm. After removing the portion of SOD material 1207 not covered by photoresist layer 1306, and the thermal oxide layer 1205 below it, one sidewall of the active region is exposed in the narrow groove. Figure 18A is a schematic top view of the structure of one stage in the manufacturing process. Figure 18B is a schematic cross-sectional view of this stage of the structure drawn along section line BB' of Figure 18A. Figure 18C is a schematic cross-sectional view of this stage of the structure drawn along section line CC' of Figure 18A. Referring to Figures 18A to 18C, the photoresist layer 1306 is removed, and a material (e.g., SiOCN) 1209 different from the thermal oxide layer 1205 is deposited in a narrow groove. A planarization process (e.g., chemical mechanical planarization) may be performed to remove a portion of the SiOCN material 1209 above the pad nitride layer 1206 and the SOD material 1207, and to make the upper surfaces of the SiOCN material 1209, the SOD material 1207, and the pad nitride layer 1206 coplanar. Therefore, asymmetric spacers containing different materials (e.g., thermal oxide layer 1205 and SiOCN material 1209) can be formed within the STI region 1214. From another perspective, these asymmetric spacers cover the two sidewalls of the active region respectively. Figure 19A is a schematic top view illustrating a stage of the manufacturing process. Figure 19B is a schematic cross-sectional view of this stage of the structure drawn along section line BB' in Figure 19A. Figure 19C is a schematic cross-sectional view of this stage of the structure drawn along section line CC' in Figure 19A. Referring to Figures 19A to 19C, SOD material 1207 is removed to form a gap between the thermal oxide layer 1205 and the SiOCN material 1209. TiN layer 1303 and tungsten layer 1305 are sequentially deposited in the gap. Then, an etching process is performed to remove a portion of TiN layer 1303 and a portion of tungsten layer 1305. After the etching process, the remaining tungsten layer 1305 can be defined as a subsurface interconnect (UGI) structure, and the remaining TiN layer 1303 can be defined as a barrier layer. TiN layer 1303 is located between tungsten layer 1305 and thermal oxide layer 1205. TiN layer 1303 is situated between tungsten layer 1305 and SiOCN material 1205. TiN layer 1303 is also situated between tungsten layer 1305 and STI region 1214. The distance (along the Z-direction) between the upper surface of thermal oxide layer 1205 and the upper surface of tungsten layer 1305 can be 39–150 nm. The distance (along the Z-direction) between the upper surface of tungsten layer 1305 and the upper surface of STI region 1214 can be 50–150 nm. The thickness of STI region 1214 along the Z-direction can be 20–50 nm. Figure 20A shows a schematic top view of the structure at one stage of the manufacturing process. Figure 20B is a schematic cross-sectional view of this stage of the structure drawn along section line BB' of Figure 20A. Figure 20C is a schematic cross-sectional view of this stage of the structure drawn along section line CC' of Figure 20A. Referring to Figures 20A to 20C, a SiN layer 1307 and an HDP (high density plasma) oxide layer 1309 are sequentially formed on the tungsten layer 1305 and the TiN layer 1303. This completes the STI region between multiple active regions. Therefore, a subsurface interconnect structure within the STI region can be provided, and a three-dimensional schematic diagram of the structure is shown in Figure 21. The manufacturing steps for forming transistors in the active regions can be performed after the stages shown in Figures 20A to 20C. In one example, a UGI structure or UGI element extending within and along the STI region can be connected to the source or drain terminals of a transistor via a connection plug within the active region. For example, after removing a portion of the active region to form a trench therein, an asymmetric spacer of SiOCN material 1209 and thermal oxide layer 1205 is exposed in the trench. Then, a thermal oxide layer is formed in the trench to cover the exposed Si portion, such that only one sidewall of the trench is covered by SiOCN material 1209. The SiOCN material 1209 is then removed to expose the sidewalls of the UGI structure. Afterward, a connection plug (e.g., tungsten or heavily doped silicon) is filled into the trench to connect the exposed sidewalls of the UGI structure. If it is not necessary to connect the UGI structure to the source or drain terminals of the transistor, the step of forming the asymmetric spacer between the SiOCN material 1209 and the thermal oxide layer 1205 can be skipped, and it is sufficient to form only the thermal oxide layer 1205, as shown in Figures 14A to 14C. Subsequently, the UGI structure can be deposited on the STI region 1214, followed by the formation of other dielectric materials (e.g., SiN layer 1307 and HDP oxide layer 1309) on the UGI structure. Figures 22A through 29C illustrate methods for manufacturing under-surface interconnect structures within an STI region according to some embodiments of the present disclosure. Figure 22A is a schematic top view illustrating a stage of the manufacturing process. Figure 22B is a schematic cross-sectional view of this stage along section line BB' in Figure 22A. Figure 22C is a schematic cross-sectional view of this stage along section line CC' in Figure 22A. Referring to Figures 22A to 22C, a pad oxide layer 2204 and a pad nitride layer 2206 are deposited to define multiple active regions. The portion of the semiconductor substrate 2202 outside the multiple active regions is removed. The semiconductor substrate 2202 may contain or be made of a semiconductor material, such as silicon. Next, an oxide layer is deposited and etched back to form a shallow trench isolation (STI) region 2214. The width of the pad nitride layer 2206 along the Y direction may be 12 nm. The distance between two adjacent active regions (along the Y direction) may be 18 nm. The distance (along the Z direction) between the lower surface of the pad oxide layer 2204 and the upper surface of the STI region 2214 can be between 150 nm and 200 nm. Figure 23A shows a schematic top view of the structure of one stage in the manufacturing process. Figure 23B is a schematic cross-sectional view of this stage of the structure drawn along section line BB' in Figure 23A. Figure 23C is a schematic cross-sectional view of this stage of the structure drawn along section line CC' in Figure 23A. Referring to Figures 23A to 23C, SiOCN material 2209 is deposited along the sidewalls of semiconductor substrate 2202, the sidewalls of pad oxide layer 2204, the sidewalls of pad nitride layer 2206, and the upper surface of pad nitride layer 2206. The thickness of SiOCN material 2209 along the Y direction can be 4 nm. The distance D23 (along the Y direction) between the multiple sidewalls of SiOCN material 2209 can be 10 nm. A portion of STI region 2214 is exposed. Figure 24A shows a schematic top view of the structure of one stage in the manufacturing process. Figure 24B is a schematic cross-sectional view of this stage of the structure drawn along section line BB' of Figure 24A. Figure 24C is a schematic cross-sectional view of this stage of the structure drawn along section line CC' of Figure 24A. Referring to Figures 24A to 24C, SOD material 2207 is deposited to fill the space between the multiple active regions. Planarization (e.g., chemical mechanical planarization) can be performed to remove the portion of SOD material 2207 above the pad nitride layer 2206 and to make the upper surface of SOD material 2207 coplanar with the upper surface of pad nitride layer 2206. Figure 25A is a schematic top view illustrating a stage of the structure in the manufacturing process. Figure 25B is a schematic cross-sectional view of this stage of the structure drawn along section line BB' in Figure 25A. Figure 25C is a schematic cross-sectional view of this stage of the structure drawn along section line CC' in Figure 25A. Referring to Figures 25A to 25C, a photoresist layer 2306 is formed and patterned to cover a portion of the active region and expose a portion of the SOD material 2207 and a portion of the SiOCN material 2209. For example, half or more than half of the active region may be covered by the photoresist layer 2306. Figure 26A is a schematic top view illustrating a stage of the structure in the manufacturing process. Figure 26B is a schematic cross-sectional view of this stage of the structure drawn along section line BB' in Figure 26A. Figure 26C is a schematic cross-sectional view of this stage of the structure drawn along section line CC' in Figure 26A. Referring to Figures 26A to 26C, remove the portion of SiOCN material 2209 not covered by photoresist layer 2306 and SOD material 2207, and remove photoresist layer 2306. A groove 2210 is formed between the retained SiOCN material 2209 and the active region. After removal, one sidewall of each active region is exposed in the groove 2210. Figure 27A is a schematic top view illustrating the structure of one stage in the manufacturing process. Figure 27B is a schematic cross-sectional view of this stage drawn along section line BB' of Figure 27A. Figure 27C is a schematic cross-sectional view of this stage drawn along section line CC' of Figure 27A. Referring to Figures 27A to 27C, a thermal oxide layer 2205 is grown within the groove 2210 along the exposed sidewall of the active region. In the Z direction, the upper surface of the thermal oxide layer 2205 may be lower than the upper surface of the pad oxide layer 2204 and the lower surface of the pad nitride layer 2206. Thus, an asymmetric spacer is formed within the STI region 2214 and comprises different materials (e.g., thermal oxide layer 2205 and SiOCN material 2209). In another view, this asymmetric spacer covers both sidewalls of each active region. Figure 28A is a schematic top view of the structure at one stage of the manufacturing process. Figure 28B is a schematic cross-sectional view of this stage of the structure drawn along section line BB' in Figure 28A. Figure 28C is a schematic cross-sectional view of this stage of the structure drawn along section line CC' in Figure 28A. Referring to Figures 28A to 28C, TiN layer 2303 and tungsten layer 2305 are deposited sequentially in the groove 2210. Then, an etching process is performed to remove a portion of the TiN layer 2303 and a portion of the tungsten layer 2305. After the etching process, the remaining tungsten layer 2305 can be defined as a subsurface interconnect (UGI) structure, and the remaining TiN layer 2303 can be defined as a barrier layer. Figure 29A is a schematic top view illustrating a stage of the manufacturing process. Figure 29B is a schematic cross-sectional view of this stage of the structure drawn along section line BB' in Figure 29A. Figure 29C is a schematic cross-sectional view of this stage of the structure drawn along section line CC' in Figure 29A. Referring to Figures 29A to 29C, a SiN layer 2307 and an HDP (high density plasma) oxide layer 2309 are sequentially formed on the tungsten layer 2305 and the TiN layer 2303. This provides a structure containing subsurface interconnect structures within the STI region. The manufacturing steps for forming transistors in the active region can be performed after the stages shown in Figures 29A to 29C. Figures 30A and 30B illustrate exemplary methods for manufacturing UGI meshes according to some embodiments of the present disclosure. Figures 30A and 30B are schematic top views illustrating the structures of different stages of the manufacturing method. A pad oxide layer and a pad nitride layer 3206 are sequentially deposited on a semiconductor substrate. Next, a temporary active region can be defined by a lithography process, and an STI region and a large STI region (shown as dashed lines in Figure 30A) are defined outside the temporary active region. Then, as previously described, the material for forming the UGI structure is formed in the STI region and the large STI region. Next, the actual active region 30A can be defined by another lithography process, and the removed temporary active region is then used for the remaining STI region, as shown in Figure 30B. This disclosure provides under-surface interconnect structures (e.g., UGI lines and UGI pads) located beneath the original semiconductor surface and within the STI region. The UGI structures are isolated from the semiconductor substrate, and some UGI structures can connect to transistors as needed. The under-surface interconnect structures can form a UGI network (or, as understood, an intermediate signal / power delivery network or heat dissipation network) within the wafer or semiconductor substrate. Because the large STI region provides ample signal path space, it offers greater misalignment tolerance, shortens the path of the back-side TSV to the UGI network to improve signal delivery voltage drop, and enhances heat dissipation. It should be noted that the structures and methods described above are for illustrative purposes only. This disclosure is not limited to the configurations and steps disclosed above. Other embodiments with different configurations of known components can be applied, and the structure of the examples can be adjusted and modified based on the actual needs of the application. Of course, it should be noted that the configurations in the drawings are for illustrative purposes only and not for limitation. Therefore, those skilled in the art will understand that the related components and layers in the semiconductor structure, the shape or positional relationship of the components, and the details of the steps can be adjusted or changed according to the actual needs of the application and / or the manufacturing steps. Although this disclosure has been described by way of example and according to exemplary embodiments, it should be understood that this disclosure is not limited thereto. Rather, this disclosure is intended to cover various variations, as well as similar configurations and steps, and therefore the scope of the appended claims should be given the broadest possible interpretation in order to cover all such variations, as well as similar configurations and steps. 10, 20, 30, 40, 60, 70, 80, 90, 91, 92: Semiconductor circuit structure; 10A, 20A, 20A-1, 20A-2, 30A, 40A: Active region; 20B, 114, 414: STI region; 20C: Pad opening layer; 100, 400, 1202, 2202: Semiconductor substrate; 100S, 400S: Raw semiconductor surface; 104, 1204, 2204: Pad oxide layer; 105, 405, 409: UGI element; 106, 1 206, 2206, 3206: Nitrided pad layer; 107, 407, 435: Barrier layer; 205, 209, 305-1, 305-2, 305-3: UGI structure; 214-1, 214-2, 214-3, 214-4, 314-1, 314-2, 314-3: STI area; 224, 224-1, 224-2, 224-3, 224-4, 424: Large STI area; 400B: Back side; 431: Connecting plug; 433, 733: TSV. 437: Back surface conductive pad; 440: Upper interconnect structure; 441: Contact structure; 442: Dielectric layer; 450: Bonding layer; 661: Connecting via; 662: UGI structure; 734, 4331: Heat dissipation film; 735: Barrier film; 737: Heat sink; 739: Top heat sink; 833: Upper thermal via; 934: Upper heat dissipation film; 1205, 2205: Thermal oxide layer; 1207, 2207: SOD material; 1209, 2209: SiOCN material; 121 4,2214: STI region; 1303,2303: TiN layer; 1305,2305: Tungsten layer; 1306,2306: Photoresist layer; 1307,2307: SiN layer; 1309,2309: HDP oxide layer; 2210: Groove; BB',CC': Profile line; M1,M2,M3: Metal layer; T1: First conductive region; T2: Second conductive region; T3: Gate structure; TS: Transistor; V1,V2: Connecting via; X,Y,Z: Direction. Figure 1 is a schematic top view of a conventional semiconductor circuit structure having an STI region and an active region; Figure 2A is a schematic top view of a semiconductor circuit structure according to some embodiments of the present disclosure; Figure 2B is a schematic cross-sectional view of a semiconductor circuit structure drawn along section line BB' of Figure 2A; Figure 2C is a schematic cross-sectional view of a semiconductor circuit structure drawn along section line CC' of Figure 2A; Figure 2D is a schematic top view of a semiconductor circuit structure according to some embodiments of the present disclosure; Figure 2E is a schematic top view of a semiconductor circuit structure according to some embodiments of the present disclosure; Figure 3 is a schematic top view of a semiconductor circuit structure according to some embodiments of the present disclosure; Figure 4 is a schematic cross-sectional view of a semiconductor circuit structure according to some embodiments of the present disclosure; Figure 5 is a schematic cross-sectional view of a semiconductor circuit structure according to some embodiments of the present disclosure; Figure 6 is a schematic cross-sectional view of a semiconductor circuit structure according to some embodiments of the present disclosure; Figure 7 is a schematic cross-sectional view of a semiconductor circuit structure according to some embodiments of the present disclosure. Figure 8 is a schematic cross-sectional view of a semiconductor circuit structure according to some embodiments of the present disclosure; Figure 9 is a schematic cross-sectional view of a semiconductor circuit structure according to some embodiments of the present disclosure; Figure 10 is a schematic cross-sectional view of a semiconductor circuit structure according to some embodiments of the present disclosure; Figure 11A shows a temperature distribution map of a FinFET created by TCAD Sentaurus; Figure 11B shows a graph showing the relationship between temperature difference and STI region thickness; Figure 12 is a schematic cross-sectional view of a semiconductor circuit structure according to some embodiments of the present disclosure; Figures 13A to 21 illustrate methods for manufacturing under-surface interconnect structures within an STI region according to some embodiments of the present disclosure; Figures 22A to 29C illustrate methods for manufacturing under-surface interconnect structures within an STI region according to some embodiments of the present disclosure; and Figures 30A to 30B illustrate methods for manufacturing under-surface interconnects according to some embodiments of the present disclosure. 20: Semiconductor Circuit Structure 20A, 20A-1: Active Zone 20B: STI area 20C: Opening layer 205, 209: UGI Structure 214-1, 214-2, 214-3, 214-4: STI area 224-1, 224-2, 224-3, 224-4: Large STI area

Claims

1. A semiconductor circuit structure includes: a semiconductor substrate having a raw semiconductor surface; a set of transistors formed on the semiconductor substrate, wherein each transistor includes a gate structure, a first conductive region, and a second conductive region; a first shallow trench isolation (STI) region adjacent to the set of transistors and extending along a first direction; a large shallow trench isolation (STI) region away from the set of transistors; a first under-surface interconnect within the first STI region and located below the raw semiconductor surface, wherein the first under-surface interconnect extends along the first direction; and a first under-surface interconnect pad electrically coupled to the first under-surface interconnect, wherein the first under-surface interconnect pad is located within the large STI region and located below the raw semiconductor surface, and a width of the first under-surface interconnect pad is greater than a width of the first under-surface interconnect. The semiconductor circuit structure as described in claim 1, wherein the first under-surface interconnect pad is directly connected to the first under-surface interconnect line. The semiconductor circuit structure as described in claim 2 further includes a semiconductor via (TSV) extending from a bottom surface of the first under-surface interconnect pad to a back surface of the semiconductor substrate, wherein the semiconductor via is electrically connected to the first under-surface interconnect pad and is configured to transmit a power signal or a data signal from the back surface of the semiconductor substrate to the first under-surface interconnect pad, the back surface being relative to the original semiconductor surface. As described in claim 3, in the semiconductor circuit structure, the first conductive region of a first transistor in the group of transistors is electrically connected to the first under-surface interconnect via a connector plug located in an active region accommodating the first transistor, and the power signal or the data signal is transmitted to the first transistor via the first under-surface interconnect pad, the first under-surface interconnect and the corresponding connector plug. The semiconductor circuit structure as described in claim 4, wherein the connection plug contacts one sidewall of the interconnect beneath the first surface. The semiconductor circuit structure as described in claim 3, wherein both the first under-surface interconnect pad and the first under-surface interconnect line comprise tungsten and titanium nitride. The semiconductor circuit structure described in claim 3, wherein the semiconductor via includes a copper pillar. The semiconductor circuit structure as described in claim 7 further includes a conductive pad located near the back side of the semiconductor substrate and connected to the semiconductor via. The semiconductor circuit structure as described in claim 1 further includes: a second shallow trench isolation (STI) region remote from the set of transistors; and a second under-surface interconnect within the second STI region and located below the original semiconductor surface, wherein the second under-surface interconnect extends along a second direction different from the first direction, and wherein the second under-surface interconnect connects to the first under-surface interconnect. The semiconductor circuit structure as described in claim 1 further includes: a second shallow trench isolation (STI) region remote from the set of transistors; and a second under-surface interconnect within the second STI region and located below the original semiconductor surface, wherein the second under-surface interconnect extends along a second direction different from the first direction, wherein the second under-surface interconnect connects to the first under-surface interconnect pad. The semiconductor circuit structure as described in claim 1 further includes: a plurality of metal layers located above the original semiconductor surface and vertically separated from each other; and a plurality of interconnect vias located above the original semiconductor surface and electrically connected to the plurality of metal layers, wherein the first conductive region of a first transistor in the group of transistors is electrically connected to the first under-surface interconnect pad through the plurality of metal layers and the plurality of interconnect vias. The semiconductor circuit structure as described in claim 1 further comprises: a plurality of metal layers located above the original semiconductor surface and perpendicularly separated from each other; a plurality of vias located above the original semiconductor surface and electrically connected to the plurality of metal layers; and a second under-surface interconnect pad located below the original semiconductor surface, wherein a width of the second under-surface interconnect pad is greater than a width of the first under-surface interconnect, wherein the first under-surface interconnect pad is electrically connected to the second under-surface interconnect pad through the plurality of metal layers and the plurality of vias. A semiconductor circuit structure includes: a semiconductor substrate having a raw semiconductor surface; a set of transistors formed on the semiconductor substrate; a first shallow trench isolation (STI) region adjacent to the set of transistors and extending along a first direction; a second shallow trench isolation (STI) region away from the set of transistors; a large shallow trench isolation (STI) region away from the set of transistors; a first under-surface interconnect within the first STI region and located below the raw semiconductor surface, wherein the first under-surface interconnect extends along the first direction; a second under-surface interconnect within the second STI region and located below the raw semiconductor surface, wherein the second under-surface interconnect extends along a second direction different from the first direction; and a first under-surface interconnect pad located within the large STI region and located below the raw semiconductor surface, wherein the second under-surface interconnect connects the first under-surface interconnect or the first under-surface interconnect pad. The semiconductor circuit structure as described in claim 13, wherein the width of the first surface under-surface interconnect pad is greater than the width of the first surface under-surface interconnect line. The semiconductor circuit structure as described in claim 13, wherein the first under-surface interconnect pad is connected to the first under-surface interconnect line. The semiconductor circuit structure as described in claim 13 further includes: a third shallow trench isolation (STI) region, away from the set of transistors; and a third under-surface interconnect, within the third STI region and located below the original semiconductor surface, wherein the third under-surface interconnect extends along the first direction, and wherein a second under-surface interconnect is located between the first under-surface interconnect and the third under-surface interconnect and connects the first under-surface interconnect and the third under-surface interconnect. A semiconductor circuit structure includes: a semiconductor substrate having a raw semiconductor surface; a set of transistors formed on the semiconductor substrate, wherein each transistor includes a gate structure, a first conductive region, and a second conductive region; a first shallow trench isolation (STI) region adjacent to the set of transistors and extending along a first direction; a large shallow trench isolation (STI) region away from the set of transistors; a first under-surface interconnect within the first STI region and located below the raw semiconductor surface, wherein the first under-surface interconnect extends along the first direction; a first under-surface interconnect pad electrically coupled to the first under-surface interconnect, wherein the first under-surface interconnect pad is located within the large STI region and located below the raw semiconductor surface; and a semiconductor via (TSV) within the large STI region and connected to the first under-surface interconnect pad. The semiconductor circuit structure as described in claim 17, wherein the large STI region extends from one edge of the first STI region, and the first under-surface interconnect pad is directly connected to the first under-surface interconnect. The semiconductor circuit structure as described in claim 18, wherein the semiconductor via extends from a bottom surface of the first under-surface interconnect pad to a back surface of the semiconductor substrate, the semiconductor via being fitted to transmit a power signal or a data signal from the back surface of the semiconductor substrate to the first under-surface interconnect pad, the back surface being relative to the original semiconductor surface. The semiconductor circuit structure as described in claim 19, wherein the first conductive region of a first transistor in the group of transistors is electrically connected to the first under-surface interconnect via a connector plug located in an active region accommodating the first transistor, and the power signal or the data signal is transmitted to the first transistor via the first under-surface interconnect pad, the first under-surface interconnect and the corresponding connector plug. The semiconductor circuit structure as described in claim 20, wherein the connection plug contacts one sidewall of the interconnect beneath the first surface. The semiconductor circuit structure as described in claim 17 further includes a conductive pad located near a back side of the semiconductor substrate and connected to the semiconductor via.