Power supply voltage drop detection device and system

Abstract

The present disclosure provides a power supply voltage drop detection device and system. The device comprises a gating unit, a first detection channel, and a second detection channel. In a first duration of a control cycle, the gating unit outputs a power supply voltage to the first detection channel, and outputs a threshold voltage to the second detection channel; and in a second duration, the gating unit outputs a threshold voltage to the first detection channel, and outputs a power supply voltage to the second detection channel. The first detection channel detects a first voltage characterization value of the first duration and a second voltage characterization value of the second duration, and outputs a first alarm signal when the first voltage characterization value is smaller than the second voltage characterization value. The second detection channel detects a third voltage characterization value of the first duration and a fourth voltage characterization value of the second duration, and outputs a second alarm signal when the fourth voltage characterization value is smaller than the third voltage characterization value.

Description

Power supply voltage drop detection device and system

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202310640562.1 filed on May 31, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to the technical field of voltage detection, and in particular to a power supply voltage drop detection device and system. Background Art

[0004] As process geometries continue to shrink, integrated circuits become larger and more integrated, placing increasing demands on power management modules. The power supply voltage of a system-on-chip (SOC) must undergo large current load step changes within a few nanoseconds or tens of nanoseconds. However, the power management module cannot respond quickly enough, causing the power supply voltage to drop rapidly during these large current load step changes. If the power supply voltage drops sufficiently low, it can cause the system to malfunction.

[0005] Summary of the Invention

[0006] The present disclosure provides a power supply voltage drop detection device and system.

[0007] In a first aspect, the present disclosure provides a power supply voltage drop detection device, which includes a gating unit, a first detection channel, and a second detection channel. The gating unit has two input terminals connected (accessed) to the power supply voltage and the threshold voltage, respectively, and two output terminals connected to the first detection channel and the second detection channel, respectively. The gating unit is configured to: output the power supply voltage to the first detection channel and output the threshold voltage to the second detection channel in the first duration of each control cycle; output the threshold voltage to the first detection channel and output the power supply voltage to the second detection channel in the second duration of each control cycle, wherein each control cycle consists of a first duration and a second duration. The first detection channel is configured to: detect a first voltage characterization value of the power supply voltage in the first duration; and detect a second voltage characterization value of the threshold voltage in the second duration; compare the first voltage characterization value of the first duration of each control cycle with the second voltage characterization value of the second duration of the same control cycle, and output a first alarm signal if the first voltage characterization value is less than the second voltage characterization value. The second detection channel is configured to: detect a third voltage characterization value of the threshold voltage in the first duration period; and detect a fourth voltage characterization value of the power supply voltage in the second duration period; compare the third voltage characterization value of the first duration period of each control cycle with the fourth voltage characterization value of the second duration period of the same control cycle, and output a second alarm signal when the fourth voltage characterization value is less than the third voltage characterization value.

[0008] A second aspect of the present disclosure provides a power supply voltage drop detection system, comprising the power supply voltage drop detection device described in the first aspect, a clock frequency reduction unit, a power supply, and a processing core. The power supply voltage drop detection device is configured to output at least one of a first alarm signal and a second alarm signal to the clock frequency reduction unit; the clock frequency reduction unit is configured to reduce the system frequency of the processing core under the control of at least one of the first alarm signal and the second alarm signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG1 is a schematic structural diagram of a power supply voltage drop detection device according to an embodiment of the present disclosure;

[0010] FIG2 is a schematic structural diagram of a first detection channel according to an embodiment of the present disclosure;

[0011] FIG3 is a schematic structural diagram of a second detection channel according to an embodiment of the present disclosure;

[0012] FIG4 is a schematic structural diagram of a first detection subunit according to an embodiment of the present disclosure;

[0013] FIG5 is a schematic diagram of a power supply voltage drop detection principle according to an embodiment of the present disclosure;

[0014] FIG6 is a schematic structural diagram of a second detection subunit according to an embodiment of the present disclosure;

[0015] FIG7 is a schematic structural diagram of a voltage divider circuit according to an embodiment of the present disclosure;

[0016] FIG8 is a schematic structural diagram of another power supply voltage drop detection device according to an embodiment of the present disclosure;

[0017] FIG9 is a schematic diagram of the working timing of a first detection channel and a second detection channel according to an embodiment of the present disclosure;

[0018] FIG10 is a schematic diagram of a workflow of a first detection channel and a second detection channel according to an embodiment of the present disclosure;

[0019] FIG11 is a schematic diagram of a calibration process according to an embodiment of the present disclosure;

[0020] FIG12 is a schematic structural diagram of a power supply voltage drop detection system according to an embodiment of the present disclosure;

[0021] FIG13 is a schematic structural diagram of a delay chain according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] The following describes the specific embodiments of the present disclosure in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure and are not intended to limit the present disclosure.

[0023] As used in this disclosure, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0024] The terms used in the present disclosure are only used to describe specific embodiments and are not intended to limit the present disclosure.As used in the present disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0025] When the terms “comprising” and / or “made of…” are used in the present disclosure, it specifies the existence of the stated features, integers, steps, operations, elements and / or components, but does not preclude the existence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0026] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meanings as those commonly understood by those skilled in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined in this disclosure.

[0027] During research into existing technologies, the inventors discovered that in traditional power management modules, voltage drop ranges are covered by increasing the operating power supply voltage to prevent abnormal system operation. However, this increases the power supply voltage during normal operation, resulting in wasted power. Existing power supply voltage drop detection mechanisms fall into two categories: analog and digital. Analog detection primarily uses a comparator to compare a reference threshold with the power supply voltage, generating an alarm signal when the power supply voltage falls below the threshold. However, this method requires a reference power supply, which increases the size of the power management module and the number of power supplies. Digital detection primarily utilizes the relationship between the power supply voltage and the delay of delay chains. When the power supply voltage decreases, the delay of the delay chain increases, achieving voltage-to-time conversion. Time-to-digital converters (TDCs) are then used to convert the time into digital data, achieving voltage-to-digital conversion. However, the delay of the delay chain varies greatly with PVT (Process, Voltage, Temperature). The solution in related art is to use a table lookup solution for calibration to eliminate the influence of PVT. However, this calibration method is complicated and requires the use of other sensors, and has limited accuracy.

[0028] To this end, the present disclosure provides a power supply voltage drop detection device, which mainly detects power supply voltage drops caused by load changes in, for example, an SOC, and issues an alarm signal when a drop is detected.

[0029] Figure 1 is a schematic diagram of the structure of a power supply voltage drop detection device according to an embodiment of the present disclosure. The device mainly includes a gating unit 10, a first detection channel 11, and a second detection channel 12. One input terminal 1 of the gating unit 10 is connected to the power supply voltage, another input terminal 2 is connected to the threshold voltage, one output terminal 3 is connected to the first detection channel 11, and another output terminal 4 is connected to the second detection channel 12.

[0030] During the first duration of each control cycle, the gating unit 10 outputs a power supply voltage to the first detection channel 11 and a threshold voltage to the second detection channel 12. During the second duration of each control cycle, the gating unit 10 outputs a threshold voltage to the first detection channel 11 and a power supply voltage to the second detection channel 12. Each control cycle consists of a first duration and a second duration. That is, within the same duration, one output terminal outputs the threshold voltage and the other output terminal outputs the power supply voltage. The same output terminal outputs the threshold voltage in one duration and the power supply voltage in the next duration, so that the two output terminals alternately output the power supply voltage and the threshold voltage.

[0031] The first detection channel 11 detects a first voltage characterizing value of the power supply voltage during a first duration period; and detects a second voltage characterizing value of the threshold voltage during a second duration period; compares the first voltage characterizing value of the first duration period of each control cycle with the second voltage characterizing value of the second duration period of the same control cycle, and outputs a first alarm signal if the first voltage characterizing value is less than the second voltage characterizing value. The second detection channel 12 detects a third voltage characterizing value of the threshold voltage during the first duration period; and detects a fourth voltage characterizing value of the power supply voltage during the second duration period; compares the third voltage characterizing value of the first duration period of each control cycle with the fourth voltage characterizing value of the second duration period of the same control cycle, and outputs a second alarm signal if the fourth voltage characterizing value is less than the third voltage characterizing value.

[0032] In this embodiment, a power supply voltage drop detection device uses two detection channels to periodically detect power supply voltage drops based on a control cycle. During the first duration of each control cycle, one detection channel detects a threshold voltage, while the other detection channel detects the power supply voltage. During the second duration of each control cycle, the detection targets are swapped, i.e., the detection channel that originally detected the threshold voltage detects the power supply voltage, and the detection channel that originally detected the power supply voltage detects the threshold voltage. Each detection channel compares the threshold voltage detected by itself with the power supply voltage within the same control cycle and outputs an alarm signal when the real-time detected power supply voltage value is less than the threshold voltage value. In this embodiment, the threshold voltage value is set to be less than the power supply voltage value. When the power supply voltage drops but remains above the threshold voltage, it can be tolerated (no alarm is output). When the power supply voltage drops below the threshold voltage, an alarm is output.

[0033] FIG2 is a schematic diagram of the structure of the first detection channel 11 according to some embodiments. The first detection channel 11 includes a first detection subunit 110, a first calibration subunit 111, and a first comparison subunit 112, which are connected in sequence. The first detection subunit 110 detects the first number of delay cells contained in each of n detection windows within the first duration of each control cycle, and uses the first number as a first voltage representation value, i.e., the number of delay cells corresponding to the power supply voltage. The number of delay cells detected in each detection window represents the magnitude of the power supply voltage. Furthermore, the first detection subunit 110 detects the second number of delay cells contained in each of m detection windows within the second duration of each control cycle, i.e., the number of delay cells corresponding to the threshold voltage, and the number of delay cells detected in each detection window represents the magnitude of the threshold voltage. Here, n is an integer greater than or equal to 1, and m is an integer greater than or equal to 1. The first calibration subunit 111 averages the q second numbers of the same control cycle, and the average value is used as the second voltage representation value for that control cycle, where q is less than or equal to m. The first comparison subunit 112 compares a first voltage characterizing value of a first duration period of each control cycle with a second voltage characterizing value of a second duration period of the same control cycle, and outputs a first alarm signal if the first voltage characterizing value is less than the second voltage characterizing value.

[0034] Here, the value of n is related to the duration of the first duration segment and the duration of a single detection window. For example, n is the number of detection windows included in the first duration segment. Similarly, the value of m is related to the duration of the second duration segment and the duration of a single detection window. For example, m is the number of detection windows included in the second duration segment. The number of q depends on the number of second numbers continuously obtained by the first calibration subunit at the averaging moment. If m second numbers can be obtained at the averaging moment, then q is equal to m. If m second numbers cannot be obtained, then q is less than m. The delay duration of a single delay unit increases as the power supply voltage decreases.

[0035] FIG3 is a schematic diagram of the structure of the second detection channel 12 according to some embodiments. The second detection channel includes a second detection subunit 120, a second calibration subunit 121, and a second comparison subunit 122, which are connected in sequence. The second detection subunit 120 detects the third number of delay cells contained in each of n detection windows within the first duration of each control cycle of the input threshold voltage, i.e., the number of delay cells corresponding to the threshold voltage, wherein each detection window detects a number of delay cells representing the magnitude of the threshold voltage. The second detection subunit also detects the fourth number of delay cells contained in each of m detection windows within the second duration of each control cycle of the input power supply voltage, and uses the fourth number as a fourth voltage representation value, i.e., the number of delay cells corresponding to the power supply voltage, wherein each detection window detects a number of delay cells representing the magnitude of the power supply voltage. Where n is an integer greater than or equal to 1, and m is an integer greater than or equal to 1. The second calibration subunit 121 averages p third numbers of the same control cycle to obtain a third voltage representation value for that control cycle, where p is less than or equal to n. The second comparison subunit 122 compares the third voltage characterizing value of the first duration period of each control cycle with the fourth voltage characterizing value of the second duration period of the same control cycle, and outputs a second alarm signal if the fourth voltage characterizing value is less than the third voltage characterizing value.

[0036] Here, the value of n is related to the duration of the first duration segment and the duration of a single detection window. For example, n is the number of detection windows included in the first duration segment. Similarly, the value of m is related to the duration of the second duration segment and the duration of a single detection window. For example, m is the number of detection windows included in the second duration segment. The number of p depends on the number of times the second calibration subunit continuously obtains a third number at the averaging moment. If n third numbers can be obtained at the averaging moment, then p is equal to n. If n third numbers cannot be obtained, then p is less than n. The delay duration of a single delay unit increases as the power supply voltage decreases.

[0037] In one example, the first comparison subunit and the second comparison subunit are respectively implemented using digital comparators.

[0038] In one example, the first duration segment and the second duration segment are of the same duration, and m and n are equal. In this case, the first duration segment and the second duration segment in each control cycle include the same number of detection windows of the same duration. Furthermore, the control cycle can be provided in a cyclic or discrete manner during all or part of the operation of the power supply, and this disclosure does not impose any particular limitation on this aspect.

[0039] FIG4 is a schematic diagram of the structure of the first detection subunit 110 according to some embodiments. The first detection subunit 110 includes a first frequency divider (div2) 41 and a first delay chain 42. The signal output of the first frequency divider 41 is connected to the signal input of the first delay chain 42, the power input of the first delay chain 42 is connected to the power supply voltage, and the output of the first delay chain 42 serves as the output of the first detection subunit 110. The first frequency divider 41 outputs a divided-by-two signal through its signal output. The high-level period of this divided-by-two signal serves as the detection window. The delay length of the first delay chain 42 increases as the power supply voltage decreases. The first frequency divider generates a clock with a 50% duty cycle, i.e., a divided-by-two signal. Assuming the input clock of the first frequency divider is 2 GHz, the high-level period is approximately 500 ps. By detecting the number of delay cells in the first delay chain within 500 ps, ​​the power supply voltage is monitored. Using the delay cells as a clock, the 500 ps is converted into data, achieving time-to-data conversion (TDC). The first delay chain 42 includes a plurality of delay units. There is no limitation on the number of delay units as long as the number can meet the TDC conversion requirement of the two-frequency-divided signal output by the first frequency divider.

[0040] Figure 5 shows a schematic diagram of the power supply voltage drop detection principle. Time period T1 is the detection window. After the first delay chain, the number of delay cells within the detection window is determined. As the power supply voltage decreases, the number of delay cells within the detection window gradually decreases. Therefore, the change in the number of delay cells within the detection window can be used to determine whether a power supply voltage drop has occurred. For example, using a detection window of 500ps, as the power supply voltage increases, the number of delay cells within 500ps increases. As the power supply voltage decreases, the number of delay cells within 500ps decreases. The number of delay cells within 500ps can be used to determine the current power supply voltage.

[0041] Figure 6 shows a schematic diagram of the structure of the second detection subunit 120 according to some embodiments. The second detection subunit 120 includes a second frequency divider 61 and a second delay chain 62. The signal output of the second frequency divider 61 is connected to the signal input of the second delay chain 62, the power input of the second delay chain 62 is connected to the power supply voltage, and the output of the second delay chain 62 serves as the output of the second detection subunit 120. The second frequency divider 61 outputs a two-frequency signal through the signal output, and the high-level period of the two-frequency signal serves as the detection window. Similar to the first detection subunit, the second detection subunit converts the high-level period of the two-frequency signal into data, achieving time-to-data conversion.

[0042] In some embodiments, the first duration segment and the second duration segment have the same duration. In an exemplary embodiment, the value range of each of the first duration segment and the second duration segment is: greater than or equal to 1ms and less than or equal to 2ms. It should be understood that the first duration segment and the second duration segment are two duration segments in one cycle of the timing signal, and the two duration segments constitute a control cycle. Under the control of the timing signal, the gating unit alternately outputs the threshold voltage and the power supply voltage at the two output terminals. The value range of the first duration segment and the second duration segment given here is an exemplary embodiment. It is not necessary to configure the first duration segment and the second duration segment according to this value range, and its value range is not limited to this.

[0043] In some embodiments, the threshold voltage can be obtained by dividing the power supply voltage using resistors. In other embodiments, the threshold voltage can be obtained by inputting an external fixed voltage, wherein the fixed voltage is set at a desired alarm voltage.

[0044] In some embodiments, the power supply voltage drop detection device further includes a voltage divider circuit 70. FIG. 7 is a schematic diagram of the structure of a voltage divider circuit according to some embodiments. The input of the voltage divider circuit 70 is connected to the power supply voltage, and the output of the voltage divider circuit 70 is connected to the second input of the selection unit. The voltage divider circuit 70 divides the power supply voltage to output a threshold voltage. In some embodiments, the threshold voltage can be set to 90% to 95% of the power supply voltage. FIG. 7 only uses the threshold voltage of 93% of the power supply voltage as an example. The actual threshold voltage can be set as needed, and the specific value of the threshold voltage is not limited here.

[0045] In some embodiments, as shown in FIG8 , the gating unit 10 of the power supply voltage drop detection device may include two groups of switching elements, each group of switching elements including two switches sw1 and sw2 . In the first group of switching elements, the two ends of switch sw1 are respectively connected to the first detection channel and the threshold voltage vth, while the two ends of switch sw2 are respectively connected to the second detection channel and the threshold voltage. In the second group of switching elements, the two ends of switch sw1 are respectively connected to the power supply voltage vdd and the second detection channel, while the two ends of switch sw2 are respectively connected to the power supply voltage and the first detection channel.

[0046] For example, in other embodiments, the gating unit includes a first single-pole double-throw switch and a second single-pole double-throw switch; the first single-pole double-throw switch has a movable terminal connected to the threshold voltage, a fixed terminal connected to the input terminal of the first detection channel, and a fixed terminal connected to the input terminal of the second detection channel; the second single-pole double-throw switch has a movable terminal connected to the power supply voltage, a fixed terminal connected to the input terminal of the second detection channel, and a fixed terminal connected to the input terminal of the first detection channel. It will be understood that each single-pole double-throw switch is equivalent to a combination of the two switches sw1 and sw2 described above.

[0047] FIG. 9 shows a schematic diagram of the working timing of the first detection channel and the second detection channel, FIG. 10 shows a schematic diagram of the working process of the first detection channel and the second detection channel, and FIG. 11 shows a schematic diagram of the calibration process. In this embodiment, the first duration period and the second duration period are equal, both being T. Each control cycle is 2T, which is composed of adjacent first and second duration periods. The channel voltage is selected by switches sw1 and sw2. During the first duration period of each control cycle, sw1 = 1 and sw2 = 0 (i.e., switch sw1 is turned on and switch sw2 is turned off), vth is the input voltage of the first detection subunit cha in the first detection channel, and vdd is used as the input voltage of the second detection subunit chb in the second detection channel. That is, the first detection channel is the threshold seeking channel, and the second detection channel is the working channel; the output data of the first detection subunit cha is dout_a, and dout_a is continuously output. The number of dout_a is determined by the length of a duration period T of the input voltage vth in cha. After being calibrated by the first calibration subunit, dout_a is output as dout_tha. For example, if the output rate of dout_a is 1 ns and T is 1 ms, then there are 1,000,000 dout_a in the T period, and 1,000,000 dout_a are obtained as the threshold voltage characterization value dout_tha after passing through the calibration algorithm.

[0048] In the next period T, that is, the second duration period, sw1 = 0 and sw2 = 1, vth is used as the input voltage of the second detection subunit chb, and vdd is used as the input voltage of the first detection subunit cha. That is, the first detection channel is the working channel, and the second detection channel is the threshold seeking channel; the output data of the second detection subunit chb is dout_b, and dout_b is continuously output. The number of dout_b is determined by the length of a duration period T of vth in the second detection subunit chb. For example, if the output rate of dout_b is 1 ns and T is 1 ms, then there are 1,000,000 dout_b in the T period, and 1,000,000 dout_b are obtained as the threshold voltage characterization value dout_thb after passing through the calibration algorithm. In the same period, the output data of the first detection subunit cha is dout_a detected for vdd, and dout_a is continuously output. The first comparison subunit compares dout_a detected for vdd and dout_tha obtained in the previous duration period T. When dout_a < dout_tha, an alarm signal warning_a is issued.

[0049] Similarly, in the next time period T, the second comparison subunit detects vdd to obtain dout_b, compares dout_b with dout_thb, and when dout_b < dout_thb, issues an alarm signal warning_b.

[0050] It can be seen that the threshold voltage is calibrated once every interval T, that is, dout_tha and dout_thb are reselected, realizing the online calibration of the threshold voltage.

[0051] The first calibration subunit and the second calibration subunit perform calibration using a digital domain averaging algorithm, which can achieve the effect of a low-pass filter in the digital domain, so as to obtain stable threshold voltage characterization values dout_tha and dout_thb. The bandwidth of the filter is determined by the length of the continuous time period T. The longer the length of T, the narrower the filter bandwidth and the better the filtering effect. However, considering that there is a continuous time period T between dout_tha and dout_a, and there is a continuous time period T between dout_thb and dout_b, a temperature deviation will be introduced. The length of T is limited within a certain range. The value of T does not exceed the set upper limit value. And considering that the temperature changes by 1 degree Celsius every 1 ms, the range of T is set to be less than or equal to <1> ms and greater than or equal to <2> ms.

[0052] As shown in FIG. 12, a power supply voltage drop detection system provided by an embodiment of the present disclosure includes the power supply voltage drop detection device 1201, a clock downscaling unit (clock strech) 1202, a power supply 1203, and a processing core (core) 1204 described above. The clock controller of the clock downscaling unit 1202 is respectively connected to the output ends of the first detection channel 11 and the second detection channel 12. The power supply voltage drop detection device 1201 outputs at least one of the first alarm signal and the second alarm signal to the clock downscaling unit 1202; the clock downscaling unit 1202 reduces the system frequency of the processing core 1204 under the control of at least one of the first alarm signal and the second alarm signal.

[0053] During operation, when there is a sudden change in the load of the power supply, as shown in Figure 12, the load current I_load suddenly increases, and the power supply voltage vdd will drop. When the power supply voltage drop is detected by the gating unit, the first detection channel, and the second detection channel, and the power supply voltage drops below the threshold voltage, that is, vdd < vth, the power supply voltage drop detection device 1201 issues the first alarm signal and / or the second alarm signal (represented as warning in Figure 12), and transmits the alarm signal to the clock frequency downscaling unit 1202. The clock frequency downscaling unit 1202 controls the processing core 1204 of the SOC system to downscale (freq_down). After the system downscales, the operating current will decrease, and the power supply voltage will increase, so that the power supply voltage will not drop too much due to a large load mutation and cause the system to work abnormally, ensuring the normal operation of the system.

[0054] The power supply voltage drop detection device provided by the embodiments of the present disclosure can quickly detect when the power supply voltage drops and cooperate with the system to reduce the operating frequency of the system, so that the power supply voltage drop rate slows down and returns to the normal value. The gating unit outputs the power supply voltage to the first detection channel and the threshold voltage to the second detection channel during the first duration of each control cycle; during the second duration of each control cycle, it outputs the threshold voltage to the first detection channel and the power supply voltage to the second detection channel, so that the two output terminals alternately output the power supply voltage and the threshold voltage. The first detection channel obtains the first voltage characterization value of the power supply voltage during the first duration and the second voltage characterization value of the threshold voltage during the second duration. If the first voltage characterization value is less than the second voltage characterization value, the first alarm signal is output. Similarly, the second detection channel outputs the second alarm signal. Therefore, the dual-channel time-sharing detection of the rapid drop of the power supply voltage by the first detection channel and the second detection channel is adopted. During each control cycle, the first detection channel and the second detection channel will re-detect the threshold voltage for calibration, realizing the PVT online calibration of the threshold voltage, improving the accuracy of the rapid drop detection of the power supply voltage, and the implementation process is simple.

[0055] Exemplarily, in the above embodiments, the structure of any delay chain in the first delay chain and the second delay chain is as shown in Figure 13. The power supply terminals of the components in the delay chain (not shown in the figure) are connected to the power supply terminal. Clkin is the clock signal. The inverter is the delay unit, and the combination of the inverter and the D flip-flop constitutes the delay chain. The delay_ctrl signal is the delay control signal, and the delay chain operates under the control of the delay control signal and clkin. The circuit circled in Figure 13 is the enlarged circuit of a single inverter. This is only an example, and the embodiments of the present disclosure do not limit the specific circuit structure of the delay chain. Any delay chain structure that can be used for time-to-data conversion can be used in the embodiments of the present disclosure.

[0056] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0057] Those skilled in the art will understand that although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features from different embodiments is meant to be within the scope of the present embodiment and to form different embodiments.

[0058] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A power supply voltage drop detection device, comprising a gating unit, a first detection channel and a second detection channel; the gating unit has two input terminals connected to a power supply voltage and a threshold voltage respectively, and two output terminals connected to the first detection channel and the second detection channel respectively; The gating unit is configured to: output the power supply voltage to the first detection channel and output the threshold voltage to the second detection channel in a first duration period of each control cycle; output the threshold voltage to the first detection channel and output the power supply voltage to the second detection channel in a second duration period of each control cycle, wherein each control cycle consists of a first duration period and a second duration period; The first detection channel is configured to: detect a first voltage characterizing value of the power supply voltage in the first duration period; and detect a second voltage characterizing value of the threshold voltage in the second duration period; compare the first voltage characterizing value in the first duration period of each control cycle with the second voltage characterizing value in the second duration period of the same control cycle, and output a first alarm signal when the first voltage characterizing value is less than the second voltage characterizing value; The second detection channel is configured to: detect a third voltage characterization value of the threshold voltage in the first duration period; and detect a fourth voltage characterization value of the power supply voltage in the second duration period; compare the third voltage characterization value of the first duration period of each control cycle with the fourth voltage characterization value of the second duration period of the same control cycle, and output a second alarm signal when the fourth voltage characterization value is less than the third voltage characterization value.

2. The power supply voltage drop detection device according to claim 1, wherein: The first detection channel comprises a first detection subunit, a first calibration subunit and a first comparison subunit connected in sequence; The first detection subunit is configured to: detect a first number of delay units respectively included in n detection windows within the first duration period of each control cycle, and use the first number as the first voltage characterization value; and detect a second number of delay units respectively included in m detection windows within the second duration period of each control cycle; wherein n is an integer greater than or equal to 1, and m is an integer greater than or equal to 1; The first calibration subunit is configured to: average q second numbers of the same control period to obtain the second voltage characterization value of the control period; wherein q is less than or equal to m; The first comparison subunit is configured to compare the first voltage characterization value of a first duration period of each control cycle with the second voltage characterization value of a second duration period of the same control cycle, and output a first alarm signal when the first voltage characterization value is less than the second voltage characterization value.

3. The power supply voltage drop detection device according to claim 1, wherein: The second detection channel comprises a second detection subunit, a second calibration subunit and a second comparison subunit connected in sequence; The second detection subunit is configured to detect the third number of delay units respectively included in the n detection windows within the first duration period of each control cycle; and the second detection subunit detects the fourth number of delay units respectively included in the m detection windows within the second duration period of each control cycle, and uses the fourth number as the fourth voltage characterization value; wherein n is an integer greater than or equal to 1, and m is an integer greater than or equal to 1; The second calibration subunit is configured to average p third numbers of the same control period to obtain the third voltage characterization value of the control period; wherein p is less than or equal to n; The second comparison subunit is configured to compare the third voltage characterizing value of the first duration period of each control cycle The fourth voltage characterizing value of the second duration period of the same control cycle, and outputting a second alarm signal when the fourth voltage characterizing value is less than the third voltage characterizing value.

4. The power supply voltage drop detection device according to claim 2, wherein: The first detection subunit includes a first frequency divider and a first delay chain; The signal output end of the first frequency divider is connected to the signal input end of the first delay chain, the power input end of the first delay chain is connected to the power supply voltage, and the output end of the first delay chain serves as the output end of the first detection subunit; The first frequency divider is configured to output a divided-by-two frequency signal through a signal output terminal, and a high level time period of the divided-by-two frequency signal is the detection window.

5. The power supply voltage drop detection device according to claim 3, wherein: The second detection subunit includes a second frequency divider and a second delay chain; The signal output end of the second frequency divider is connected to the signal input end of the second delay chain, the power input end of the second delay chain is connected to the power supply voltage, and the output end of the second delay chain serves as the output end of the second detection subunit; The second frequency divider is configured to output a divided-by-two frequency signal through a signal output terminal, and a high level time period of the divided-by-two frequency signal is the detection window.

6. The power supply voltage drop detection device according to any one of claims 1 to 5, wherein: The gating unit includes a first group of switch elements and a second group of switch elements; The first group of switch elements includes a first switch and a second switch; one end of the first switch is connected to the threshold voltage, and the other end is connected to the input end of the first detection channel; one end of the second switch is connected to the threshold voltage, and the other end is connected to the input end of the second detection channel; The second group of switch elements includes a third switch and a fourth switch; one end of the third switch is connected to the power supply voltage, and the other end is connected to the input end of the second detection channel; one end of the fourth switch is connected to the power supply voltage, and the other end is connected to the input end of the first detection channel.

7. The power supply voltage drop detection device according to any one of claims 1 to 6, wherein: The first duration period and the second duration period have the same duration.

8. The power supply voltage drop detection device according to any one of claims 1 to 7, wherein: The device also includes a voltage divider circuit; The input end of the voltage divider circuit is connected to the power supply voltage, and the output end of the voltage divider circuit is connected to the second input end of the gating unit; The voltage dividing circuit is configured to divide the power supply voltage and output the threshold voltage.

9. A power supply voltage drop detection system, wherein: The device comprises a power supply voltage drop detection device according to any one of claims 1 to 8, a clock frequency reduction unit, a power supply and a processing core; The power supply voltage drop detection device is configured to output at least one of the first alarm signal and the second alarm signal to the clock frequency reduction unit; The clock frequency reduction unit is configured to reduce the system frequency of the processing core under the control of at least one of the first alarm signal and the second alarm signal.

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