METHODS TO EXTEND NoC INTERCONNECT ACROSS MULTIPLE DICE IN 3D
The integration of an inter-die bus with a driver circuit in vertically-stacked IC devices addresses timing and signal strength issues in 3D NoC interconnects, achieving efficient and low-latency communication across multiple dice, thus improving IC performance and memory access.
Patent Information
- Application Number
- PCT/US2024/028435
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-05-31
- Filing Date
- 2024-05-08
- Publication Date
- 2024-12-05
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Figure US2024028435_05122024_PF_FP_ABST
Abstract
Claims
CLAIMSWhat is claimed is:1 . An integrated circuit (IC) device, comprising: first and second vertically-stacked IC dice, wherein the first IC die comprises network-on-chip (NoC) circuitry; and an inter-die bus configured to interface between the packet-switched NoC and the second IC die, wherein the inter-die bus comprises a first driver circuit coupled to inter-die links of the inter-die bus.
2. The IC device of claim 1 , wherein the first driver circuit is further configured to drive packets over the inter-die links synchronous with the NoC circuitry.
3. The IC device of claim 1 , wherein the inter-die bus is further configured to de-packetize a request, and wherein the first driver circuit is further configured to drive the de-packetized request over the inter-die links asynchronous with the NoC circuitry.
4. The IC device of claim 3, wherein the inter-die bus is further configured to de-packetize the request based on a point-to-point protocol, and wherein the first driver circuit is further configured to drive the de-packetized request over the interdie links based on the point-to-point protocol.
5. The IC device of claim 1 , wherein the inter-die bus is configured as a unidirectional inter-die bus.
6. The IC device of claim 1 , wherein the inter-die bus is configured as a bidirectional inter-die bus.
7. The IC device of claim 1 , further comprising one or more additional inter-die buses configured to interface between the packet-switched NoC and the second IC die.
8. The IC device of claim 1 , wherein:the first IC die further comprises a first interface circuit of the inter-die bus and a first NoC packet switch (NPS); the first interface circuit comprises a first master interface circuit configured to receive a first request from the first NPS and de-packetize the first request based on a point-to-point protocol; and the first interface circuit further comprises the first driver circuit, wherein the first driver circuit is further configured to drive the de-packetized first request over the inter-bus links, asynchronously with the NoC circuitry.
9. The IC device of claim 8, wherein: the second IC die comprises a second interface circuit of the inter-die bus and a second NPS; and the second interface circuit comprises a first slave interface circuit configured to receive the de-packetized first request over the inter-die links, re- packetize the de-packetized first request, and forward the re-packetized first request to the second NPS.
10. The IC device of claim 1 , wherein: the first IC die further comprises a first interface circuit of the inter-die bus and a NoC packet switch (NPS); the second IC die further comprises a circuit block configured to output a request based on a point-to-point protocol, and a second interface circuit of the inter-die bus, wherein the second interface comprises the first driver circuit, and wherein the first driver circuit is further configured to drive the request over the inter-die links asynchronous with the packet-switched NoC; and the first interface circuit comprises a NoC slave unit (NSU) configured to receive the request over the inter-die links, packetize the request, and forward the packetized request to the NPS.
11. The IC device of claim 1 , wherein: the first IC die further comprises a first interface circuit of the inter-die bus configured to receive a packetized request from a NoC packet switch (NPS) of the NoC circuitry, wherein the first interface circuit comprises a NoC master unit (NMU) configured to de-packetize the request based on a point-to-point protocol, andwherein the first interface circuit further comprises the first driver circuit configured to drive the de-packetized request over the inter-die links; and the second IC die further comprises a second interface circuit of the inter-die bus, wherein the second interface is configured to provide the de-packetized request to a circuit block of the second IC die.
12. The IC device of claim 11 , wherein: the second IC die further comprises a second driver circuit configured to boost the de-packetized request.
13. An integrated circuit (IC) device, comprising: first and second vertically-stacked IC dice comprising respective first and second network-on-chip (NoC) packet switches (NPSs) of a 3-dimensional (3D) packet-switched NoC; and an inter-die bus configured to interface between the first and second NPSs asynchronous with the 3D packet-switched NoC, wherein the inter-die bus comprises a driver circuit coupled to inter-die links of the inter-die bus.
14. The IC device of claim 13, wherein the first and second IC dice further comprise respective first and second interface circuits of the inter-die bus, and wherein the first and second interface circuits are configured to communicate over the inter-die links based on a point-to-point protocol.
15. An integrated circuit (IC) device, comprising: first and second vertically-stacked IC dice, wherein the first IC die comprises a network-on-chip (NoC) packet switch (NPS) of a packet-switched NoC; and a dedicated inter-die bus configured to interface between the NPS and a circuit block of second IC die asynchronous with the packet-switched NoC based on a point-to-point protocol, wherein the inter-die bus comprises a driver circuit coupled to inter-die links of the inter-die bus.
Citation Information
Patent Citations
Three-dimensional network-on-chip structure and working method
CN113238984A
