Efficient radio resources utilization for transmissions of control information compressed with deep learning and arithmetic coding techniques

Abstract

There are provided measures for efficient radio resources utilization in control information transmissions. Such measures exemplarily comprise estimating, for a present sequence of bits, a probability distribution, wherein said probability distribution being indicative of, for each bit of said present sequence of bits, a respective probability of said bit having a first predetermined value, and encoding, as an encoded present sequence of bits, said present sequence of bits utilizing arithmetic encoding with said probability distribution and said present sequence of bits as inputs.

Description

[0001] EFFICIENT RADIO RESOURCES UTILIZATION FOR TRANSMISSIONS OF CONTROL INFORMATION COMPRESSED WITH DEEP LEARNING AND ARITHMETIC CODING TECHNIQUES

[0002] Field

[0003] Various example embodiments relate to efficient radio resources utilization in control information transmissions. More specifically, various example embodiments exemplarily relate to measures (including methods, apparatuses and computer program products) for realizing efficient radio resources utilization in control information transmissions.

[0004] Background

[0005] The present specification generally relates to transmission of control information, the generation and encoding and decoding thereof, as well as negotiation processing in relation thereto.

[0006] With a growing demand for wireless communication systems, radio resources become precious. A higher efficiency of using limited bandwidth provides a larger capacity. In particular, 3rdGeneration Partnership Project (3GPP) 6thGeneration (6G) networks are presumed as needing to handle massive numbers of devices, and it is expected that even more device types will connect to the 6G network than to the current 5thGeneration (5G) system.

[0007] To precisely control these large number of devices, control channels need to efficiently utilize the limited resources.

[0008] As a result, accurately transmitting e.g. source downlink / uplink control information to the receiver side with a low overhead delivers a larger capacity.

[0009] Moreover, the large variety of wireless scenarios introduces numerous functions that a wireless device needs to respond to, based on the control information. Consequently, the control information requires a (an increasingly) long binary sequence to carry all the necessary information, which means that more radio resources are required for the control plane.

[0010] In fact, a shorter control message would require a smaller number of radio resources so that more devices could be served in a limited time and a potential coding gain could be obtained to further improve the reliability of the channel.

[0011] Hence, the problem arises that it is to be coped with an increasing amount of control information to be transmitted for an increasing number of served devices over a limited amount of transmission resources.

[0012] Hence, there is a need to provide for efficient radio resources utilization in control information transmissions.

[0013] Summary

[0014] Various example embodiments aim at addressing at least part of the above issues and / or problems and drawbacks.

[0015] Various aspects of example embodiments are set out in the appended claims.

[0016] According to an exemplary aspect, there is provided a method comprising estimating, for a present sequence of bits, a probability distribution, wherein said probability distribution being indicative of, for each bit of said present sequence of bits, a respective probability of said bit having a first predetermined value, and encoding, as an encoded present sequence of bits, said present sequence of bits utilizing arithmetic encoding with said probability distribution and said present sequence of bits as inputs.

[0017] According to an exemplary aspect, there is provided a method comprising estimating, for a present sequence of bits, a probability distribution, wherein said probability distribution being indicative of, for each bit of said present sequence of bits, a respective probability of said bit having a first predetermined value, receiving an encoded present sequence of bits, and decoding, as said present sequence of bits, said encoded present sequence of bits utilizing arithmetic decoding with said probability distribution and said encoded present sequence of bits as inputs.

[0018] According to an exemplary aspect, there is provided an apparatus comprising estimating circuitry configured to estimate, for a present sequence of bits, a probability distribution, wherein said probability distribution being indicative of, for each bit of said present sequence of bits, a respective probability of said bit having a first predetermined value, and encoding circuitry configured to encode, as an encoded present sequence of bits, said present sequence of bits utilizing arithmetic encoding with said probability distribution and said present sequence of bits as inputs.

[0019] According to an exemplary aspect, there is provided an apparatus comprising estimating circuitry configured to estimate, for a present sequence of bits, a probability distribution, wherein said probability distribution being indicative of, for each bit of said present sequence of bits, a respective probability of said bit having a first predetermined value, receiving circuitry configured to receive an encoded present sequence of bits, and decoding circuitry configured to decode, as said present sequence of bits, said encoded present sequence of bits utilizing arithmetic decoding with said probability distribution and said encoded present sequence of bits as inputs.

[0020] According to an exemplary aspect, there is provided an apparatus comprising at least one processor, and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to perform estimating, for a present sequence of bits, a probability distribution, wherein said probability distribution being indicative of, for each bit of said present sequence of bits, a respective probability of said bit having a first predetermined value, and encoding, as an encoded present sequence of bits, said present sequence of bits utilizing arithmetic encoding with said probability distribution and said present sequence of bits as inputs.

[0021] According to an exemplary aspect, there is provided an apparatus comprising at least one processor, and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to perform estimating, for a present sequence of bits, a probability distribution, wherein said probability distribution being indicative of, for each bit of said present sequence of bits, a respective probability of said bit having a first predetermined value, receiving an encoded present sequence of bits, and decoding, as said present sequence of bits, said encoded present sequence of bits utilizing arithmetic decoding with said probability distribution and said encoded present sequence of bits as inputs.

[0022] According to an exemplary aspect, there is provided a computer program product comprising computer-executable computer program code which, when the program is run on a computer (e.g. a computer of an apparatus according to any one of the aforementioned apparatus-related exemplary aspects of the present disclosure), is configured to cause the computer to carry out the method according to any one of the aforementioned method- related exemplary aspects of the present disclosure.

[0023] Such computer program product may comprise (or be embodied) a (tangible) computer-readable (storage) medium or the like on which the computerexecutable computer program code is stored, and / or the program may be directly loadable into an internal memory of the computer or a processor thereof.

[0024] Any one of the above aspects enables an efficient reduction of radio resources necessary for transmission of a compilation of control information without decreasing accuracy of the control information to thereby solve at least part of the problems and drawbacks identified in relation to the prior art. By way of example embodiments, there is provided efficient radio resources utilization in control information transmissions. More specifically, by way of example embodiments, there are provided measures and mechanisms for realizing efficient radio resources utilization in control information transmissions.

[0025] Thus, improvement is achieved by methods, apparatuses and computer program products enabling / realizing efficient radio resources utilization in control information transmissions.

[0026] Brief description of the drawings

[0027] In the following, the present disclosure will be described in greater detail by way of non-limiting examples with reference to the accompanying drawings, in which

[0028] FIG. 1 is a block diagram illustrating an apparatus according to example embodiments,

[0029] FIG. 2 is a block diagram illustrating an apparatus according to example embodiments,

[0030] FIG. 3 is a block diagram illustrating an apparatus according to example embodiments,

[0031] FIG. 4 is a block diagram illustrating an apparatus according to example embodiments,

[0032] FIG. 5 is a schematic diagram of a procedure according to example embodiments,

[0033] FIG. 6 is a schematic diagram of a procedure according to example embodiments, FIG. 7 is a diagram schematically comparing utilization of radio resources,

[0034] FIG. 8 is a block diagram illustrating a processing chain on a transmitter and receiver side according to example embodiments,

[0035] FIG. 9 is a block diagram illustrating processing chains on a transmitter and receiver side according to example embodiments,

[0036] FIG. 10 is a schematic diagram of a procedure according to example embodiments,

[0037] FIG. 11 (FIG. 11(A) and 11(B)) shows schematic diagrams of signaling sequences according to example embodiments,

[0038] FIG. 12 (FIG. 12(A) and 12(B)) shows schematic diagrams of signaling sequences according to example embodiments,

[0039] FIG. 13 is a schematic diagram illustrating a distribution of lengths resulting from encoding processing according to example embodiments,

[0040] FIG. 14 is a schematic diagram illustrating a coding gain resulting from encoding processing according to example embodiments, and

[0041] FIG. 15 is a block diagram alternatively illustrating apparatuses according to example embodiments.

[0042] Detailed description

[0043] The present disclosure is described herein with reference to particular nonlimiting examples and to what are presently considered to be conceivable embodiments. A person skilled in the art will appreciate that the disclosure is by no means limited to these examples, and may be more broadly applied. It is to be noted that the following description of the present disclosure and its embodiments mainly refers to specifications being used as non-limiting examples for certain exemplary network configurations and deployments. Namely, the present disclosure and its embodiments are mainly described in relation to 3GPP specifications being used as non-limiting examples for certain exemplary network configurations and deployments. As such, the description of example embodiments given herein specifically refers to terminology which is directly related thereto. Such terminology is only used in the context of the presented non-limiting examples, and does naturally not limit the disclosure in any way. Rather, any other communication or communication related system deployment, etc. may also be utilized as long as compliant with the features described herein.

[0044] Hereinafter, various embodiments and implementations of the present disclosure and its aspects or embodiments are described using several variants and / or alternatives. It is generally noted that, according to certain needs and constraints, all of the described variants and / or alternatives may be provided alone or in any conceivable combination (also including combinations of individual features of the various variants and / or alternatives).

[0045] As used herein, "at least one of the following: " and "at least one of " and similar wording, where the list of two or more elements are joined by "and" or "or", mean at least any one of the elements, or at least any two or more of the elements, or at least all the elements.

[0046] According to example embodiments, in general terms, there are provided measures and mechanisms for (enabling / realizing) efficient radio resources utilization in control information transmissions. As mentioned above, it is to be coped with an increasing amount of control information to be transmitted for an increasing number of served devices over a limited amount of transmission resources.

[0047] To cope with an increasing number of served devices and a limited amount of transmission resources, the amount of control information per served device may either be reduced or it may be compressed.

[0048] Reduction would contradict the demand for an increased amount of information to be transmitted in view of the expected large variety of wireless scenarios introducing numerous functions that a wireless device needs to respond to. Compression, of not lossless, would reduce accuracy of the control information, and may contradict the demand for an increased amount of information to be transmitted as well. Downlink control information (DCI) messages require high reliability, and information loss through lossy compression cannot be an option.

[0049] In 5G New Radio (NR), once a DCI message is generated, cyclic redundancy check (CRC) is attached to it, and the concatenated sequence is encoded by a channel code.

[0050] DCI messages are generally assumed to be independently generated.

[0051] However, in real-systems, the behavior of devices is not random and usually follows recognizable patterns. This creates correlations in the DCI messages. For this case, machine learning (ML) techniques were found as being helpful for learning and exploiting these correlations, that can potentially reduce the length of a DCI message.

[0052] In 5G NR, polar codes may be used as channel codes for the DCI message.

[0053] Using a variational autoencoder to provide an estimation on latent variables that are required by bits-back coding as a lossless compression technique requires additional random bits as the initialization for sampling. This makes it unsuitable for DCI compression, as the additional random bits extend the DCI length.

[0054] According to example embodiments, a recurrent neural network is used to estimate a probability distribution for symbols to be encoded. This architecture explores the correlation in a batch of symbols. In addition thereto, this architecture exploits both temporal and spatial correlations of control bits.

[0055] According to example embodiments, the problem of reducing the transmission overhead of the downlink (DL) control plane (CP) is addressed to improve the system throughput and overall reliability.

[0056] FIG. 7 is a diagram schematically comparing utilization of radio resources, and in particular illustrates a high-level representation of the motivation of DCI compression.

[0057] Namely, as illustrated in FIG. 7, according to example embodiments, it is targeted to a reduction of the DCI message length, so that more devices can be scheduled in a limited time interval and a better reliability can be obtained.

[0058] In 5G NR, the DCI messages intended for any given user equipment (UE) are generated anew in each slot that the UE is scheduled in. The content of such DCI messages depends on the decisions made by the different resource allocation functions in the radio access network (RAN), such as link adaptation (LA), closed-loop power control (CLPC), and the scheduler, among others.

[0059] Despite the independence of these decisions between consecutive slots, many of the fields in the DCI data structure will repeat themselves often.

[0060] This redundancy is currently neglected and could be leveraged to compress the bit size of the DCI itself. Furthermore, when the wireless connectivity follows certain patterns (e.g., the channel is stable, or the device is non-active / active frequently), redundancies will occur even more often.

[0061] In addition, it is expected that in 6G, more complex functionalities will be required, which increases the DCI length even more.

[0062] Ultimately, the 6G CP will require abundant radio resources, which will limit the number of UEs that the system can serve in a limited time interval.

[0063] To tackle this problem, a direct solution is to reduce the length of DCI message without degrading the decoding performance.

[0064] According to example embodiments, a lossless compressor is selected so that all information is preserved during the encoding. A similar approach can be applied to the uplink control channel. The framework according to example embodiments is extremely valuable for future massive connectivity scenario where many devices require scheduling resources. Specifically, according to example embodiments, a deep learning-based method is provided, which learns hidden time-domain correlations and then uses them to compress the DCI message.

[0065] According to example embodiments, thus, among others, a new DCI compressor (compressing entity) and a new DCI decompressor (decompressing entity) is provided.

[0066] Hence, in brief, according to example embodiments, methods and means and signaling for encoding e.g. a downlink control information message in e.g. 6G radio access networks are provided. The ML-based encoding method according to example embodiments is a powerful technique for producing ultra-reliable devices and providing massive connectivity services for future 6G networks efficiently.

[0067] According to example embodiments, a deep learning-based DCI message compression method is provided to improve the reliability of the downlink control plane and the capacity of a wireless system.

[0068] In particular, a lossless compression technique is applied to encode the DCI message so that there is no information loss compared to the existing design.

[0069] According to example embodiments, the temporal and spatial correlations of DCI messages are leveraged, and the length of a DCI message is reduced. A shorter DCI increases the number of addressable devices and improves the decoding success rate. In other words, a base transceiver station (BTS) can schedule more UEs per transmission time interval (TTI) due to the lower number of necessary physical downlink control channel (PDCCH) resources (i.e., lower aggregation level (AL)).

[0070] According to example embodiments, a DCI compression concept and its corresponding encoder-decoder pair are provided: In particular, the DCI compression performs a lossless compression, which not only augments the PDCCH capacity, but it also improves the DCI decoding success rate.

[0071] According to further example embodiments, an encoder based on deep learning and arithmetic coding is provided: To encode the DCI, a neural network-based structure is utilized to estimate the probability distribution of the DCI control bits to be encoded by arithmetic coding. The neural network explores the temporal and spatial correlations from the input features and provides an accurate estimate on the probability distribution. As a result, a shorter DCI message can be obtained. According to further example embodiments, list decoding for encoded DCI messages is applied: Besides the compression structure for DCI, to explore the potential coding gain, usage of a list decoding method is contemplated to decode the polar encoded DCI message without any prior knowledge on the DCI compressed length. With the help of list decoding, the decoding performance can be further enhanced.

[0072] FIG. 8 is a block diagram illustrating a processing chain on a transmitter and receiver side according to example embodiments, and in particular illustrates a high-level representation of DCI compression and decompression.

[0073] FIG. 8 briefly summarizes the DCI compression and decompression chain. Compared to traditional DCI generation and transmission steps over a PDCCH, example embodiments additionally introduce a deep learning-based lossless DCI compression processor, which reduces the DCI length. Symmetrically, at the receiver side, a lossless decompression block is required to recuperate the DCI message.

[0074] In summary, according to example embodiments, there is a training phase for the neural network to learn the probability distribution of each control bit. In the test phase, the neural network model is loaded and used by the arithmetic coding. The benefits of adding the DCI compression and decompression processors include:

[0075] - A higher-capacity PDCCH: Less radio resources are required for the transmitter and receiver to coordinate. The radio resources are limited, and reducing the DCI length is a direct way to schedule more devices in a certain time interval.

[0076] - Improved reliability in the control channel: A shorter DCI length provides the room to reduce the code rate for channel coding. With the assistance of more redundant bits, the reliability of decoding can be further improved.

[0077] Example embodiments are specified below in more detail. FIG. 1 is a block diagram illustrating an apparatus according to example embodiments. The apparatus may be an access node 10 such as a base station or base transceiver station (BTS) comprising an estimating circuitry 11 and an encoding circuitry 12. The estimating circuitry 11 estimates, for a present sequence of bits, a probability distribution, wherein said probability distribution being indicative of, for each bit of said present sequence of bits, a respective probability of said bit having a first predetermined value. The encoding circuitry 12 encodes, as an encoded present sequence of bits, said present sequence of bits utilizing arithmetic encoding with said probability distribution and said present sequence of bits as inputs. FIG. 5 is a schematic diagram of a procedure according to example embodiments. The apparatus according to FIG. 1 may perform the method of FIG. 5 but is not limited to this method. The method of FIG. 5 may be performed by the apparatus of FIG. 1 but is not limited to being performed by this apparatus.

[0078] As shown in FIG. 5, a procedure according to example embodiments comprises an operation of estimating (S51), for a present sequence of bits, a probability distribution, wherein said probability distribution being indicative of, for each bit of said present sequence of bits, a respective probability of said bit having a first predetermined value, and an operation of encoding (S52), as an encoded present sequence of bits, said present sequence of bits utilizing arithmetic encoding with said probability distribution and said present sequence of bits as inputs.

[0079] FIG. 2 is a block diagram illustrating an apparatus according to example embodiments. In particular, FIG. 2 illustrates a variation of the apparatus shown in FIG. 1. The apparatus according to FIG. 2 may thus further comprise a transmitting circuitry 21, a utilizing circuitry 22, a machine-learning circuitry 23, an adding circuitry 24, a receiving circuitry 25, and / or an inhibiting circuitry 26. In an embodiment at least some of the functionalities of the apparatus shown in FIG. 1 (or 2) may be shared between two physically separate devices forming one operational entity. Therefore, the apparatus may be seen to depict the operational entity comprising one or more physically separate devices for executing at least some of the described processes. Such shared architecture, may comprise a remote control unit (RCU), such as a host computer or a server computer, operatively coupled (e.g. via a wireless or wired network) to a remote radio head (RRH) located in the base station or eNB, for example. In an embodiment, at least some of the described processes may be performed by the RCU. In an embodiment, the execution of at least some of the described processes may be shared among the RRH and the RCU. In practice, any digital signal processing task may be performed in either the RRH or the RCU and the boundary where the responsibility is shifted between the RRH and the RCU may be selected according to implementation.

[0080] According to a variation of the procedure shown in FIG. 5, exemplary additional operations are given, which are inherently independent from each other as such. According to such variation, an exemplary method according to example embodiments may comprise an operation of transmitting said encoded present sequence of bits.

[0081] According to a variation of the procedure shown in FIG. 5, exemplary details of the estimating operation (S51) are given, which are inherently independent from each other as such. Such exemplary estimating operation (S51) according to example embodiments may comprise an operation of utilizing a neural network estimator model fed with a predetermined number of previous sequences of bits previous to said present sequence of bits.

[0082] According to a variation of the procedure shown in FIG. 5, exemplary additional operations are given, which are inherently independent from each other as such. According to such variation, an exemplary method according to example embodiments may comprise an operation of machine-learning said neural network estimator model.

[0083] According to a variation of the procedure shown in FIG. 5, exemplary additional operations are given, which are inherently independent from each other as such. According to such variation, an exemplary method according to example embodiments may comprise an operation of transmitting said neural network estimator model.

[0084] According to further example embodiments, said neural network estimator model represents temporal and spatial correlations among said previous sequences of bits.

[0085] According to a variation of the procedure shown in FIG. 5, exemplary details of the encoding operation (S52) are given, which are inherently independent from each other as such. Such exemplary encoding operation (S52) according to example embodiments may comprise an operation of adding zero-paddings to said encoded present sequence of bits.

[0086] According to a variation of the procedure shown in FIG. 5, exemplary additional operations are given, which are inherently independent from each other as such. According to such variation, an exemplary method according to example embodiments may comprise an operation of transmitting a bit sequence compression request, an operation of receiving a bit sequence compression response, and, if said bit sequence compression response is indicative of acknowledgement, an operation of transmitting information on a bit sequence compression being based on neural network estimation and a count of previous sequences of bits to be considered for said neural network estimation, and, if said bit sequence compression response is indicative of non-acknowledgement, an operation of inhibiting encoding of said present sequence of bits utilizing arithmetic encoding. According to a variation of the procedure shown in FIG. 5, exemplary additional operations are given, which are inherently independent from each other as such. According to such variation, an exemplary method according to example embodiments may comprise an operation of receiving a bit sequence compression request, an operation of transmitting a bit sequence compression response, and, if said bit sequence compression response is indicative of acknowledgement, an operation of transmitting information on a bit sequence compression being based on neural network estimation and a count of previous sequences of bits to be considered for said neural network estimation, and, if said bit sequence compression response is indicative of non-acknowledgement, an operation of inhibiting encoding of said present sequence of bits utilizing arithmetic encoding.

[0087] According to further example embodiments, said present sequence of bits represents downlink control information.

[0088] According to further example embodiments, said present sequence of bits represents uplink control information.

[0089] FIG. 3 is a block diagram illustrating an apparatus according to example embodiments. The apparatus may be a terminal 30 such as a user equipment (UE) comprising an estimating circuitry 31, a receiving circuitry 32, and a decoding circuitry 33. The estimating circuitry 31 estimates, for a present sequence of bits, a probability distribution, wherein said probability distribution being indicative of, for each bit of said present sequence of bits, a respective probability of said bit having a first predetermined value. The receiving circuitry 32 receives an encoded present sequence of bits. The decoding circuitry 33 decodes, as said present sequence of bits, said encoded present sequence of bits utilizing arithmetic decoding with said probability distribution and said encoded present sequence of bits as inputs. FIG. 6 is a schematic diagram of a procedure according to example embodiments. The apparatus according to FIG. 3 may perform the method of FIG. 6 but is not limited to this method. The method of FIG. 6 may be performed by the apparatus of FIG. 3 but is not limited to being performed by this apparatus.

[0090] As shown in FIG. 6, a procedure according to example embodiments comprises an operation of estimating (S61), for a present sequence of bits, a probability distribution, wherein said probability distribution being indicative of, for each bit of said present sequence of bits, a respective probability of said bit having a first predetermined value, an operation of receiving (S62) an encoded present sequence of bits, and an operation of decoding (S63), as said present sequence of bits, said encoded present sequence of bits utilizing arithmetic decoding with said probability distribution and said encoded present sequence of bits as inputs.

[0091] FIG. 4 is a block diagram illustrating an apparatus according to example embodiments. In particular, FIG. 4 illustrates a variation of the apparatus shown in FIG. 3. The apparatus according to FIG. 4 may thus further comprise a utilizing circuitry 41, a machine-learning circuitry 42, a performing circuitry 43, a passing circuitry 44, a transmitting circuitry 45, a considering circuitry 46, and / or an inhibiting circuitry 47.

[0092] In an embodiment at least some of the functionalities of the apparatus shown in FIG. 3 (or 4) may be shared between two physically separate devices forming one operational entity. Therefore, the apparatus may be seen to depict the operational entity comprising one or more physically separate devices for executing at least some of the described processes.

[0093] According to a variation of the procedure shown in FIG. 6, exemplary details of the estimating operation (S61) are given, which are inherently independent from each other as such. Such exemplary estimating operation (S61) according to example embodiments may comprise an operation of utilizing a neural network estimator model fed with a predetermined number of previous sequences of bits previous to said present sequence of bits. According to a variation of the procedure shown in FIG. 6, exemplary additional operations are given, which are inherently independent from each other as such. According to such variation, an exemplary method according to example embodiments may comprise an operation of machine-learning said neural network estimator model.

[0094] According to a variation of the procedure shown in FIG. 6, exemplary additional operations are given, which are inherently independent from each other as such. According to such variation, an exemplary method according to example embodiments may comprise an operation of receiving said neural network estimator model.

[0095] According to further example embodiments, said neural network estimator model represents temporal and spatial correlations among said previous sequences of bits.

[0096] According to a variation of the procedure shown in FIG. 6, exemplary details of the decoding operation (S63) are given, which are inherently independent from each other as such. Such exemplary decoding operation (S63) according to example embodiments may comprise an operation of performing, as a preparation to cope with zero-paddings added to said encoded present sequence of bits, list-decoding on said encoded present sequence of bits including a cyclic redundancy check, and an operation of passing a result of said list-decoding to said arithmetic decoding.

[0097] According to a variation of the procedure shown in FIG. 6, exemplary additional operations are given, which are inherently independent from each other as such. According to such variation, an exemplary method according to example embodiments may comprise an operation of receiving a bit sequence compression request, an operation of transmitting a bit sequence compression response, and, if said bit sequence compression response is indicative of acknowledgement, an operation of receiving information on a bit sequence compression being based on neural network estimation and a count of previous sequences of bits to be considered for said neural network estimation, and an operation of considering said count of previous sequences of bits for determining a predetermined number of previous sequences of bits previous to said present sequence of bits to be fed to a neural network estimator model, and, if said bit sequence compression response is indicative of nonacknowledgement, an operation of inhibiting decoding of said encoded present sequence of bits utilizing arithmetic encoding.

[0098] According to a variation of the procedure shown in FIG. 6, exemplary additional operations are given, which are inherently independent from each other as such. According to such variation, an exemplary method according to example embodiments may comprise an operation of transmitting a bit sequence compression request, an operation of receiving a bit sequence compression response, and, if said bit sequence compression response is indicative of acknowledgement, an operation of receiving information on a bit sequence compression being based on neural network estimation and a count of previous sequences of bits to be considered for said neural network estimation, and an operation of considering said count of previous sequences of bits for determining a predetermined number of previous sequences of bits previous to said present sequence of bits to be fed to a neural network estimator model, and, if said bit sequence compression response is indicative of nonacknowledgement, an operation of inhibiting decoding of said encoded present sequence of bits utilizing arithmetic encoding.

[0099] According to further example embodiments, said present sequence of bits represents downlink control information. According to further example embodiments, said present sequence of bits represents uplink control information.

[0100] Example embodiments outlined and specified above are explained below in more specific terms.

[0101] According to example embodiments, input features for the neural network may be implemented as follows:

[0102] As mentioned above, according to example embodiments, a deep learningbased method for DCI compression is provided.

[0103] This includes building the compressor using arithmetic coding, which requires a probability distribution over the DCI bits at its input. The probability distribution refers to the probability estimate of each DCI bit being a 0 or 1.

[0104] To estimate this probability distribution, according to example embodiments, a neural network (NN) is implemented. In particular, during the training phase, the previous DCI messages are collected, and they serve as the input features for the neural network.

[0105] Let b* be the DCI with a bit length of A at a scheduling time index t and (x) = pbt^ be the neural network function that maps input features x to the estimated probability for the i -th control bit bt of being a 1. Correspondingly, 1 - (x) = pb^0gives the probability for the i-th control bit btof being a 0. Note that DCI bit lengths can vary as per standards specifications, but for a model according to example embodiments, all DCI messages are assumed to have the length A, where A is the maximum DCI message length and all shorter DCI messages are zero padded to have length A.

[0106] Given a memory buffer with a size of M, the input features of the ith control bit contain two portions of features to explore the correlations in the time and spatial domains, respectively. Denote x as the input features for i e {1,2, ... , A) at time index t, the two portions of features are denoted as xtl=

[0107] To exploit the temporal correlation, according to example embodiments, a memory buffer stores the most recent M DCI messages which give xt= that has xxe IF2XJ4M. Note that btis not included in xtllas is the DCI message to be encoded and all the control bits at time index t share the common information from previous DCI messages. The neural network estimator does not have any prior knowledge on b1.

[0108] Since DCI is encoded sequentially by arithmetic coding, to exploit the spatial correlation, according to example embodiments, a Toeplitz matrix is set up, and each row is concatenated with xtll, which refers to the temporal information to form the final features for the neural network estimator. -1 is used to distinguish the null information from the binary control bit. As a result, the first row of the Toeplitz matrix has all -Is with a length of A - 1 and the first column of the Toeplitz matrix contains [-l,b{,b2, ...,b^_±]T. In the end, the Toeplitz matrix becomes: and each row of xt 2, which serves as x^2lis finally concatenated with x^to form the final input features for the neural network.

[0109] According to example embodiments, DCI compression may be implemented as follows:

[0110] FIG. 9 is a block diagram illustrating processing chains on a transmitter and receiver side according to example embodiments, and in particular illustrates a supervised-learning technique for DCI compression and decompression according to example embodiments. As illustrated in FIG. 9, once the input features for each control bit have been settled, the neural network takes the temporal and spatial features sequentially from x to x to provide the estimate on probability distribution. Eventually, an encoded binary sequence is generated as the output of DCI compressor.

[0111] Note that since the neural network provides an estimate on the probability distribution, the length of encoded DCI at a particular TTI varies. To solve the variety issue of the length of encoded DCI, according to example embodiments, zero-paddings can be attached to fix the output length of a DCI encoder.

[0112] According to example embodiments, channel decoding may be implemented as follows:

[0113] According to example embodiments, a list decoding algorithm is provided to explore the prior information on the zero-paddings to obtain the coding gain from the encoded DCI.

[0114] FIG. 10 is a schematic diagram of a procedure according to example embodiments, and in particular schematically illustrates list polar decoding according to example embodiments.

[0115] Namely, to explore the coding gain with a shorter DCI length, according to example embodiments, a direct method is to implement a list decoding at the receiver side to further enhance the decoding performance. Without any prior knowledge on the length of encoded DCI, the receiver can preset a list size of L. Since zero-paddings are added to the end of encoded DCI, the channel decoder can manually set the last I bits to Os (for a soft-decision decoder, the log-likelihood ratios (LLR) can be set to the largest threshold) and repeat the decoder for L times with I e {0,1,2, 1}. In this way, the receiver does not need to know the exact length of encoded DCI. If the CRC is passed, the channel decoder can convey the decoding result to the DCI decoder to recover the original DCI message. The coding gain is obtained from the channel decoder. The DCI is compressed by a lossless compressor, which does not introduce bit errors when the channel encoded sequence is successfully decoded.

[0116] According to example embodiments, DCI decompression may be implemented as follows:

[0117] Regarding the DCI decoding, as shown in FIG. 9, according to example embodiments, the DCI decompressor follows the sequential encoding structure from the transmitter side. The input features for neural network are the same as the DCI encoder. The UE locally has its previous DCI messages, which have been successfully decoded. Since the arithmetic coding behaves as a lossless compression, the control bit starting from index i = 1 is decoded first without any error until the last control bit is correctly decoded. To guarantee that the neural network returns the same estimate on probability distributions, according to example embodiments, the neural network estimator is shared by the BTS and UE once it has been well-trained. As another option, the neural network may be trained by both entities separately and in parallel on the basis of the same input. Therefore, when the BTS and UE share the same input features for the neural network, the DCI message can be decompressed without losses.

[0118] In other words, an ML trained NN estimator estimates, for a present DCI to be encoded, based on a number of foregoing DCIs (input features), a probability distribution (for each DCI bit a probability of being 1 (or 0)).

[0119] The probability distribution (for each DCI bit a probability of being 1 (or 0)) is basis for arithmetic coding of a present DCI to be encoded.

[0120] In addition, the probability distribution (for each DCI bit a probability of being 1 (or 0)) is basis for arithmetic decoding of present DCI to be encoded.

[0121] According to example embodiments, signaling may be implemented as follows: According to example embodiments, an agreement is negotiated between the BTS and the UE prior to the DCI message transmission. This is because not all the UEs might be capable of using a NN-based DCI decompression. Therefore, a handshake needs to be made between the BTS and the UE before going ahead with the proposed DCI compression scheme.

[0122] FIG. 11 (FIG. 11(A) and 11(B)) and FIG. 12 (FIG. 12(A) and 12(B)) show schematic diagrams of signaling sequences according to example embodiments, and in particular illustrate signaling sequences for NN-based DCI compression.

[0123] In particular, FIG. 11 (FIG. 11(A) and 11(B)) and FIG. 12 (FIG. 12(A) and 12(B)) show example RRC message sequences involved in this handshake.

[0124] There are two possibilities for establishing a handshake, reflected by FIGs. 11 and 12, respectively.

[0125] On the one hand, according to example embodiments, the handshake may be BTS-initiated, which is reflected by FIG. 11 (FIG. 11(A) and 11(B)).

[0126] Here, the BTS sends a request to the served UE to check whether it can accept compressed DCI messages. The UE either accepts or rejects the request. In the former scenario (FIG. 11(A)), the BTS subsequently sends a broadcast message with the DCI compression parameters. The compression parameters include (and are not limited to) the number of prior DCI messages M and the type of compression being done (e.g., with a NN or with a look-up table). Upon receiving an acknowledgement from the UE, the BTS compresses the DCI and transmits it to the UE. If the UE does not accept the original request (FIG. 11(B)), the BTS continues with the normal DCI transmission.

[0127] On the other hand, according to example embodiments, the handshake may be UE-initiated, which is reflected by FIG. 12 (FIG. 12(A) and 12(B)). In this case, the UE initiates the request. The BTS either accepts or rejects the request. In the former scenario (FIG. 12(A)), the BTS subsequently sends a broadcast message with the DCI compression parameters. The compression parameters include (and are not limited to) the number of prior DCI messages M and the type of compression being done (e.g., with a NN or with a look-up table). Upon receiving an acknowledgement from the UE, the BTS compresses the DCI and transmits it to the UE. If the BTS does not accept the original request (FIG. 12(B)), the BTS continues with the normal DCI transmission.

[0128] It is important to note that this handshake needs to be done only once with respect to a UE. If there are several UEs to transmit individual DCI messages to and many of them having already accepted the DCI compression request, according to example embodiments, the BTS will broadcast the DCI compression parameters.

[0129] An example use case reflecting reliability enhancement by DCI compression is discussed below:

[0130] The proof-of-concept results are presented hereinbelow to demonstrate the potential performance gain on decompressing a DCI message with the DCI compression method according to example embodiments. In the following simulation results, a DCI message is generated and encoded following the structure discussed in relation to FIG. 8.

[0131] According to example embodiments, NN structure may be implemented as follows:

[0132] The NN structure implemented in the example use case is a deep feedforward NN that has two hidden layers with 256 and 128 neurons. A rectified linear unit is used as the non-linear activation function and a binary cross-entropy loss function is used to compare the label (i-th control bit in the DCI message) to the prediction (estimated probability for the i-th control bit of being 0 or 1). The prediction from NN serves as the input for the arithmetic encoding algorithm. An even resource scheduler and a modulation and coding scheme (MCS) selector are implemented at the BTS to generate the control bits that are included in a DCI message. During the training phase, it is assumed that the data packets are modulated into orthogonal frequency division multiplexing (OFDM) symbols and transmitted through a clustered delay line (CDL) channel. The data packets for each UE are generated from a Poisson distribution. It is assumed that there are 12 resource blocks (RB) and 20 TTIs. At the UE side, channel estimation is performed to estimate the effective noise variance, and the UE reports sub-band channel quality indicators (CQI) to the BTS. The source DCI length is set to be 90, and the channel encoded DCI message has 128 bits. At the base station, based on the reported CQI, a bitmap of size 12 bits describing the frequency domain resource assignment with RB granularity is generated by the scheduler. Similarly, 5 control bits are generated from the MCS selector. The probability distribution of these 17 bits is estimated by a NN, which has two hidden layers with 256 and 128 neurons respectively. A rectified linear unit is used as a non-linear activation function for the hidden layers, and a sigmoid function is applied to the output layer to estimate the probability of being a 0 or 1 for the estimated bit. For simplicity, the other control bits are randomly generated from a Bernoulli distribution with a probability of 0.3 for being 0 or 1, i.e., bL~ Bern(p = 0.3) for i e {17, 18, ... ,89}, and the prior knowledge of the Bernoulli distribution is used as the input for the arithmetic encoding. The channel encoded DCI message is transmitted through an additive white Gaussian noise (AWGN) channel. If the DCI message is successfully decoded by the UE, it is assumed that the data packet will also be successfully decoded and removed from the buffer. The neural network model is learned to estimate the probability distribution for each control bit, and the source DCI message is encoded by the DCI compression method according to example embodiments. The list size for channel decoding is set to be L = 20 to exploit the zero-paddings that are attached to the encoded DCI.

[0133] FIG. 13 is a schematic diagram illustrating a distribution of lengths resulting from encoding processing according to example embodiments, and in particular illustrates a distribution of encoded DCI length (with original DCI length being 90).

[0134] FIG. 14 is a schematic diagram illustrating a coding gain resulting from encoding processing according to example embodiments, and in particular illustrates a frame error rate (FER) for decoding the DCI message.

[0135] FIG. 13 illustrates the distribution of encoded DCI length, and it can be observed that by using the DCI compression method according to example embodiments, the DCI message can be encoded into a shorter length compared to the original length of 90.

[0136] Correspondingly, with the list decoding method according to example embodiments, a 0.3 dB coding gain can be obtained at a block error rate (BLER): BLER = 10-2, compared to the traditional PDCCH decoding (FIG. 14).

[0137] The above-described procedures and functions may be implemented by respective functional elements, processors, or the like, as described below.

[0138] In the foregoing exemplary description of the network entity, only the units that are relevant for understanding the principles of the disclosure have been described using functional blocks. The network entity may comprise further units that are necessary for its respective operation. However, a description of these units is omitted in this specification. The arrangement of the functional blocks of the devices is not construed to limit the disclosure, and the functions may be performed by one block or further split into sub-blocks.

[0139] When in the foregoing description it is stated that the apparatus, i.e. network node or entity (or some other means) is configured to perform some function, this is to be construed to be equivalent to a description stating that a (i.e. at least one) processor or corresponding circuitry, potentially in cooperation with computer program code stored in the memory of the respective apparatus, is configured to cause the apparatus to perform at least the thus mentioned function. Also, such function is to be construed to be equivalently implementable by specifically configured circuitry or means for performing the respective function (i.e. the expression "unit configured to" is construed to be equivalent to an expression such as "means for").

[0140] In FIG. 15, an alternative illustration of apparatuses according to example embodiments is depicted. As indicated in FIG. 15, according to example embodiments, the apparatus (network node) 10' (corresponding to the network node 10) comprises a processor 151, a memory 152 and an interface 153, which are connected by a bus 154 or the like. Further, according to example embodiments, the apparatus (terminal) 30' (corresponding to the terminal 30) comprises a processor 155, a memory 156 and an interface 157, which are connected by a bus 158 or the like, and the apparatuses may be connected via link 159, respectively.

[0141] The processor 151 / 155 and / or the interface 153 / 157 may also include a modem or the like to facilitate communication over a (hardwire or wireless) link, respectively. The interface 153 / 157 may include a suitable transceiver coupled to one or more antennas or communication means for (hardwire or wireless) communications with the linked or connected device(s), respectively. The interface 153 / 157 is generally configured to communicate with at least one other apparatus, i.e. the interface thereof.

[0142] The memory 152 / 156 may store respective programs assumed to include program instructions or computer program code that, when executed by the respective processor, enables the respective electronic device or apparatus to operate in accordance with the example embodiments.

[0143] In general terms, the respective devices / apparatuses (and / or parts thereof) may represent means for performing respective operations and / or exhibiting respective functionalities, and / or the respective devices (and / or parts thereof) may have functions for performing respective operations and / or exhibiting respective functionalities. When in the subsequent description it is stated that the processor (or some other means) is configured to perform some function, this is to be construed to be equivalent to a description stating that at least one processor, potentially in cooperation with computer program code stored in the memory of the respective apparatus, is configured to cause the apparatus to perform at least the thus mentioned function. Also, such function is to be construed to be equivalently implementable by specifically configured means for performing the respective function (i.e. the expression "processor configured to [cause the apparatus to] perform xxx-ing" is construed to be equivalent to an expression such as "means for xxx-ing").

[0144] According to example embodiments, an apparatus representing the network node 10 comprises at least one processor 151, at least one memory 152 including computer program code, and at least one interface 153 configured for communication with at least another apparatus. The processor (i.e. the at least one processor 151, with the at least one memory 152 and the computer program code) is configured to perform estimating, for a present sequence of bits, a probability distribution, wherein said probability distribution being indicative of, for each bit of said present sequence of bits, a respective probability of said bit having a first predetermined value (thus the apparatus comprising corresponding means for estimating), and to perform encoding, as an encoded present sequence of bits, said present sequence of bits utilizing arithmetic encoding with said probability distribution and said present sequence of bits as inputs (thus the apparatus comprising corresponding means for encoding).

[0145] According to example embodiments, an apparatus representing the network node 30 comprises at least one processor 155, at least one memory 156 including computer program code, and at least one interface 157 configured for communication with at least another apparatus. The processor (i.e. the at least one processor 155, with the at least one memory 156 and the computer program code) is configured to perform estimating, for a present sequence of bits, a probability distribution, wherein said probability distribution being indicative of, for each bit of said present sequence of bits, a respective probability of said bit having a first predetermined value (thus the apparatus comprising corresponding means for estimating), to perform receiving an encoded present sequence of bits (thus the apparatus comprising corresponding means for receiving), and to perform decoding, as said present sequence of bits, said encoded present sequence of bits utilizing arithmetic decoding with said probability distribution and said encoded present sequence of bits as inputs (thus the apparatus comprising corresponding means for decoding).

[0146] For further details regarding the operability / functionality of the individual apparatuses, reference is made to the above description in connection with any one of FIGs. 1 to 14, respectively.

[0147] For the purpose of the present disclosure as described herein above, it should be noted that

[0148] - method steps likely to be implemented as software code portions and being run using a processor at a network server or network entity (as examples of devices, apparatuses and / or modules thereof, or as examples of entities including apparatuses and / or modules therefore), are software code independent and can be specified using any known or future developed programming language as long as the functionality defined by the method steps is preserved;

[0149] - generally, any method step is suitable to be implemented as software or by hardware without changing the idea of the embodiments and its modification in terms of the functionality implemented;

[0150] - method steps and / or devices, units or means likely to be implemented as hardware components at the above-defined apparatuses, or any module(s) thereof, (e.g., devices carrying out the functions of the apparatuses according to the embodiments as described above) are hardware independent and can be implemented using any known or future developed hardware technology or any hybrids of these, such as MOS (Metal Oxide Semiconductor), CMOS (Complementary MOS), BiMOS (Bipolar MOS), BiCMOS (Bipolar CMOS), ECL (Emitter Coupled Logic), TTL (Transistor-Transistor Logic), etc., using for example ASIC (Application Specific IC (Integrated Circuit)) components, FPGA (Field-programmable Gate Arrays) components, CPLD (Complex Programmable Logic Device) components or DSP (Digital Signal Processor) components;

[0151] - devices, units or means (e.g. the above-defined network entity or network register, or any one of their respective units / means) can be implemented as individual devices, units or means, but this does not exclude that they are implemented in a distributed fashion throughout the system, as long as the functionality of the device, unit or means is preserved;

[0152] - an apparatus like the user equipment and the network entity / network register may be represented by a semiconductor chip, a chipset, or a (hardware) module comprising such chip or chipset; this, however, does not exclude the possibility that a functionality of an apparatus or module, instead of being hardware implemented, be implemented as software in a (software) module such as a computer program or a computer program product comprising executable software code portions for execution / being run on a processor;

[0153] - a device may be regarded as an apparatus or as an assembly of more than one apparatus, whether functionally in cooperation with each other or functionally independently of each other but in a same device housing, for example.

[0154] In general, it is to be noted that respective functional blocks or elements according to above-described aspects can be implemented by any known means, either in hardware and / or software, respectively, if it is only adapted to perform the described functions of the respective parts. The mentioned method steps can be realized in individual functional blocks or by individual devices, or one or more of the method steps can be realized in a single functional block or by a single device. Generally, any method step is suitable to be implemented as software or by hardware without changing the idea of the present disclosure. Devices and means can be implemented as individual devices, but this does not exclude that they are implemented in a distributed fashion throughout the system, as long as the functionality of the device is preserved. Such and similar principles are to be considered as known to a skilled person.

[0155] Software in the sense of the present description comprises software code as such comprising code means or portions or a computer program or a computer program product for performing the respective functions, as well as software (or a computer program or a computer program product) embodied on a tangible medium such as a computer-readable (storage) medium having stored thereon a respective data structure or code means / portions or embodied in a signal or in a chip, potentially during processing thereof.

[0156] The present disclosure also covers any conceivable combination of method steps and operations described above, and any conceivable combination of nodes, apparatuses, modules or elements described above, as long as the above-described concepts of methodology and structural arrangement are applicable.

[0157] In view of the above, there are provided measures for efficient radio resources utilization in control information transmissions. Such measures exemplarily comprise estimating, for a present sequence of bits, a probability distribution, wherein said probability distribution being indicative of, for each bit of said present sequence of bits, a respective probability of said bit having a first predetermined value, and encoding, as an encoded present sequence of bits, said present sequence of bits utilizing arithmetic encoding with said probability distribution and said present sequence of bits as inputs.

[0158] Even though the disclosure is described above with reference to the examples according to the accompanying drawings, it is to be understood that the disclosure is not restricted thereto. Rather, it is apparent to those skilled in the art that the present disclosure can be modified in many ways without departing from the scope of the inventive idea as disclosed herein.

[0159] List of acronyms and abbreviations

[0160] 3GPP 3rd Generation Partnership Project

[0161] 5G 5th Generation

[0162] 6G 6th Generation

[0163] AL aggregation level

[0164] AWGN additive white Gaussian noise

[0165] BLER block error rate

[0166] BTS base transceiver station

[0167] CDL clustered delay line

[0168] CLPC closed-loop power control

[0169] CP control plane

[0170] CQI channel quality indicator

[0171] CRC cyclic redundancy check

[0172] DCI downlink control information

[0173] DL downlink

[0174] FER frame error rate

[0175] LA link adaptation

[0176] LLR log-likelihood ratio

[0177] MCS modulation and coding scheme

[0178] ML machine learning

[0179] NN neural network

[0180] NR New Radio

[0181] OFDM orthogonal frequency division multiplexing

[0182] PDCCH physical downlink control channel

[0183] RAN radio access network

[0184] RB resource block

[0185] RCU remote control unit

[0186] RRH remote radio head TTI transmission time interval

[0187] UE user equipment

[0188] UL uplink

[0189] UP user plane

Claims

Claims1. A method comprising estimating, for a present sequence of bits, a probability distribution, wherein said probability distribution being indicative of, for each bit of said present sequence of bits, a respective probability of said bit having a first predetermined value, and encoding, as an encoded present sequence of bits, said present sequence of bits utilizing arithmetic encoding with said probability distribution and said present sequence of bits as inputs.

2. The method according to claim 1, further comprising transmitting said encoded present sequence of bits.

3. The method according to claim 1 or 2, wherein in relation to said estimating, the method further comprises utilizing a neural network estimator model fed with a predetermined number of previous sequences of bits previous to said present sequence of bits.

4. The method according to claim 3, further comprising machine-learning said neural network estimator model.

5. The method according to claim 4, further comprising transmitting said neural network estimator model.

6. The method according to any of claims 3 to 5, wherein said neural network estimator model represents temporal and spatial correlations among said previous sequences of bits.

7. The method according to any of claims 1 to 6, wherein in relation to said encoding, the method further comprisesadding zero-paddings to said encoded present sequence of bits.

8. The method according to any of claims 1 to 7, further comprising transmitting a bit sequence compression request, receiving a bit sequence compression response, and if said bit sequence compression response is indicative of acknowledgement transmitting information on a bit sequence compression being based on neural network estimation and a count of previous sequences of bits to be considered for said neural network estimation, and if said bit sequence compression response is indicative of nonacknowledgement inhibiting encoding of said present sequence of bits utilizing arithmetic encoding.

9. The method according to any of claims 1 to 7, further comprising receiving a bit sequence compression request, transmitting a bit sequence compression response, and if said bit sequence compression response is indicative of acknowledgement transmitting information on a bit sequence compression being based on neural network estimation and a count of previous sequences of bits to be considered for said neural network estimation, and if said bit sequence compression response is indicative of nonacknowledgement inhibiting encoding of said present sequence of bits utilizing arithmetic encoding.

10. A method comprising estimating, for a present sequence of bits, a probability distribution, wherein said probability distribution being indicative of, for each bit of said present sequence of bits, a respective probability of said bit having a first predetermined value,receiving an encoded present sequence of bits, and decoding, as said present sequence of bits, said encoded present sequence of bits utilizing arithmetic decoding with said probability distribution and said encoded present sequence of bits as inputs.

11. The method according to claim 10, wherein in relation to said estimating, the method further comprises utilizing a neural network estimator model fed with a predetermined number of previous sequences of bits previous to said present sequence of bits.

12. The method according to claim 11, further comprising machine-learning said neural network estimator model.

13. The method according to claim 11, further comprising receiving said neural network estimator model.

14. The method according to any of claims 11 to 13, wherein said neural network estimator model represents temporal and spatial correlations among said previous sequences of bits.

15. The method according to any of claims 10 to 14, wherein in relation to said decoding, the method further comprises performing, as a preparation to cope with zero-paddings added to said encoded present sequence of bits, list-decoding on said encoded present sequence of bits including a cyclic redundancy check, and passing a result of said list-decoding to said arithmetic decoding.

16. The method according to any of claims 10 to 15, further comprising receiving a bit sequence compression request, transmitting a bit sequence compression response, and if said bit sequence compression response is indicative of acknowledgementreceiving information on a bit sequence compression being based on neural network estimation and a count of previous sequences of bits to be considered for said neural network estimation, and considering said count of previous sequences of bits for determining a predetermined number of previous sequences of bits previous to said present sequence of bits to be fed to a neural network estimator model, and if said bit sequence compression response is indicative of nonacknowledgement inhibiting decoding of said encoded present sequence of bits utilizing arithmetic encoding.

17. The method according to any of claims 10 to 15, further comprising transmitting a bit sequence compression request, receiving a bit sequence compression response, and if said bit sequence compression response is indicative of acknowledgement receiving information on a bit sequence compression being based on neural network estimation and a count of previous sequences of bits to be considered for said neural network estimation, and considering said count of previous sequences of bits for determining a predetermined number of previous sequences of bits previous to said present sequence of bits to be fed to a neural network estimator model, and if said bit sequence compression response is indicative of nonacknowledgement inhibiting decoding of said encoded present sequence of bits utilizing arithmetic encoding.

18. The method according to any of claims 1 to 17, wherein said present sequence of bits represents downlink control information.

19. An apparatus comprisingestimating circuitry configured to estimate, for a present sequence of bits, a probability distribution, wherein said probability distribution being indicative of, for each bit of said present sequence of bits, a respective probability of said bit having a first predetermined value, and encoding circuitry configured to encode, as an encoded present sequence of bits, said present sequence of bits utilizing arithmetic encoding with said probability distribution and said present sequence of bits as inputs.

20. The apparatus according to claim 19, further comprising transmitting circuitry configured to transmit said encoded present sequence of bits.

21. The apparatus according to claim 19 or 20, further comprising utilizing circuitry configured to utilize a neural network estimator model fed with a predetermined number of previous sequences of bits previous to said present sequence of bits.

22. The apparatus according to claim 21, further comprising machine-learning circuitry configured to machine-learn said neural network estimator model.

23. The apparatus according to claim 22, further comprising transmitting circuitry configured to transmit said neural network estimator model.

24. The apparatus according to any of claims 21 to 23, wherein said neural network estimator model represents temporal and spatial correlations among said previous sequences of bits.

25. The apparatus according to any of claims 19 to 24, further comprising adding circuitry configured to add zero-paddings to said encoded present sequence of bits.

26. The apparatus according to any of claims 19 to 25, further comprising transmitting circuitry configured to transmit a bit sequence compression request, receiving circuitry configured to receive a bit sequence compression response, transmitting circuitry configured to, if said bit sequence compression response is indicative of acknowledgement, transmit information on a bit sequence compression being based on neural network estimation and a count of previous sequences of bits to be considered for said neural network estimation, and inhibiting circuitry configured to, if said bit sequence compression response is indicative of non-acknowledgement, inhibit encoding of said present sequence of bits utilizing arithmetic encoding.

27. The apparatus according to any of claims 19 to 25, further comprising receiving circuitry configured to receive a bit sequence compression request, transmitting circuitry configured to transmit a bit sequence compression response, transmitting circuitry configured to, if said bit sequence compression response is indicative of acknowledgement, transmit information on a bit sequence compression being based on neural network estimation and a count of previous sequences of bits to be considered for said neural network estimation, and inhibiting circuitry configured to, if said bit sequence compression response is indicative of non-acknowledgement, inhibit encoding of said present sequence of bits utilizing arithmetic encoding.

28. An apparatus comprising estimating circuitry configured to estimate, for a present sequence of bits, a probability distribution, wherein said probability distribution being indicative of, for each bit of said present sequence of bits, a respective probability of said bit having a first predetermined value,receiving circuitry configured to receive an encoded present sequence of bits, and decoding circuitry configured to decode, as said present sequence of bits, said encoded present sequence of bits utilizing arithmetic decoding with said probability distribution and said encoded present sequence of bits as inputs.

29. The apparatus according to claim 28, further comprising utilizing circuitry configured to utilize a neural network estimator model fed with a predetermined number of previous sequences of bits previous to said present sequence of bits.

30. The apparatus according to claim 29, further comprising machine-learning circuitry configured to machine-learn said neural network estimator model.

31. The apparatus according to claim 29, further comprising receiving circuitry configured to receive said neural network estimator model.

32. The apparatus according to any of claims 29 to 31, wherein said neural network estimator model represents temporal and spatial correlations among said previous sequences of bits.

33. The apparatus according to any of claims 28 to 32, further comprising performing circuitry configured to perform, as a preparation to cope with zero-paddings added to said encoded present sequence of bits, listdecoding on said encoded present sequence of bits including a cyclic redundancy check, and passing circuitry configured to pass a result of said list-decoding to said arithmetic decoding.

34. The apparatus according to any of claims 28 to 33, further comprisingreceiving circuitry configured to receive a bit sequence compression request, transmitting circuitry configured to transmit a bit sequence compression response, receiving circuitry configured to, if said bit sequence compression response is indicative of acknowledgement, receive information on a bit sequence compression being based on neural network estimation and a count of previous sequences of bits to be considered for said neural network estimation, considering circuitry configured to, if said bit sequence compression response is indicative of acknowledgement, consider said count of previous sequences of bits for determining a predetermined number of previous sequences of bits previous to said present sequence of bits to be fed to a neural network estimator model, and inhibiting circuitry configured to, if said bit sequence compression response is indicative of non-acknowledgement, inhibit decoding of said encoded present sequence of bits utilizing arithmetic encoding.

35. The apparatus according to any of claims 28 to 33, further comprising transmitting circuitry configured to transmit a bit sequence compression request, receiving circuitry configured to receive a bit sequence compression response, receiving circuitry configured to, if said bit sequence compression response is indicative of acknowledgement, receive information on a bit sequence compression being based on neural network estimation and a count of previous sequences of bits to be considered for said neural network estimation, considering circuitry configured to, if said bit sequence compression response is indicative of acknowledgement, consider said count of previous sequences of bits for determining a predetermined number of previous sequences of bits previous to said present sequence of bits to be fed to a neural network estimator model, andinhibiting circuitry configured to, if said bit sequence compression response is indicative of non-acknowledgement, inhibit decoding of said encoded present sequence of bits utilizing arithmetic encoding.

36. The apparatus according to any of claims 19 to 35, wherein said present sequence of bits represents downlink control information.

37. An apparatus comprising at least one processor, and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to perform: estimating, for a present sequence of bits, a probability distribution, wherein said probability distribution being indicative of, for each bit of said present sequence of bits, a respective probability of said bit having a first predetermined value, and encoding, as an encoded present sequence of bits, said present sequence of bits utilizing arithmetic encoding with said probability distribution and said present sequence of bits as inputs.

38. The apparatus according to claim 37, wherein the instructions, when executed by the at least one processor, cause the apparatus at least to perform: transmitting said encoded present sequence of bits.

39. The apparatus according to claim 37 or 38, wherein in relation to said estimating, the instructions, when executed by the at least one processor, cause the apparatus at least to perform: utilizing a neural network estimator model fed with a predetermined number of previous sequences of bits previous to said present sequence of bits.

40. The apparatus according to claim 39, whereinthe instructions, when executed by the at least one processor, cause the apparatus at least to perform: machine-learning said neural network estimator model.

41. The apparatus according to claim 40, wherein the instructions, when executed by the at least one processor, cause the apparatus at least to perform: transmitting said neural network estimator model.

42. The apparatus according to any of claims 39 to 41, wherein said neural network estimator model represents temporal and spatial correlations among said previous sequences of bits.

43. The apparatus according to any of claims 37 to 42, wherein in relation to said encoding, the instructions, when executed by the at least one processor, cause the apparatus at least to perform : adding zero-paddings to said encoded present sequence of bits.

44. The apparatus according to any of claims 37 to 43, wherein the instructions, when executed by the at least one processor, cause the apparatus at least to perform: transmitting a bit sequence compression request, receiving a bit sequence compression response, and if said bit sequence compression response is indicative of acknowledgement transmitting information on a bit sequence compression being based on neural network estimation and a count of previous sequences of bits to be considered for said neural network estimation, and if said bit sequence compression response is indicative of nonacknowledgement inhibiting encoding of said present sequence of bits utilizing arithmetic encoding.

45. The apparatus according to any of claims 37 to 43, wherein the instructions, when executed by the at least one processor, cause the apparatus at least to perform: receiving a bit sequence compression request, transmitting a bit sequence compression response, and if said bit sequence compression response is indicative of acknowledgement transmitting information on a bit sequence compression being based on neural network estimation and a count of previous sequences of bits to be considered for said neural network estimation, and if said bit sequence compression response is indicative of nonacknowledgement inhibiting encoding of said present sequence of bits utilizing arithmetic encoding.

46. An apparatus comprising at least one processor, and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to perform: estimating, for a present sequence of bits, a probability distribution, wherein said probability distribution being indicative of, for each bit of said present sequence of bits, a respective probability of said bit having a first predetermined value, receiving an encoded present sequence of bits, and decoding, as said present sequence of bits, said encoded present sequence of bits utilizing arithmetic decoding with said probability distribution and said encoded present sequence of bits as inputs.

47. The apparatus according to claim 46, wherein in relation to said estimating, the instructions, when executed by the at least one processor, cause the apparatus at least to perform:utilizing a neural network estimator model fed with a predetermined number of previous sequences of bits previous to said present sequence of bits.

48. The apparatus according to claim 47, wherein the instructions, when executed by the at least one processor, cause the apparatus at least to perform: machine-learning said neural network estimator model.

49. The apparatus according to claim 47, wherein the instructions, when executed by the at least one processor, cause the apparatus at least to perform: receiving said neural network estimator model.

50. The apparatus according to any of claims 47 to 49, wherein said neural network estimator model represents temporal and spatial correlations among said previous sequences of bits.

51. The apparatus according to any of claims 46 to 50, wherein in relation to said decoding, the instructions, when executed by the at least one processor, cause the apparatus at least to perform : performing, as a preparation to cope with zero-paddings added to said encoded present sequence of bits, list-decoding on said encoded present sequence of bits including a cyclic redundancy check, and passing a result of said list-decoding to said arithmetic decoding.

52. The apparatus according to any of claims 46 to 51, wherein the instructions, when executed by the at least one processor, cause the apparatus at least to perform: receiving a bit sequence compression request, transmitting a bit sequence compression response, and if said bit sequence compression response is indicative of acknowledgementreceiving information on a bit sequence compression being based on neural network estimation and a count of previous sequences of bits to be considered for said neural network estimation, and considering said count of previous sequences of bits for determining a predetermined number of previous sequences of bits previous to said present sequence of bits to be fed to a neural network estimator model, and if said bit sequence compression response is indicative of nonacknowledgement inhibiting decoding of said encoded present sequence of bits utilizing arithmetic encoding.

53. The apparatus according to any of claims 46 to 51, wherein the instructions, when executed by the at least one processor, cause the apparatus at least to perform: transmitting a bit sequence compression request, receiving a bit sequence compression response, and if said bit sequence compression response is indicative of acknowledgement receiving information on a bit sequence compression being based on neural network estimation and a count of previous sequences of bits to be considered for said neural network estimation, and considering said count of previous sequences of bits for determining a predetermined number of previous sequences of bits previous to said present sequence of bits to be fed to a neural network estimator model, and if said bit sequence compression response is indicative of nonacknowledgement inhibiting decoding of said encoded present sequence of bits utilizing arithmetic encoding.

54. The apparatus according to any of claims 37 to 53, wherein said present sequence of bits represents downlink control information.

55. A computer program product comprising computer-executable computer program code which, when the program is run on a computer, is configured to cause the computer to carry out the method according to any one of claims 1 to 9 or 10 to 18.

56. The computer program product according to claim 55, wherein the computer program product comprises a computer-readable medium on which the computer-executable computer program code is stored, and / or wherein the program is directly loadable into an internal memory of the computer or a processor thereof.

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