Frame pulse synchronization in a packet optical transport platform (p-OTP)

The method ensures reliable clock synchronization and smooth switchover in P-OTP systems by aligning internal clocks with primary and secondary clock inputs, addressing the challenge of out-of-sync clocks and enhancing system reliability and robustness.

WO2025074397A1 Publication Date: 2025-04-10CENT FOR DEV OF TELEMATICS
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Patent Information

Application Number
PCT/IN2024/051955
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2023-10-05
Filing Date
2024-10-04
Publication Date
2025-04-10

AI Technical Summary

Technical Problem

In Packet Optical Transport Platforms (P-OTPs), primary and secondary clock inputs often become out of synchronization, leading to potential disruptions during protection switch-over events, which can compromise the reliability and robustness of the system.

Method used

A method is implemented where line cards periodically sample primary and secondary clock inputs using a high-frequency sampling clock. When the primary clock is unavailable, the method determines the phase difference between the clocks, generates an internal clock aligned with the primary clock's frequency and phase, and shifts it until it aligns with the secondary clock within a predetermined limit, allowing for seamless switchover.

Benefits of technology

This method ensures reliable clock synchronization and smooth switchover in P-OTP systems, enabling real-time monitoring, immediate response to failures, and uninterrupted operation during clock transitions.

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Abstract

The present disclosure provides a method for achieving synchronization in a Packet- Optical Transport Platform when primary and secondary clock inputs are out of sync. The method comprises periodically sampling (202) the clock inputs using a high-frequency sampling clock. When the primary clock input is unavailable, the method comprises determining (204) the phase difference (β) between the clock inputs based on the previously known phase of the primary clock input, and generating (206) an internal clock with the same frequency and phase as the primary clock input using the high-frequency clock input. Further, the method comprises shifting (208) the internally generated clock with each clock cycle until it aligns with a phase that ensures the phase difference between the internally generated clock and the secondary clock input falls within a predetermined limit, and initiating (210) a switch- over to the secondary clock input, thereby ensuring uninterrupted operation during clock transitions.
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