Apparatuses and methods for scalable 1-pass error correction code operations

Abstract

Apparatuses, systems, and methods for scalable 1-pass error correction code operations. A memory device includes an error correction code (ECC) circuit which generates a number of parity bits based on a plurality of data bits during a write operation. The number of parity bits may be selected based on a setting in a mode register. The data and parity are written to the memory array as part of a single access pass. The data may be written to a selected portion of the data column planes, while the parity is written to one or more column planes of the extra column plane or a non-selected portion of the data column planes.

Description

APPARATUSES AND METHODS FOR SCALABLE 1-PASS ERROR CORRECTION CODE OPERATIONSCROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit under 35 U.S.C. § 119 of the earlier filing date of U.S. Provisional Application Serial No. 63 / 587,627 filed October 3, 2023 the entire contents of winch is hereby incorporated by reference in its entirety for any purpose.

[0002] This disclosure relates generally to semiconductor devices, and more specifically to semiconductor memory devices. In particular, the disclosure relates to volatile memory, such as dynamic random access memory (DRAM). Information may be stared on individual memory cells of the memory as a physical signal (e.g., a charge on a capacitive element). During an access operation, an access command may be received along with address information which specifies which memory cells should be accessed.

[0003] There is a growing interest in enabling the memory to correct the information stored therein. Memories may include an error correction code (ECU) circuit which is used to determine if there are errors in the accessed information (and may correct one or more of the errors). There may be a need to increase the flexibility of foe ECC circuitBRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a block diagram of a memory' system according to some embodiments of the present disclosure.

[0005] Figure 2 is a block diagram of a semiconductor device according an embodiment of the disclosure.

[0006] Figure 3 is a block diagram of a memory device according to some embodiments of the present disclosure.

[0007] Figure 4 is a block diaigram of a memory array accoixiing to some examples of foe present disclosure,

[0008] figure 5 is a flow chart of a method of writing data and parity to a memory array according to some examples of the present disclosure.DETAILED DESCRIPTION

[0009] The following description of certain embodiments is merely exemplary in nature and is in no way intended to limit foe scope of foe disclosure or its applications or uses, hi foe following detailed description of embodiments of the present systems and methods, reference is made to the accompanying drawings winch form a part hereof, and which are shown by way of illustration specific embodiments in winch the described systems and methods may be practiced. These embodiments are described in sufficient detail to enable those skilled in foe art to practice presently disclosed systems and methods, and it is to be understood that other embodiments may be utilized and that structural and logical changes may be made without departing from foe spirit and scope of foe disclosure. Moreover, for foe purpose of darity, detailed descriptions of certain features will not be discussed when they would be apparent to those with skill in the art so as not to obscure the description of embodiments of foe disclosure. The following detailed description is therefore not to be taken in a limiting sense, and the scope of the disclosure is defined only by the appended claims.

[0010] Memory arrays may generally include a number of memory cells arranged at the intersection of Word lines (rows) and bit lines / digit lines (columns). The columns may be grouped together into column planes, and a column select (CS) signal may be used to select a set of columns within each of foe active column planes to provide data. When an access command such as a read or a write is received, one or more column planes may be activated and the a data codeword may be read fam or written to tire memory cells at the intersection of an active word line specified by a row address, and the bit lines in the active column planes specified by the CS signal (e,g, , which is based on a column address). Some memory’s may operate in a mode where fewer than all of tire column planes are activated in a given access operation (e.g., and the data codeword is smaller). Feu example, a column plane select hit of tire column address may specify a first portion (e.g., a first half) of a second portion (e g., a second half ) of the column planes.

[0011] Memory devices include error correction circuits, such as error correction code (ECC) circuits, which are used to determine if there are errors in the data. During a write operation, the ECC circuit receives the data codeword and generates parity bits based on that data codeword. During a read operation, the ECC circuit receives the data codeword and foe parity stored in the array and determines errors based on the data codeword and parity. The parity may be stored in an extra column plane set aside for parity storage, which maybe fired along with the other data column planes.

[0012] In to example implementation, the ECC circuit may implement single error correction(SEC) where up to a single bit Of error may be located and corrected, or single error correction, double error detection (SECDED) where up to a single error may be located, but up to two bits of error may be detected (without locating them to correct them). Hie amount of error bite which may be detected / corrected may depend, in part, on the number of data bits and tire number of parity bite. Increasing die number of parity bite may generally increase ECC Capability, however this may come at the cost of more space since the parity column, plane may already fit a number of bits matched to the number of data codewords stored in the array. While space in the data column planes may be set aside for additional parity, in memory modes where all of the column pltoes are activated, it may be difficult to increase the number of parity bits without using multiple access passes to retrieve additional parity (e.g., since all of tire column planes are already being used for normal data and parity access). There may be a need to increase the flexibility of error correction code operations to allow for ECC implementations to be chosen without increasing the mnnber of access passes;

[0013] The present disclosure is drawn to apparatuses, systems, and methods fry scalable 1- pass error correction code operations. hi memory modes where less than all of the column planes are used for to access^ the data codeword may be stored in the selected portion of the data column planes, while space for the parity may be set aside in one or more of the extra column plane and the non-selected data column planes. This may allow for an increased mnnber of parity trite to be Used for each codeword, which may in turn allow for increased ECC capability. This may allow for the data and parity to be accessed in a single access pass since even with tire increased number of parity trite the total amount of accessed information is less than the maximum number that can be accessed in a single pass. This may also increase tire flexibility of ECC operations, since mode register settings may increase the number of parity bits per codeword through remapping of where in the array the extra parity is stored and which and how many column planes are accessed.

[0014] hr some embodiments, parity bits for a single data codeword may be stored in multiple ones of the non-selected column planes (which may inchide the extra column plane). For example, if each column select signal selects 8 bit lines in a column plane, but more than 8 bite of parity are desired, then the parity bits may be stored across multiple column planes.

[0015] In an example implementation, the memory array may include 16 column planes and an extra column plane. Each codeword includes 64 Sets of bit fines (each associated with a respective value of the column select signal) arid eadi set includes 8 bit lines activated by thatvalue of the CS signal. Each data codeword includes 64 bits of data, and the ECC circuit is configured to generate 8 bite of parity for each data codeword. Accordingly, there may be mere total parity bits than tian fit in the extra column plane. To make room for this, Spice may be reserved in die data column planes such that for each codeword, die data is written in a selected half (e.g., 8) of the data column planes and die parity is either in a selected half of the sets of die bit lines in the extra column plane or in a near-selected data column plane.

[0016] A single access or single access pass mayrefer to au operation where the data and parity are retrieved together at approximately the same time. For example, the column decoder may provide column select signals to die column planes where the data and parity are stored simultaneously, and the data and parity may get accessed all at mice. This may be useful because each access operation may invoke a delay time before the next access pass (e.g., CCD). By retrieving infixmation as part of a single pass, this delay time is not invoked between accessing die data and die parity, which may allow fix decreased latency,

[0017] Figure 1 is a block diagram of a memory system according to some embodiments of the present disclosure. The memory system 100 includes a:memory module 102 and a controller 150 which operates die memory module 102. The module inchides a number of memory devices 104 and 110. The memory devices 104 may be used to store data and may generally be referred to as data memory devices 104, while the memory device 110 is used to correct errors in data read from die data memory devices 104. The memory device 110 may be referred to as an error correction memory device 110. A module logic 112 receives commands and addresses over a command / address CZA bus from the controller 150 through a C / A terminal 114 and distributes those commands and addresses to the memory devices 104 and 110 over internal command and address buses (not shown). Data is communicated between the controller 150 and the module 102 along data buses which couple to Ada terminals (DQ) terminals 124 of the module 102. The data terminals 124- are organized into pseudochannels 122 and channels 120. Each channel is a set of data terminals 124 associated with a memory device 104.

[0018] As an example, the present disclosure may generally be described with respect to a9x2p2 memory module 102. bi tire 9x2p2 architecture, there are nine total memory devices 104 and 110. Eight data memory devices 104(0) to 104(7) and one error correction memory device 110. Each channel 120(0) to 120(7) includes one or more pseudo-channels 122, which may be operated independently of each other. In this embodiment, each channel 120 includes two pseudo-channels 122, each of which includes two data terminals 124. Since die memorydevices and channels may generally be similar to each other, only a single device 104(0) and its associate channel 120(0) are described in detail herein. In order to simplify the layout of the figure* ah arrangement of two rows of four devices 104 each is shown, and their associated channels 120 are drown as stacked boxes. However the representation of Figure 1 does not necessarily represent the layout of a physical device. For example, a single row of 8 devices 104 may be used. Similarly, various buses and Signal lines have been simplified down to a single line far clarity on the drawing, however, multiple physical signal lines may be represented by a single line in the drawing. Other module architectures may be used in other example embodiments.

[0019] During an example write operation, the controller 150 provides a write command and addresses (e.g, row, column, and / or bank addresses as explained in more detail herein) over the C / A terminal 114 to the module 102. The module logic 112 distributes the command and address to the data memory devices 104(0) to 1Q4(7). The controller 150 also provides data to be written along the various DQ channels 120(0) to 120(7). Since the pseudochannels 122 may be operated independently, we will consider a single pseudo-channel 122 and its two DQ terminals 124. Each data terminal receives a serial burst Of bite, which together represent a codeword of date. For example, each terminal receives 32 data bits in series, for a total of 64 data bits. Each device 104 includes an ECC circuit, which generates parity bits based on the received 64 bite of date and stores the date and tiro parity in the array;

[0020] During an example read operation, tire controller 150 provides a read command and addresses along the C / A terminal 114. The module logic 112 distributes these to the memory devices 104 to 110 and date is read out from the locations specified by tire addresses. Aspart of the read operation, each memory device 104 may perform error correction based on tire data and parity which is read out from the array. The corrected data is provided off the device to the controller. The parity may generally not be read out to the controller 150. In some embodiments, if die device’s error correction detects a mistake then tire device 104 may provide a signal to the controller 150 indicating a detected error.

[0021] The read and write operations may use a single-access pass to store both the data and parity. Each memory device maybe capable of accessing upto l 36 bite ip a single access pass (e.g., generally 128 data bits and 8 parity bits). In the 9x2p2 architecture. 64 date bite phis a specified number of parity bits are used. Accordingly* the data plus parity may all be accessed as a single access pass. For example, as explained in more detail herein, the memory array may be split into two portions, each of which is associated with a value of a column plane selectbit in the column address. Data may be stored in a selected one of the portions, while the parity may be stored in an extra column plane or in the non-selected portion.

[0022] During an exanjple read operation, the enorcorrectionmemorydevice llOmay belised to identify and correct errors in the data. The error correction memory device 110 may support correction of the data and metadata along one DQ terminal (e.g., the 34 or 36 bits provided along one of the terminals 124 in a pseudo-channel). The controller 150 may use information stored on the error correction memory device 110 to enable correction of the information after (he information is received by the controller 150 during a read operation. For example, the error correction memory' device 110 may store repair information (e g., parity bits) which are associated with the data and metadata read oat across all the data devices 104(0) to 104(7), and that parity may be used by a repair circuit (not shown) of the controller 150 to enable correction in the data and metadata of up to one of the DQ terminals. For example, if the data and metadata being provided along a first DQ terminal in a first pseudo-channel associated with memory 104(0) is corrupted, then the erra correction device 11.0 enables the repair of that data and metadata. However, if the errors exist in bits across both DQ terminals in the pseudo^ channel then correction may not be possible.

[0023] Figure 2 is a block diagram of a semiconductor device according an embodiment of tire disclosure; The semiconductor device 200 may be a semicanductor memory device, such as a DRAM device integrated on a single semiconductor chip. In some embodiments of the present disclosure, the memory device 100 may be a standalone memory device. In some embodiments, the memory device 200 may be packaged together with other memory devices onto a module. For example, tire device 200 may implement one of the devices 104 of flie module 102 of Figure 1.

[0024] The semiconductor device 200 includes a memory array 218, The memory array 218 is shown as including a plurality of memory banks, hi the embodiment of Figure 2, the memory array 218 is shown as including eight memory banks BANK0-BANK7. More or fewer banks may be included in the memory array 218 of other embodiments.

[0025] Each memory bank includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL. The selection of the word line WL is performed by a row decoder 108 and the selection of the bit lines BL is performed by a column decoder 210; In the embodiment of Figure 2, the row decoder 208 inchides a respective row decoder for eachmaiKwy bank and the Column diecoder 210 includes a respective column decoder for each memory bank.

[0026] The bit lines BL are coupled to a respective sense amplifier (SAMP). Read data from the bit line BL is amplified by the sense amplifier SAMP, and transferred to an ECC circuit 220 over local data lines (LIO), transfer gate (TG), and global data lines (GIO). Conversely, write data outputted from die ECC circtiit 220 is transferred to the sense amplifier SAMP over file complementary main data lines GIO, the transfer gate TG, and the complementary local data lines LIO. and written in the memory cell MC coupled to the bit line BL.

[0027] The semiconductor device 200 may employ a plurality of external terminals, such as solder pads, that include command and address (C / A) terminals coupled to a command and address bus to receive commands and addresses, dock tenninals to receive docks CK and / CK, data terminals DQ coupled to a data bus to provide data, and power supply terminals to receive power supply potentials VDD, VSS, VDDQ, and VSSQ. The external terminals may couple directly to the controller (e.g., 150 of Figure 1) and / or may couple to Various buse&'connectors of themodule (e.g., 102 ofFigure 1).

[0028] The clock terminals are supplied with external docks CK and / CK that are provided to an input circuit 212. The external docks may be complementary. The input circuit 212 generates an internal clock ICLK based cm the CK and / CK docks. The ICLK clock is provided to the command decoder 206 and to an internal clock generator 214. The internal clock generator 214 provides various internal clocks LCLK based on the ICLK dock. The LCLK clocks may be used for timing operation of various internal circuits. The internal data docks LCLK are provided to the input / output circuit 222 to time operation of circuits included in the input / output circuit 222, for example, to (fata receivers to time the receipt of write data. The input / output circuit 222 may include a number of interface connections, each of which may be couplable to one of the DQ pads (e.g., the solder pads which may act as external connections to the device 200).

[0029] The C / A tenninals may be supplied with memory addresses. The memory addresses supplied to the C / A terminals are transferred, via a command / address input circuit .202, to an address decoder 204. The address decoder 204 receives the address and supplies a decoded row address XADD to the row decoder 208 and supplies a decoded column address YADD to the column decoder 210. The decoded row address XADD may be used to determine which row should be opened, which may cause the data along the bit lines to be read out along the bit lines. The column decoder 210 may provide a column select Signal CS, which may be used todetermine which sense amplifiers provide data to the LIO. The address decoder 204 may also supply a decoded bank address BADD, which may indicate the bank of the memory array 218 containing the decoded row address XADD and column address YADD.

[0030] The C / A terminals may be supplied with commands. Examples of commands inchide timing commands for controlling die timing of various operations, access commands for accessing the memory, such as read commands for performing read operations and write commands for performing write operations, as well as other commands arid operations. The access commands may be associated with one or mote row address XADD, column address YADD, and bank address BADD to indicate the memory cell(s) to be accessed.

[0031] The commands pray be provided as internal command signals to a command decoder 106 via the command / address input circuit 202. The command decoder 206 includes circuits to decode the internal command signals to generate various internal signals and commands for performing operations. For example, foe command decoder 206 may provide signals which indicate if data is to be read, written, etc.

[0032] The device 200 may receive an access command which is a write command. When foe write command is received, and a bank address, a row address and a column address are timely supplied with the write command, write data supplied to the data terminals DQ by the controller is provided along the data bust and written to memory cells in foe memory array 218 corresponding to the row address and column address. The write command is received by foe command decoder 206, which provides internal commands so that foe write data along the data bus and data terminals DQ is received by data receivers in foe input / output circuit 222. The write data is supplied via the input / output circuit 222 to foe ECC circuit 220. The ECC circuit generates parity bits based on the received data and foe data and parity a® provided to foe memory array 218 to be written along a word line specified by the row address to memory cells specified by the column address- The column address may specify a portion of the memory array (e.g., a portion of foe column planes) and foe data may be written to the specified portion while the parity is written to the non-specified portion. The data and parity are written together as part of a single access pass.

[0033] The device 200 may receive an access command which is a read command When a read command is received, and a bank address, a row address and a column address are timely supplied with the read command, read data and read parity is read from memory cells in foe memory array 218 corresponding to the row address and column address. The read command is received by foe command decoder 206, which provides internal commands so that read dataand read parity from the memory array 218 is provided to tire ECC circuit 220. The ECC circuit 220 receives detects and-'or corrects errors in the data based on the parity. The correct read data is provided along the data bus, and tile data is output to outside from the data terminals DQ via the iuput / output circuit 222. The data and parity may be read out as part of a single access pass.

[0034] The device 200 includes refresh control circuits 216 each associated with a bank of the memory array 218. Each refresh control circuit 216 may determine when to perform a refresh, operation on the associated bank The refresh control circuit 216 provides a refresh address RXADD (along with one or more refresh signals, not shown in Figure 1). Hie row decoder 208 performs a refresh operation on one or more word lines associated with RXADD. The refresh control circuit 216 may perform multiple types of refresh operation, which may determine how the address RXADD is generated, as well as other details such as how many word lines are associated with the address RXADD.

[0035] The ECC circuit 220 may detect and / or correct errors in the accessed data. As part of a write operation, the ECC circuit 220 may receive bits from the IO circuit 222 and generate parity bits based on those received bits. The received bits Mid parity bits are written to the memory array 218. During an example read operation, the ECC circuit 220 receives a set of bits and their associated parity bits from the array 218 and uses them to locate and / or correct errors. The ECC circuit 220 may correct the information and then provide the corrected information (and'or a signal indicated detected errors) to the IO circuit 222. The parity bits may generally not be provided to the IO circuit 222.

[0036] The mode register 230 may include various settings. In some embodiments, flie number of parity bits may be a setting of the mode register 230. Different levels of parity may be implemented tty changing how much space in the array 218 is set aside for parity bits. For example, if die mode register 230 specifies 8 bits of parity per codeword, then a single column plane may be used for each codeword’s parity. ff the mode register specifies 10 bits of parity per codeword, then two column planes may be used for each codeword’s parity. The setting in the mode register 230 which determines how many parity hits to use may be received by the column decoder 210 which may change the mapping of CS values which are provided responsive to a column address.

[0037] The ECC circuit 220 may also receive the setting and may adjust to account for increased (or decreased) levels of parity. In Some embodiments, the device 200 may include multiple ECC engines which may be selected for different ECC modes and different numbersof parity. Based cm the mode register setting 230, the ECC circuit 220 may implement different levels of error correction. For example, in a single error correction (SEC) scheme, up to one bit of error may be Ideated and detected; In a single error correction double error detection (SECDED) scheme, up to one bit of error may be corrected, but two errors may be detected (although the bits causing those errors are not individually located, so no correction can be made). In a double error correction (DEC) rip to two bits of error may be located and corrected, in a triple error correction (TEC) up to three bits, and so forth, hi some embodiments, foe number of parity bits and foe ECC implementation may be determined by the hardware and may be not be selectable.

[0038] The memory 200 may be operated in various modes based on a number of the DQ pads which are used. In some embodiments, foe mode register 230 may include settings which determine how many DQ pads are used, even if there are more DQ pads available. The mode may determine both how many DQ pads foe controller expects to send / receive data along, as well as the format and / or number of bits which the controller expects as part of a single access command. Forexample, the memory may have 16 physical DQ pads. In a 2p2 mode, four of those DQ pads are used, divided info two pseudo-channels of two DQ pads each. The mode may also determine a burst. length at each DQ terminal as part, of a DQ operation. The burst length represents a number of serial bits at. each DQ terminal during an access operation. For example, in foe 2p2 mode, each data terminal may receive a burst of 32 data bits plus some number of metadata bits (e.g., either 2 dr 4 per DQ terinmal).

[0039] The power supply terminals are supplied with power supply potentials VDD and VSS.The power supply potentials VDD and VSS are supplied to an internal voltage generator circuit 224. The internal voltage generator circuit 224 generates various internal potentials VARY, and the like based on the power supply potentials VDD and VSS supplied to the power supply terminals.

[0040] The power supply terminals are also supplied with power supply potentials VDDQ andVSSQ. The power supply potentials VDDQ and VSSQ are supplied to foe mput'output circuit 222. The power supply potentials VDDQ and VSSQ supplied to foe power supply terminals may be the same potentials as the powersupply potentials VDD and VSS supplied tp foe power supply terminals in an embodiment of foe disclosure. The power supply potentials VDDQ and VSSQ supplied to foe power Supply terminals may be different potentials from the power supply potentials VDD and VSS supplied to foe power supply terminals in another embodiment of die disclosure. The power supply potentials VDDQ and VSSQ supplied to the power supplyterminals are used for the input / output circuit 122 so that power supply noise generated by the input / output circuit 122 does not propagate to the other circuit blocks.

[0041] Figure 3 is a block diagram of a memory device according to some embodiments of the present disclosure. The memory device 300 may, in some embodiments, represent a portion of the memory device 200 of Figure 2. The view of figure 3 shows a portion of a memory array 310-314 and 320-324 which may be part Of a memory bank (e.g,, 218 of Figure 2) along with selected circuits Used in the data path such aS the ECC circuit 332 (e.g., 220 of Figure 2) and IO circuits 334 (e.g., 222 of Figure 2). For clarity certain circuits and signals have been omitted from the view of Figure 3.

[0042] The memory device 300 is organized into a number of column planes 310-314. Each of the column planes represents a portion of a memory bank. Each column plane 310-314 includes a number of memory cells at the intersection of word lines WL and bit lines. The bit lines may be grouped together into sets which are activated by a value of a column select (CS) signal For die sake of clarity, only a single vertical line is used to represent the bit lines of each column select set, however, there may be multiple columns accessed by that Value of CS. For example, each line may represent 8 bit lines, all accessed in common by a value of CS. As used herein, a ‘value’ of CS may refer to a decoded signal provided to sets of bit lines. So a first value may represent a first value of a multibit CS signal, or after decoding a signal line associated with that value being active. The word Hues may be extend’ across multiple of the column planes 310-314.

[0043] The memory 300 includes a set of data column planes 310 as Well as an extra column plane 312. The extra column plane 312 may be used to store additional information, such as error correction parity bits. In some embodiments, the memory 300 may also inchide an optional global column redundancy (GCR) column plane 314. Insomeembodimeuts, fee GCR plane 314 may have fewer memory cells (e.g, fewer column select groups) than the data column planes 310. The GCR CP 314 includes a number of redundant columns which may be used as part of a repair operation. If a value: of the CS signal is identified as including defective memory cells in one of the data column planes 310, then the memory may be remapped such that fee data winch would have been stored in that cohunn plane for feat value of CS is instead storedin the GCR CP 314.

[0044] In an example embodiment, the memory 310 may include 16 data column planes 310(0)- 310(15). Each of those data column planes 31.0 includes 64 sets of column selects activated by a respective value of fee column select signal and each set of column select includes 8 bitlines. Accordingly, When a word line is opened responsive to a row address, if a column select signal is provided to each of the 16 column planes then 8 bits are accessed from each of the 16 column planes for a total of 128 bits. The column select signal may also be provided to the extra column plane 312, although that column select signal may be a different value than the one provided to the data column planes 310 for ah additional 8 bits (e.g., which may generally be parity bits). If a repair has been performed, the GCR CP 314 may also be accessed by providing a value of the CS signal, and the values which ate read out from the GCR 315 onto a GCR LIO may be used while ignoring the LIO of the column plane it is replacing. Accordingly, the maximum number of bits that can be retrieved as part of an access pass is 128 bits from the data column planes 310 (with 8 bite substituted from the GCR. CP 314 if there has been a repair) along with 8 additional bite from the extra CP 312.

[0045] In the 2p2 architecture, fewer than 128 bits of data are accessed for a given access operation. Accordingly, only a portion of the data column planes 310 may be used to send / receive data. The eohmin address may include a Column plane select bit or bite which ate used to determine which portion of the data column planes 310 are used, For example, the data column planes 310 may be split into two sets of eight data colmnn planes each. A bit of tire column address (e.g. , an 11* bit of the column address dr CA10) may be used as tire column, plane select bit and may select which portion of the data column planes 310 is being used to Store data as part of the current access operation.

[0046] As described in mdte detail herein, during a given access operation, data maybe stored in the portion of the column planes selected by the column plane select bit, while parity may be stored in one or more iron-selected column planessuch as the extra column plane 312 and / or tiie data column planes 310 which were not selected by tiro column plane select bit. For example, the dajte may be stored in each column plane of the selected portion (e.g, 8 bits in each of 8 selected data column planes 310 for a total of 64 data bite).

[0047] The ECC circuit 332 generates a number of parity bits based on those 64 data bite. The number of parity bits may be based on a setting of the memory (e.g., in a mode register such as 230 of Figure 2) . Since each 64 bit data codeword is associated with some number of parity bits, there maynotberoom in the extra column plane 312 to store tiro parity for all oftiro data codewords. Accordingly, some data codewords may have their parity stored in tiro extra column plane 312, and some data codewords may have their parity stored in data column planes 310 which were not selected by the value of the column plane select bit associated with where the data is stored. For example, if the value of the column plane select bit selects either evenor odd column planes, then data stored in even column planes may have its parity located in tiie extra cohmm plane 312 and / or one or more of the odd column planes 310. Other wax's of dividing up the column planes into portions may be used in other example embodiments.

[0048] ha. an example write operation, a controller (e.g., 150 of Figure 1 ) provides data and to the memory device. The ECC circuit 332 generates parity bite which are written along with the data to the column planes 310-314 as part of a single access pass. In the example discussed herein, the IO circuit receives 64 bits of data in two bursts of 32 bits. The data is provided to the ECC circuit 332 which generates a set ofP parity bits based on the data and metadata bits. The number P is based on a setting of the mode register. Based on the column address half of the data column planes 310 may be selected and the column decoder may provide a first value of the CS signal to die selected half of the column planes. The data may be writte[ to the memory cells at the intersection of the active word line and the tit lines selected by the first value of CS in the selected half of the column planes 310. Depending on the column address and how many parity bits P were generated, the parity tits may either be written to the memory cells at the intersection of the word line and the tit lines selected by a CS signal (which may be the first CS value or a different value) in tile extra column plane 312, and / or they may be written to the memory cells at. the intersection of the word line and the tit lines selected by a second value of the CS signal in one of the data column planes in the non-selec ted portion

[0049] In some embodiments, each data codeword (e g,, every 64 tits of data) may be associated with 8 parity bite (e.g., P = 8). Accordingly, the parity for a given codeword may fit in a single column plane since up to 8 tits in a single column plane may be activated at once by a value of the CS signal. Based on mapping in tire column decoder, the parity may be stored in a non-selected column plane (e.g., die extra column plane 312 or one of the data column planes 310 which was not selected by the cohmm plane select value). Hie value of the CS signal used to stare the parity may be different than the value of the CS signal used to store tiie data. Which of the non-selected column planes is used and what value of the CS signal is used may be determined by the column decoder based on the column address associated with the data.

[0050] hi some embodiments, each date codeword may be associated with more than 8 bits of parity (e.g., P > 8). To maintain single-pass access, the parity may be split into different portions and the different portionsmay be stored inmore than one column plane. For example, if 12 tits of parity are used, then 4 bits each may be stored in three non-selected cohmm planes (e.g,, the extra column plane 312 and two of the non-selected data column planes 310 dr threeof the non-selected data column planes 310). In this manner, all 12 bits may be accessed along with the 64 data bits as part of a single access pass. While this example used a number of parity bits which was evenly divisible, in some embodiments, different column planes may receive different numbers of parity bits. For example, if 9 paritybits are used, then one column plane may be tried to hold 8 parity bits, while a second column plane stares 1 parity bit.

[0051] The value of the CS signal used to store the parity may be different than the value of die CS signal used to Store the data, hi some embodiments, the value of the CS Signal provided to the different column planes maybe different from each other. For example, fi a mix of data and extra column planes is used, then die extra column plane may receive a different value than the data column planes Which of the non-selected column planes is used and what value of the CS si gnal is used may be determined by the column decoder based on the column address associated with the data.

[0052] In some embodiments, since 8 bit lines are activated by each CS value, when there are fewer than 8 parity bits being stored in a column plane, it may be usefill to protect the remaining bits associated with that CS value so they are not erroneously overwritten. hi some em ments, the memory may perform a read'modifyAvrite cycle to readout all 8 bits, modify only the bits which are being changed (e g., to overwrite them with parity), and then write all 8 bits back, hi some embodiments, separate write enable signals may be used such that only some ofthe Sense amplifiers associated with the CS value are modified at one time (rather than all 8). For example, only the istirie amplifiers associated with the bitimes which will store the new parity bits may be modified. This may prevent the data on the bit tines coupled io the non-'ielated sense amplifiers from being modified without requiring additional operations (e g., a read / mpdify / write cycle). Other options for protecting the non-accessed bits associated with the CS signal may be used in other example embodiments.

[0053] hi an example read operation, the data, and parity are retrieved as part of a single access pass. For example, the column decoder provides the first CS signal to the selected portion of die column planes 310 (based on the column plane select bit) and the data bits are read from memory cells at the intersection of the active word tine and the bit lines activated by the first CS signal value in the selected portion of the column planes 310, The parity is retrieved either from file extra column plane 312 based on the first CS signal, and / or from one or more of the non-selected data column planes 310 based on a second CS signal, value. The data and parity are provided to the ECC circuit 332 which performs error correction on the data and metadata based on the received bits. The level of Correction performed by the ECC circuit 332 may bebased On the number of parity bits (e.g., based on a setting in the mode register). For example, based on the setting the ECC circuit 332 may perform SECDED, DEC, TEC, and / or other types of error correction. The corrected data bits and are provided to the I / O circuit 334, where they provided to the DQ terminals.

[0054] Figure 4 is a block diagram of a memory array according to some examples of the present disclosure. The memory array 400 may, in some embodiments, represent the memory array in one or more of the memory devices 104- 110 of Figure 1, 200 of Figure 2, and / or 300 of Figure 3. The block diagram 400 represents how information may be distributed in a memory array 400, rather than foe physical layout of the location where that information is stored. The blocks of Figure 4 may be subdivided to show what percentage of the array is set aside for different purposes and not foe spatial relationships between where that information is stored.

[0055] The memory array 400 includes a second portion 402 and a first portion 401 of a plurality of data column planes (e.g., 310 of Figure 3) and an extra column plane 408 (e.g., 312 of Figure 3). The first portion 401 is selected for data storage when a column plane select bit (e.g., CA10) is in a low logical state (e.g., CA10 - 0) while the second potion 402 is selected for data storage when a column plane select bit is m. a high logical state (e^g., CA10 = 1). Some Of foe space in the data column planes 401 mid 402 is set aside for storing parity bits associated with data winch is stored in foe other portion. For example, the first portion 401 may include parity bits (CA10 = 1 ECC bits) associated with data stored in the second portion 402, and foe second portion 402 may include parity bits (CAI 0 = 0 ECC bits) associated with data stored in foe first portion 401.

[0056] The space in the portions 401 and 402 which are used for parity may represent different column select values which are reserved for parity in one or more of foe column planes. For example, if there are CS value 0-Mfor each column plane, then CS values 0-(N-l) may be used for data while CS values N-M may be used to store the parity. In some embodiments, some column planes may have space set aside for parity while others may not.

[0057] Similar to the portions 401 and 402, the extra column plane 408 is divided imp a first section which includes parity bits associated with data stored in the first portion and a second section which includes parity bits associated with data stared in foe second portion. The division between the Sections of foe extra column planes may be based on the CS signal. For example a first half of foe CS values in foe extra column plane 408 may be set aside for CA10= 1 and a second half of the CS values in the extra column plane 408 may be set aside for CA 10 = 0.

[0058] In ah example read operation, 10 tits of parity may be used (e.g, based on a setting of the memory device). Responsive to a row address a word line is opened, and die column decoder may provide CS signals and read commands to the column planes. In this example, a read is performed where tire column plane select bit is a logical high. The column decoder provides a first CS value to each of the 8 column planes in the first portion 401, and reads out 64 bits of data. The column decoder also provides a second CS value to the extra column plane 408 and reads out 8 tits. The second CS value is chosen so that it’s in a section of the extra column plane which is associated with CA10 = 0. The column decoder also provides a third CS value to a selected column plane in the second portion 402, and reads out 2 parity bits from that column plane. An ECC circuit 410 (e.g., 220 of Figure 2 and / or 332 of Figure 3) receives the 64 data tits and the 10 parity bits and performs error correction based on thedata and parity.

[0059] Figure 5 is a flow chart of a method of writing data and parity to a memory array according to some examples of the present disclosure. The method 500 may, in some embodiments, be implemented by one or more of the apparatuses and system described herein. For example, the method may be implemented by a memory device such as 104-110 of Figure 1, 200 of Figure 2, and / or 300 of Figure 3 and / or in a memory array such as 400 of Figure 4.

[0060] The method 500 may generally begin with box 510 winch describes selecting’ a number of parity bits based on a mode register setting. The mode register (e.g., 230 of Figure 2) includes a setting which may indicate a number of parity bits to be used by the memory device.

[0061] Box 510 may generally be followed by box 520 which describes generating the number of parity tits based on a plurality of data bits. The method 500 may include receiving the plurality of data bits from a controller (e.g., 150 pfFigure 1) as part of a write operation. An ECC circuit (e.g., 220 of Figtre 2, 332 of Figure 3, and / or 410 of Figure 4) generates the parity bits. The logic of the ECC circuit and the number of active outputs for parity bits may be selected based on the mode register setting

[0062] The box 510 may generally be followed by boxes 530 and 540. Box 530 describes selecting a first portion or a second portion of a plurality of data column planes. The selection may be based on a column plane Select bit, which may be part of tire column address (e.g, C A10). The first, portion and the second portion (e. g., 401 and 402 of Figure 4) may representa first half and a second half of the data cohnnn planes. The selecting may be done by a column decoder (e.g., 210 of Figure 2).

[0063] Box 540 describes Selecting one or more column planes from the extra column plane or a non-selected one of the first portion or the second portion of the plurality of data cohnnn planes. The column decoder may include mapping which determines which and how many of the column planes are selected as the one or more column planes. For example the mapping may be based in part on. the setting of the number of parity bite in the mode register and the column address.

[0064] In some embodiments, a single column plane may be selected. For example, if the number of parity bits is equal to or less than the number of bite which are accessed in a single column plane by a Single CS signal (e.g, 8 or fewer bite) then a single column plane may be used. The single column plane may either be die extra column plane or one of thenon-selected data column planes (e.g., die data column planes not selected by the value of CA10). Which single column plane is used for a given siet of data may depend on the column address.

[0065] In some embodiments, multiple column planes may be selected for the parity. For example, if the number of parity bits is greater than the number of bits which are accessed in a single column plane a CS signal (e.g., more than 8 bits) than multiple column planes may be used. The two or more column planes may inchide the extra column plane as well as one or more of the non-selected data column planes, or may include two or moire of the data column planes. Which column planes are selected may be based on die column address.

[0066] Boxes 530 and 540 may generally be followed by box 550, which describes writing the plurality of data bits to the selected ate of the first portion or the second portion of the plurality of data column planes and writing die number of parity bits to the one or more cohnnn planes. Both writing steps may be performed as part of a single access pass. The writing may include providing a first cohnnn select signal value to the selected one of the first partial or the second portion of the plurality of data column planes and providing a second column select signal value to the one or more column planes.

[0067] hr some embodiments if there are two or more column planes used to store the parity, the method 500 may include providing a second column select signal value to one of them and a third column select signal value to the other. In some embodiments the secondcolumn select signal value may be provided to multiple of the cohnnn planes used to store the parity, hi some embodiments where there are two column planes used to store the parity, a first columnplane mayreceive a first portion of the plurality of parity bits and a second column plane may receive a second portion of the plurality of parity bits. The portions may be of different sizes.

[0068] In some embodiments, the method 500 may include reading the data which was written inboxes 510-550. Forexample. the method 500 may include reading the plurality of data bite from the selected one of the fist portion or the second portion of the plurality of data column planes and reading the number of parity bits from the one or more column planes and performing error correction on the plurality bf data bits based oh. the number of parity bits at a level based on the mode register setting. The method may include performing single error correction double error detection (SECDED), double mor correction (DEC), or triple error correction (TEC) on the plurality of data bits read from the selected one of the fist portion or the second portion of the plurality of data column planes based on the number of parity bits.

[0069] Of course, it is to be appreciated that any one of the examples, embodiments ot processes described herein may be combined with one or more other examples, embodiments and / or processes or be separated and'or performed amongst separate devices or device portions in accordance with the present systems, devices and methods.

[0070] Finally, the above-discussion is intended to be merely illustrative of the present system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Thus, while the present system has been described in particular detail with reference to exemplary embodiments, it should also be appreciated that numerous modifications and alternative embodiments may be devised by those having ordinary skill in the art without departing from the broader and intended spirit arid scope of the present system as set forth in the claims that follow. Accordingly, the specification and drawings are to be regarded in ah illustrative manner and are not intended to limit the scope of the appended claims.

Claims

CLAIMSWhat is claimed is:

1. An apparatus comprising: a memory array comprising: a plurality of data column planes including a first portion of the plurality of data cohmm planes and a second portion of die plurality of data cohmm planes; and an extra column plane; an error correction code (ECC) circuit configured to receive a plurality of data bits and generate a plurality of parity bits based on the plurality of data bits; and a column decoder, wherein responsive to a write command the column decoder is configured to provide a first column select signal value and write the phnality of date bits to a selected one of the first or the second portion of the plurality of data cohmm planes and configured to provide a second column select signal value and write the plurality of parity bits to the extra column plane, a non-selected one of the first or the second portion of the plurality Of data column planes, or combinations thereof as part of a single access pass.

2. The apparatus of claim 1, wherein the column: decoder is further configured to provide the second cdlumn select signal value to the extra column plane and a third column select signal to a selected column plane in the non-selected one of the first portion or the second portion of the plurality of data cohmm planes and write a first portion of the plurality of parity bits to die extra column plane and a second portion of die plurality of parity bits to the selected column plane.3- The apparatus of claim I, wherein the column decoder is configured to select die selected one of die first portion or die second portion of die plurality of data column planes based on a column select bit of the cohmm address.4- The apparatus of claim 1, wherein responsive to a read command the cohuun decoder is configured to provide the first column Select signal value and read the plurality of data bits from the selected one of the first or the second portion of the plurality of data column planes and configured to provide the second column select signal and read the plurality ofparity bite from the extra column plane, the non-selected one of the first or the secraid portion of the plurality of date column planes, or combinations thereof as part of a single access pass.

5. The apparatus of claim whereintheECC is configured to receive the plurality of date bits and the plurality of parity bite responsive to the read command and perform error correction on tire plurality of date bits based on tire plurality of parity bite.

6. The apparatus of claim I, further comprising a mode register configured to select a number of the parity bits.

7. The apparatus of claim 6, wherein the ECC circuit is configured to implement single error correction double error detection (SECDED), double error correction (DEC), or triple error correction (TEC) based on the number of parity bits.

8. An apparatus comprising: a memory array comprising: a plurality of data column planes inchidinga first portion of the plurality of date column planes and a second portion of the plurality of data column planes; and an extra column plane; an error correction code (ECC) circuit configured to receive a plurality of date bite and generate a plurality of parity bits based on the plurality qf data bits; and a column decoder configured to write the plurality of data bits in to a selected one of die first portion or the second portion of the plurality of date column planes and configured to write the plurality of parity bits in at least two column planes selected from the extra, column plane and a non-selected one of the first portion or the second portion of the plurality of data column planes.

9. The apparatus of claim 8, wherein the column decoder is configured to write the plurality of data bits and the plurality of parity bits as part of a single access pass.

10. Tire apparatus of claim 8, further comprising a mode register configured to select a number of the plurality of parity bite .

11. The apparatus of claim 8, wherein the column decoder is configured to provide a first column select signal value to a first one of the at least two column planes and a second column select signal value to a second one of the at least two column planes.

12. The apparatus of claim 11, wherein die column decoder is fiirther configured to provide a third column select signal value to die selected one of the first portion dr the second portion of the plurality of data column planes.

13. The apparatus of claim 8, wherein die column decoder is configured to write a first portion of the plurality of parity bits to a first of the at least two column planes and a second portion of the plurality of parity bits to a second of the at least two column planes wherein the first portion and die second portion of die plurality of parity bits are different in size.

14. A method comprising: selecting a number of parity bits based on a mode register setting; generating die number of parity bits based on a plurality of data bits; selecting a firstportion or a second portion of a plurality of data- columnplanes: selecting one or more column planes from the extra column plane dr a nonselected one of the first portion or the second portion of die plurality of data column planes; and writing the plurality of data bits to die selected one of die first portion or die second portion of the plurality of data column planes and writing the number of parity bits to the one or more column planes.

15. The method of claim 14, furtiier comprising writing die number of parity bits to at least two of the one or more column planes.

16. The method of claim 15, fiirther comprising writing a firstportion of the number of parity bits to a first one of the at least two of the one or more column planes and writing a second portion of the number of parity bits to a second one of the at least two of the one or more column planes, wherein the first portion and the second portion are different in size.

17. The method of claim 15, wherein a first one of tbe at least two of die one or more column planes is the extra column plane and wherein a second one of the at least two of die one or more column planes is a column plane in the nan-selected one of the first, portion or the second portion of the plurality of data column planes.

18. The method of claim 14, further comprising: providing a first column select signal value to the selected one of the first portion or the second petition of die plurality of column planes; and providing a second column select signal value to the selected one or more column planes.

19. The method of claim 14, fiirther comprising: reading the plurality of data bits from the selected one of the fist portion or the second portion of the plurality of data column planes ami reading the number of parity bits from the one or more column planes; and performing error correction on the plurality of data bits based On the number of parity bits at a level based on die mode register setting.

20. The method of claim 19, fiirther comprising performing single error correction double error detection (SECDED), double error correction (DEC), or triple error correction (TEC) oil the plurality of data bits read from the selected one of the fist: portion or die second portion of the plurality of data column planes based on the number of parity bits.

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