Method for handling ce in memory, and computing device

Abstract

Provided in the present application is a method for handling a CE in a memory. In an embodiment, the method is applied to a computing device, and comprises: acquiring information of corrected errors (CEs) generated in a memory; on the basis of the information of the CEs, determining a first numerical value, wherein the first numerical value indicates the frequency at which the CEs occur in the memory during the process of a computing device refreshing the memory according to a first memory refresh frequency; on the basis of the first numerical value, adjusting the first memory refresh frequency to a second memory refresh frequency, wherein the second memory refresh frequency is greater than the first memory refresh frequency; and refreshing the memory according to the second memory refresh frequency. Thus, when the frequency at which CEs occurs in a memory is relatively large, a memory refresh frequency can be increased, so as to reduce the probability of CEs frequently occurring in the memory.

Description

Memory CE processing method and computing device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on October 11, 2023, with application number 202311314896.6 and application name “Memory CE processing method and computing device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of computer technology, and in particular to a memory CE processing method and computing device. Background Art

[0003] With the advancement of central processing unit (CPU) technology, the memory capacity supported by a single CPU has increased. This has led to an increasing probability of memory problems throughout the entire computer system. As a key component that directly provides data cache to the CPU, a failure in memory can directly cause the CPU to stop responding, leading to system downtime.

[0004] Current memory modules have built-in error checking and correction (ECC). However, if a certain bit frequently experiences correctable errors (CE) during operation, and CE occurs again in other bits when data is read, the data cannot be corrected by ECC, resulting in uncorrectable errors.

[0005] Therefore, the probability of uncorrectable errors (UCE) occurring in a memory that frequently experiences CE will increase, and a method for reducing the probability of CE occurring in the memory is urgently needed.

[0006] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the application and should not be regarded as an admission or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art.

[0007] Summary of the Invention

[0008] The embodiment of the present application provides a memory CE processing method, which can increase the memory refresh frequency and reduce the probability of frequent CE occurrence in the memory when the frequency of CE occurrence in the memory is high.

[0009] In a first aspect, an embodiment of the present application provides a memory CE processing method, applied to a computing device, the method comprising:

[0010] Obtain information about correctable errors (CE) generated on the memory; determine a first value based on the CE information; the first value indicates the frequency of CE occurring in the memory during a process in which the computing device refreshes the memory at a first memory refresh frequency; based on the first value, adjust the first memory refresh frequency to a second memory refresh frequency; the second memory refresh frequency is greater than the first memory refresh frequency; and refresh the memory at the second memory refresh frequency.

[0011] In this solution, when the frequency of CE in the memory is high, the memory refresh frequency can be increased to reduce the probability of frequent CE in the memory.

[0012] In one possible implementation, determining the first value based on the CE information includes: determining the number of CE occurrences within a statistical period; and determining the first value based on the number of CE occurrences within the statistical period. For example, the first value may be the number of CE occurrences within the statistical period, or the number of CE occurrences within the statistical period and the duration of the statistical period.

[0013] In this solution, the first value is obtained by counting the number of CE occurrences within a period of time. The first value can more accurately reflect the frequency of CE occurrences in the memory.

[0014] In one possible implementation, the first memory refresh frequency is adjusted to the second memory refresh frequency based on the first value, including: when the first value is greater than or equal to a preset threshold, the first memory refresh frequency is adjusted to the second memory refresh frequency; the second memory refresh frequency is greater than the first memory refresh frequency.

[0015] In one possible implementation, before refreshing the memory according to the first memory refresh frequency, the memory is refreshed according to the third memory refresh frequency, and the method also includes: determining a second value, which indicates the frequency of CE appearing in the memory during the process of the computing device refreshing the memory according to the third memory refresh frequency.

[0016] In an example of this implementation, adjusting the first memory refresh frequency to the second memory refresh frequency according to the first value includes: when the second value is less than or equal to the first value, adjusting the first memory refresh frequency to the second memory refresh frequency.

[0017] In this solution, when the second value is less than or equal to the first value, it means that the current memory refresh frequency does not reduce the frequency of CE in the memory. In this case, the memory refresh frequency can be further increased.

[0018] In an example of this implementation, when the second value is greater than or equal to the first value and the first memory refresh frequency is equal to the memory refresh frequency upper limit, the second memory refresh frequency is less than the first memory refresh frequency, or is equal to the third memory refresh frequency.

[0019] In this solution, when the second value is less than or equal to the first value, it means that the current memory refresh frequency has not improved the frequent occurrence of CE in the memory. At the same time, the current memory refresh frequency has reached the upper limit. At this time, it means that increasing the memory refresh frequency has not reduced the probability of CE in the memory. By reducing the memory refresh frequency, the impact on memory performance is reduced.

[0020] In one example of this example, refreshing the memory according to the second memory refresh frequency includes:

[0021] Isolate the location where the CE occurs in the memory; after the isolation is successful, refresh the memory based on the second memory refresh frequency.

[0022] In this solution, the location where CE occurs is isolated, and memory is refreshed after isolation is successful, thereby ensuring memory performance.

[0023] In one possible implementation, adjusting the first memory refresh frequency to the second memory refresh frequency includes:

[0024] The processor is set to be in unlock mode so that the register in the processor is in a modified state, and the register is used to store the memory refresh frequency of the memory; the memory refresh frequency of the memory stored in the register is modified to the second memory refresh frequency; the processor is set to release the unlock mode so that the register is in a locked state.

[0025] In this solution, by changing the state of the processor, the memory refresh frequency of the memory can be flexibly changed during the operation of the computing device.

[0026] In one possible implementation, the memory refresh frequency of the memory is stored in a target bit in a register; and the memory refresh frequency of the memory stored in the register is modified to a second memory refresh frequency, including: modifying the value of the target bit in the register of the memory controller so that the memory refresh frequency of the memory is the second memory refresh frequency.

[0027] In a second aspect, an embodiment of the present application provides a memory CE processing method, which is applied to a computing device, wherein the computing device includes an input / output system BIOS, a baseboard management controller BMC, and a central processing unit CPU, and the method includes:

[0028] The CPU runs BIOS to obtain information about correctable errors (CEs) generated on the memory from the CPU's memory controller;

[0029] The BMC determines a first value based on the CE information obtained from the BIOS, and notifies the BIOS to adjust the first memory refresh frequency to a second memory refresh frequency based on the first value; the first value indicates a frequency of CE occurring in the memory during a process in which the computing device refreshes the memory according to the first memory refresh frequency; the second memory refresh frequency is greater than the first memory refresh frequency;

[0030] The memory controller in the CPU refreshes the memory based on the second memory refresh frequency.

[0031] In this solution, when the frequency of CE in the memory is high, the memory refresh frequency is increased to reduce the probability of frequent CE in the memory; the CE statistics function is handed over to the BMC, which can reduce the use of CPU resources.

[0032] In one possible implementation, the BMC determines the number of CE occurrences within a statistical period and determines a first value based on the number of CE occurrences within the statistical period. For example, the first value may be the number of CE occurrences within the statistical period or the frequency of CE occurrences within the statistical period, where the frequency is the ratio of the number of CE occurrences within the statistical period to the duration of the statistical period.

[0033] In this solution, the first value is obtained by counting the number of CE occurrences within a period of time. The first value can more accurately reflect the frequency of CE occurrences in the memory.

[0034] In a possible implementation, when the first value is greater than or equal to a preset threshold, the BMC adjusts the first memory refresh frequency to a second memory refresh frequency through the BIOS; the second memory refresh frequency is greater than the first memory refresh frequency.

[0035] In one possible implementation, before the CPU's memory controller refreshes the memory at the first memory refresh frequency, the CPU refreshes the memory at a third memory refresh frequency; the BMC determines a second value, which indicates the frequency of CE occurring in the memory during the process of the computing device refreshing the memory at the third memory refresh frequency.

[0036] In an example of this implementation, when the second value is less than or equal to the first value, the BMC adjusts the first memory refresh frequency to the second memory refresh frequency through the BIOS.

[0037] In this solution, when the second value is less than or equal to the first value, it means that the current memory refresh frequency does not reduce the probability of CE occurring in the memory. At this time, the memory refresh frequency can be further increased.

[0038] In an example of this implementation, when the second value is greater than or equal to the first value and the first memory refresh frequency is equal to the memory refresh frequency upper limit, the second memory refresh frequency is less than the first memory refresh frequency, or is equal to the third memory refresh frequency.

[0039] In this solution, when the second value is less than or equal to the first value, it means that the current memory refresh frequency has not improved the frequency of CE occurrence in the memory. At the same time, the current memory refresh frequency has reached the upper limit. At this time, it means that increasing the memory refresh frequency has not reduced the probability of CE occurrence in the memory. By reducing the memory refresh frequency, the impact on memory performance is reduced.

[0040] In one example of this embodiment, the CPU runs the BIOS or the operating system OS to isolate the location where the CE appears in the memory; after the isolation is successful, the memory is refreshed based on the second memory refresh frequency.

[0041] In this solution, the location where CE occurs is isolated, and memory is refreshed after isolation is successful, thereby ensuring memory performance.

[0042] In one possible implementation, the BIOS sets the CPU to an unlocked mode so that the registers in the CPU are in a modified state, and the registers are used to store the memory refresh frequency of the memory; the memory refresh frequency of the memory stored in the registers is modified to a second memory refresh frequency; and the CPU is set to release the unlocked mode so that the registers are in a locked state.

[0043] In this solution, by changing the state of the processor, the memory refresh frequency of the memory can be flexibly changed during the operation of the computing device.

[0044] In one possible implementation, the memory refresh frequency of the memory is stored in a target bit in a register of the memory controller; the BIOS modifies the value of the target bit in the register of the memory controller so that the memory refresh frequency of the memory is the second memory refresh frequency.

[0045] In a third aspect, an embodiment of the present application provides a memory CE processing method, which is applied to a baseboard management controller (BMC). The method includes:

[0046] Obtain information about correctable errors (CE) generated on the memory; determine a first value based on the CE information; the first value indicates the frequency of CE occurring in the memory during a process in which the computing device refreshes the memory at a first memory refresh frequency; based on the first value, send a memory refresh frequency adjustment notification to the input / output system BIOS, so that the BIOS adjusts the first memory refresh frequency to a second memory refresh frequency, and the central processing unit (CPU) refreshes the memory at the second memory refresh frequency; the second memory refresh frequency is greater than the first memory refresh frequency.

[0047] In this solution, when the frequency of CE in the memory is high, the memory refresh frequency is increased to reduce the probability of frequent CE in the memory; the CE statistics function is handed over to the BMC, which can reduce the use of CPU resources.

[0048] In one possible implementation, before the computing device refreshes the memory at the first memory refresh frequency, the computing device refreshes the memory at the third memory refresh frequency, and the method further includes:

[0049] Determine a second value, which indicates the frequency of CE in the memory when the computing device refreshes the memory according to the third memory refresh frequency; when the second value is less than the first value and the first memory refresh frequency is the upper limit of the memory refresh frequency, an alarm is issued.

[0050] In a fourth aspect, an embodiment of the present application provides a memory CE processing device, which includes several modules, each of which is used to execute each step of the memory CE processing method provided in the first aspect of the embodiment of the present application. The division of modules is not limited here. The specific functions performed by each module of the memory CE processing device and the beneficial effects achieved can be referred to the functions of each step of the memory CE processing method provided in the first aspect of the embodiment of the present application, and will not be repeated here.

[0051] For example, the memory CE processing device includes:

[0052] A memory CE acquisition module is used to obtain information about correctable errors CE generated on the memory;

[0053] A memory CE evaluation and judgment module is configured to determine a first value based on CE information; the first value indicates a frequency of CE occurring in the memory during a process in which the computing device refreshes the memory at a first memory refresh frequency;

[0054] A memory refresh frequency adjustment module, configured to adjust the first memory refresh frequency to a second memory refresh frequency according to the first value; the second memory refresh frequency being greater than the first memory refresh frequency;

[0055] The refresh module is used to refresh the memory according to the second memory refresh frequency.

[0056] In one possible implementation, the memory CE evaluation and judgment module is configured to determine the number of CE occurrences within a statistical period and determine a first value based on the number of CE occurrences within the statistical period. For example, the first value may be the number of CE occurrences within the statistical period, or the number of CE occurrences within the statistical period and the duration of the statistical period.

[0057] In a possible implementation, the memory refresh frequency adjustment module is configured to adjust the first memory refresh frequency to a second memory refresh frequency when the first value is greater than or equal to a preset threshold; the second memory refresh frequency is greater than the first memory refresh frequency.

[0058] In one possible implementation, before refreshing the memory according to the first memory refresh frequency, the memory is refreshed according to the third memory refresh frequency, and the memory CE evaluation and judgment module is used to determine a second value, which indicates the frequency of CE appearing in the memory during the process of the computing device refreshing the memory according to the third memory refresh frequency.

[0059] In an example of this implementation, the memory refresh frequency adjustment module is configured to adjust the first memory refresh frequency to the second memory refresh frequency when the second value is less than or equal to the first value.

[0060] In an example of this implementation, when the second value is greater than or equal to the first value and the first memory refresh frequency is equal to the memory refresh frequency upper limit, the second memory refresh frequency is less than the first memory refresh frequency, or is equal to the third memory refresh frequency.

[0061] In one example of this example, the memory CE processing device further includes: an isolation module for isolating the location where CE appears in the memory; and a refresh module for refreshing the memory based on the second memory refresh frequency after the isolation is successful.

[0062] In one possible implementation, the memory refresh frequency adjustment module is configured to set the processor to an unlocked mode, thereby placing a register in the processor in a modified state. The register is configured to store a memory refresh frequency of a memory; modify the memory refresh frequency stored in the register to a second memory refresh frequency; and release the processor from the unlocked mode, thereby placing the register in a locked state.

[0063] In one possible implementation, the memory refresh frequency of the memory is stored in a target bit in a register; the memory refresh frequency adjustment module is used to modify the value of the target bit in the register of the memory controller so that the memory refresh frequency of the memory is a second memory refresh frequency.

[0064] In the fifth aspect, an embodiment of the present application provides a memory CE processing device, comprising: at least one memory for storing programs; at least one processor for executing the programs stored in the memory, and when the program stored in the memory is executed, the processor is used to execute the method provided in the first aspect.

[0065] In a sixth aspect, an embodiment of the present application provides a memory CE processing device, characterized in that the device runs computer program instructions to execute the method provided in the first aspect. Exemplarily, the device can be a chip or a processor.

[0066] In one example, the apparatus may include a processor, which may be coupled to a memory, read instructions from the memory, and execute the method provided in the first aspect according to the instructions. The memory may be integrated into a chip or processor, or may be independent of the chip or processor.

[0067] In a seventh aspect, an embodiment of the present application provides a computer storage medium, in which instructions are stored. When the instructions are executed on a computer, the computer executes the method provided in the first aspect, the second aspect or the third aspect.

[0068] In an eighth aspect, an embodiment of the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method provided in the first aspect, the second aspect, or the third aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] FIG1 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0070] FIG2 a is a first structural diagram of the memory 112 in FIG1 ;

[0071] FIG2 b is a structural diagram 1 of the connection between the memory controller and the memory 112 in the CPU 111 in FIG1 ;

[0072] FIG2 c is a second structural diagram of the connection between the memory controller and the memory 112 in the CPU 111 in FIG1 ;

[0073] FIG3 is a schematic diagram of reading data from the memory 112 according to an embodiment of the present application;

[0074] FIG4a is a schematic diagram of a hard isolation process provided in the related art;

[0075] FIG4 b is a schematic diagram of a soft isolation process provided in the related art;

[0076] FIG5 is a flow chart of a memory CE processing method provided in an embodiment of the present application;

[0077] FIG6 is a flow chart of another memory CE processing method provided in an embodiment of the present application;

[0078] FIG7 is a flow chart of another memory CE processing method provided in an embodiment of the present application;

[0079] FIG8 is a schematic structural diagram of a memory CE processing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0080] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

[0081] In the description of the embodiments of the present application, words such as "exemplary," "for example," or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary," "for example," or "for example" in the embodiments of the present application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary," "for example," or "for example" is intended to present the relevant concepts in a concrete manner.

[0082] In the description of the embodiments of this application, the term "and / or" is simply a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone, B exists alone, and A and B exist at the same time. In addition, unless otherwise specified, the term "plurality" means two or more. For example, "multiple systems" refers to two or more systems, and "multiple terminals" refers to two or more terminals.

[0083] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly identifying the technical features being referred to. Thus, features specified as "first" or "second" may explicitly or implicitly include one or more of such features. The terms "include," "comprising," "having," and their variations all mean "including but not limited to," unless otherwise specifically emphasized.

[0084] The following is an explanation of some of the terms used in this embodiment. It should be noted that these explanations are for the purpose of facilitating understanding by those skilled in the art and are not intended to limit the scope of protection claimed in this application.

[0085] Error Checking and Correcting (ECC): is a memory data error correction technology that uses the concept of data blocks and complex algorithms to correct data. It can not only detect multi-bit errors but also correct single-bit errors.

[0086] Correctable Error (CE): A correctable error that occurs during memory operation but can be corrected using ECC. Therefore, CE errors are sometimes referred to as ECC errors. CE errors can occur due to occasional address command errors, multi-bit errors in a single x4 memory chip, or single-bit errors in a single x8 memory chip.

[0087] Uncorrected Error (UCE): An uncorrectable error that occurs during memory operation and cannot be corrected by ECC. Multi-bit errors in x8 memory chips, multi-bit errors in multiple memory chips in x4 memory chips, and continuous address command errors may all cause UCE.

[0088] Non-maskable external interrupt (System Management Interrupt, SMI): has a higher priority than all debug interrupts, NMI, maskable interrupts and soft interrupts.

[0089] Bank: represents a logical storage library in memory.

[0090] System Management Mode (SMM): When SMI is triggered, the processor enters SMM and executes the SMI interrupt program in SMM. This mode has a separate memory space that occupies actual memory, not mapped memory.

[0091] Row Refresh Cycle Time (tRFC): This defines the cycle time required to refresh all bank row addresses. Memory is volatile, and the charge in the capacitors of memory cells gradually disappears. Therefore, to maintain data integrity, the memory must periodically refresh the row addresses of one or more banks.

[0092] DRAM Refresh Interval Time (tREFI): This is the interval between the completion of tRFC and the next row address refresh cycle. Compared with tRFC, tREFI will have a more significant impact on read and write performance, but tREFI will also have a more significant impact on memory stability.

[0093] Basic Input / Output System (BIOS): The BIOS contains the initialization routines that run when the computer is turned on. The BIOS is stored in a read-only memory (ROM) chip on the motherboard. The contents of this chip are programmed using specialized manufacturing equipment before the computer leaves the factory. Once installed, they are typically not modified by the user.

[0094] Baseboard Management Controller (BMC): It is a dedicated controller used to monitor and manage servers. Its four main functions are as follows: ① Equipment information management: recording server information (model, manufacturer, date, production and technical information of each component, chassis information, motherboard information, etc.), BMC information (server host name, IP, BMC firmware version, etc.); ② Server status monitoring and management: detecting the temperature, voltage and other health status of each component of the server (CPU, memory, hard disk, fan, chassis, etc.), and adjusting the fan speed in real time according to the conditions of each temperature collection point to ensure that the server does not overheat and the overall power consumption is controlled not too high; if any abnormality occurs in the single-board component, the information will be reported to the upper-level network management in a timely manner through a variety of industry-standard specifications; ③ Remote control management of the server: server power on and off, restart, maintenance, firmware update, system installation, etc.; ④ Maintenance management: log management, user management, BIOS management, alarm management, etc. BMC can be understood as BMC firmware. BMC firmware is a software program running on the BMC chip. It can be thought of as software that runs as soon as the server is powered on. Running on a separate BMC chip on the server, such as an ARM chip, it is an independent system that does not rely on other system hardware (such as the CPU, memory, etc.) or the BIOS or OS. However, the BMC can interact with the BIOS and OS to better manage the platform. The OS includes system management software that can work with the BMC to achieve better management results. Therefore, the BMC is a small operating system independent of the server system, responsible for implementing functions such as remote control, management, and monitoring of the server. The BMC chip is either integrated into the motherboard or plugged into the motherboard via a PCI Express connector. This chip serves as the BMC firmware's CPU, and the chip itself is equipped with its own peripherals, such as RAM and Flash. As soon as the server is plugged in, the BMC firmware begins to run.

[0095] First, the computing device provided in the embodiments of the present application is introduced. In some possible cases, the computing device can be used to provide cloud services.

[0096] As shown in Figure 1, computing device 100 can be a rack server, or a server node in a multi-node server. A server node has the functionality of a complete server and, in some cases, can be referred to as a compute node. For example, a multi-node server can be a high-density server, a blade server, or a full-rack server. A full-rack server is an architecture that integrates the original separate rack and machine into a single, independent product.

[0097] For example, as shown in FIG. 1 , the computing device 100 may include a power supply 121 and a mainboard 110 . The power supply 121 is electrically connected to the mainboard 110 to supply power to components on the mainboard 110 .

[0098] Exemplarily, the motherboard 110 includes a CPU (central processing unit) 111, memory 112, a BIOS chip 113, a BMC (baseboard management controller) chip 114, a PCIE slot 115, a network card 122, a hard disk 123, and a fan 124. The BIOS chip stores BIOS software, and the BMC chip stores BMC software.

[0099] The memory 112 can be provided as memory particles in a memory stick, or can be inserted into a memory slot as a memory stick. For example, the memory particles can be random access memory (RAM). By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0100] For example, a memory bank may include multiple, for example, 2, ranks, each rank includes multiple memory particles, and each memory particle includes multiple banks. As shown in Figure 2a, each bank includes a word line WL, a bit line bL, and a basic cell. The cell is composed of a capacitor and a transistor. The gate (g) of the transistor is connected to the bit line bL, the drain (d) of the transistor is connected to the word line WL, the source (3) of the transistor is connected to the capacitor, and the capacitor is connected to the voltage source; wherein the capacitor has leakage current. It can be seen that each bank is a 2-dimensional array composed of basic cells, indexed by rows and columns. The basic cells in the same row are connected together by word lines (WL), and the basic cells in the same column share a set of bit lines (BL). In actual use, when the charge of the cell's capacitor is high, such as 80% to 100%, the cell is used to store data 1; when the charge of the cell's capacitor is low, such as 0% to 20%, the cell is used to store data 0; otherwise, the cell cannot represent the data; it should be noted that 80% to 100% and 0% to 20% are only examples, and are closely related to the memory technology of the memory manufacturer. In actual applications, the charge of the cell's capacitor will change over time. If the capacitor is fully charged (can store data 1), the charge will be lost. If the capacitor has no charge (data 0), external charge will flow into the capacitor in the cell. When the charge of the capacitor in the cell is damaged to a certain extent, the data will not be able to be read and written normally, resulting in memory failure. The cell needs to be charged or discharged within a certain period of time. This operation is called a refresh operation.

[0101] As shown in FIG2b , CPU 111 may include an integrated memory controller (IMC). A memory refresh frequency parameter (indicating the time interval between refreshes of memory 112) may be set in the IMC, thereby controlling the memory refresh frequency of memory 112. For example, as shown in FIG2b , the memory refresh frequency of memory 112 is stored in a register in the IMC, for example, in bits 0 to 14 of a 32-bit register.

[0102] In one possible scenario, as shown in FIG2 b , one register in the memory controller (IMC) can control the memory refresh frequency of all memories 112. For example, one register in the memory controller (IMC) can control the memory refresh frequency of memory chips in all memory banks.

[0103] In another possible scenario, a register in a memory controller (IMC) can control the memory refresh rate of at least one memory 112. As shown in Figure 2c, assume that there are n memories 112, labeled memory 1, memory 2, ..., memory n, and the memory controller includes n registers, labeled register 1, register 2, ..., register n. Register i is used to control the refresh rate of memory i, where i = 1, 2, ..., n. For example, a register in a memory controller (IMC) can control the memory refresh rate of each memory chip in a memory bank.

[0104] Among them, the PCIE slot 115 is suitable for expanding at least one of a GPU card, a network card, a video capture card, an HBA (Host Bus Adapter) card, a RAID (redundant arrays of independent disks) card, and an SSD (solid state disk or solid state drive), and can also support the expansion of various adapter cards.

[0105] The hard disk 123 can be a hard disk drive (HDD) or a solid-state drive. For example, the solid-state drive can be a PCIe channel solid-state drive, such as a solid-state drive that conforms to the Nonvolatile Memory Express (NVME) logical device interface specification (used to access non-volatile memory media attached via the PCI Express (PCIe) bus). It should be understood that the hard disk 123 is merely an example of a non-volatile memory and does not constitute a specific limitation. In actual applications, a non-volatile memory can be selected based on actual circumstances.

[0106] It should be noted that FIG1 is merely an example of the computing device 100 and does not constitute a specific limitation. In actual applications, more or fewer devices than those shown in FIG1 may be included, such as a complex programmable logic device (CPLD), a field programmable gate array (FPGA), a single-chip microcomputer (an integrated circuit chip equivalent to a microcomputer), a digital signal processor (DSP), an application specific integrated circuit (ASIC), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, general-purpose processors, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0107] In related technologies, with the advancement of CPU processor technology, the memory capacity supported by a single CPU is increasing. The bandwidth and frequency of the channel between current mainstream CPUs and DDR SDRAM are gradually increasing. Consequently, servers are equipped with more and more memory sticks, with larger and larger total memory capacity and higher operating frequencies. This has led to an increasing rate of memory problems throughout computer systems. As a key component that directly provides data cache to the CPU, failures in the memory system can directly cause the CPU to stop responding, leading to system downtime.

[0108] Currently, memory 112 has built-in ECC. To facilitate understanding, we first explain the ECC mode. As shown in Figure 3, memory 112 uses double-bit rate (DDR) and x4 chips. Each cacheline (the smallest cache unit in the CPU's cache) reads 64 bytes of data, divided into eight bursts (execution times), with each burst reading 64 bits of data. The normal ECC mode is 64 / 8 SEC (single-error-correcting, SEC) / DED (double-error correction) Hamming code. On the one hand, it can detect and correct a single-bit error; on the other hand, it can detect two-bit errors but cannot correct them. As shown in Figure 3, if CE occurs frequently in D0 of Burst 0, and CE occurs again in any bit D1-D63, the 64-bit Burst 0 cannot be corrected by ECC, causing Burst 0 data to become uncorrected code (UCE). Therefore, the presence of CE in memory increases the probability of UCE.

[0109] In summary, if a certain bit of memory 112 frequently experiences CE during operation, and CE occurs again in other bits when data is read, the read data cannot be corrected by ECC, resulting in an uncorrectable error (UCE). Therefore, the probability of UCE occurring in memory 112 that frequently experiences CE increases. UCE will directly cause a system crash on the current Intel CPU architecture. ECC eliminates potential risks that affect the normal operation of the system by processing the basic cells (cells) in memory 112 that have experienced errors, thereby improving system reliability. Therefore, although the memory 112 of current servers already supports single-bit automatic error correction, in order to improve system reliability and reduce performance degradation and downtime risks caused by memory problems, the single-bit error correction function of the memory is not sufficient. Some additional measures are needed to improve system reliability.

[0110] In the related art, the probability of UCE occurring in the memory 112 can be reduced through various methods.

[0111] Implementation method 1: In addition to the ECC mechanism built into the memory 112, CE that occurs in the memory 112 can also be handled through isolation. Currently, there are two main isolation methods: hard isolation and soft isolation.

[0112] The implementation of hard isolation is as follows: As shown in Figure 4a, the error correction mechanism within CPU 111 identifies CEs that appear in memory 112. The BIOS running within CPU 111 counts CEs and determines whether they exceed a threshold. If so, bottom-level isolation is implemented (i.e., isolating the location of the fault in memory 112). The main methods for bottom-level isolation are as follows:

[0113] 1) Bank Isolation: This can be achieved through Adaptive Double Device Data Correction Sparing (ADDDC). ADDDC, used during system operation, is a set of error correction and isolation methods based on a memory chip parity check algorithm. When using DIMMs with 4-bit bit width chips, the CPU111's memory controller (IMC) uses virtual lockstep technology to ensure that 36 chips participate in each read and write of a cache line. Of these 36 chips, 32 are used to store business data, 2 store CRC check values, 1 stores parity values, and 1 serves as a backup. If a memory chip experiences multiple minor faults and is determined to be unstable, the unstable chip can be replaced with a backup chip, thus shielding the potential fault. After the replacement is completed, if a memory chip is still found to be unstable, the unstable chip can be replaced with a chip storing parity values ​​to further isolate the potential fault.

[0114] 2) Row Isolation: This can be achieved through post package repair (PPR). The memory controller (IMC) of CPU 111 utilizes the row isolation function and redundant row design of memory 112. For failed storage cells, it uses internal circuit fusion to replace the failed row with a redundant row, thereby shielding the failed storage cell (shielding requires a reboot).

[0115] 3) Cell Isolation: This can be achieved through Partial Cache Line Sparing (PCLS). PCLS can correct single-bit errors. When a permanent single-bit error occurs on a cache line, a backup bit (the basic cell) can be used to replace the erroneous bit. This makes PCLS performance better than ADDDC. A single memory channel can support up to 16 sets of PCLS.

[0116] The implementation of soft isolation is as follows: As shown in Figure 4b, the error correction mechanism inside CPU 111 identifies the CE appearing in memory 112 and reports it to the operating system (OS). The OS running in CPU 111 counts the CEs and determines the severity of the fault. If the fault is determined to be severe, the OS triggers the error isolation mechanism.

[0117] Hard isolation technology has the following disadvantages:

[0118] 1) Simple counting algorithms lead to inaccurate judgments, and some hard isolations rely on restarts;

[0119] 2) The essence of hard isolation is to replace the memory unit, and it cannot repair the CE of the memory part;

[0120] 3) According to current statistics, among the 15,228 servers that experienced CE, only 8% reached the CPU internal counting threshold, and the probability of triggering hard isolation is low.

[0121] Soft isolation technology has the following disadvantages:

[0122] 1) The OS can only perform upper-layer actions, wasting the underlying hard isolation capabilities;

[0123] 2) The OS layer supports technologies such as page isolation, which poses a risk of downtime;

[0124] 3) The memory space will be reduced after OS layer isolation.

[0125] Implementation method 2: The occurrence of CE in some memory 112 can be reduced to a certain extent by increasing the memory refresh frequency (at least the length of the time interval between two consecutive refreshes of the memory 112. The higher the memory refresh frequency, the shorter the time interval between the two refreshes). Industry server manufacturers currently configure memory double refresh / multiple refresh in BIOS, but it will only take effect after the device is restarted and the BIOS settings are entered. It cannot be dynamically modified while the device is running to reduce the probability of memory failure.

[0126] In order to facilitate understanding of the memory CE processing method proposed in the embodiment of the present application, the relevant content of memory refresh is first described.

[0127] Considering that by increasing the memory refresh frequency of memory 112, some cells that fail at the normal memory refresh frequency can be repaired, thereby reducing the failure rate of memory 112. At present, there are two ways to refresh memory 112. One is self-refreshing, which is implemented inside memory 112. The other is that the memory controller (IMC) of CPU111 issues a refresh instruction (which can be called a REF instruction) to control the refresh of memory 112. The memory controller (IMC) of the CPU implements the issuance of the REF instruction by controlling the high and low levels of the memory pins (for example, mainly CKE, CS_n, ACT_n, RAS_n, CAS_n, WE). The REF instruction issued by the memory controller (IMC) of the CPU has a corresponding time interval requirement. For a row unit of memory 112, two consecutive REF instructions must be greater than tRFC (the time required for memory 112 to complete a refresh). In order to improve the operating efficiency of the memory, the refresh instruction can be postponed for a period of time before being sent. The memory controller (IMC) of CPU111 can control the issuance of REF instructions by adjusting the values ​​stored in specific registers (such as the tcrftp register). For example, for 1866MT / s, the default setting is 1C70, which is 7280 (1C70 converted to decimal) * 7.8us ≈ 56ms. When it is set to 0E38, the refresh time is 3640 (0E38 converted to decimal) * 7.8us ≈ 28ms, which becomes a double refresh.

[0128] In summary, during the operation of the computing device 100, the value of the register in the CPU's memory controller (IMC) can be adjusted, and the memory refresh instruction can be reissued to increase the memory refresh frequency, thereby reducing the probability of CE in the memory and further reducing the probability of UCE in the memory.

[0129] Based on this, the embodiment of the present application proposes the following memory CE processing method.

[0130] During the operation of the computing device 100, by analyzing the frequency of CE occurrences in the memory 112 (used to indicate the number of times the memory 112 has CE occurrences within a statistical period), if it is determined that the memory 112 has CE occurrences more frequently, for example, with a large frequency, the memory refresh frequency is dynamically modified to increase the memory refresh frequency, thereby reducing the probability of memory UCE occurrences without requiring a system restart. Specifically, the method for dynamically modifying the memory refresh frequency during the operation of the computing device 100 can be: combining the control characteristics of the registers of the memory controller (IMC) in the CPU, dynamically modifying the values ​​stored in the registers of the memory refresh control, and then modifying the memory refresh frequency; in this way, this solution can increase the memory refresh frequency of the memory 112 by modifying the values ​​stored in the registers of the memory controller (IMC) without requiring a system restart, thereby reducing the probability of CE occurrences in the memory 112, thereby reducing the probability of UCE occurrences in the memory 112, and improving the reliability of the memory 112.

[0131] In a specific implementation, the computing device 100 determines the frequency of CE occurrences in the memory 112. If it is determined that the frequency is large, for example, the frequency is greater than or equal to a preset threshold, indicating that CE occurs frequently in the memory 112, the memory refresh frequency is increased. After increasing the memory refresh frequency, the computing device 100 determines whether the frequency of CE occurrences in the memory 112 is significantly reduced after the memory refresh frequency is increased. If it is not significantly reduced, it means that CE occurs frequently in the memory 112. The computing device 100 may continue to increase the memory refresh frequency until the set upper limit of the memory refresh frequency is reached (for ease of description and distinction, it may be referred to as the upper limit of the memory refresh frequency). After reaching the upper limit of the memory refresh frequency, it means that the probability of CE occurrence in the memory 112 cannot be reduced by increasing the memory refresh frequency. At this time, isolation means such as hard isolation or soft isolation are used to process the location where CE occurs in the memory 112. The computing device 100 may also reduce the memory refresh frequency, or set the memory refresh frequency to the lower limit of the memory refresh frequency (for ease of description and distinction, it may be referred to as the lower limit of the memory refresh frequency). If it is significantly reduced, it means that the probability of CE occurrence in the memory 112 is reduced. The computing device 100 may also increase the memory refresh frequency until the memory refresh frequency is significantly reduced. Among them, the upper limit of the memory refresh frequency can be manually set by accessing the computing device 100 through a terminal such as a mobile phone or a computer, or it can default to the maximum memory refresh frequency allowed by the computing device 100.

[0132] For example, assuming that the preset threshold is 5 CEs per 10 minutes, the memory 112 of the computing device 100 has three memory refresh frequencies: 1X refresh, 2X refresh, and 4X refresh. The refresh interval of 2X refresh is half that of 1X refresh, and the refresh interval of 4X refresh is 3 / 4 that of 1X refresh. For example, assuming that the refresh interval of 1X refresh is T, the refresh interval of 2X refresh is T / 2, and the refresh interval of 4X refresh is T / 4. The memory 112 of the computing device 100 is refreshed at 1X. When CE occurs in the memory 112 of the computing device 100, the frequency of CE in the memory 112 is counted. When the preset threshold is reached, the method of modifying the value stored in the specified register is triggered to adjust the memory refresh frequency to 2X refresh online (the refresh interval is half that of 1X refresh). If the frequency of CE in the memory 112 becomes 2 per 10 minutes after the 2X refresh is set, it is considered that 2X refresh effectively reduces the probability of CE in the memory 112, which is helpful for memory reliability, and the memory refresh frequency is maintained at 2 times the current refresh. Otherwise, the method of modifying the value stored in the specified register is triggered to adjust the memory refresh frequency to 4X refresh online (the refresh interval is reduced by 3 / 4 relative to 1X refresh, which is also the upper limit of the memory refresh frequency). The adjustment of 4X refresh is the same as 2X refresh. The difference is that when 4x refresh cannot effectively reduce the frequency of memory CE, it will be restored to 1X refresh (the lower limit of memory refresh frequency) and start other isolation measures such as the original Bank isolation, row isolation and Cell isolation in BIOS, or soft isolation.

[0133] This is just a brief description of the method. For details about the method, please refer to the description below.

[0134] Next, in combination with the computing device 100 and the memory CE processing method provided above, the process of a memory CE processing method provided in an embodiment of the present application is introduced in detail.

[0135] FIG5 is a flow chart of a memory CE processing method provided in an embodiment of the present application. This embodiment can be applied to a computing device, such as computing device 100. As shown in FIG5 , an embodiment of the present application provides a memory CE processing method, which is used to describe a method for adjusting the memory frequency of a memory 112. The memory 112 can be a single memory chip in a memory bank, or a single memory bank. The method includes at least the following steps:

[0136] Step 501: Obtain information of CE generated in the memory 112.

[0137] Among them, step 501 can be executed by CPU111, for example, it can be executed by the BIOS running on CPU111. Here, the information of CE generated on memory 112 can be obtained by the BIOS running in CPU111. In a specific implementation, when CE appears in memory 112, the memory controller (IMC) in CPU111 records the CE information and saves it in the register; at the same time, an interrupt such as SMI is generated in BIOS, and after the interrupt, SMM is entered, and BIOS reads the CE information stored in the register in CPU11. It should be noted that the BIOS running in CPU111 obtaining the information of CE generated on memory 112 is only an example and does not constitute a specific limitation. In some possible implementations, the OS running in CPU111 can also obtain the information of CE generated on memory 112.

[0138] For example, the CE information is used to describe the CE and may include: the CE fault address (used to indicate the location of the CE in the memory 112), and further, may include the CE error bit information, error type, error number, etc. The specific information may be determined based on actual conditions.

[0139] In practice, the operating system (OS) manages the continuous logical addresses of 4KB memory pages, and the corresponding physical page frames are distributed across the same row of multiple memory chips in the memory bank. The cache block size is 64 bytes, and the corresponding memory storage block is the basic unit of memory access (cell). A 4KB memory page consists of 64 cache blocks, and the corresponding memory storage blocks of the 64 cache blocks are located in a continuous row of different memory chips.

[0140] In one embodiment of the present application, if memory 112 represents a memory bank, the CE's fault address may include: memory controller (IMC), rank, bank, row, column, etc.; the CE's error bit information may include: which memory cell is faulty, which burst is faulty, and which bits are faulty; the CE's error count may be, for example, the number of errors counted by a register in the memory controller (IMC). If memory 112 represents memory cells in a memory bank, the CE's fault address may include: bank, row, column, etc.; the CE's error bit information may include: which bits are faulty.

[0141] Step 502: Determine a first value based on the CE information; the first value indicates the frequency of CE appearing in the memory 112 when the computing device refreshes the memory 112 according to the first memory refresh frequency.

[0142] Step 502 can be executed by the BMC running on the BMC chip 114, so that the resources of the CPU 111 will not be occupied. Here, the BMC running on the BMC chip 114 can determine the first value based on the information of the CE generated on the memory 112. For example, when a CE appears in the memory 112, the memory controller (IMC) in the CPU 111 records the CE information and saves it in the register; at the same time, an interrupt such as SMI is generated in the BIOS, and after the interruption, the SMM is entered. The BIOS reads the CE information stored in the register in the CPU 11 and passes it to the BMC; the BMC determines the first value based on the CE information. It should be noted that the determination of the first value by the BMC running on the BMC chip 114 based on the CE information generated on the memory 112 is only an example and does not constitute a specific limitation. In some possible implementations, the OS running on the CPU 111 can also determine the first value based on the CE information generated on the memory 112. The following description takes the determination of the first value by the BMC as an example.

[0143] In some possible implementations, the first value specifically indicates the frequency of occurrence of CE in the statistical period. The frequency can reflect the possibility or frequency of occurrence of CE in memory 112. For example, the first value can be the number of occurrences of CE in the statistical period, or the frequency, where the frequency is the ratio of the number of CE to the statistical period.

[0144] In this implementation, the determination in step 502 may be made as follows:

[0145] The BMC determines the number of times CE occurs within a statistical period; and determines a first value based on the number of times CE occurs within the statistical period.

[0146] Among them, the statistical period indicates the duration, which can be determined manually by accessing the computing device 100 through a mobile phone, terminal, etc., and can be specifically designed based on the duration of the period in which CE appears multiple times in the historical operation process of the memory 112.

[0147] In a specific implementation, a dynamic sliding window mechanism may be used to calculate the number of CEs that occur in the memory 112 within a statistical period. Specifically, the BMC uses the statistical period as a dimension to calculate and store the number of CEs that occur in the memory 112 within the statistical period.

[0148] The principle of the dynamic sliding window mechanism is as follows: the sliding window size is set to the number of sampling times, such as 10, the sampling interval of each element in the sliding window is interval, such as 1 minute, the time period of all data in the sliding window is the number of sampling times, such as 10*interval, and the element value of each element is used to represent the number of times CE appeared in memory 112 between the time of the last sampling and the time of the current sampling. The sliding window is mobile, that is, it continues to slide as the number of sampling times of the number of CEs appearing in memory 112 increases; the size of the sliding window is fixed, which can be the default value, a custom value, or dynamically determined by the BMC based on the historical operation status of memory 112 and the sampling interval, used to illustrate the statistical period.

[0149] In a specific implementation, the BMC samples the information of CE appearing in the memory 112 through the sampling interval Inteval, and records the sampling number or time, and the number of CE appearing in the memory 112 for each sampling. If no CE is found in the memory 112, the number of CE appearing in the memory 112 is 0; then, the number of CE appearing in each sampling record in the sliding window is counted to determine the total number of CE appearing in the memory 112 collected within the statistical period, and the number is used as the first value, or the ratio of the number to the duration of the statistical period is calculated, and the ratio is used as the first value.

[0150] For example, assuming that the sliding window includes 10 elements, the i-th sampling result is recorded as Si, assuming that among the 1st to 10th samplings, only the result S8 of the 8th sampling indicates that the number of times CE appears in memory 112 is 2, and the others are 0, and the last element in the sliding window is the 10th sampling, then the number of times CE appears in memory 112 during the statistical period is 2, and the frequency of memory CE is 2 / 10; then, the result S11 of the 11th sampling indicates that the number of times CE appears in memory 112 is 1, and the sliding window slides 1 element, then the number of times CE appears in memory 112 during the statistical period is 3, and the frequency of memory CE is 3 / 10; and so on.

[0151] In addition, BMC can flexibly configure the size of the sliding window (used to represent the statistical period) and the sampling interval. In specific implementation, users can flexibly configure the size of the sliding window and the sampling interval through the web page (Web) or standard command interface in terminal devices such as mobile phones and computers.

[0152] Step 503: Based on the first value, adjust the first memory refresh frequency to a second memory refresh frequency; the second memory refresh frequency is greater than the first memory refresh frequency.

[0153] Among them, step 503 can be executed by the BIOS running on CPU 111. Here, the first memory refresh frequency can be adjusted to the second memory refresh frequency by the BIOS running in CPU 111. In a specific implementation, when step 502 is executed by the BMC, the BMC notifies the BIOS to adjust the first memory refresh frequency to the second memory refresh frequency based on the first value; when step 502 is executed by CPU 111, the CPU 111 notifies the BIOS to adjust the first memory refresh frequency to the second memory refresh frequency based on the first value. The following description takes the BMC notifying the BIOS to adjust the first memory refresh frequency to the second memory refresh frequency based on the first value as an example.

[0154] In the embodiment of the present application, whether CE appears frequently in memory 112 can be analyzed based on the first value, which can also be understood as the possibility of CE appearing in memory 112. When CE appears frequently in memory 112 and the first memory refresh frequency does not reach the lower limit of the memory refresh frequency, the memory refresh frequency is increased to reduce the probability of CE appearing in memory 112.

[0155] In some possible cases, the first memory refresh frequency is the initial memory refresh frequency, which is generally the lower limit of the memory refresh frequency, so as to ensure the performance of the memory 112. In this case, step 503 is determined as follows:

[0156] When the first value is greater than or equal to the preset threshold (indicating that the probability of CE appearing in memory 112 is high), the BMC notifies the BIOS to adjust the first memory refresh frequency to the second memory refresh frequency; the second memory refresh frequency is greater than the first memory refresh frequency. Among them, the BMC can flexibly configure the preset threshold. In specific implementation, the user can flexibly configure the preset threshold through a web page (Web) or a standard command interface in a terminal device such as a mobile phone or a computer. The preset threshold can be determined in combination with the CE situation that occurred during the historical operation of the memory 112; for example, under the condition that the first value is the number of CEs that occurred in the memory 112 during the statistical period, the preset threshold can be determined in combination with the minimum and maximum values ​​of the number of CEs that occurred during the statistical period during the historical operation of the memory 112, such as taking the average; under the condition that the first value is the frequency of CEs that occurred in the memory 112 during the statistical period, the preset threshold can be determined in combination with the minimum and maximum values ​​of the frequency of CEs that occurred during the statistical period during the historical operation of the memory 112, such as taking the average.

[0157] It should be noted that when the memory 112 has a memory refresh frequency upper limit, the BMC notifies the BIOS to adjust the first memory refresh frequency to the second memory refresh frequency when the first value is greater than or equal to the preset threshold (indicating that the probability of CE occurring in the memory 112 is high) and the first memory refresh frequency is less than the memory refresh frequency upper limit;

[0158] In some possible cases, before the computing device 100 refreshes the memory 112 at the first memory refresh frequency, the computing device 100 refreshes the memory 112 at a third memory refresh frequency, where the third memory refresh frequency is less than the first memory refresh frequency. In this case, step 503 is determined as follows:

[0159] The BMC determines a second value, which indicates the frequency of CE occurring in the memory 112 during the process of the computing device 100 refreshing the memory 112 according to the third memory refresh frequency; when the second value is less than or equal to the first value, it indicates that the probability of CE occurring in the memory 112 due to the first memory refresh frequency is relatively high, and notifies the BIOS to adjust the first memory refresh frequency to the second memory refresh frequency, increase the memory refresh frequency, and thus reduce the probability of CE occurring in the memory 112.

[0160] The second value is determined in the same manner as the first value. For details, please refer to the above description of step 502.

[0161] In step 503, adjusting the first memory refresh frequency to the second memory refresh frequency can be achieved by:

[0162] The BIOS sets a processor, such as CPU 111, to an unlocked mode, such as unlock mode, so that registers in the processor are in a modified state. The registers are used to store the memory refresh rate of memory 112; the memory refresh rate of memory 112 stored in the registers is modified to a second memory refresh rate; and the processor is set to unlock mode, such as lock mode, so that the registers are in a locked state. By changing the processor state, the memory refresh rate can be flexibly changed during the operation of the computing device 100.

[0163] Among them, the registers are located in the memory controller (IMC).

[0164] Among them, the memory refresh frequency of memory 112 is stored in the target bit in the register; the computing device 110 modifies the memory refresh frequency of memory 112 stored in the register to the second memory refresh frequency. The specific implementation method is: modify the value of the target bit in the register so that the memory refresh frequency of memory 112 is the second memory refresh frequency.

[0165] There are various ways to increase the first memory refresh frequency. For example, the first memory refresh frequency can be increased by n (greater than or equal to 2) times. The increase method here is merely an example and does not constitute a specific limitation. The specific method can be determined based on actual needs. It is worth noting that in the embodiment of the present application, the increase in the first memory refresh frequency can be determined based on the actual performance of the memory 112. The greater the increase, the greater the performance degradation of the memory 112.

[0166] Step 504: Refresh the memory 112 according to the second memory refresh frequency.

[0167] The CPU 111 in the computing device 100 includes a memory controller (IMC). Step 504 may be performed by the memory controller (IMC) in the CPU 111. Here, the memory controller (IMC) refreshes the memory 112 at the second memory refresh frequency. Specifically, the memory controller (IMC) controls the high and low levels of memory pins (exemplarily, CKE, CS_n, ACT_n, RAS_n, CAS_n, and WE) based on the second memory refresh frequency, determines a REF instruction, and issues the REF instruction to the memory 112, causing the memory 112 to be refreshed at the second memory refresh frequency.

[0168] In one embodiment of the present application, if memory 112 represents a memory bank, a memory controller (IMC) may control each memory chip in the memory bank to be refreshed at a second memory refresh frequency. If memory 112 represents a memory chip in a memory bank, the memory controller (IMC) may control the memory bank where memory 112 is located to be refreshed at the second memory refresh frequency. If the memory bank where memory 112 is located can independently control memory chips, the memory bank may refresh the memory 112 at the second memory refresh frequency.

[0169] It is worth noting that, in the scenario where the memory 112 is represented as a memory stick, when the computing device 100 has multiple memories 112, if the memory controller (IMC) in the CPU 111 is unable to adjust the memory refresh frequency for each memory 112 individually, and if the probability of CE occurring in any of the multiple memories 112 is high, then in step 504, the computing device 100 refreshes the multiple memories 112 at the second memory refresh frequency. When the computing device 100 has multiple memories 112, as shown in FIG2c , if the memory controller (IMC) in the CPU 111 is able to adjust the memory refresh frequency for one memory 112 individually, and if the probability of CE occurring in any of the multiple memories 112 is high, then in step 504, the computing device 100 refreshes the memory 112 with the higher probability of CE occurring at the second memory refresh frequency.

[0170] In summary, the refresh of memory 112 is generally implemented at a certain granularity. For example, it can be refreshed at the granularity of a memory bar, or at the granularity of a memory granule in a memory bar. The present embodiment does not specifically limit this, and can be reasonably expanded in combination with future technology solutions. It is worth noting that the information of CE appearing in memory 112 obtained in step 501 needs to be adapted to the granularity of memory 112 refresh; for example, in the scenario of refreshing at the granularity of a memory bar, step 501 needs to obtain information of CE appearing in the memory bar, or information of CE appearing in the memory granule; in the scenario of refreshing at the granularity of a memory granule, step 501 needs to obtain information of CE appearing in the memory granule.

[0171] In this solution, when the frequency of CE in the memory is high, the memory refresh frequency is increased to reduce the probability of frequent CE in the memory.

[0172] For the situation described above: before the memory 112 is refreshed at the first memory refresh frequency, the memory controller (IMC) refreshes the memory 112 at the third memory refresh frequency, and the third memory refresh frequency is less than the first memory refresh frequency; at this time, the BMC or CPU 111 can determine the second value, and the second value indicates the frequency of CE in the memory 112 during the process of the computing device 100 refreshing the memory 112 at the third memory refresh frequency. In this case, when the second value is greater than or equal to the first value, and the first memory refresh frequency is equal to the upper limit of the memory refresh frequency, it means that the probability of CE in the memory 112 cannot be reduced by increasing the memory refresh frequency. In order to ensure the performance of the memory 112, the memory refresh frequency needs to be reduced. Correspondingly, the second memory refresh frequency is less than the first memory refresh frequency. For example, if the third memory refresh frequency is the lower limit of the memory refresh frequency, the second memory refresh frequency can be equal to the third memory refresh frequency; if the third memory refresh frequency is greater than the lower limit of the memory refresh frequency, the second memory refresh frequency can be the lower limit of the memory refresh frequency.

[0173] It is worth noting that when the second value is greater than or equal to the first value, and the first memory refresh frequency is equal to the upper limit of the memory refresh frequency, it means that the probability of CE cannot be reduced by increasing the memory refresh frequency. In order to ensure the stable operation of the computing device 100, isolation measures such as hard isolation or soft isolation are also needed to handle memory CE.

[0174] In this case, correspondingly, in step 504, the computing device 100 isolates the location where CE appears in the memory 112; after the isolation is successful, the memory 112 is refreshed based on the second memory refresh frequency. The computing device 100 can determine the location where CE appears in the memory 112 based on the fault address of CE in the CE information; the isolation method can be hard isolation or soft isolation; successful isolation can be understood as the location where CE appears in the memory 112 will no longer be used, specifically, the location where CE appears in the memory 112 will no longer be used for data writing or data reading. In actual applications, the computing device 100 isolates the location where CE appears in the memory 112, and after the processing is completed, a processing result will be obtained, which is used to indicate whether the isolation is successful.

[0175] FIG5 shows only a basic embodiment of the method of the embodiment of the present application. By performing certain optimization and expansion on this basis, other preferred embodiments of the method can be obtained.

[0176] In one embodiment, based on the previous embodiment, this embodiment provides a more detailed description and optimization of the memory CE processing process. The method in this embodiment includes:

[0177] The CPU runs the BIOS and obtains the information of CE generated on the memory from the CPU's memory controller (IMC) (for details, see the description of step 501 above); the BMC determines a first value based on the CE information; the first value indicates the frequency of CE appearing in the memory during the process of the computing device refreshing the memory at the first memory refresh frequency (for details, see the description of step 502 above); based on the first value, the BMC notifies the BIOS to adjust the first memory refresh frequency to the second memory refresh frequency; the second memory refresh frequency is greater than the first memory refresh frequency (for details, see the description of step 503 above); the memory controller of CPU111 refreshes the memory 112 at the second memory refresh frequency (for details, see the description of step 504 above).

[0178] In one possible implementation, before refreshing the memory according to the first memory refresh frequency, the memory is refreshed according to the third memory refresh frequency, and the BMC can determine a second value, which indicates the frequency of CE occurring in the memory during the process of the computing device refreshing the memory according to the third memory refresh frequency; if the second value is less than the first value and the first memory refresh frequency is the upper limit of the memory refresh frequency, an alarm is issued.

[0179] In a specific application, it is assumed that the memory 112 of the computing device 100 has three memory refresh frequencies: 1X refresh, 2X refresh, and 4X refresh. The refresh interval of 2X refresh is reduced by half compared to 1X refresh, and the refresh interval of 4X refresh is reduced by 3 / 4 compared to 1X refresh. For example, assuming that the refresh interval of 1X refresh is T, the refresh interval of 2X refresh is T / 2, and the refresh interval of 4X refresh is T / 4. When the computing device 100 is started, the BIOS sets the memory refresh frequency to 1X refresh by default (1x refresh, the lower the memory refresh frequency, the lower the memory performance). When the computing device 100 is running, the BMC first collects the frequency of CE generated by the memory 112 during the statistical period. When the preset threshold is reached, the frequency of CE in the memory 112 is recorded, and then the BMC notifies the BIOS to adjust the memory refresh frequency of the memory 112.

[0180] After receiving the notification to adjust the memory refresh frequency, BIOS first sets CPU111 to unlock mode (in this mode, the hidden underlying registers can be operated). After entering the unlock mode, it modifies the register value according to the memory model, increases the memory refresh frequency, such as adjusting it to 2X refresh (the refresh time is reduced to half of 1X refresh), and reduces the time interval of REF instructions issued by the memory controller (IMC) of CPU111.

[0181] When the memory refresh frequency is adjusted to 2X refresh (that is, double refresh), the BMC combines the dynamic sliding window mechanism to monitor the frequency of CE occurrences during the statistical period. When it is found that the frequency of CE occurrences during the 2X refresh process of memory 112 decreases compared to the frequency of CE occurrences during the 1X refresh process of memory 112, it is considered that the 2X refresh of memory 112 has reduced the probability or frequency of CE occurrences in memory 112, and the memory refresh frequency is maintained at 2X refresh (because the higher the memory refresh frequency, the more the memory performance decreases. When the probability of memory CE has been effectively reduced, the memory refresh frequency will no longer be increased). When it is found that the frequency of CE occurrences during the 2X refresh process of memory 112 has not decreased compared to the frequency of CE occurrences during the 1X refresh process of memory 112, the BMC notifies the BIOS to adjust the memory refresh frequency again; the BIOS adjusts the memory refresh frequency to 4X (the refresh time is reduced to half of 1X refresh, 1 / 4).

[0182] When the memory refresh frequency is adjusted to 4X refresh (that is, double refresh), the BMC combines the dynamic sliding window mechanism to monitor the frequency of CE occurrence within the statistical period; when it is found that the frequency of CE occurrence during the memory 112 refresh according to 4X is reduced compared with the frequency of CE occurrence during the memory 112 refresh according to 2X, it is considered that the 4x memory refresh frequency can effectively improve the probability or frequency of CE occurrence in the memory 112, and the memory refresh frequency is maintained at 4X refresh; when it is found that the frequency of CE occurrence during the memory 112 refresh according to 4X is not reduced compared with the frequency of CE occurrence during the memory 112 refresh according to 2X, the BMC is notified to generate an alarm, indicating that the probability of CE occurrence in the memory cannot be reduced by increasing the memory refresh frequency, and the BIOS is notified to reset the memory refresh frequency to 1X to prevent 4X refresh from causing memory performance degradation. At the same time, the BIOS is notified to use other isolation measures to improve memory reliability to reduce the probability of memory UCE.

[0183] As shown in Figure 6, another specific embodiment of the memory CE processing method provided in the embodiment of the present application. Based on the previous embodiment, this embodiment provides a more specific description and a certain degree of optimization for the memory CE processing process. In this embodiment, the first memory refresh frequency, the second memory refresh frequency, and the third memory refresh frequency are no longer used for description, and the current memory refresh frequency is uniformly used. The method in this embodiment includes the following steps:

[0184] Step 601: BIOS obtains CE information generated during the process of refreshing the memory 112 according to the current memory refresh frequency.

[0185] The current memory refresh frequency may be referred to as a third memory refresh frequency. For details, see the above description of step 501 .

[0186] Step 602: The BMC determines a second value based on the CE information; the second value indicates the frequency of CE in the memory when the computing device refreshes the memory according to the current memory refresh frequency.

[0187] The second value is determined in the same manner as the first value. For details, see the above description of step 502.

[0188] Step 603 : The BMC determines whether the second value is greater than or equal to a preset threshold. If yes, the process goes to step 604 ; if not, the process goes to step 601 .

[0189] Step 604: The BIOS modifies the memory refresh frequency stored in the register of the memory controller (IMC) by increasing the current memory refresh frequency to update the current memory refresh frequency.

[0190] For details, see the above description of step 504.

[0191] The updated current memory refresh frequency may be referred to as a first memory refresh frequency, and the memory refresh frequency after the first memory refresh frequency is updated may be referred to as a second memory refresh frequency.

[0192] Step 605: The memory controller (IMC) refreshes the memory 112 according to the updated current memory refresh frequency.

[0193] Step 606: The BMC determines a first value, where the first value indicates a frequency of CE occurring in the memory when the computing device refreshes the memory according to the updated current memory refresh frequency.

[0194] Step 607 : The BMC determines whether the first value is greater than or equal to the second value. If yes, the process goes to step 608 ; if not, the process goes to step 611 .

[0195] Step 608 : The BMC determines whether the current memory refresh frequency is equal to the upper limit of the memory refresh frequency. If so, step 609 is executed. If not, the first value is used as the second value and step 604 is executed.

[0196] Step 609: The BIOS isolates the location where the CE appears in the memory.

[0197] Isolation can be achieved through soft or hard isolation.

[0198] Step 610 : The BIOS modifies the memory refresh frequency stored in the register of the memory controller (IMC) by increasing or decreasing the current memory refresh frequency to update the current memory refresh frequency, and then executes step 605 .

[0199] Step 611: BIOS maintains the current memory refresh rate.

[0200] Figure 7 is a schematic diagram of a specific application scenario provided by the present application. As shown in Figure 7, it specifically includes the following contents:

[0201] 1. The computing device 100 starts up.

[0202] 2. The CPU refreshes the memory at 1x refresh rate, which means it refreshes at the lower limit of the memory refresh rate.

[0203] 3. The BIOS detects the frequency of CE in the memory during operation.

[0204] 4. The BMC determines whether the frequency reaches the preset threshold. If yes, go to step 5; if no, go to step 3.

[0205] 5. BIOS sets the CPU to enter Unlock mode.

[0206] 6. BIOS sets the memory to 2x refresh mode. The refresh interval in 2x refresh mode is half that of 1x refresh mode.

[0207] 7.BIOS sets the CPU to enter lock mode.

[0208] 8. The BMC checks whether the frequency of CE errors in the memory has decreased. If not, go to 9. If so, go to 6.

[0209] 9. BIOS sets the CPU to enter Unlock mode

[0210] 10. BIOS sets the memory to 4x refresh mode. The refresh interval in 4x refresh mode is half that of 2x refresh mode.

[0211] 11.BIOS sets the CPU to enter lock mode.

[0212] 12. The BMC checks whether the memory CE frequency has decreased. If so, go to 10. If not, go to 13.

[0213] 13.BMC alarm.

[0214] 14. BIOS uses other isolation methods.

[0215] Based on the same concept as the embodiment of the method of the present application, the embodiment of the present application also provides a memory CE processing device. The memory CE processing device includes several modules, each module is used to execute each step in the memory CE processing method provided in the embodiment of the present application, and the division of the modules is not limited here. Those skilled in the art can clearly understand that in actual applications, the various steps in the memory CE processing method provided in the embodiment of the present application can be assigned to different modules as needed, that is, the internal structure of the device is divided into different modules to complete all or part of the functions described above. The modules in the embodiment can be integrated into a processing unit, or each unit can exist physically separately, or two or more modules can be integrated into a unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of a software functional unit. In addition, the specific names of the modules are only for the convenience of distinguishing each other and are not used to limit the scope of protection of this application. The specific working process of the modules in the above-mentioned device can refer to the corresponding process in the aforementioned method embodiment and will not be repeated here.

[0216] For example, a memory CE processing device is used to execute the memory CE processing method provided in an embodiment of the present application. FIG8 is a schematic diagram of the structure of the memory CE processing device provided in an embodiment of the present application. As shown in FIG8, the memory CE processing device provided in an embodiment of the present application includes:

[0217] The memory CE acquisition module 801 is used to obtain information about correctable errors CE generated in the memory;

[0218] The memory CE evaluation and determination module 802 is configured to determine a first value based on the CE information; the first value indicates the frequency of CE in the memory during a process in which the computing device refreshes the memory at a first memory refresh frequency;

[0219] A memory refresh frequency adjustment module 803 is configured to adjust the first memory refresh frequency to a second memory refresh frequency according to the first value; the second memory refresh frequency is greater than the first memory refresh frequency;

[0220] The refresh module 804 is configured to refresh the memory according to a second memory refresh frequency.

[0221] According to one possible implementation, before the computing device refreshes the memory at the first memory refresh frequency, the computing device refreshes the memory at the third memory refresh frequency. The memory CE evaluation and determination module is configured to determine a second value, where the second value indicates a frequency of CE occurring in the memory during the process of the computing device refreshing the memory at the third memory refresh frequency.

[0222] The memory CE processing device further includes: an alarm module 805, which is used to issue an alarm when the second value is less than the first value and the first memory refresh frequency is the upper limit of the memory refresh frequency.

[0223] The memory CE processing device also includes: an isolation module 806, which is used to isolate the location where CE appears in the memory under the condition that the second value is less than the first value and the first memory refresh frequency is the upper limit of the memory refresh frequency; a refresh module, which is used to refresh the memory based on the second memory refresh frequency after the isolation is successful.

[0224] As shown in Figure 8 , the memory CE acquisition module 801 and the memory refresh frequency adjustment module 803 can be set in the BIOS, the memory CE evaluation and judgment module 802 can be set in the BMC, and the refresh module can be set in the CPU 111. When hard isolation is used, the isolation module 806 can be set in the BIOS, and when soft isolation is used, the isolation module 806 is set in the CPU 111.

[0225] This application takes the isolation module 806 set in BIOS as an example to describe in detail the improvements and specific implementation details of the embodiment of the present application on the software layer.

[0226] In a specific implementation, the BIOS has a memory CE memory CE acquisition module 801 and an isolation module 806. In an embodiment of the present application, a memory refresh frequency adjustment module 803 is added to the BIOS. For the BMC management software (used to implement out-of-band management), a memory CE evaluation and judgment module 802 and an alarm module 805 can be added; in this way, the memory CE memory CE acquisition module 801 originally in the BIOS is combined with the memory refresh frequency adjustment module 803 and the memory CE evaluation and judgment module 802, and the memory refresh frequency of the memory 112 is adjusted during the operation of the computing device 100 to reduce the probability of UCE in the memory. It should be noted that the memory CE evaluation and judgment module 802 and the alarm module 805 are set in the BMC only as an example. In some possible scenarios, the memory CE evaluation and judgment module 802 and the alarm module 805 can be set in the BIOS or in the OS. The embodiment of the present application does not specifically limit this. The memory CE evaluation and judgment module 802 and the alarm module 805 are set in the BIOS or OS, which will occupy the resources of the CPU, but setting them in the BMC will not occupy the resources of the CPU 111, thereby ensuring the performance of the CPU. The embodiment of the present application takes the memory CE evaluation and judgment module 802 and the alarm module 805 being set in the BMC as an example to describe the solution.

[0227] Among them, the memory CE memory CE acquisition module 801 is used to record and save the information of the CE that appears in the memory 112 in a register (different from the register that records the memory refresh frequency of the memory 112 in the IMC) when the CE appears on the memory 112; at the same time, an interrupt is generated in the BIOS, and after the interrupt, the CE information stored in the register of the CPU 111 is read and passed to the BMC.

[0228] It should be noted that, since the parsing and recording of the CE information generated by the memory 112 are all performed in the BMC, the memory CE evaluation and judgment module 802 is set in the BMC.

[0229] Memory CE evaluation and judgment module 802 is configured to parse and record information about CEs generated by memory 112, monitor and count the occurrence of CEs in memory 112, such as their frequency. For example, the BMC may calculate the frequency of memory CEs received within a statistical period using a dynamic sliding window mechanism. See the description of step 502 above for details. If it is determined that the frequency of CEs occurring in memory 112 is high, such as when the frequency exceeds a preset threshold, indicating a high probability or frequent occurrence of CEs in memory 112, the BIOS is notified to adjust the memory refresh frequency to increase it. If multiple adjustments to the memory refresh frequency fail to improve the frequency of CEs occurring in memory 112, such as if the frequency does not decrease, the BIOS may be notified to employ other isolation measures (e.g., hard isolation, such as ADDDC Sparing, PPR, PCLS, etc., which are currently inherited by default in the BIOS) and generate relevant alarm records. Alternatively, the OS in CPU 111 may be notified to employ soft isolation.

[0230] In addition, the memory CE evaluation and judgment module 802 integrates a flexible and configurable module for the statistical period (that is, the size of the sliding window) and the sampling interval. In the specific implementation, the user can flexibly configure the statistical period and the monitoring interval through the web page (Web) or standard command interface in terminal devices such as mobile phones and computers.

[0231] Memory refresh frequency adjustment module 803: This module is integrated into the BIOS in conjunction with the BMC's action of notifying the BIOS after evaluating and judging the memory CE 802. This module is used to adjust the memory refresh frequency, thereby causing the memory controller (IMC) of CPU 111 to issue REF instructions to refresh memory 112 according to the adjusted memory refresh frequency. In some possible implementations, when the BMC notifies the BIOS to adjust the memory refresh frequency, the BIOS first adjusts CPU 111 to unlock mode. In unlock mode, the BIOS adjusts the value of a specified register (the IMC stores the memory refresh frequency of memory 112) to adjust the memory refresh frequency. After the adjustment, CPU 111 is set to lock mode to ensure the security of CPU operation.

[0232] Alarm module 805: is used to generate an alarm when, after adjustment by the memory refresh frequency adjustment module 803, the probability of CE occurring in memory 112 is still large or still relatively frequent, for example, the frequency is still greater than the preset threshold, for example, the frequency is greater than the frequency of CE occurring in memory 112 when the memory refresh frequency is not adjusted, and the memory refresh frequency has reached the upper limit of the memory refresh frequency, indicating that the probability of memory CE occurring cannot be reduced by memory refresh methods, and it is likely that there is a fault in the storage unit body of the memory particle, and other means such as hard isolation or soft isolation are needed to process the location where CE occurs in memory 112.

[0233] Isolation Module 806: Implements the inherent hard isolation of the BIOS. For example, the existing bank isolation, row isolation, and cell isolation in the BIOS. In the embodiments of the present application, when increasing the memory refresh rate fails to reduce the frequency of memory CE occurrences, existing reliability technologies are used to reduce the occurrence of memory CEs by isolating banks, memory rows, or memory storage cells.

[0234] In addition to the above-mentioned methods, devices and electronic devices, an embodiment of the present application may also provide a computer program product, which includes computer program instructions. When the computer program instructions are executed by a processor, the processor executes the steps of the memory CE processing method of the various embodiments of the present application described in the "Method" section above. The computer program product can be written in any combination of one or more programming languages ​​to write computer program codes for performing the operations of the embodiments of the present application. The programming languages ​​include object-oriented programming languages ​​such as Java, C++, etc., and also include conventional procedural programming languages ​​such as "C" language or similar programming languages. The computer program code can be in source code form, object code form, executable file or some intermediate form. The computer program code can be executed entirely on the user computing device, partially on the user device, as an independent software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0235] In addition, an embodiment of the present application may also provide a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, causes the processor to perform the steps of the XXX method according to various embodiments of the present disclosure described in the "Method" section above. The computer-readable storage medium may adopt any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may, for example, include but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any combination of the above. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. It should be noted that the content contained in the computer-readable medium may be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0236] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0237] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0238] The basic principles of the present application have been described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, and effects mentioned in this application are merely illustrative and not restrictive, and it should not be assumed that these advantages, strengths, and effects are required of each embodiment of the present disclosure. In addition, the specific details disclosed above are merely illustrative and facilitating understanding, and are not restrictive. The above details do not limit the present disclosure to necessarily being implemented using the above specific details.

[0239] The block diagrams of the devices, devices, equipment, and systems involved in this disclosure are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, devices, equipment, and systems can be connected, arranged, or configured in any manner. Words such as "include," "comprise," "have," and the like are open-ended words, meaning "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or" and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0240] It should also be noted that in the apparatus, device, and method of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present disclosure.

[0241] The above description has been provided for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although a number of example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

[0242] It will be understood that the various numerical numbers involved in the embodiments of the present application are merely distinctions for the convenience of description and are not intended to limit the scope of the embodiments of the present application.

Claims

1. A memory CE processing method, characterized in that: Applied to a computing device, the method comprises: Get the information of correctable error CE generated on the memory; Determine a first value according to the CE information; the first value indicates the frequency of CE appearing in the memory during the process of the computing device refreshing the memory according to the first memory refresh frequency; Based on the first value, adjusting the first memory refresh frequency to a second memory refresh frequency, wherein the second memory refresh frequency is greater than the first memory refresh frequency; The memory is refreshed according to the second memory refresh frequency.

2. The method according to claim 1, characterized in that The determining a first value according to the CE information includes: Determine the number of CE occurrences during the statistical period; A first value is determined based on the number of times CE occurs within the statistical period.

3. The method according to claim 1, characterized in that: Adjusting the first memory refresh frequency to a second memory refresh frequency based on the first value includes: When the first value is greater than or equal to a preset threshold, the first memory refresh frequency is adjusted to a second memory refresh frequency; and the second memory refresh frequency is greater than the first memory refresh frequency.

4. The method according to claim 1, characterized in that: Before refreshing the memory according to the first memory refresh frequency, refreshing the memory according to the third memory refresh frequency, the method further includes: Determine a second value, where the second value indicates a frequency of CE occurring in the memory during a process in which the computing device refreshes the memory according to the third memory refresh frequency; The step of adjusting the first memory refresh frequency to a second memory refresh frequency according to the first value includes: When the second value is less than or equal to the first value, the first memory refresh frequency is adjusted to a second memory refresh frequency.

5. The method according to claim 4, characterized in that When the second value is greater than or equal to the first value, and the first memory refresh frequency is equal to the memory refresh frequency upper limit, the second memory refresh frequency is less than the first memory refresh frequency, or is equal to the third memory refresh frequency.

6. The method according to claim 5, characterized in that The refreshing of the memory according to the second memory refresh frequency includes: Isolate the location where the CE appears in the memory; After the isolation is successful, the memory is refreshed based on the second memory refresh frequency.

7. The method according to any one of claims 1 to 6, characterized in that: The step of adjusting the first memory refresh frequency to the second memory refresh frequency includes: Setting the processor to an unlocked mode so that a register in the processor is in a modified state, the register being used to store a memory refresh frequency of the memory; Modify the memory refresh frequency of the memory stored in the register to a second memory refresh frequency; The processor is configured to release the unlock mode so that the register is in a locked state.

8. A memory CE processing method, characterized in that: Applied to a computing device, the computing device includes an input / output system BIOS, a baseboard management controller BMC and a central processing unit CPU, the method includes: The CPU runs BIOS to obtain information about correctable errors CE generated on the memory from the CPU's memory controller; The BMC determines a first value based on the information of the CE obtained from the BIOS, and notifies the BIOS to adjust the first memory refresh frequency to the second memory refresh frequency according to the first value; the first value indicates the frequency of CE appearing in the memory during the process of the computing device refreshing the memory according to the first memory refresh frequency; the second memory refresh frequency is greater than the first memory refresh frequency; The memory controller in the CPU refreshes the memory based on the second memory refresh frequency.

9. A memory CE processing method, characterized in that: Applied to a baseboard management controller BMC, the method comprises: Get the information of correctable error CE generated on the memory; Determine a first value according to the CE information; the first value indicates the frequency of CE appearing in the memory during the process of the computing device refreshing the memory according to the first memory refresh frequency; Based on the first value, a memory refresh frequency adjustment notification is sent to the input / output system BIOS, so that the BIOS adjusts the first memory refresh frequency to a second memory refresh frequency, and the central processing unit CPU refreshes the memory according to the second memory refresh frequency; the second memory refresh frequency is greater than the first memory refresh frequency.

10. A computing device, characterized in that comprising a processor and a memory; wherein, The memory is used to store programs; The processor is used to execute the program stored in the memory. When the program stored in the memory is executed, the method described in any one of claims 1 to 7 is performed.

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