Magnetic storage element, storage device, and electronic apparatus

Abstract

A magnetic storage element according to one embodiment of the present disclosure comprises: a tunnel barrier layer; a storage layer provided to the tunnel barrier layer; and a voltage modulation enhancement layer provided on a surface of the storage layer on the side opposite to the tunnel barrier layer side.

Description

Magnetic memory element, memory device and electronic device

[0001] The present disclosure relates to a magnetic memory element, a memory device, and an electronic device.

[0002] The magnetic memory element has a magnetic tunnel junction (MTJ) structure in which a tunnel barrier layer is sandwiched between two magnetic layers. As materials, for example, MgO is generally used for the tunnel barrier layer, and materials containing at least one element selected from Fe, Co, Ni, and Mn are generally used for the memory layer and the reference layer.

[0003] A write operation of a voltage-driven magnetic memory element (for example, VC-MRAM: Voltage Controlled Magnetic Random Access Memory) requires high voltage-controlled magnetic anisotropy (VCMA) efficiency, and a structure is known in which a 5d electron heavy metal element (for example, Ir or Os) that enhances the VCMA efficiency is added to the interface between the tunnel barrier layer and the memory layer (for example, see Patent Document 1).

[0004] International Publication No. 2018 / 179961

[0005] However, in the above-described structure, although the VCMA efficiency is improved by adding heavy metal elements, the presence of non-magnetic elements at the interface between the tunnel barrier layer and the storage layer reduces the tunnel magnetoresistance ratio (TMR).

[0006] Therefore, the present disclosure provides a magnetic memory element, a memory device, and an electronic device that can improve VCMA efficiency and suppress a decrease in the tunneling magnetoresistance change rate.

[0007] A magnetic memory element according to one embodiment of the present disclosure includes a tunnel barrier layer, a memory layer provided on the tunnel barrier layer, and a voltage modulation enhancement layer provided on a surface of the memory layer opposite to the tunnel barrier layer side.

[0008] A memory device according to one embodiment of the present disclosure includes a magnetic memory element, the magnetic memory element having a tunnel barrier layer, a memory layer provided on the tunnel barrier layer, and a voltage modulation enhancement layer provided on a surface of the memory layer opposite to the tunnel barrier layer side.

[0009] An electronic device according to one embodiment of the present disclosure includes a storage device having a magnetic memory element, the magnetic memory element having a tunnel barrier layer, a memory layer provided on the tunnel barrier layer, and a voltage modulation enhancement layer provided on a surface of the memory layer opposite to the tunnel barrier layer.

[0010] FIG. 1 is a diagram showing a configuration example of a magnetic memory element according to a first embodiment; FIG. 2 is a diagram for explaining an example of a writing principle for the magnetic memory element according to the first embodiment; FIG. 3 is a diagram showing a modified example of the magnetic memory element according to the first embodiment; FIG. 4 is a diagram for explaining an example of the magnetic memory element according to the first embodiment; FIG. 5 is a graph showing the annealing temperature dependence of VCMA efficiency according to the first embodiment; FIG. 6 is a graph showing the annealing temperature dependence of saturation magnetization Ms according to the first embodiment; FIG. 7 is a graph showing the annealing temperature dependence of Half TMR according to the first embodiment; ＰＭＡ t ｆｒｅｅ 10 is a graph showing the annealing temperature dependence of perpendicular magnetic anisotropy energy K ＰＭＡ t ｆｒｅｅ10 is a graph showing the dependence of VCMA efficiency on the thickness of the inserted Ir film according to the first embodiment. FIG. 11 is a graph showing the dependence of saturation magnetization Ms on the thickness of the inserted Ir film according to the first embodiment. FIG. 12 is a graph showing the dependence of Half TMR on the thickness of the inserted Ir film according to the first embodiment. FIG. 13 is a diagram showing a configuration example of a magnetic memory element according to the second embodiment. FIG. 14 is a diagram showing a modified example of a magnetic memory element according to the second embodiment. FIG. 15 is a diagram showing a configuration example of a magnetic memory element according to the third embodiment. FIG. 16 is a diagram showing a modified example of a magnetic memory element according to the third embodiment. FIG. 17 is a diagram showing a configuration example of a magnetic memory element according to the fourth embodiment. FIG. 18 is a diagram showing a modified example of a magnetic memory element according to the fourth embodiment. FIG. 19 is a diagram showing a modified example of a magnetic memory element according to the fifth embodiment. FIG. 19 is a diagram showing a modified example of a magnetic memory element according to the fifth embodiment. FIG. 19 is a diagram showing a modified example of a magnetic memory element according to the sixth embodiment. FIG. 19 is a diagram showing a modified example of a magnetic memory element according to the sixth embodiment. FIG. 19 is a diagram showing a modified example of a magnetic memory element according to the seventh embodiment. FIG. 19 is a diagram showing a modified example of a magnetic memory element according to the seventh embodiment. FIG. 19 is a diagram showing a modified example of a magnetic memory element according to the eighth embodiment. FIG. 19 is a diagram showing a modified example of a magnetic memory element according to the eighth embodiment. FIG. 19 is a diagram showing a configuration example of a memory cell of the memory device according to the above-mentioned embodiments. Fig. 1 is a diagram showing an example of a flowchart of a write process of the storage device described above. Fig. 2 is a diagram showing an example of a timing chart of a write process of the storage device described above. Fig. 3 is a diagram showing an application example of the storage device described above. Fig. 4 is a diagram showing an example of the configuration of an imaging device according to an application example. Fig. 5 is a diagram showing an example of the configuration of a distance measuring device according to an application example.

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The embodiments include examples and modified examples. Note that the elements, devices, equipment, methods, etc. according to the present disclosure are not limited to the embodiments of the present disclosure. Furthermore, in the following embodiments, essentially identical components are designated by the same reference numerals, and redundant explanations will be omitted.

[0012] One or more of the following embodiments can be implemented independently. However, at least a portion of the following embodiments may be implemented in appropriate combination with at least a portion of another embodiment. These embodiments may include novel features that are different from one another. Therefore, each embodiment may contribute to solving different objectives or problems, and may achieve different effects. The effects of each embodiment are merely examples and are not intended to be limiting, and other effects may also be achieved.

[0013] The present disclosure will be described in the following order: 1. First Embodiment 1-1. Configuration example of magnetic memory element 1-2. Example of writing principle to magnetic memory element 1-3. Modified example of magnetic memory element 1-4. Example of magnetic memory element 2. Second Embodiment 2-1. Configuration example of magnetic memory element 2-2. Modified example of magnetic memory element 3. Third Embodiment 3-1. Configuration example of magnetic memory element 3-2. Modified example of magnetic memory element 4. Fourth Embodiment 4-1. Configuration example of magnetic memory element 4-2. Modified example of magnetic memory element 5. Fifth Embodiment 5-1. Configuration example of magnetic memory element 5-2. Modified example of magnetic memory element 6. Sixth Embodiment 6-1. Configuration example of magnetic memory element 6-2. Modified example of magnetic memory element 7. Seventh Embodiment 7-1. Configuration example of magnetic memory element 7-2. Modified example of magnetic memory element 8. Eighth Embodiment 8-1. 8. Configuration example of magnetic memory element 8-2. Modified example of magnetic memory element 9. Storage device according to each embodiment 9-1. Configuration example of storage device 9-2. Configuration example of memory cell 9-3. Example of write processing 9-3-1. Flowchart 9-3-2. Timing chart 10. Actions and effects according to each embodiment 11. Other embodiments 12. Application examples 12-1. Various devices 12-2. Imaging device 12-3. Distance measuring device 13. Supplementary notes

[0014] <1. First embodiment> <1-1. Configuration example of magnetic memory element> A configuration example of a magnetic memory element 1 according to this embodiment will be described with reference to Fig. 1. Fig. 1 is a diagram showing a configuration example of a magnetic memory element 1 according to this embodiment.

[0015] 1, the magnetic memory element 1 according to this embodiment includes an underlayer 10, a reference layer 20, a tunnel barrier layer 30, a memory layer 40, a voltage modulation enhancement layer 50, and a cap layer 60. In the example of Fig. 1, the underlayer 10, the reference layer 20, the tunnel barrier layer 30, the memory layer 40, the voltage modulation enhancement layer 50, and the cap layer 60 are stacked in this order to form the magnetic memory element 1. The magnetic memory element 1 is also referred to as, for example, a magnetoresistive element (magnetoresistive effect element).

[0016] The magnetic memory element 1 is provided with a bottom electrode 70 and a top electrode 80. The bottom electrode 70 and the top electrode 80 are arranged to sandwich the magnetic memory element 1. The bottom electrode 70 and the top electrode 80 are conductive layers for supplying a voltage to the stack of the magnetic memory element 1. A voltage is supplied to the stack including the reference layer 20, the tunnel barrier layer 30, the memory layer 40, and the voltage modulation enhancement layer 50 via these conductive layers. The magnetic memory element 1 may include the bottom electrode 70 and the top electrode 80.

[0017] FIG. 1 also shows an XYZ coordinate system. The X-axis direction and Y-axis direction (XY plane direction) correspond to the surface direction of the layer, and the Z-axis direction (vertical direction) corresponds to the thickness direction of the layer. In the example of FIG. 1, multiple layers in a stacked state are adjacent, and adjacent layers are in surface contact. Note that the word "layer" may be interpreted as meaning a film, and "layer" and "film" may be interpreted appropriately as long as there is no contradiction.

[0018] The underlayer 10 is a layer that improves flatness, promotes crystal growth, and prevents interdiffusion of elements. The underlayer 10 may contain at least one element selected from, for example, Hf, Ti, Ta, Ru, Pt, Mo, W, V, Ni, Co, Cr, Fe, B, and C. The underlayer 10 may also be formed by laminating metals or alloys containing the aforementioned elements.

[0019] The reference layer 20 is a ferromagnetic layer that has magnetic anisotropy and an invariable magnetization direction. For example, the magnetization direction of this reference layer 20 is controlled to be perpendicular to the layer surface (film surface) due to the magnetic anisotropy. The reference layer 20 may contain, for example, at least one element selected from Fe, Co, Ni, and Mn. The reference layer 20 may also contain, for example, at least one element selected from B, C, Mg, Y, Si, Al, Ta, Zr, Hf, Pt, Pd, and rare earth elements for adjusting the saturation magnetization, controlling the magnetocrystalline anisotropy energy, and adjusting the crystal grain size and inter-crystal grain coupling. The reference layer 20 is also referred to as, for example, a fixed layer or a magnetization fixed layer.

[0020] The tunnel barrier layer 30 is adjacent to the reference layer 20 and the memory layer 40 and is provided between the reference layer 20 and the memory layer 40. This tunnel barrier layer 30 imparts a voltage-controlled magnetic anisotropy effect, for example, by applying an electric field to the memory layer 40. The tunnel barrier layer 30 includes, for example, MgO. In addition to MgO, the tunnel barrier layer 30 may include at least one of an oxide having at least one element selected from Mg, Ca, Li, Si, Al, Sr, Zr, Hf, Ti, Zn, Sc, La, Ta, Eu, Cu, Ba, Mo, W, V, Y, Ni, Co, Mn, Cr, Fe, B, and C, a nitride having at least one of these elements, and a fluoride having at least one of these elements. The tunnel barrier layer 30 may also be configured by stacking at least two or more elements selected from the above-mentioned element group. The tunnel barrier layer 30 may also include, for example, a single crystal oriented in the (001) plane or a polycrystal preferentially oriented in the (001) plane. The tunnel barrier layer 30 is also referred to as, for example, a barrier layer or an insulating layer.

[0021] The memory layer 40 is a ferromagnetic layer having magnetic anisotropy and a variable magnetization direction. For example, the magnetization direction of this memory layer 40 is controlled perpendicular to the layer surface (film surface) by the magnetic anisotropy. For example, the memory layer 40 is a layer having a VCMA effect. The memory layer 40 may contain at least one element selected from Fe, Co, Ni, and Mn. Furthermore, the memory layer 40 may contain at least one element selected from Hf, Zr, Ti, Ta, W, Au, Mo, Ru, Pd, Y, V, Sc, Gd, Tb, La, Mg, Al, Ag, Cu, Cr, B, C, Si, Ga, and Ge to increase VCMA efficiency, control interface magnetic anisotropy energy, adjust saturation magnetization, control magnetocrystalline anisotropy energy, and adjust crystal grain size and inter-crystal grain bonding. The memory layer 40 may also be configured to have, for example, a body-centered cubic lattice (bcc) structure. The memory layer 40 may also include, for example, a single crystal oriented in the (001) plane or a polycrystal preferentially oriented in the (001) plane. The memory layer 40 is also referred to as, for example, a free layer.

[0022] Here, a state in which the magnetization direction of the memory layer 40 is the same as that of the reference layer 20 is called a parallel state, and a state in which the magnetization direction of the memory layer 40 is different from that of the reference layer 20 is called an antiparallel state. The magnetic memory element 1 is in a low resistance state when in the parallel state, and in a high resistance state when in the antiparallel state. The magnetization direction of the memory layer 40 can be changed by applying a voltage to the magnetic memory element 1.

[0023] By adjusting the thickness (film thickness) of the memory layer 40 to, for example, 3.0 nm or less, the magnetization direction is controlled perpendicular to the layer surface (film surface) by interfacial magnetic anisotropy during standby. Furthermore, in order to increase the anisotropy modulation effect due to voltage and improve controllability during rewriting, the thickness of the memory layer 40 is preferably 1.5 nm or less. Furthermore, in order to maintain quality, the thickness of the memory layer 40 is preferably 0.26 nm or more. The magnetization direction of at least a portion of the memory layer 40 changes, for example, by application of a voltage pulse.

[0024] The voltage modulation enhancement layer 50 improves the VCMA efficiency (enhances the VCMA efficiency) and controls the interfacial magnetic anisotropy energy. The voltage modulation enhancement layer 50 is provided adjacent to the memory layer 40 on the surface of the memory layer 40 opposite the tunnel barrier layer 30 side, and enhances (increases) the voltage modulation efficiency, such as the VCMA efficiency. The voltage modulation enhancement layer 50 may contain at least one element selected from the group consisting of Ir, Os, Pt, Rh, Hf, Zr, Ti, Ta, W, Re, Au, Mo, Ru, Pd, Y, V, Sc, Gd, Tb, La, Mg, Al, Ag, Cu, Cr, Co, Fe, and Ni.

[0025] The VCMA efficiency is enhanced by adjusting the thickness (film thickness) of the voltage modulation enhancement layer 50 to, for example, less than 0.5 nm. From the viewpoint of enhancing the VCMA efficiency, the thickness (film thickness) of the voltage modulation enhancement layer 50 is preferably 0.3 nm or less.

[0026] The cap layer 60 is a layer that prevents an increase in the interface magnetic anisotropy energy with the storage layer 40 and interdiffusion of elements. The cap layer 60 acts as an interlayer film, preventing, for example, the diffusion of metals from wiring members. The cap layer 60 may contain at least one element selected from the group consisting of Mg, Ca, Li, Si, Al, Sr, Zr, Hf, Ti, Zn, Sc, La, Ta, Eu, Cu, Ba, Mo, W, V, Y, Ni, Co, Mn, Cr, Fe, B, and C. The cap layer 60 may also contain at least one of an oxide, a nitride, and a fluoride containing an element selected from the aforementioned group of elements. For example, the cap layer 60 may contain MgO.

[0027] The magnetic memory element 1 may have layers other than the aforementioned layers, such as a magnetic field generation layer (magnetic field generating layer) that functions as a bias layer. The magnetic field generation layer generates a magnetic field in an in-plane direction (horizontal direction), for example. The in-plane direction is, for example, a direction perpendicular to the stacking direction (thickness direction) of the aforementioned layers. Furthermore, a method other than the magnetic field generation layer may be used to generate the magnetic field. For example, a method of providing a magnet layer above or below the magnetic memory element 1 or a method of arranging a permanent magnet around the magnetic memory element 1 may be used.

[0028] The various layers described above may be fabricated by, for example, a physical vapor deposition (PVD) method such as sputtering, ion beam deposition, or vacuum evaporation, or a chemical vapor deposition (CVD) method such as atomic layer deposition (ALD). These layers may also be patterned by, for example, reactive ion etching (RIE) or ion milling. It is preferable that the various layers are successively formed in a vacuum apparatus, and then patterned.

[0029] Data (e.g., 0 or 1) is written to the memory cell 11 by switching the resistance state (resistance value) of the magnetic memory element 1 between a low resistance state (low resistance value) and a high resistance state (high resistance value). The low resistance state is a state in which the magnetization of the reference layer 20 and the magnetization of the memory layer 40 are parallel to each other, and the high resistance state is a state in which the magnetization of the reference layer 20 and the magnetization of the memory layer 40 are antiparallel to each other. For example, by reversing the magnetization direction of the memory layer 40 between the positive direction of the Z-axis and the negative direction of the Z-axis, the resistance state of the magnetic memory element 1 can be switched between a low resistance state and a high resistance state. For example, data corresponding to the low resistance state is 0, and data corresponding to the high resistance state is 1. The magnetic memory element 1 is, for example, an MTJ element that can reverse the magnetization of the memory layer 40 by utilizing the VCMA effect.

[0030] As mentioned above, the basic structure of the magnetic memory element 1 is a sandwich structure consisting of two magnetic layers made of thin magnetic materials sandwiching a non-magnetic thin insulating film. This structure is called a magnetic tunnel junction (MTJ). Because the non-magnetic thin films are very thin, only a few nanometers thick, a tunnel current flows when a voltage is applied to both ends of the element. The magnitude of this tunnel current is characterized by its dependence on the relative angle between the magnetizations of the two magnetic layers. This is called the tunnel magnetoresistance (TMR) effect. In MRAM, the magnetization of one of the two magnetic layers (reference layer 20) is fixed, and the magnetization of the other magnetic layer (storage layer 40) is controlled by an external field. Examples of external fields used to control the magnetization direction include methods that utilize magnetic anisotropy control using voltage. The TMR effect is used to read the state.

[0031] <1-2. Example of the principle of writing to a magnetic memory element> An example of the principle of writing to the magnetic memory element 1 according to this embodiment will be described with reference to Fig. 2. Fig. 2 is a diagram for explaining an example of the principle of writing to the magnetic memory element 1 according to this embodiment. In the example of Fig. 2, (a) standby, (b) during a write operation, and (c) after a write operation are shown, with the upper row showing changes in applied voltage, the middle row showing changes in magnetic energy A1, and the lower row showing changes in the magnetization direction.

[0032] As shown in Figure 2, (a) during standby (timing T1 related to applied voltage), magnetic energy A1 is most stable in two directions (initial direction S and reverse direction E) for the magnetization direction, and because there is an energy barrier A2 at the angle between these two directions, non-volatile data retention is possible even when the voltage is turned off. (b) During a write operation (timing T2 related to applied voltage), the energy barrier A2 is removed by voltage modulation of magnetic anisotropy (VCMA) under the application of an in-plane magnetic field Hext, and the magnetization of the storage layer 40 begins to precess with the applied magnetic field direction as the precession axis. (c) After the write operation (timing T3 related to applied voltage), the voltage is turned off when the magnetization faces the reverse direction E, completing the write operation. The in-plane magnetic field Hext is applied to the magnetic storage element 1 by, for example, a magnetic field generation layer.

[0033] In the example of FIG. 2, for convenience of explanation, an XYZ coordinate system (with the Y axis perpendicular to the plane of the paper) is shown. The X-axis direction and the Y-axis direction correspond to the in-plane directions of the layers of the magnetic memory element 1 having the aforementioned stacked structure. The X-axis direction, the Y-axis direction, and the XY plane direction may also be referred to as horizontal directions. The Z-axis direction corresponds to the direction perpendicular to the in-plane directions of the layers of the magnetic memory element 1 (stacking direction). The Z-axis direction may also be referred to as the vertical direction.

[0034] More specifically, Figure 2 illustrates the principle of magnetization reversal using the VCMA effect. The curves in the middle of Figure 2 show the relationship between the magnetization direction and magnetic energy A1. The (a) standby magnetic energy A1 curve indicates that the two valleys, where the magnetization direction is perpendicular to the layer surface (film surface), are the most stable in terms of energy. The peak between them represents the in-plane energy at which the magnetization becomes energetically unstable. This peak acts as an energy barrier A2, providing nonvolatility for retaining information during standby. The greater the perpendicular magnetic anisotropy induced at the interface between the tunnel barrier layer 30 and the storage layer 40 in the MTJ film, the more stable the perpendicular energy becomes, deepening the valley. This results in a higher peak of the energy barrier A2, improving standby data retention. However, since a write operation requires enough energy to overcome this peak, it is generally known that there is a trade-off between data retention and write energy.

[0035] In the VCMA effect, the magnetic anisotropy is modulated by applying a voltage, making it possible to change the height of the mountain (energy barrier A2) in the magnetic energy A1, as in (b) during a write operation. If an in-plane magnetic field is applied at this time, the magnetization precesses around the axis of the magnetic field direction. By cutting off the voltage at the right time to match this precession cycle, the energy barrier A2 is restored, and the magnetization is stabilized in the intended magnetization direction, completing the write operation. Writing techniques using the VCMA effect eliminate the commonly known trade-off between retention and write energy, enabling high-speed reversal and low power consumption. An important factor for this is the VCMA efficiency, which is an index of the efficiency of voltage modulation of the height of the energy barrier A2.

[0036] To improve this VCMA efficiency, it is effective to provide a voltage modulation enhancement layer 50 in the magnetic memory element 1. However, if the voltage modulation enhancement layer 50 is inserted between the tunnel barrier layer 30 and the memory layer 40, the TMR (tunneling magnetoresistance change rate) will decrease. Therefore, by providing the voltage modulation enhancement layer 50 on the surface of the memory layer 40 opposite to the tunnel barrier layer 30 side, it is possible to improve the VCMA efficiency while suppressing the decrease in TMR. Therefore, it is possible to improve the VCMA efficiency and suppress the decrease in the tunneling magnetoresistance change rate.

[0037] In more detail, for example, if a 5d electron heavy metal element (e.g., Ir or Os) that enhances VCMA efficiency is added to the interface between the tunnel barrier layer 30 and the memory layer 40 and a voltage modulation enhancement layer 50 is provided between the tunnel barrier layer 30 and the memory layer 40, the VCMA efficiency is improved by the addition of the heavy metal element, but the TMR is reduced due to the presence of a nonmagnetic element at the interface between the tunnel barrier layer 30 and the memory layer 40. Therefore, as described above, by providing the voltage modulation enhancement layer 50 on the surface of the memory layer 40 opposite to the tunnel barrier layer 30 side, it is possible to suppress the presence of a nonmagnetic element at the interface between the tunnel barrier layer 30 and the memory layer 40, and therefore it is possible to suppress the reduction in TMR while improving the VCMA efficiency.

[0038] <1-3. Modified Example of Magnetic Memory Element> A modified example of the magnetic memory element 1 according to this embodiment will be described with reference to Fig. 3. Fig. 3 is a diagram showing a modified example of the magnetic memory element 1 according to this embodiment.

[0039] As shown in Fig. 3, in the modified example of the magnetic memory element 1 according to this embodiment, the stacking order of the reference layer 20, the tunnel barrier layer 30, the memory layer 40, and the voltage modulation enhancement layer 50 is different from that of the configuration of Fig. 1. That is, the voltage modulation enhancement layer 50, the memory layer 40, the tunnel barrier layer 30, and the reference layer 20 are stacked on the underlayer 10 in the order shown. As with the configuration of Fig. 1, the modified configuration of Fig. 3 can also achieve improved VCMA efficiency and suppressed reduction in the tunnel magnetoresistance change rate. Note that it is possible to select an appropriate structure depending on the convenience of the film formation process, element characteristics, and the like.

[0040] <1-4. Examples of Magnetic Memory Element> Examples of the magnetic memory element 1 according to this embodiment will be described with reference to FIGS. 4 to 12. FIG.

[0041] FIG. 4 is a diagram for explaining an example of the magnetic memory element 1 according to this embodiment. FIG. 4 shows a schematic configuration of an experimental sample according to the example. As shown in FIG. 4, the underlayer 10 is made of a TaB layer, and the reference layer 20 is made of CoFeB ((Co ５０ Fe ５０ ) ８０ B ２０ ), the tunnel barrier layer 30 is made of an MgO layer, and the memory layer 40 is made of CoFeB ((Co ５０ Fe ５０ ) ８０ B ２０ ), the voltage modulation enhancement layer 50 is made of material X, and the cap layer 60 is made of an MgO layer. The lower electrode 70 is made of a Ta layer, a Pt layer, and a Ru layer stacked in the order listed, and the upper electrode 80 is made of a Ru layer, a Ta layer, and a Ru layer stacked in the order listed. The reference layer 20 has a thickness of 3 nm, the tunnel barrier layer 30 has a thickness of 2 nm, the memory layer 40 has a thickness of 1 nm, the voltage modulation enhancement layer 50 has a thickness of t nm, and the cap layer 60 has a thickness of 1 nm.

[0042] In the example, the resistance (area resistance) RA of the tunnel barrier layer 30 is, for example, 10 Ωμm ２ Resistance RA is, for example, resistance RL when the magnetization directions of reference layer 20 and memory layer 40 are parallel. For use in a voltage-controlled MRAM, it is desirable that memory layer 40 have a thickness of 1.5 nm or less.

[0043] (Annealing Temperature Dependence) FIG. 5 is a graph showing the annealing temperature dependence of the VCMA efficiency (fJ / Vm) according to this embodiment. FIG. 5 shows the results of measuring the VCMA efficiency for each sample, after forming multiple samples in which the material X of the voltage modulation enhancement layer 50 in the magnetic memory element 1 configured as shown in FIG. 4 was changed, and the heat treatment (annealing) temperature conditions were changed. In the example of FIG. 5 , W / O indicates a sample without a voltage modulation enhancement layer 50, and an element symbol indicates a sample with a voltage modulation enhancement layer 50 containing that element (material X). The elements shown are Mo, Mg, Ti, Ru, Ir, TaB, Cr, and Ta. The thickness of the voltage modulation enhancement layer 50 is fixed at t = 0.2 nm in all cases.

[0044] As shown in FIG. 5 , the sample (W / O) without the voltage modulation enhancement layer 50 exhibited a VCMA efficiency of approximately 55 fJ / Vm after annealing at 300° C., whereas the sample using Ir as the voltage modulation enhancement layer 50 exhibited an increase in VCMA efficiency of 90 fJ / Vm after annealing at 300° C. Similarly, the VCMA efficiency after annealing at 200° C. or 250° C. also increased. These results confirmed that inserting the voltage modulation enhancement layer 50 at the interface of the memory layer 40 opposite the tunnel barrier layer 30 increased the VCMA efficiency. A similar increase was also observed in samples using Mo as the voltage modulation enhancement layer 50, and under certain annealing conditions, it was also observed in samples using Ru or Ta as the voltage modulation enhancement layer 50. It should be noted that the increase in VCMA efficiency with increasing annealing temperature for the sample using Ir as the voltage modulation enhancement layer 50 is thought to be due to the diffusion of Ir elements into the memory layer 40.

[0045] FIG. 6 is a graph showing the annealing temperature dependence of the saturation magnetization Ms (emu / cc) according to the present embodiment. Unlike the example, when a voltage modulation enhancement layer 50 made of a nonmagnetic material such as Ir is inserted between the tunnel barrier layer 30 and the storage layer 40 (comparative example), the saturation magnetization Ms and the magnetoresistance ratio TMR may decrease. To avoid this decrease, in the example, the voltage modulation enhancement layer 50 is provided at the interface of the storage layer 40 on the side opposite to the tunnel barrier layer 30. As shown in FIG. 6 , it was confirmed that the saturation magnetization Ms does not decrease significantly in samples using Ir or Mg as the voltage modulation enhancement layer 50 compared to samples (W / O) without the voltage modulation enhancement layer 50. It was also confirmed that the saturation magnetization Ms does not decrease significantly even when the annealing temperature is increased.

[0046] 7 is a graph showing the annealing temperature dependence of Half TMR (%) according to this embodiment. This graph shows the annealing temperature dependence of Half TMR (Half-TMR), calculated from the resistance change rate when the magnetization direction of the reference layer 20 is parallel and the magnetization direction of the storage layer 40 is orthogonal. As shown in FIG. 7 , in all samples provided with the voltage modulation enhancement layer 50, even when the voltage modulation enhancement layer 50 is provided, the Half TMR (%) showed a change similar to that of the sample (W / O) without the voltage modulation enhancement layer 50, and it was confirmed that there was almost no decrease compared to the sample (W / O) without the voltage modulation enhancement layer 50.

[0047] FIG. 8 shows the perpendicular magnetic anisotropy energy K ＰＭＡ t ｆｒｅｅ (mJ / m ２ 8 is a graph showing the annealing temperature dependence of the perpendicular magnetic anisotropy energy K ＰＭＡ t ｆｒｅｅ It was confirmed that the perpendicular magnetic anisotropy increased by about 2 times. Also, an increase in perpendicular magnetic anisotropy was confirmed in the sample using Cr as the voltage modulation enhancement layer 50. By providing the voltage modulation enhancement layer 50 at the interface on the side opposite to the tunnel barrier layer 30 side in the storage layer 40, the K ＰＭＡ t ｆｒｅｅIt was confirmed that the magnetic anisotropy that facilitates perpendicular alignment was not lost.

[0048] (Ir Insertion Film Thickness Dependence) FIG. 9 shows the perpendicular magnetic anisotropy energy K ＰＭＡ t ｆｒｅｅ (mJ / m ２ 9 is a graph showing the dependence of the voltage modulation enhancement layer 50 on the thickness of the inserted Ir film. In the example of FIG. 9, the material of the voltage modulation enhancement layer 50 is fixed to Ir, and the different types of plotted lines correspond to the different annealing temperature conditions (T ａｎ = 200°C, 250°C, 300°C). The Ir insertion film thickness is the thickness of the voltage modulation enhancement layer 50 containing Ir. In other words, a sample with an Ir insertion film thickness (thickness of the voltage modulation enhancement layer 50) of 0 nm is a sample (W / O) without the voltage modulation enhancement layer 50.

[0049] As shown in FIG. 9, the perpendicular magnetic anisotropy energy K ＰＭＡ t ｆｒｅｅ When the thickness of the Ir insertion film is 0.5 nm, the perpendicular magnetic anisotropy energy K ＰＭＡ t ｆｒｅｅ is increased compared to when the thickness of the Ir insertion film is 0.0 nm. Therefore, by making the thickness of the Ir insertion film at least less than 0.5 nm, a high perpendicular magnetic anisotropy energy K ＰＭＡ t ｆｒｅｅ More preferably, by setting the thickness of the Ir insertion film to 0.3 nm or less, a higher perpendicular magnetic anisotropy energy K ＰＭＡ t ｆｒｅｅ can be obtained.

[0050] Here, in the magnetic memory element 1, high perpendicular magnetic anisotropy energy K ＰＭＡ t ｆｒｅｅ That is, high perpendicular magnetic anisotropy is desired. High perpendicular magnetic anisotropy stabilizes the magnetization direction against, for example, thermal fluctuations. By achieving high magnetic anisotropy, it is possible to obtain good thermal stability even when the storage section (for example, memory cell) is miniaturized. This makes it possible to improve the storage density of a storage device, for example.

[0051] 10 is a graph showing the dependency of the VCMA efficiency (fJ / Vm) on the thickness of the inserted Ir film according to this embodiment. In the example of FIG. 10, the material of the voltage modulation enhancement layer 50 is fixed to Ir, as in FIG. 9, and the different types of plotted lines correspond to the different annealing temperature conditions (T ａｎ = 200°C, 250°C, 300°C).

[0052] As shown in Figure 10, when the Ir insertion film thickness is 0.5 nm, the VCMA efficiency is similar to or lower than when the Ir insertion film thickness is 0.0 nm. On the other hand, when the Ir insertion film thickness is less than 0.5 nm, the VCMA efficiency is increased compared to when the Ir insertion film thickness is 0.0 nm. Therefore, by setting the Ir insertion film thickness to at least less than 0.5 nm, a high VCMA efficiency enhancement effect can be obtained. More preferably, by setting the Ir insertion film thickness to 0.3 nm or less, a higher VCMA efficiency enhancement effect can be obtained.

[0053] 11 is a graph showing the dependence of the saturation magnetization MS (emu / cc) on the thickness of the inserted Ir film according to this embodiment. In the example of FIG. 11, the material of the voltage modulation enhancement layer 50 is fixed to Ir, as in FIGS. 9 and 10, and the different types of plotted lines correspond to the different annealing temperature conditions (T ａｎ = 200°C, 250°C, 300°C).

[0054] 11, when the Ir insertion film thickness is 0.5 nm, the saturation magnetization Ms is lower than when the Ir insertion film thickness is 0.0 nm, and when the Ir insertion film thickness is 0.2 or 0.3 nm, it is approximately the same as when the Ir insertion film thickness is 0.0 nm. Therefore, by setting the Ir insertion film thickness to at least less than 0.5 nm, it is possible to suppress the decrease in saturation magnetization Ms. More preferably, by setting the Ir film thickness to 0.3 nm or less, the decrease in saturation magnetization Ms can be further suppressed.

[0055] 12 is a graph showing the dependence of the half TMR (%) on the thickness of the inserted Ir film according to this embodiment. In the example of FIG. 12, similarly to FIGS. 9 to 11, the material of the voltage modulation enhancement layer 50 is fixed to Ir, and the different types of plotted lines correspond to the different annealing temperature conditions (T ａｎ = 200°C, 250°C, 300°C).

[0056] As shown in Figure 12, when the Ir insertion film thickness is 0.5 nm, the TMR is lower than when the Ir insertion film thickness is 0.0 nm, and when the Ir insertion film thickness is 0.2 or 0.3 nm, the TMR is approximately the same as when the Ir insertion film thickness is 0.0 nm. Therefore, by setting the Ir insertion film thickness to at least less than 0.5 nm, it is possible to suppress the decrease in Half TMR. More preferably, by setting the Ir film thickness to 0.3 nm or less, the decrease in Half TMR can be further suppressed.

[0057] <2. Second embodiment> <2-1. Configuration example of magnetic memory element> A configuration example of a magnetic memory element 1 according to this embodiment will be described with reference to Fig. 13. Fig. 13 is a diagram showing a configuration example of a magnetic memory element 1 according to this embodiment. This embodiment is basically the same as the first embodiment (see Fig. 1), but differences between them will be described.

[0058] 13 , the magnetic memory element 1 according to this embodiment includes a tunnel barrier layer 30, a memory layer 40, and a voltage modulation enhancement layer 50. In the example of FIG. 13 , the tunnel barrier layer 30, the memory layer 40, and the voltage modulation enhancement layer 50 are stacked in this order to form the magnetic memory element 1. The magnetic memory element 1 is provided with a lower electrode 70 and an upper electrode 80. As with the configuration of FIG. 1 , the configuration of this embodiment shown in FIG. 13 can also achieve an improvement in VCMA efficiency and suppression of a decrease in the tunnel magnetoresistance change rate.

[0059] <2-2. Modified Example of Magnetic Memory Element> A modified example of the magnetic memory element 1 according to this embodiment will be described with reference to Fig. 14. Fig. 14 is a diagram showing a modified example of the magnetic memory element 1 according to this embodiment.

[0060] As shown in Fig. 14, in the modified example of the magnetic memory element 1 according to this embodiment, the stacking order of the tunnel barrier layer 30, the memory layer 40, and the voltage modulation enhancement layer 50 is different from that of the configuration of Fig. 13. That is, the voltage modulation enhancement layer 50, the memory layer 40, and the tunnel barrier layer 30 are stacked on the lower electrode 70 in the order shown. As with the configuration of Fig. 13, the modified configuration of Fig. 14 can also achieve improvement in VCMA efficiency and suppression of a decrease in the tunnel magnetoresistance change rate. Note that it is possible to select an appropriate structure in accordance with convenience of the film formation process, element characteristics, and the like.

[0061] <3. Third embodiment> <3-1. Configuration example of magnetic memory element> A configuration example of the magnetic memory element 1 according to this embodiment will be described with reference to Fig. 15. Fig. 15 is a diagram showing a configuration example of the magnetic memory element 1 according to this embodiment. This embodiment is basically the same as the first embodiment (see Fig. 1), but differences between them will be described.

[0062] 15 , the magnetic memory element 1 according to this embodiment includes a tunnel barrier layer 30, a memory layer 40, a voltage modulation enhancement layer 50, and a cap layer 60. In the example of FIG. 15 , the tunnel barrier layer 30, the memory layer 40, the voltage modulation enhancement layer 50, and the cap layer 60 are stacked in this order to form the magnetic memory element 1. The magnetic memory element 1 is provided with a lower electrode 70 and an upper electrode 80. As with the configuration of FIG. 1 , the configuration of this embodiment shown in FIG. 15 can also achieve an improvement in VCMA efficiency and a suppression of a decrease in the tunnel magnetoresistance change rate.

[0063] <3-2. Modified Example of Magnetic Memory Element> A modified example of the magnetic memory element 1 according to this embodiment will be described with reference to Fig. 16. Fig. 16 is a diagram showing a modified example of the magnetic memory element 1 according to this embodiment.

[0064] As shown in Fig. 16, in the modified example of the magnetic memory element 1 according to this embodiment, the stacking order of the tunnel barrier layer 30, memory layer 40, voltage modulation enhancement layer 50, and cap layer 60 is different from that of the configuration of Fig. 15. That is, the cap layer 60, voltage modulation enhancement layer 50, memory layer 40, and tunnel barrier layer 30 are stacked on the lower electrode 70 in the order shown. As with the configuration of Fig. 15, the modified configuration of Fig. 16 can also achieve improvement in VCMA efficiency and suppression of a decrease in the tunnel magnetoresistance change rate. Note that it is possible to select an appropriate structure in accordance with convenience of the film formation process, element characteristics, and the like.

[0065] <4. Fourth embodiment> <4-1. Configuration example of magnetic memory element> A configuration example of a magnetic memory element 1 according to this embodiment will be described with reference to Fig. 17. Fig. 17 is a diagram showing a configuration example of a magnetic memory element 1 according to this embodiment. This embodiment is basically the same as the first embodiment (see Fig. 1), but differences between them will be described.

[0066] 17 , the magnetic memory element 1 according to this embodiment includes an underlayer 10, a fixed layer 21, a spacer layer 22, a reference layer 20, a tunnel barrier layer 30, a memory layer 40, a voltage modulation enhancement layer 50, and a cap layer 60. In the example of FIG. 17 , the underlayer 10, the fixed layer 21, the spacer layer 22, the reference layer 20, the tunnel barrier layer 30, the memory layer 40, the voltage modulation enhancement layer 50, and the cap layer 60 are stacked in this order to form the magnetic memory element 1. The magnetic memory element 1 is provided with a lower electrode 70 and an upper electrode 80. As with the configuration of FIG. 1 , the configuration of this embodiment shown in FIG. 17 can also achieve improved VCMA efficiency and suppression of a decrease in the tunnel magnetoresistance change rate.

[0067] The fixed layer 21 is a ferromagnetic layer having magnetic anisotropy and a fixed magnetization direction. The magnetization direction of this fixed layer 21 is controlled perpendicular to the layer surface (film surface) by the magnetic anisotropy. The magnetization direction of the fixed layer 21 is antiparallel to the magnetization direction of the reference layer 20. Therefore, the fixed layer 21 has the function of canceling out the leakage magnetic field applied from the reference layer 20 to the storage layer 40. The fixed layer 21 may contain at least one element selected from, for example, Co, Fe, Ni, Pt, Pd, Cr, Ir, Sm, and Nd. Furthermore, when the fixed layer 21 contains two or more elements selected from the aforementioned element group, the elements may be alloyed together, or may be formed of an artificial lattice such as CoPt (Co / Pt), CoNi (Co / Ni), or CoPd (Co / Pd).

[0068] The spacer layer 22 is interposed between the fixed layer 21 and the reference layer 20 and serves to separate the fixed layer 21 and the reference layer 20. The spacer layer 22 is, for example, a layer for magnetically coupling the magnetization directions of the fixed layer 21 and the reference layer 20 in antiparallel relation. The spacer layer 22 may contain, for example, at least one element selected from Ru, Ir, Rh, and Re. The spacer layer 22 is also referred to as, for example, a separation layer.

[0069] <4-2. Modified Example of Magnetic Memory Element> A modified example of the magnetic memory element 1 according to this embodiment will be described with reference to Fig. 18. Fig. 18 is a diagram showing a modified example of the magnetic memory element 1 according to this embodiment.

[0070] As shown in Figure 18, in the modified example of the magnetic memory element 1 according to this embodiment, the stacking order of the fixed layer 21, spacer layer 22, reference layer 20, tunnel barrier layer 30, memory layer 40, and voltage modulation enhancement layer 50 is different from the configuration in Figure 17. That is, the voltage modulation enhancement layer 50, memory layer 40, tunnel barrier layer 30, reference layer 20, spacer layer 22, and fixed layer 21 are stacked on the underlayer 10 in the order shown. As with the configuration in Figure 17, the modified configuration in Figure 18 can also achieve improved VCMA efficiency and suppressed reduction in the tunnel magnetoresistance change rate. Note that it is possible to select an appropriate structure depending on the convenience of the film formation process, element characteristics, and the like.

[0071] <5. Fifth embodiment> <5-1. Configuration example of magnetic memory element> A configuration example of a magnetic memory element 1 according to this embodiment will be described with reference to Fig. 19. Fig. 19 is a diagram showing a configuration example of a magnetic memory element 1 according to this embodiment. This embodiment is basically the same as the second embodiment (see Fig. 13), but differences therebetween will be described.

[0072] As shown in FIG. 19 , in the magnetic memory element 1 according to this embodiment, the memory layer 40 is composed of a first memory layer 41 and a second memory layer 42. In the example of FIG. 19 , the first memory layer 41 and the second memory layer 42 are stacked on the tunnel barrier layer 30 in the order shown. Specifically, the first memory layer 41 is located closer to the tunnel barrier layer 30 than the second memory layer 42, and the voltage modulation enhancement layer 50 is provided on the surface of the second memory layer 42 opposite to the first memory layer 41 side. The first memory layer 41 and the second memory layer 42 are magnetically coupled. As with the configuration of FIG. 13 , the configuration of this embodiment shown in FIG. 19 can also achieve improved VCMA efficiency and suppressed reduction in the tunnel magnetoresistance change rate.

[0073] <5-2. Modified Example of Magnetic Memory Element> A modified example of the magnetic memory element 1 according to this embodiment will be described with reference to Fig. 20. Fig. 20 is a diagram showing a modified example of the magnetic memory element 1 according to this embodiment.

[0074] As shown in Fig. 20 , in the modified example of the magnetic memory element 1 according to this embodiment, the stacking order of the tunnel barrier layer 30, the first memory layer 41, the second memory layer 42, and the voltage modulation enhancement layer 50 is different from that of the configuration of Fig. 19 . That is, the voltage modulation enhancement layer 50, the second memory layer 42, the first memory layer 41, and the tunnel barrier layer 30 are stacked on the lower electrode 70 in the order shown. As with the configuration of Fig. 19 , the modified configuration of Fig. 20 can also achieve improvement in VCMA efficiency and suppression of a decrease in the tunnel magnetoresistance change rate. Note that it is possible to select an appropriate structure in accordance with convenience of the film formation process, element characteristics, and the like.

[0075] In the above-described embodiment, the memory layer 40 is configured of two layers, the first memory layer 41 and the second memory layer 42. However, the number of layers configuring the memory layer 40 is not particularly limited, and may be three or more layers. Each layer may contain the same element or different elements. The element content (concentration) of each layer may be the same or different from one layer to another. For example, the element content of each layer may change like a gradation in the Z-axis direction.

[0076] <6. Sixth Embodiment> <6-1. Configuration Example of Magnetic Memory Element> A configuration example of a magnetic memory element 1 according to this embodiment will be described with reference to Fig. 21. Fig. 21 is a diagram showing a configuration example of a magnetic memory element 1 according to this embodiment. This embodiment is basically the same as the fifth embodiment (see Fig. 13), but differences therebetween will be described.

[0077] As shown in FIG. 21 , in the magnetic memory element 1 according to this embodiment, the memory layer 40 is composed of a first memory layer 41 and a second memory layer 42. In the example of FIG. 21 , the first memory layer 41, the voltage modulation enhancement layer 50, and the second memory layer 42 are stacked on the tunnel barrier layer 30 in this order. Specifically, the first memory layer 41 is located closer to the tunnel barrier layer 30 than the second memory layer 42, and the voltage modulation enhancement layer 50 is adjacent to the first memory layer 41 and the second memory layer 42 and sandwiched between them. The first memory layer 41 and the second memory layer 42 are magnetically coupled. As with the configuration of FIG. 13 , the configuration of FIG. 21 according to this embodiment can also achieve improved VCMA efficiency and suppression of a decrease in the tunnel magnetoresistance change rate.

[0078] <6-2. Modified Example of Magnetic Memory Element> A modified example of the magnetic memory element 1 according to this embodiment will be described with reference to Fig. 22. Fig. 22 is a diagram showing a modified example of the magnetic memory element 1 according to this embodiment.

[0079] As shown in Fig. 22 , in the modified example of the magnetic memory element 1 according to this embodiment, the stacking order of the tunnel barrier layer 30, the first memory layer 41, the voltage modulation enhancement layer 50, and the second memory layer 42 is different from that of the configuration of Fig. 21 . That is, the second memory layer 42, the voltage modulation enhancement layer 50, the first memory layer 41, and the tunnel barrier layer 30 are stacked on the lower electrode 70 in the order shown. As with the configuration of Fig. 21 , the modified configuration of Fig. 22 can also achieve improvement in VCMA efficiency and suppression of a decrease in the tunnel magnetoresistance change rate. Note that it is possible to select an appropriate structure in accordance with convenience of the film formation process, element characteristics, and the like.

[0080] In the above-described embodiment, the memory layer 40 is composed of two layers, the first memory layer 41 and the second memory layer 42. However, the number of layers constituting the memory layer 40 is not particularly limited, and may be three or more layers. Even in this case, the voltage modulation enhancement layer 50 is sandwiched between any two of the layers constituting the memory layer 40. Each of the layers may contain the same element or different elements. The element content (concentration) of each layer may be the same or different from one another. For example, the element content of each layer may vary in a gradational manner in the Z-axis direction.

[0081] <7. Seventh embodiment> <7-1. Configuration example of magnetic memory element> A configuration example of a magnetic memory element 1 according to this embodiment will be described with reference to Fig. 23. Fig. 23 is a diagram showing a configuration example of a magnetic memory element 1 according to this embodiment. This embodiment is basically the same as the second embodiment (see Fig. 13), but differences therebetween will be described.

[0082] 23 , in the magnetic memory element 1 according to this embodiment, the tunnel barrier layer 30 is composed of a first tunnel barrier layer 31 and a second tunnel barrier layer 32. In the example of FIG. 23 , the second tunnel barrier layer 32 and the first tunnel barrier layer 31 are stacked on the lower electrode 70 in the order shown. Specifically, the first tunnel barrier layer 31 is located closer to the memory layer 40 than the second tunnel barrier layer 32, and the memory layer 40 is provided on the surface of the first tunnel barrier layer 31 opposite to the second tunnel barrier layer 32. As with the configuration of FIG. 13 , the configuration of FIG. 23 according to this embodiment can also achieve an improvement in VCMA efficiency and a suppression of a decrease in the tunnel magnetoresistance change rate.

[0083] <7-2. Modified Example of Magnetic Memory Element> A modified example of the magnetic memory element 1 according to this embodiment will be described with reference to Fig. 24. Fig. 24 is a diagram showing a modified example of the magnetic memory element 1 according to this embodiment.

[0084] As shown in Fig. 24 , in the modified example of the magnetic memory element 1 according to this embodiment, the stacking order of the first tunnel barrier layer 31, the second tunnel barrier layer 32, the memory layer 40, and the voltage modulation enhancement layer 50 is different from that of the configuration of Fig. 23 . That is, the voltage modulation enhancement layer 50, the memory layer 40, the first tunnel barrier layer 31, and the second tunnel barrier layer 32 are stacked on the lower electrode 70 in the order shown. As with the configuration of Fig. 23 , the modified configuration of Fig. 24 can also achieve improvement in VCMA efficiency and suppression of a decrease in the tunnel magnetoresistance change rate. Note that it is possible to select an appropriate structure in accordance with convenience of the film formation process, element characteristics, and the like.

[0085] In the above-described embodiment, the tunnel barrier layer 30 is composed of two layers, the first tunnel barrier layer 31 and the second tunnel barrier layer 32. However, the number of layers constituting the tunnel barrier layer 30 is not particularly limited, and the tunnel barrier layer 30 may be composed of three or more layers. Each layer may contain the same element or different elements. The element content (concentration) of each layer may be the same or different from one another. For example, the element content of each layer may vary in a gradational manner in the Z-axis direction.

[0086] <8. Eighth Embodiment> <8-1. Configuration Example of Magnetic Memory Element> A configuration example of a magnetic memory element 1 according to this embodiment will be described with reference to Fig. 25. Fig. 25 is a diagram showing a configuration example of a magnetic memory element 1 according to this embodiment. This embodiment is basically the same as the third embodiment (see Fig. 15), but differences therebetween will be described.

[0087] 25 , in the magnetic memory element 1 according to this embodiment, the voltage modulation enhancement layer 50 is composed of a first voltage modulation enhancement layer 51 and a second voltage modulation enhancement layer 52. In the example of FIG. 25 , the tunnel barrier layer 30, the first voltage modulation enhancement layer 51, the memory layer 40, the second voltage modulation enhancement layer 52, and the cap layer 60 are stacked on the lower electrode 70 in the order shown. More specifically, the first voltage modulation enhancement layer 51 and the second voltage modulation enhancement layer 52 are provided adjacent to the memory layer 40 so as to sandwich the memory layer 40. As with the configuration of FIG. 15 , the configuration of FIG. 25 according to this embodiment can also achieve improvement in VCMA efficiency and suppression of a decrease in the tunnel magnetoresistance change rate.

[0088] <8-2. Modified Example of Magnetic Memory Element> A modified example of the magnetic memory element 1 according to this embodiment will be described with reference to Fig. 26. Fig. 26 is a diagram showing a modified example of the magnetic memory element 1 according to this embodiment.

[0089] 26 , in the modified example of the magnetic memory element 1 according to this embodiment, the stacking order of the tunnel barrier layer 30, the first voltage modulation enhancement layer 51, the memory layer 40, the second voltage modulation enhancement layer 52, and the cap layer 60 is different from that of the configuration of FIG. 25 . That is, the cap layer 60, the second voltage modulation enhancement layer 52, the memory layer 40, the first voltage modulation enhancement layer 51, and the tunnel barrier layer 30 are stacked on the lower electrode 70 in the order shown. As with the configuration of FIG. 25 , the modified configuration of FIG. 26 can also achieve improved VCMA efficiency and suppression of a decrease in the tunnel magnetoresistance change rate. Note that it is possible to select an appropriate structure depending on the convenience of the film formation process, element characteristics, and the like.

[0090] In the above-described embodiment, the voltage modulation enhancement layer 50 is composed of two layers, the first voltage modulation enhancement layer 51 and the second voltage modulation enhancement layer 52. However, the number of layers constituting the voltage modulation enhancement layer 50 is not particularly limited, and may be three or more layers. The memory layer 40 is sandwiched between any two of the layers constituting the voltage modulation enhancement layer 50. Each layer may contain the same element or different elements. The element content (concentration) of each layer may be the same or different from one another. For example, the element content of each layer may vary in a gradational manner in the Z-axis direction.

[0091] <9. Storage Device According to Each Embodiment> <9-1. Configuration Example of Storage Device> A configuration example of a storage device 100 according to each embodiment will be described with reference to Fig. 27. Fig. 27 is a diagram showing a configuration example of a storage device 100 according to each embodiment. This storage device 100 is an example of a storage device having a magnetic memory element 1 according to any of the above-mentioned embodiments.

[0092] 27 , the memory device 100 includes a memory cell array 110. The memory cell array 110 includes a plurality of memory cells 11 arranged in a matrix. These memory cells 11 are connected to bit lines BL, source lines SL, and word lines WL, respectively. For example, the plurality of word lines WL are wired so as to extend in the row direction, and the plurality of bit lines BL and the plurality of source lines SL are wired so as to extend in the column direction. The bit lines BL, source lines SL, and word lines WL each function as control lines.

[0093] Each memory cell 11 has a magnetic memory element 1 and a select transistor 2. The magnetic memory element 1 is a magnetic memory element according to any of the above-described embodiments. In the example of FIG. 27 , the memory cells 11 share one source line SL for every two columns in the column direction. That is, each memory cell 11 arranged in two columns in the column direction is connected to two bit lines BL and one source line SL (2BL / 1SL).

[0094] The magnetic memory element 1 is electrically connected between a bit line BL and a source line SL. In the example of Fig. 27, one end of the magnetic memory element 1 is connected to the bit line BL, and the other end is connected to the source line SL via the selection transistor 2.

[0095] The selection transistor 2 is an example of a selection element for selecting a memory cell 11 from which data is to be read or written, from among the multiple memory cells 11. Various types of transistors, such as a field effect transistor, can be used as the selection transistor 2. The function of the selection transistor 2 is also referred to as a selector function, for example.

[0096] This selection transistor 2 switches between a state that enables data access (data reading and writing) to the corresponding magnetic memory element 1 and a state that prevents data access. In the example of FIG. 27 , one of the source and drain of the selection transistor 2 is connected to the magnetic memory element 1, and the other is connected to a source line SL. The gate of the selection transistor 2 is connected to a word line WL. When the selection transistor 2 is turned on (conductive state), data access to the magnetic memory element 1 to which the selection transistor 2 is connected becomes possible. When the selection transistor 2 is turned off (non-conductive state), data access to the magnetic memory element 1 to which the selection transistor 2 is connected is prevented.

[0097] The memory device 100 includes various peripheral circuits in addition to the memory cell array 110. In the example of Figure 27, the peripheral circuits include an I / O (input / output circuit) 12, a control circuit 13, a voltage generating circuit 14, a bit line address decoder 15, a bit line control circuit 16, a word line address decoder 17, a word line control circuit 18, and a sense amplifier 19. The bit line control circuit 16 is connected to the bit line BL, the word line control circuit 18 is connected to the word line WL, and the sense amplifier 19 is connected to the source line SL. The basic configuration and operation of such a memory device 100 are publicly known, so the basic configuration and operation will be briefly described.

[0098] The I / O 12 enables the exchange of commands related to reading and writing data, addresses of memory cells 11 to be accessed, data, etc. between an external circuit (e.g., an arithmetic circuit) of the memory device 100 and the control circuit 13 of the memory device 100.

[0099] In response to a command, the control circuit 13 controls writing and reading of data to the memory cell 11, specifically the magnetic memory element 1 in the memory cell 11. For example, the control circuit 13 receives a command (such as a write or read command) from an external circuit, and controls writing and reading of data based on the received command.

[0100] The voltage generating circuit 14 generates voltages (e.g., data write voltages and data read voltages) used to write and read data to and from the memory cells 11, and supplies the generated voltages (e.g., pulse voltages) to the bit line control circuit 16.

[0101] The bit line address decoder 15 obtains the address of the bit line BL corresponding to the address received at the I / O 12 described above.

[0102] The bit line control circuit 16 selects and controls the bit line BL corresponding to the address of the bit line address decoder 15. For example, writing data to the memory cell 11 using the data write voltage generated by the voltage generation circuit 14, and reading data from the memory cell 11 using the data read voltage generated by the voltage generation circuit 14 are performed via the bit line control circuit 16, etc.

[0103] The word line address decoder 17 obtains the address of the word line WL corresponding to the address received at the I / O 12 described above.

[0104] The word line control circuit 18 selects and controls the word line WL corresponding to the address of the word line address decoder 17 .

[0105] The sense amplifier 19 detects the data read from the memory cell 11 , specifically the resistance value of the magnetic memory element 1 .

[0106] 9-2. Example of memory cell configuration An example of the configuration of the memory cell 11 of the memory device 100 described above will be described with reference to Fig. 28. Fig. 28 is a diagram showing an example of the configuration of the memory cell 11 of the memory device 100 described above. In addition to the magnetic memory element 1 and select transistor 2 of the memory cell 11, Fig. 28 also shows the magnetic field generating layer 3, contact layer 4, semiconductor substrate 5, bit line BL, word line WL, and source line SL.

[0107] The select transistor 2 includes a source region 2a, a drain region 2b, and a gate electrode. The source region 2a and the drain region 2b are formed in a semiconductor substrate 5. The gate electrode is a word line WL in the example of FIG.

[0108] The magnetic field generating layer 3 applies a magnetic field in, for example, the horizontal direction (XY plane direction) of the magnetic memory element 1. The magnetic field generating layer 3 is used to apply an external magnetic field to the magnetic memory element 1. In the example of FIG. 28 , the magnetic field generating layer 3 is arranged above the magnetic memory element 1 (positive Z-axis direction side). However, the magnetic field generating layer 3 may also be arranged below the magnetic memory element 1 (positive Z-axis direction side). The magnetic field generating layer 3 is also referred to as, for example, a ferromagnetic bias layer.

[0109] The magnetic field generating layer 3 may be disposed for each magnetic memory element 1, or may be disposed in common across multiple magnetic memory elements 1. Instead of the magnetic field generating layer 3, a method may be used in which a magnetic field is applied to the entire memory cell array 110 including the memory cells 11, or a magnetic field induced by wiring for applying a magnetic field and a current is used.

[0110] The contact layer 4 is a layer that electrically connects several elements and is configured to include, for example, vias. In the example of Fig. 28, three contact layers 4 are shown: a contact layer 4 that connects the magnetic field generating layer 3 and the bit line BL, a contact layer 4 that connects the magnetic memory element 1 and the source region 2a, and a contact layer 4 that connects the drain region 2b and the source line SL.

[0111] <9-3. Example of Write Processing> <9-3-1. Flowchart> An example of a flowchart of the write processing of the storage device 100 described above will be described with reference to Fig. 29. Fig. 29 is a diagram showing an example of a flowchart of the write processing of the storage device 100 described above.

[0112] The control circuit 13 (for example, a state machine included in the control circuit 13) controls the write process. The flowchart starts when a write command and write data are input to the control circuit 13 from the I / O 12. For convenience, data corresponding to a low resistance state is 0, and data corresponding to a high resistance state is 1.

[0113] As shown in FIG. 29 , in step S1, an initial read is performed. In step S2, a comparison is made between the read data and the write data. In step S3, it is determined whether the read data matches the write data. If it is determined that the read data matches the write data (step S3: Yes), the process ends. On the other hand, if it is determined in step S3 that the read data does not match the write data (step S3: No), in step S4, a write voltage is applied to the selected cell (selected memory cell 11). In step S5, a verify read is performed, and the process returns to step S2. Thereafter, the processes from step S2 onwards are executed again.

[0114] 29, the number of times the verify read is repeated is not set, but it is also possible to set a maximum number of times it is repeated in advance. Also, the process may be terminated without performing the verify read.

[0115] <9-3-2. Timing Chart> An example of a timing chart of the write process of the storage device 100 will be described with reference to Fig. 30. Fig. 30 is a diagram showing an example of a timing chart of the write process of the storage device 100.

[0116] As shown in Figure 30, a read start signal and a write start signal are generated by a control circuit 13. A bit line control signal is generated by a bit line control circuit 16, and a word line control signal is generated by a word line control circuit 18. Selection of a bit line BL and a word line WL is performed by a bit line address decoder 15 and a word line address decoder 17. An applied voltage is generated by a voltage generation circuit 14 and becomes an input voltage to a sense amplifier 19 during reading. The example of Figure 30 schematically shows the difference between a high resistance state (High) and a low resistance state (Low) when a voltage is applied to a magnetic memory element 1. Note that the actual signal response is not limited to the example of Figure 30.

[0117] The sense amplifier control signal is a signal that controls the timing for determining read data, and is generated by the control circuit 13. The sense amplifier 19 determines whether the resistance state of the magnetic memory element 1 is a high resistance state (High) or a low resistance state (Low), and outputs the result, i.e., read data, to the control circuit 13. The control circuit 13 compares the read data with the write data to determine whether they match.

[0118] Next, the operation will be described in chronological order. In the example of Fig. 30, several times are shown as time t1 to time t12.

[0119] The control circuit 13 outputs a read start signal and an address to the voltage generation circuit 14 (time t1). The word line address decoder 17 and the word line control circuit 18 decode the address and turn on the corresponding bit line control signal and word line control signal (time t1).

[0120] The voltage generation circuit 14 generates a read voltage and applies it to the bit line BL (time t2). The read voltage changes to High or Low depending on whether the magnetic memory element 1 is in a high-resistance state or a low-resistance state (time t2 to time t3). In the example of FIG. 30, the read voltage changes to High. After the read voltage is determined, the sense amplifier control signal turns on, and the sense amplifier 19 outputs the read result (time t3).

[0121] The control circuit 13 compares the read data with the write data. If the two data match, the write operation ends; if the two data do not match, the write signal is turned on. In the example of FIG. 30, the two data do not match, so the corresponding bit line control signal and word line control signal are turned on (time t5), and then the write voltage is applied (time t6). Furthermore, a read is performed for verification (time t10), and if the read data matches the write data, the data write ends (time t11).

[0122] Note that the control of the verify read and the control of the initial read may be the same, and the read voltage may be different between the control of the verify read and the control of the initial read. In the example of Figure 30, an example is shown in which writing is successful with one voltage application, but if it fails, the write voltage may be applied again. Also, the write control is not limited to the example of Figure 30. Various start signals may not be necessary depending on the circuit design, and the timing of controlling the bit line BL and the word line WL is arbitrary.

[0123] 29 and 30 show examples of writing, but various read methods may also be used for reading. The read flow chart and timing chart can be explained as part of, for example, Figures 29 and 30, and therefore detailed explanations thereof will be omitted.

[0124] 10. Actions and Effects of Each Embodiment As described above, according to each embodiment, the magnetic memory element 1 includes the tunnel barrier layer 30, the memory layer 40 provided on the tunnel barrier layer 30, and the voltage modulation enhancement layer 50 provided on the surface of the memory layer 40 opposite to the tunnel barrier layer 30 side (see FIGS. 1 , 3 , 13 , 14 , etc.). For example, if the voltage modulation enhancement layer 50 is inserted between the tunnel barrier layer 30 and the memory layer 40, the TMR (tunneling magnetoresistance change rate) decreases. On the other hand, since the voltage modulation enhancement layer 50 is provided on the surface of the memory layer 40 opposite to the tunnel barrier layer 30 side as described above, it is possible to improve the VCMA efficiency while suppressing the decrease in TMR. Therefore, it is possible to improve the VCMA efficiency and suppress the decrease in the tunneling magnetoresistance change rate.

[0125] The magnetic memory element 1 may further include a cap layer 60 provided on the surface of the voltage modulation enhancement layer 50 opposite to the memory layer 40 (see FIGS. 1, 3, 15, 16, etc.). Even with such a configuration, it is possible to improve the VCMA efficiency and suppress the decrease in the tunneling magnetoresistance change rate.

[0126] Furthermore, the magnetic memory element 1 may further include a reference layer 20 provided on the surface of the tunnel barrier layer 30 opposite to the memory layer 40 side (see FIGS. 1, 3, 17, and 18). Even with such a configuration, it is possible to improve the VCMA efficiency and suppress the decrease in the tunnel magnetoresistance change rate.

[0127] Furthermore, magnetic memory element 1 may further include spacer layer 22 provided on the surface of reference layer 20 opposite to tunnel barrier layer 30, and fixed layer 21 provided on the surface of spacer layer 22 opposite to reference layer 20 (see FIGS. 17 and 18 ). Even with such a configuration, it is possible to improve the VCMA efficiency and suppress the decrease in the tunneling magnetoresistance change rate.

[0128] Furthermore, the memory layer 40 may include a first memory layer 41 and a second memory layer 42, the first memory layer 41 being located closer to the tunnel barrier layer 30 than the second memory layer 42, and the voltage modulation enhancement layer 50 being provided on the surface of the second memory layer 42 opposite to the first memory layer 41 side (see FIGS. 19 and 20 ). Even with such a configuration, it is possible to achieve an improvement in VCMA efficiency and suppression of a decrease in the tunnel magnetoresistance change rate.

[0129] Furthermore, the memory layer 40 may include a first memory layer 41 and a second memory layer 42, the first memory layer 41 being located closer to the tunnel barrier layer 30 than the second memory layer 42, and the voltage modulation enhancement layer 50 being adjacent to the first memory layer 41 and the second memory layer 42 and sandwiched between the first memory layer 41 and the second memory layer 42 (see FIGS. 21 and 22 ). Even with such a configuration, it is possible to achieve an improvement in VCMA efficiency and suppression of a decrease in the tunnel magnetoresistance change rate.

[0130] Alternatively, the tunnel barrier layer 30 may include a first tunnel barrier layer 31 and a second tunnel barrier layer 32, with the first tunnel barrier layer 31 being located closer to the memory layer 40 than the second tunnel barrier layer 32, and the memory layer 40 being provided on the surface of the first tunnel barrier layer 31 opposite to the second tunnel barrier layer 32 (see FIGS. 23 and 24 ). Even with this configuration, it is possible to improve the VCMA efficiency and suppress a decrease in the tunnel magnetoresistance change rate.

[0131] Furthermore, the voltage modulation enhancement layer 50 may include a first voltage modulation enhancement layer 51 and a second voltage modulation enhancement layer 52, and the first voltage modulation enhancement layer 51 and the second voltage modulation enhancement layer 52 may be provided adjacent to the memory layer 40 so as to sandwich the memory layer 40 (see FIGS. 25 and 26 ). Even with such a configuration, it is possible to achieve an improvement in VCMA efficiency and suppression of a decrease in the tunneling magnetoresistance change rate.

[0132] The voltage modulation enhancement layer 50 may also contain at least one element selected from the group consisting of Ir, Os, Pt, Rh, Hf, Zr, Ti, Ta, W, Re, Au, Mo, Ru, Pd, Y, V, Sc, Gd, Tb, La, Mg, Al, Ag, Cu, Cr, Co, Fe, and Ni (see FIG. 1, etc.), thereby ensuring improved VCMA efficiency.

[0133] The memory layer 40 may also be configured to have a body-centered cubic lattice structure (see FIG. 1, etc.), which allows a desired crystal structure to be obtained.

[0134] The storage layer 40 may also include a single crystal oriented in the (001) plane or a polycrystal preferentially oriented in the (001) plane (see FIG. 1, etc.), thereby achieving a desired crystal orientation.

[0135] Furthermore, the tunnel barrier layer 30 may contain at least one of an oxide having at least one element selected from Mg, Ca, Li, Si, Al, Sr, Zr, Hf, Ti, Zn, Sc, La, Ta, Eu, Cu, Ba, Mo, W, V, Y, Ni, Co, Mn, Cr, Fe, B, and C, a nitride having the one or more elements, and a fluoride having the one or more elements (see FIG. 1 , etc.). This ensures that the voltage-controlled magnetic anisotropy effect is imparted to the memory layer 40.

[0136] The tunnel barrier layer 30 may also contain MgO (see FIG. 1, etc.), which ensures that the voltage-controlled magnetic anisotropy effect is imparted to the storage layer 40.

[0137] The tunnel barrier layer 30 may also include a single crystal oriented in the (001) plane or a polycrystal preferentially oriented in the (001) plane (see FIG. 1 , etc.). This ensures that the voltage-controlled magnetic anisotropy effect is imparted to the memory layer 40. Furthermore, controlling the orientation can improve, for example, the barrier properties and processability.

[0138] The thickness of the voltage modulation enhancement layer 50 may be less than 0.5 nm (see FIGS. 4 to 12), which can reliably improve the VCMA efficiency.

[0139] The thickness of the voltage modulation enhancing layer 50 may be 0.3 nm or less (see FIGS. 4 to 12), which makes it possible to more reliably achieve an improvement in VCMA efficiency.

[0140] The thickness of the memory layer 40 may be 1.5 nm or less (see FIG. 1, etc.), which increases the VCMA effect due to voltage and improves controllability during rewriting.

[0141] The sheet resistance of the tunnel barrier layer 30 is 10 Ωμm ２ This makes it possible to achieve low power consumption in voltage control operation.

[0142] 11. Other Embodiments The configurations and processes according to the above-described embodiments (including examples and modified examples) may be implemented in various different forms other than the above-described embodiments. For example, the configurations and processes are not limited to the above-described examples and may be implemented in various forms. Furthermore, for example, the configurations, processing procedures, specific names, or information including various data and parameters shown in the above documents and drawings may be changed arbitrarily unless otherwise specified.

[0143] Furthermore, the components and processes according to the above-described embodiments (including examples and modifications) do not necessarily have to be physically configured as shown in the drawings. In other words, the specific forms of distribution and integration of the components and processes are not limited to those shown in the drawings, and all or part of them may be functionally or physically distributed or integrated in any unit depending on various loads, usage conditions, etc.

[0144] Furthermore, the configurations and processes of the above-described embodiments (including examples and modified examples) may be combined as appropriate. For example, at least a part of an embodiment may be combined as appropriate with at least a part of another embodiment. Furthermore, the effects of the embodiments are merely examples and are not intended to be limiting, and other effects may also be obtained.

[0145] <12. Application Examples> <12-1. Various Devices> An application example of the magnetic memory element 1 according to any of the above-described embodiments (examples and modifications), for example, an application example of the above-described memory device 100, will be described with reference to Fig. 31. Fig. 31 is a diagram showing an application example of the above-described memory device 100.

[0146] The storage device 100 may be applied to various cases where light such as visible light, infrared light, ultraviolet light, X-rays, etc. For example, the storage device 100 may be applied to various devices (examples of electronic devices) such as those listed below.

[0147] As shown in FIG. 31 , the storage device 100 is used in, for example, "devices for capturing images for viewing, such as digital cameras and portable devices with camera functions," "devices for traffic use, such as in-vehicle sensors for capturing images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and for recognizing the driver's state, surveillance cameras for monitoring moving vehicles and roads, and distance measuring sensors for measuring distances between vehicles," "devices for home appliances such as TVs, refrigerators, and air conditioners for capturing images of user gestures and operating the device in accordance with the gestures," "devices for medical and healthcare use, such as endoscopes and devices for capturing blood vessel images by receiving infrared light," "devices for security use, such as surveillance cameras for crime prevention and cameras for person authentication," "devices for beauty use, such as skin measuring devices for capturing images of the skin and microscopes for capturing images of the scalp," "devices for sports use, such as action cameras and wearable cameras for sports use," and "devices for agriculture, such as cameras for monitoring the condition of fields and crops."

[0148] The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be realized as an electronic device mounted on any type of moving object, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, a construction machine, or an agricultural machine (tractor). Furthermore, the technology according to the present disclosure may be realized as an electronic device mounted on an endoscopic surgery system, a microsurgery system, or the like. Furthermore, the technology according to the present disclosure may be realized as a magnetic sensor, which is an example of an electronic device.

[0149] <12-2. Imaging Device> An imaging device 300 according to an application example will be described with reference to Fig. 32. Fig. 32 is a diagram showing an example of the configuration of the imaging device 300 according to an application example. This imaging device 300 is, for example, an example of an electronic device to which the above-mentioned storage device 100 is applied. Examples of the imaging device 300 include electronic devices such as digital still cameras, video cameras, smartphones and mobile phones with imaging functions.

[0150] 32, the imaging device 300 includes an optical system 301, a shutter device 302, an imaging element (solid-state imaging device) 303, a control circuit (drive circuit) 304, a signal processing circuit 305, a monitor 306, and a memory 307. The imaging device 300 is capable of capturing still images and moving images.

[0151] The optical system 301 includes one or more lenses. The optical system 301 guides light from a subject (incident light) to the image sensor 303, and forms an image on the light receiving surface of the image sensor 303.

[0152] The shutter device 302 is disposed between the optical system 301 and the image sensor 303. The shutter device 302 controls the light irradiation period and the light blocking period for the image sensor 303 under the control of the control circuit 304.

[0153] The image sensor 303 accumulates signal charges for a certain period of time in response to light that is focused on the light receiving surface via the optical system 301 and the shutter device 302. The signal charges accumulated in the image sensor 303 are transferred in accordance with a drive signal (timing signal) supplied from the control circuit 304. The image sensor 303 may be, for example, a solid-state image sensor.

[0154] The control circuit 304 outputs a drive signal that controls the transfer operation of the image sensor 303 and the shutter operation of the shutter device 302 , thereby driving the image sensor 303 and the shutter device 302 .

[0155] The signal processing circuit 305 performs various signal processing on the signal charges output from the image sensor 303. The image (image data) obtained by the signal processing performed by the signal processing circuit 305 is supplied to a monitor 306 and also to a memory 307.

[0156] The monitor 306 displays moving or still images captured by the image sensor 303 based on the image data supplied from the signal processing circuit 305. As the monitor 306, for example, a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel is used.

[0157] The memory 307 stores image data supplied from the signal processing circuit 305, that is, image data of moving images or still images captured by the image sensor 303. As the memory 307, for example, the storage device 100 described above is used.

[0158] In the imaging device 300 configured in this manner, by applying the above-described storage device 100 as the memory 307, it is possible to improve the VCMA efficiency and suppress the decrease in the rate of change of tunneling magnetoresistance.

[0159] <12-3. Distance Measuring Device> A distance measuring device 400 according to an application example will be described with reference to Fig. 33. Fig. 33 is a diagram showing an example of the configuration of the distance measuring device 400 according to an application example. This distance measuring device 400 is, for example, an example of an electronic device to which the above-mentioned storage device 100 is applied.

[0160] 33, distance measuring device (distance image sensor) 400 includes a light source unit 401, an optical system 402, an image sensor (solid-state image sensor) 403, a control circuit (drive circuit) 404, a signal processing circuit 405, a monitor 406, and a memory 407. Distance measuring device 400 projects light from light source unit 401 toward an object and receives light (modulated light or pulsed light) reflected from the surface of the object, thereby obtaining a distance image according to the distance to the object.

[0161] The light source unit 401 projects light toward the subject. For example, a vertical cavity surface emitting laser (VCSEL) array that emits laser light as a surface light source, or a laser diode array in which laser diodes are arranged in a line, is used as the light source unit 401. The laser diode array is supported by a predetermined drive unit (not shown) and scanned in a direction perpendicular to the direction in which the laser diodes are arranged.

[0162] The optical system 402 includes one or more lenses. The optical system 402 guides light from a subject (incident light) to the image sensor 403, and forms an image on the light receiving surface (sensor portion) of the image sensor 403.

[0163] The image sensor 403 accumulates signal charges in response to light that is imaged on the light receiving surface via the optical system 402. A distance signal indicating a distance determined from a light receiving signal (APD OUT) output from the image sensor 403 is supplied to a signal processing circuit 405. As the image sensor 403, for example, a solid-state image sensor such as an image sensor is used.

[0164] The control circuit 404 outputs a drive signal (control signal) that controls the operation of the light source unit 401, the image sensor 403, and the like, thereby driving the light source unit 401, the image sensor 403, and the like.

[0165] The signal processing circuit 405 performs various signal processing on the distance signal supplied from the image sensor 403. For example, the signal processing circuit 405 performs image processing (e.g., histogram processing, peak detection processing, etc.) to construct a distance image based on the distance signal. The image (image data) obtained by the signal processing performed by the signal processing circuit 405 is supplied to a monitor 406 and also to a memory 407.

[0166] The monitor 406 displays the distance image captured by the image sensor 403 based on the image data supplied from the signal processing circuit 405. The monitor 406 may be, for example, a panel display device such as a liquid crystal panel or an organic EL panel.

[0167] The memory 407 stores the image data supplied from the signal processing circuit 405, that is, the image data of the distance image captured by the image sensor 403. As the memory 407, for example, the storage device 100 described above is used.

[0168] In the distance measuring device 400 configured as above, by applying the above-described storage device 100 as the memory 407, it is possible to improve the VCMA efficiency and suppress the decrease in the rate of change of tunneling magnetoresistance.

[0169] As described above, the storage device 100 can be implemented in various electronic devices. For example, the storage device 100 may be installed in various electronic devices such as an HDD (hard disk drive), a notebook PC (personal computer), a mobile device (e.g., a smartphone or tablet PC), a PDA (personal digital assistant), a wearable device, a game device, or a music device, in addition to the imaging device 300 or the distance measuring device 400. For example, the storage device 100 may be used as various types of memory such as storage.

[0170] <13. Supplementary Note> The present technology may also have the following configurations. (1) A magnetic memory element comprising: a tunnel barrier layer; a memory layer provided relative to the tunnel barrier layer; and a voltage modulation enhancement layer provided on a surface of the memory layer opposite to the tunnel barrier layer side. (2) The magnetic memory element according to (1), further comprising: a cap layer provided on a surface of the voltage modulation enhancement layer opposite to the memory layer side. (3) The magnetic memory element according to (1) or (2), further comprising: a reference layer provided on a surface of the tunnel barrier layer opposite to the memory layer side. (4) The magnetic memory element according to (3), further comprising: a spacer layer provided on a surface of the reference layer opposite to the tunnel barrier layer side; and a fixed layer provided on a surface of the spacer layer opposite to the reference layer side. (5) The magnetic memory element according to any one of (1) to (4), wherein the memory layer includes a first memory layer and a second memory layer, the first memory layer is located closer to the tunnel barrier layer than the second memory layer, and the voltage modulation enhancement layer is provided on a surface of the second memory layer opposite to the first memory layer side. (6) The magnetic memory element according to any one of (1) to (5), wherein the memory layer includes a first memory layer and a second memory layer, the first memory layer is located closer to the tunnel barrier layer than the second memory layer, and the voltage modulation enhancement layer is adjacent to the first memory layer and the second memory layer and sandwiched between the first memory layer and the second memory layer. (7) The magnetic memory element according to any one of (1) to (6), wherein the tunnel barrier layer includes a first tunnel barrier layer and a second tunnel barrier layer, the first tunnel barrier layer is located closer to the memory layer than the second tunnel barrier layer, and the memory layer is provided on a surface of the first tunnel barrier layer opposite to the second tunnel barrier layer.(8) The magnetic memory element according to any one of (1) to (7), wherein the voltage modulation enhancement layer includes a first voltage modulation enhancement layer and a second voltage modulation enhancement layer, and the first voltage modulation enhancement layer and the second voltage modulation enhancement layer are provided adjacent to the memory layer so as to sandwich the memory layer. (9) The magnetic memory element according to any one of (1) to (8), wherein the voltage modulation enhancement layer includes at least one element selected from Ir, Os, Pt, Rh, Hf, Zr, Ti, Ta, W, Re, Au, Mo, Ru, Pd, Y, V, Sc, Gd, Tb, La, Mg, Al, Ag, Cu, Cr, Co, Fe, and Ni. (10) The magnetic memory element according to any one of (1) to (9), wherein the memory layer is configured to have a body-centered cubic lattice structure. (11) The magnetic memory element according to any one of (1) to (10), wherein the memory layer includes a single crystal oriented in the (001) plane or a polycrystal preferentially oriented in the (001) plane. (12) The magnetic memory element according to any one of (1) to (11), wherein the tunnel barrier layer includes at least one of an oxide having at least one element selected from Mg, Ca, Li, Si, Al, Sr, Zr, Hf, Ti, Zn, Sc, La, Ta, Eu, Cu, Ba, Mo, W, V, Y, Ni, Co, Mn, Cr, Fe, B, and C, a nitride having the one or more elements, and a fluoride having the one or more elements. (13) The magnetic memory element according to any one of (1) to (11), wherein the tunnel barrier layer includes MgO. (14) The magnetic memory element according to any one of (1) to (13), wherein the tunnel barrier layer includes a single crystal oriented in the (001) plane or a polycrystal preferentially oriented in the (001) plane. (15) The magnetic memory element according to any one of (1) to (14), wherein the voltage modulation enhancement layer has a thickness of less than 0.5 nm. (16) The magnetic memory element according to (15), wherein the voltage modulation enhancement layer has a thickness of 0.3 nm or less. (17) The magnetic memory element according to any one of (1) to (16), wherein the memory layer has a thickness of 1.5 nm or less. (18) The sheet resistance of the tunnel barrier layer is 10 Ω μm. ２The magnetic memory element according to any one of (1) to (17) above. (19) A storage device comprising a magnetic memory element, wherein the magnetic memory element has: a tunnel barrier layer, a memory layer provided with respect to the tunnel barrier layer, and a voltage modulation enhancement layer provided on the surface of the memory layer opposite to the tunnel barrier layer side. (20) An electronic device comprising: a storage device having a magnetic memory element, wherein the magnetic memory element has: a tunnel barrier layer, a memory layer provided with respect to the tunnel barrier layer, and a voltage modulation enhancement layer provided on the surface of the memory layer opposite to the tunnel barrier layer side. (21) A storage device comprising the magnetic memory element according to any one of (1) to (18). (22) An electronic device comprising the storage device according to (21).

[0171] 1 Magnetic memory element 2 Select transistor 2a Source region 2b Drain region 3 Magnetic field generation layer 4 Contact layer 5 Semiconductor substrate 10 Underlying layer 11 Memory cell 12 I / O 13 Control circuit 14 Voltage generation circuit 15 Bit line address decoder 16 Bit line control circuit 17 Word line address decoder 18 Word line control circuit 19 Sense amplifier 20 Reference layer 21 Fixed layer 22 Spacer layer 30 Tunnel barrier layer 31 First tunnel barrier layer 32 Second tunnel barrier layer 40 Memory layer 41 First memory layer 42 Second memory layer 50 Voltage modulation enhancement layer 51 First voltage modulation enhancement layer 52 Second voltage modulation enhancement layer 60 Cap layer 70 Lower electrode 80 Upper electrode 100 Memory device 110 Memory cell array 300 Imaging device 307 Memory 400 Distance measuring device 407 Memory BL Bit line SL Source line WL Word line

Claims

1. A magnetic memory device comprising a tunnel barrier layer, a memory layer provided with respect to the tunnel barrier layer, and a voltage modulation enhancement layer provided on a surface of the memory layer opposite to the tunnel barrier layer side.

2. The magnetic memory device according to claim 1, further comprising a cap layer provided on a surface of the voltage modulation enhancement layer opposite to the memory layer side.

3. The magnetic memory device according to claim 1, further comprising a reference layer provided on a surface of the tunnel barrier layer opposite to the memory layer side.

4. The magnetic memory device according to claim 3, further comprising a spacer layer provided on a surface of the reference layer opposite to the tunnel barrier layer side, and a fixed layer provided on a surface of the spacer layer opposite to the reference layer side.

5. The memory layer includes a first memory layer and a second memory layer. The first memory layer is located closer to the tunnel barrier layer side than the second memory layer. The voltage modulation enhancement layer is provided on a surface of the second memory layer opposite to the first memory layer side. The magnetic memory device according to claim 1.

6. The memory layer includes a first memory layer and a second memory layer. The first memory layer is located closer to the tunnel barrier layer side than the second memory layer. The voltage modulation enhancement layer is adjacent to the first memory layer and the second memory layer and is sandwiched between the first memory layer and the second memory layer. The magnetic memory device according to claim 1.

7. The tunnel barrier layer includes a first tunnel barrier layer and a second tunnel barrier layer. The first tunnel barrier layer is located closer to the memory layer side than the second tunnel barrier layer. The memory layer is provided on a surface of the first tunnel barrier layer opposite to the second tunnel barrier layer side. The magnetic memory device according to claim 1.

8. The voltage modulation enhancement layer includes a first voltage modulation enhancement layer and a second voltage modulation enhancement layer. The first voltage modulation enhancement layer and the second voltage modulation enhancement layer are provided adjacent to the memory layer so as to sandwich the memory layer. The magnetic memory device according to claim 1.

9. The magnetic memory element according to claim 1, wherein the voltage modulation enhancement layer contains at least one element selected from Ir, Os, Pt, Rh, Hf, Zr, Ti, Ta, W, Re, Au, Mo, Ru, Pd, Y, V, Sc, Gd, Tb, La, Mg, Al, Ag, Cu, Cr, Co, Fe, and Ni.

10. The magnetic memory element according to claim 1, wherein the memory layer is configured in a body-centered cubic lattice structure.

11. The magnetic memory element according to claim 1, wherein the memory layer includes a single crystal oriented in the (001) plane or a polycrystal preferentially oriented in the (001) plane.

12. The magnetic memory element according to claim 1, wherein the tunnel barrier layer includes at least any one of an oxide having at least one element selected from Mg, Ca, Li, Si, Al, Sr, Zr, Hf, Ti, Zn, Sc, La, Ta, Eu, Cu, Ba, Mo, W, V, Y, Ni, Co, Mn, Cr, Fe, B, and C, a nitride having the at least one element, and a fluoride having the at least one element.

13. The magnetic memory element according to claim 1, wherein the tunnel barrier layer contains MgO.

14. The magnetic memory element according to claim 1, wherein the tunnel barrier layer includes a single crystal oriented in the (001) plane or a polycrystal preferentially oriented in the (001) plane.

15. The magnetic memory element according to claim 1, wherein the thickness of the voltage modulation enhancement layer is less than 0.5 nm.

16. The magnetic memory element according to claim 15, wherein the thickness of the voltage modulation enhancement layer is 0.3 nm or less.

17. The magnetic memory element according to claim 1, wherein the thickness of the memory layer is 1.5 nm or less.

18. The sheet resistance of the tunnel barrier layer is 10 Ωμm ２ or more. The magnetic memory element according to claim 1.

19. A memory device comprising a magnetic memory element, wherein the magnetic memory element includes a tunnel barrier layer, a memory layer provided with respect to the tunnel barrier layer, and a voltage modulation enhancement layer provided on a surface of the memory layer opposite to the tunnel barrier layer side.

20. An electronic device comprising a memory device having a magnetic memory element, wherein the magnetic memory element includes a tunnel barrier layer, a memory layer provided with respect to the tunnel barrier layer, and a voltage modulation enhancement layer provided on a surface of the memory layer opposite to the tunnel barrier layer side.

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