Offset calibration method and circuit applied to comparator array

Abstract

An offset calibration method and circuit applied to a comparator array. The offset calibration circuit comprises a global calibration voltage generation module, integrators, comparators, a global logic control circuit and local logic control circuits. The entire comparator array shares one global calibration voltage generation module, and simply by means of providing an integrator circuit and a local logic control circuit for each comparator, a large calibration range and a small calibration step size can be realized and a requirement for a small area is satisfied. In the offset calibration method, a sampling bisection method is used to search for an offset voltage, which requires a short calibration time period.

Description

Offset calibration method and circuit for comparator array Technical Field

[0001] The invention relates to an offset calibration method and a circuit applied to a comparator array, and belongs to the field of integrated circuit design. Background Art

[0002] In fields such as image sensors and integrated storage and computing, while device size continues to decrease with process advancement, the array size within the device continues to expand. Consequently, more readout circuits are required to read out the array output current, which contradicts the trend of shrinking device size. Therefore, low-area design of the readout circuits is necessary. In these fields, column-level signal processing typically requires an analog-to-digital converter (ADC) per column, or multiplexing an ADC across multiple columns. The ADC's performance significantly impacts the overall system performance. As a key module in ADCs, the comparator must meet performance requirements such as low area and low offset. However, as process parameters fluctuate, the comparator will exhibit a normally distributed offset voltage, with its equivalent input offset voltage potentially reaching tens of millivolts. This reduces the ADC's dynamic input range and degrades its performance.

[0003] To reduce offset voltage and improve comparator performance, one approach is to use larger devices, but this increases area and load. Another approach is to add a calibration circuit to the comparator, measuring and correcting the offset voltage. In this second approach, the quality of a calibration technique is evaluated based on a comprehensive assessment of the circuit's performance after calibration, the increased area and power consumption due to calibration, and the calibration time.

[0004] Currently, common calibration methods include offset voltage storage methods, represented by auto-zeroing and correlated double sampling, and digitally assisted analog fine-tuning methods. The offset voltage storage method adds an additional calibration cycle before each comparison cycle and introduces a capacitive load in the signal path, which reduces the comparator's response speed and is therefore unsuitable for high-speed dynamic comparators. Digitally assisted analog fine-tuning, on the other hand, applies a digitally controlled calibration voltage to a signal path within the comparator to offset the offset voltage, thereby completing the comparator calibration. This calibration method only requires calibration before the comparator operates normally, without introducing additional comparison cycles during operation. This makes it suitable for high-speed comparator calibration. However, there is a trade-off between calibration accuracy, circuit area, and calibration time. Achieving a large calibration range and a small calibration step size requires a long calibration cycle and a large circuit area. Existing calibration circuits for comparator arrays typically employ independent calibration circuits for each comparator, which not only consumes excessive area but also introduces mismatch issues between comparators.

[0005] Summary of the Invention

[0006] In order to solve one or more of the above problems, the present invention provides a method and circuit applicable to comparator array calibration, so as to achieve offset calibration with small area cost, short calibration time and high calibration accuracy.

[0007] A first object of the present invention is to provide an offset calibration circuit for a comparator array, comprising a global calibration voltage generation module, an integrator, a comparator, a global logic control circuit, and a local logic control circuit; wherein the global logic control circuit has a calibration enable signal and a clock signal as inputs, and an output connected to a control terminal of the global calibration voltage generation module for generating the control signal required for the global calibration voltage generation module; the output of the global calibration voltage generation module is connected to an input of the integrator for generating the voltage required for calibration of the entire comparator array; a comparator is configured for every two integrators, and the outputs of the two integrators are respectively connected to a calibration port of the comparator; the integrator is used to integrate the voltage generated by the global calibration voltage generation module during the calibration phase, and to maintain the integrated calibration voltage during the normal operation phase of the comparator; the input of the local logic control circuit is connected to the output port of the comparator, and the output of the local logic control circuit is connected to the control terminal of the integrator for generating the control signal required for the integrator.

[0008] In one embodiment, the comparator includes two calibration ports Vcal_P and Vcal_N. The calibration ports Vcal_P and Vcal_N are gates of a calibration pair of transistors connected in parallel with the input pair of transistors of the comparator or substrates of the input pair of transistors of the comparator.

[0009] In one embodiment, when calibration starts, the global logic control circuit generates a control signal to control the global calibration voltage generation module to sequentially generate voltages of magnitudes Vref, ... The global calibration voltage Vgcal, where the reference voltage Vref and N determine the calibration range and calibration accuracy of the calibration module. If the reference voltage Vref is larger, the offset calibration range is larger and larger offsets can be calibrated. The smaller it is, the smaller the calibration step is and the higher the calibration accuracy is.

[0010] In one embodiment, the global calibration voltage generation module consists of a capacitor array, a reset switch, a switch array and a buffer. The capacitor array is connected in parallel, the lower plate of each capacitor is connected to a switch, the upper plate is connected to the positive pole of the buffer, and the negative pole of the buffer is connected to the global calibration voltage Vgcal; the switch array is connected to the global logic control circuit, and the global logic control circuit controls each switch to select the reference voltage or ground. The reset switch is connected in parallel with the capacitor array. When the reset switch is closed, the upper plates of all capacitors are connected to the reference voltage for resetting the capacitor array.

[0011] In one embodiment, the integrator is composed of a switch S int1 ~S int5 , capacitor C int1 ~C int3 It consists of a 2x gain amplifier and a selector, and the capacitor C int1 ~C int3 The capacitance is equal; the selector is controlled by the control signal CRE:

[0012] When CRE is high, the capacitor C int2 The upper plate is connected to the switch S int2 and switch S int3 Between, and the capacitor C int3 Connect to the output of the integrator;

[0013] When CRE is low, the capacitor C int3 The upper plate is connected to the switch S int2 and switch S int3 Between, and the capacitor C int2 The global calibration voltage Vgcal is connected to the output of the integrator through the switch S int1 Connected to capacitor C int1 The upper plate, capacitor C int1 The upper plate of the switch S int2 Connected to capacitor C int2 The upper plate, capacitor C int2 The upper plate of the switch S int3 Connected to the input of the 2x gain amplifier, the output of the amplifier is connected to the input of the 2x gain amplifier through the switch Sint4 Connected to the calibration port Vcal_P or Vcal_N of the comparator, capacitor C int3 The upper plate of the capacitor is connected to the output terminal, the lower plates of all capacitors are connected to the ground, and the reset switch S int5 Connect the output terminal and ground in series to reset the output voltage.

[0014] A second object of the present invention is to provide a calibration method for an offset calibration circuit applied to a comparator array, based on the above-mentioned offset calibration circuit, the method comprising:

[0015] Step 1: When the comparator calibration starts, the comparator input terminals VIP and VIN are connected to the common mode voltage Vcm. At the same time, the comparator local calibration terminals Vcal_P and Vcal_N and the global calibration voltage Vgcal are reset, and the comparator outputs the first comparison result.

[0016] Step 2: Based on the first output of the comparator in step 1, the local logic control circuit determines the calibration side, and the integrator integrates the global calibration voltage so that the voltage at the Vcal_P terminal increases by Vref or the voltage at the Vcal_N terminal increases by Vref. The comparator outputs the second comparison result.

[0017] Step 3: The global logic control circuit controls the global calibration voltage generation module to reduce the generated global calibration voltage from Vref to

[0018] Step 4: Based on the second output of the comparator in step 2, the local logic control circuit determines the calibration side, and the integrator integrates the global calibration voltage Vgcal, so that the voltage at the Vcal_P terminal increases Or the voltage at Vcal_N increases The comparator outputs the third comparison result;

[0019] Step 5: Repeat the operations of step 3 and step 4 until the output Vgcal of the global calibration voltage generation module is At this time, the last integration is performed based on the previous comparison result of the comparator. After the integration is completed, the voltages at the integrator output terminals Vcal_P and Vcal_N are the calibration voltages of the local comparator, and the comparator offset calibration is completed.

[0020] In one embodiment, the local logic control circuit determines the calibration side in the following manner:

[0021] If the comparator outputs a high level after completing a comparison in the calibration phase, the voltage at the Vcal_N terminal will be added to the global calibration voltage Vgcal through the integrator, while the voltage at the Vcal_P terminal remains unchanged;

[0022] If the comparator outputs a low level after completing a comparison in the calibration phase, the voltage at the Vcal_P terminal will be added to the global calibration voltage Vgcal through the integrator, while the voltage at the Vcal_N terminal remains unchanged.

[0023] A third object of the present invention is to provide an image sensor that employs the above-mentioned offset calibration circuit for a comparator array.

[0024] A fourth object of the present invention is to provide a memory-computing integrated chip that employs the above-mentioned offset calibration circuit for comparator arrays.

[0025] A fifth object of the present invention is to provide an application of the offset calibration circuit applied to a comparator array or a calibration method of the offset calibration circuit applied to a comparator array in the field of integrated circuit design.

[0026] Beneficial effects of the present invention:

[0027] (1) The comparator array offset calibration circuit provided by the present invention achieves a large calibration range and a small calibration step size by only adjusting the voltage generated by the global calibration voltage generation module. Since the entire comparator array shares one global calibration voltage generation module, each comparator only needs to add an integrator circuit and a local logic control circuit, thus resolving the contradiction between calibration accuracy and area and meeting the requirement of low area. At the same time, since the global calibration voltage generation module is shared, the mismatch between comparators caused by traditional independent calibration circuits is reduced, thereby improving the array-level matching.

[0028] (2) The offset calibration method provided by the present invention is similar to the binary search algorithm, which searches for the offset voltage using the sampling binary search method to achieve The calibration step only requires N cycles, and the calibration time is short;

[0029] (3) The present invention can flexibly adjust the calibration accuracy by adjusting the global calibration voltage generation module, and the technology has strong portability. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0031] FIG1 is a diagram showing the overall structure of an offset calibration circuit for an array-level comparator according to the present invention.

[0032] FIG2 is a schematic diagram of a global calibration voltage generation module provided in a second embodiment of the present invention.

[0033] FIG3 is a schematic diagram of an integrator according to a second embodiment of the present invention.

[0034] FIG4 is a schematic diagram of a comparator according to a second embodiment of the present invention, in which the gates of the calibration pair of transistors connected in parallel with the comparator input pair of transistors are used as calibration ports.

[0035] FIG5 is a schematic diagram of a comparator according to a second embodiment of the present invention, in which the substrate of the comparator input pair is used as a calibration port.

[0036] FIG6 is a comparator calibration flow chart provided in the second embodiment of the present invention.

[0037] FIG7 is a timing diagram provided by the second embodiment of the present invention. DETAILED DESCRIPTION

[0038] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present invention. The same or similar symbols appearing in the embodiments represent the same or similar elements or elements with the same or similar functions. The embodiments described are only part of the embodiments of the present invention and not all of the embodiments. Based on the embodiments of the present invention, other embodiments obtained by those skilled in the art without creative work are all within the scope of protection of the present invention.

[0039] Example 1

[0040] This embodiment provides an offset calibration circuit applied to a comparator array, as shown in FIG1 , which includes a global calibration voltage generation module, an integrator, a comparator, a global logic control circuit, and a local logic control circuit.

[0041] The global logic control circuit receives a calibration enable signal EN and a clock signal CLK as inputs, and its output is connected to the input of a global calibration voltage generation module to generate the control signals required by the global calibration voltage generation module. The output of the global calibration voltage generation module is connected to the input of an integrator to generate the voltage required for calibration of the entire comparator array. A comparator is configured for every two integrators, with the output of one integrator connected to the comparator's calibration port Vcal_P and the output of the other integrator connected to the comparator's calibration port Vcal_N. During the calibration phase, the integrator integrates the voltage generated by the global calibration voltage generation module and maintains the integrated calibration voltage during the normal operation of the comparator. The comparator's two calibration ports, Vcal_P and Vcal_N, serve as the gates of a calibration pair of transistors connected in parallel to the comparator's input transistors, or as the substrates of the comparator's input transistors. The input of the local logic control circuit is connected to the output of the comparator, and the output of the local logic control circuit is connected to the control terminal of the integrator to generate the control signals required by the integrator. (To avoid clutter in the figure, the line connecting the output of the local logic control circuit to the control terminal of the integrator is not shown in FIG. 1 ).

[0042] Example 2:

[0043] This embodiment provides an offset calibration circuit for a comparator array, which is implemented based on the first embodiment. As shown in FIG2 , the global calibration voltage generation module of this embodiment comprises a capacitor array, a reset switch, and a switch array S1 to S2. N and buffer A1, where the capacitor array includes capacitors C0 to C N , the switch array includes switches S1~S N Each capacitor in the capacitor array is connected to a switch in the switch array and then connected in parallel. The lower plate of the capacitor is connected to the switch, and the upper plate is connected to the positive terminal of the buffer. The negative terminal of the buffer A1 is connected to the global calibration voltage Vgcal; the switch array S1~S N Connected to the global logic control circuit, the global logic control circuit controls each switch to select the reference voltage or ground; the reset switch is used to reset the capacitor array. When a switch in the switch array is closed, the top plate of the corresponding capacitor is connected to the reference voltage Vref.

[0044] When N=6, the capacitance values ​​of capacitors C0~C6 are C, C, 2C, 4C...2 5 C, where C represents the capacitance of the unit capacitor. Buffer A1 is used to isolate the capacitor array from the integrator and provide driving capability. The global logic control circuit generates the control signals required to reset the switch and switch array. Its inputs are the calibration enable signal EN and the clock signal CLK. By detecting the high and low levels of EN at the rising edge of CLK, it determines whether the circuit is in calibration mode or normal comparator operation mode:

[0045] When the rising edge of CLK comes, if EN is at a low level at this time, the comparator enters the normal working mode. At this time, the global control logic circuit generates a control signal to make the switch array S1~S N Connect the reference voltage Vref and close the reset switch at the same time. At this time, the global calibration voltage Vgcal is Vref;

[0046] When the rising edge of CLK comes, if EN is at a high level at this time, it enters the calibration mode. First, the reset switch is disconnected, and the other switch signals remain unchanged. After one clock cycle, the global control logic circuit generates a switch S N The control signal of , makes the switch connected to the ground, at this time the global calibration voltage Vgcal is After another clock cycle, switch S N-1 Grounded, the global calibration voltage Vgcal is After N clock cycles, the global calibration voltage Vgcal is

[0047] The integrators in this embodiment are used to integrate the global calibration voltage, and the required control signals are generated by a local logic control circuit. This offset calibration circuit includes comparators 1 through M, each of which corresponds to two integrators, P and N. The global calibration voltage is input to both integrators. The output of integrator P is connected to the comparator's local calibration terminal, Vcal_P, while the output of integrator N is connected to the calibration terminal, Vcal_N. All control signals for the two integrators are independent.

[0048] Refer to Figure 3. Each integrator is connected by a switch S int1 ~S int5 , capacitor C int1 ~C int3 It consists of a 2x gain amplifier and a selector, and the capacitor C int1 ~C int3 The selector is controlled by the control signal CRE. When CRE is high, the capacitor C int2 The upper plate is connected to the switch S int2 and switch S int3 Between, and the capacitor C int3 Connect to the output of the integrator, when CRE is low, the capacitor C int3 The upper plate is connected to the switch S int2 and switch S int3 Between, and the capacitor C int2 The global calibration voltage Vgcal is connected to the output of the integrator through the switch S int1 Connected to capacitor C int1 The upper plate, capacitor C int1 The upper plate of the switch S int2 Connected to capacitor C int2 The upper plate, capacitor C int2 The upper plate of the switch S int3 Connected to the input of the 2x gain amplifier, the output of the amplifier is connected to the input of the 2x gain amplifier through the switch S int4 Connected to the comparator local calibration terminal Vcal_P or Vcal_N, capacitor C int3 The upper plate of the capacitor is connected to the output terminal, the lower plates of all capacitors are connected to the ground, and the reset switch S int5 Connect the output terminal and ground in series to reset the output voltage. The local logic control circuit generates a switch S int1 ~S int5 When the circuit enters calibration mode, in the first clock cycle, the global calibration voltage Vgcal is Vref. At this time, the local logic control circuit judges and controls the integrator to integrate the calibration terminal Vcal_P or Vcal_N based on the comparison result of the comparator. The integration principle of the integrator is as follows:

[0049] The local logic control circuit generates the switch Sint1 ~S int5 The control signal of switch S int1 Closed, switch S int2 ~S int4 Disconnect, then the capacitor C int1 The global calibration voltage Vgcal is sampled within the clock cycle. If the clock cycle is the first clock cycle, Vgcal is Vref, and S int5 Close, clear capacitor C int3 The charge on the switch S int1 Disconnect, S int2 Closed, S int5 Disconnected, and CRE is low, then the capacitor C int1 and C int3 Perform charge sharing and disconnect S immediately after sharing is completed. int2 , close switch S int1 , S int3 and S int4 At this time, the output voltage of the calibration terminal is Vref, the integration is completed, and the capacitor C int1 At the same time, the global calibration voltage Vgcal of the second clock cycle is sampled. When the third clock cycle comes, the switch S int1 Disconnect, S int2 Closed, S int5 Disconnected, and CRE is high, then the capacitor C int1 and C int2 Perform charge sharing and disconnect S immediately after sharing is completed. int2 , close switch S int1 , S int3 and S int4 , at this time the calibration terminal output voltage is And the capacitor C int1 At the same time, the global calibration voltage Vgcal of the third clock cycle is sampled, and the above operations are repeated in the subsequent integration process.

[0050] The comparator of this embodiment is shown in Figures 4 and 5. The comparator is composed of PMOS transistors PM1 to PM7, NMOS transistors NM1 to NM6, and inverters INV1 and INV2. Its input terminals are VIP and VIN, and its calibration terminals are Vcal_P and Vcal_N. The calibration port is connected through a calibration pair of transistors in parallel with the comparator input pair or directly through the comparator input pair. The comparator is controlled by a clock signal CLK. When CLK is high, the comparator is reset, and the output terminals COMP_P and COMP_N are both high. When CLK is low, the comparator compares the voltages at the input terminals VIP and VIN. If the voltage at the VIP terminal is greater than the voltage at the VIN terminal, the output terminal COMP_P is high and the output terminal COMP_N is low. Conversely, if the voltage at the VIN terminal is greater than the voltage at the VIP terminal, the output terminal COMP_N is high and the output terminal COMP_P is low.

[0051] Figure 4 is a schematic diagram of the calibration port being led out through a calibration pair of transistors connected in parallel with the comparator input pair of transistors, wherein PM1 and PM2 are the comparator input pair of transistors, whose gates are led out to the input ports VIP and VIN; PM3 and PM4 are the calibration pair of transistors connected in parallel with the comparator input pair of transistors PM1 and PM2, respectively, whose gates are led out to the calibration ports Vcal_P and Vcal_N.

[0052] FIG5 is a schematic diagram showing that the calibration port is directly led out through the comparator input pair transistors, wherein the gates of the comparator input pair transistors PM1 and PM2 lead out the input ports VIP and VIN, and the substrates thereof lead out the calibration ports Vcal_P and Vcal_N.

[0053] The calibration process of this embodiment is as follows: FIG6 is a flow chart of the calibration process, and FIG7 is a timing chart of the calibration.

[0054] Calibration terminal Vcal_P corresponds to integrator P, and calibration terminal Vcal_N corresponds to integrator N. All control signals in integrators P and N are independent and do not communicate with each other. The following describes the calibration process in detail, using the example of a positive offset voltage VOS on the P side.

[0055] Step 1: Connect the two input terminals VIP and VIN of the comparator to switches S1 and S2 respectively, and connect switches S1 and S2 to the common mode voltage Vcm. When the comparator calibration starts, the common mode switch at the comparator input is closed, and VIP and VIN are connected to the common mode voltage Vcm. At the same time, the switch S in the integrator is closed. int5 Close, reset the comparator's local calibration terminals Vcal_P and Vcal_N, close the reset switch in the global calibration module to reset the global calibration voltage Vgcal, close switches S1 to S6, connect the lower plate of the capacitor array to the reference voltage Vref, and the comparator outputs the first comparison result, that is, COMP_P is high;

[0056] Step 2: Since COMP_P is at a high level, the voltage of the calibration terminal Vcal_N needs to be increased through the integrator. When the switch S in the integrator N corresponding to the calibration terminal Vcal_N is int1 Closed, switch S int2 ~S int4 When disconnected, the capacitor C int1 The global calibration voltage Vgcal is sampled, and S int5 Close, clear capacitor C int3 On the charge, then S int2 Closed, switch S int1 Disconnected, and CRE is low, capacitor C int1 and C int3 Charge sharing, then disconnect S int2 , closed S int3 and S int4 The shared voltage is amplified by 2 times and stored in C int3 , at this time the voltage at the calibration terminal Vcal_N increases to Vref, completing the integration;

[0057] Step 3: After the integration phase is over, the comparator performs the next comparison. At the same time, the switch S6 in the global calibration voltage generation module is grounded. At this time, the global calibration voltage Vgcal drops to

[0058] Step 4: According to the comparison result of the comparator in step 3, determine whether to integrate the calibration voltage on the P side or the N side. If COMP_P is high, the calibration terminal Vcal_N is integrated through the integrator N. Specifically, the switch S in the integrator N is turned on. int1 Closed, switch S int2 ~S int4 Disconnect, capacitor C int1 The global calibration voltage Vgcal is sampled, and then S int2 Closed, switch S int1 Disconnected, and CRE is high, capacitor C int1 and C int2 Charge sharing, then disconnect S int2 , closed S int3 and S int4 The shared voltage is amplified by 2 times and stored in C int3 , so that the voltage at Vcal_N increases to If COMP_N is low, the calibration terminal Vcal_P is integrated through the integrator P. Specifically, the switch S in the integrator P int1 Closed, switch S int2 ~S int4 Disconnect, capacitor C int1The global calibration voltage Vgcal is sampled, and then S int2 Closed, switch S int1 Disconnected, and CRE is low, capacitor C int1 and C int2 Charge sharing, then disconnect S int2 , closed S int3 and S int4 The shared voltage is amplified by 2 times and stored in C int3 , so that the voltage at Vcal_P increases to

[0059] Step 5: Repeat the operations of step 3 and step 4 until the output Vgcal of the global calibration voltage generation module is At this time, the last integration is performed according to the last comparison result of the comparator. After the integration is completed, the voltage of the integrator output terminals Vcal_P and Vcal_N is the calibration voltage of the local comparator, and the capacitor C stored on the integrator is int3 The comparator offset calibration is completed.

[0060] After the calibration phase is completed, the input signal is connected to the input of the comparator for normal comparison operation.

[0061] According to the above comparator calibration workflow, taking the Mth comparator as an example, if its output is B during the calibration phase i , where i = 0, 1, 2…, N, and B0 is the first comparison result of the comparator, B N The N+1th comparison result of the comparator. When the calibration phase is completed, the comparison result B N Calculate the voltage of its calibration terminal, when B i = 0, the calibration end Where 0≤i≤N, when B i =1, the calibration end Where 0≤i≤N, the minimum step size of calibration is

[0062] Example 3:

[0063] This embodiment provides a calibration method for an offset calibration circuit applied to a comparator array, which is implemented using the calibration circuit applied to a comparator array provided in the first or second embodiment, and includes the following steps:

[0064] Step 1: When the comparator calibration starts, the common-mode switch at the comparator input is closed, VIP and VIN are connected to the common-mode voltage Vcm, and at the same time, the comparator's local calibration terminals Vcal_P and Vcal_N and the global calibration voltage Vgcal are reset, and the comparator outputs the first comparison result.

[0065] Step 2: Based on the first output of the comparator in step 1, the local logic control circuit determines the calibration side, and the integrator integrates the global calibration voltage so that the voltage at the Vcal_P terminal increases by Vref or the voltage at the Vcal_N terminal increases by Vref;

[0066] Step 3: The comparator performs a second comparison and is controlled by the global logic control circuit. The global calibration voltage is reduced from Vref to

[0067] Step 4: Based on the second output of the comparator, the local logic control circuit determines the calibration side, and the integrator integrates the global calibration voltage Vgcal, causing the voltage at the Vcal_P terminal to increase Or the voltage at Vcal_N increases And steps 3 and 4 should be completed within one clock cycle;

[0068] Step 5: Repeat the operations of step 3 and step 4 until the output Vgcal of the global calibration voltage generation module is At this time, the last integration is performed based on the previous comparison result of the comparator. After the integration is completed, the voltages at the integrator output terminals Vcal_P and Vcal_N are the calibration voltages of the local comparator, and the comparator offset calibration is completed.

[0069] Some steps in the embodiments of the present invention may be implemented using software, and the corresponding software program may be stored in a readable storage medium, such as a CD or a hard disk.

[0070] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An offset calibration circuit for a comparator array, characterized in that: The offset calibration circuit includes a global calibration voltage generation module, an integrator, a comparator, a global logic control circuit, and a local logic control circuit; wherein the output end of the global logic control circuit is connected to the control end of the global calibration voltage generation module to generate the control signal required by the global calibration voltage generation module; the output end of the global calibration voltage generation module is connected to the input end of the integrator to generate the voltage required for calibration of the entire comparator array; a comparator is configured for every two integrators, and the output ends of the two integrators are respectively connected to a calibration port of the comparator. The integrator is used to integrate the voltage generated by the global calibration voltage generation module during the calibration phase and maintain the integrated calibration voltage during the normal operation phase of the comparator; the input end of the local logic control circuit is connected to the output port of the comparator, and the output end of the local logic control circuit is connected to the control end of the integrator to generate the control signal required by the integrator.

2. The offset calibration circuit according to claim 1, wherein: The comparator includes two calibration ports Vcal_P and Vcal_N. The calibration ports Vcal_P and Vcal_N are gates of a calibration pair of transistors connected in parallel with the comparator input pair of transistors or are substrates of the comparator input pair of transistors.

3. The offset calibration circuit according to claim 1, wherein: The global logic control circuit generates a control signal at the beginning of calibration to control the global calibration voltage generation module to generate a voltage of magnitude of The global calibration voltage Vgcal.

4. The offset calibration circuit according to claim 1, wherein: The global calibration voltage generation module is composed of a capacitor array, a reset switch, a switch array, and a buffer. The capacitor arrays are connected in parallel, with the lower plate of each capacitor connected to a switch, the upper plate connected to the positive electrode of the buffer, and the negative electrode of the buffer connected to the global calibration voltage Vgcal. The switch array is connected to a global logic control circuit, which controls each switch to select a reference voltage or ground. The reset switch is connected in parallel to the capacitor array. When the reset switch is closed, the upper plates of all capacitors are connected to the reference voltage to reset the capacitor array.

5. The offset calibration circuit according to claim 1, wherein: The integrator is composed of switch S int1 ~S int5 , capacitor C int1 ~C int3 It consists of a 2x gain amplifier and a selector, and the capacitor C int1 ~C int3 The capacitance is equal; the selector is controlled by the control signal CRE: When CRE is high, the capacitor C int2 The upper plate is connected to the switch S int2 and switch S int3 Between, and the capacitor C int3 Connect to the output of the integrator; When CRE is low, the capacitor C int3 The upper plate is connected to the switch S int2 and switch S int3 Between, and the capacitor C int2 Connect to the output of the integrator; The global calibration voltage Vgcal is connected to the switch S int1 Connected to capacitor C int1 The upper plate, capacitor C int1 The upper plate of the switch S int2 Connected to capacitor C int2 The upper plate, capacitor C int2 The upper plate of the switch S int3 Connect to the 2x gain amplifier input The output of the amplifier is connected to the switch S int4 Connected to the calibration port Vcal_P or Vcal_N of the comparator, capacitor C int3 The upper plate of the capacitor is connected to the output terminal, the lower plates of all capacitors are connected to the ground, and the reset switch S int5 Connect the output terminal and ground in series to reset the output voltage.

6. A calibration method for an offset calibration circuit of a comparator array, characterized in that: The method is implemented based on the offset calibration circuit according to any one of claims 1 to 5, and the method includes: Step 1: When the comparator calibration starts, the comparator input terminals VIP and VIN are connected to the common mode voltage Vcm. At the same time, the comparator local calibration terminals Vcal_P and Vcal_N and the global calibration voltage Vgcal are reset, and the comparator outputs the first comparison result. Step 2: Based on the first output of the comparator in step 1, the local logic control circuit determines the calibration side, and the integrator integrates the global calibration voltage so that the voltage at the Vcal_P terminal increases by Vref or the voltage at the Vcal_N terminal increases by Vref. The comparator outputs the second comparison result. Step 3: The global logic control circuit controls the global calibration voltage generation module to reduce the generated global calibration voltage from Vref to Step 4: Based on the second output of the comparator in step 2, the local logic control circuit determines the calibration side, and the integrator integrates the global calibration voltage Vgcal, so that the voltage at the Vcal_P terminal increases Or the voltage at Vcal_N increases The comparator outputs the third comparison result; Step 5: Repeat the operations of step 3 and step 4 until the global calibration voltage Vgcal output by the global calibration voltage generation module is At this time, the last integration is performed based on the last comparison result of the comparator. After the integration is completed, the voltages at the calibration terminals Vcal_P and Vcal_N become the calibration voltages of the local comparator, and the comparator offset calibration is completed.

7. The method according to claim 6, characterized in that In step 4, the local logic control circuit determines the calibration side in the following manner: If the comparator outputs a high level after completing a comparison in the calibration phase, the voltage at the Vcal_N terminal will be added to the global calibration voltage Vgcal through the integrator, while the voltage at the Vcal_P terminal remains unchanged; If the comparator outputs a low level after completing a comparison in the calibration phase, the voltage at the Vcal_P terminal will be added to the global calibration voltage Vgcal through the integrator, while the voltage at the Vcal_N terminal remains unchanged.

8. An image sensor, characterized in that: The offset calibration circuit applied to a comparator array as claimed in any one of claims 1 to 5 is adopted.

9. A storage and computing integrated chip, characterized in that: The offset calibration circuit applied to a comparator array as claimed in any one of claims 1 to 5 is adopted.

10. Use of the offset calibration circuit for a comparator array according to any one of claims 1 to 5 or the method according to claims 6 to 7 in the field of integrated circuit design.

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