Digital amplifier for correcting pulse error

Abstract

The present invention relates to a digital amplifier for outputting a pulse-width-modulated output switching signal by amplifying a pulse-width-modulated digital input signal, the amplifier minimizing pulse error between the pulse-width-modulated digital input signal and a PWM pulse signal at the rear of a comparison unit according to audio information so that the distortion rate of an output audio signal can be alleviated and error amplifier characteristics can be enhanced, and being capable of minimizing wafer area and production costs when implemented as a semiconductor integrated circuit.

Description

Digital amplifier for pulse error compensation

[0001] The present invention relates to a digital amplifier for correcting pulse errors, and more particularly, to a digital amplifier for correcting pulse errors that can improve the distortion of an output audio signal, enhance the characteristics of an error amplifier, and minimize the wafer area when implemented in a semiconductor integrated circuit by minimizing the pulse error between a digital input signal pulse-width modulated according to audio information and a pulse-width modulated pulse signal at a subsequent stage.

[0002] Audio power amplifiers, which amplify audio input signals to drive speakers, have been rapidly replaced by the Class-D method, which uses switching elements, from the conventional Class-AB method, and most of the latest products or mobile products are now using the Class-D method as the mainstream.

[0003] Here, the Class-D audio amplifier is called a digital amplifier or switching amplifier, unlike the Class-AB method which is called an analog amplifier. Specifically, it generates a pulse width modulated PWM (Pulse Width Modulation) signal according to the audio input signal, amplifies it at the output stage, and then restores the audio signal with a low-pass filter to drive the speaker.

[0004] These digital amplifiers can achieve high efficiency by utilizing PWM waveforms through the switching operation of switch elements at the output stage.

[0005] FIG. 1 is a block diagram illustrating a first embodiment of a digital amplifier according to the prior art, and FIG. 2 is a block diagram illustrating a second embodiment of a digital amplifier according to the prior art.

[0006] Referring to FIG. 1, one embodiment of a digital amplifier according to the prior art is configured to include an error amplifier (20) that compares an analog input signal (AIN) which is an audio signal and an output switching signal (OUT) and outputs an error signal, a comparison unit (30) that compares the error signal with a predetermined carrier signal (e.g., a triangle wave signal) to generate a PWM-modulated comparison pulse signal, a switch driving unit (40) that amplifies the voltage and / or current of the comparison pulse signal or shifts the voltage level to output a driving pulse signal (not shown in the drawing), and an output stage (50) that performs a switching operation according to the driving pulse signal and outputs an output switching signal (OUT). At this time, the output stage (50) is provided with a switch element that performs a switching operation according to the driving pulse signal.

[0007] As illustrated in Fig. 2, the digital amplifier can be configured in a bridge configuration to output output switching signals (OUT1, OUT2) of opposite phases. A digital amplifier of this configuration can be suitably applied when the power supply voltage is a single voltage rather than a positive voltage, and is provided with two symmetrical comparison units (30), two switch driving units (40), and two output stages (50). A representative driving method thereof is as follows.

[0008] FIG. 3 is an operational waveform diagram illustrating a two-level modulation method for the digital amplifier of FIG. 2, and FIG. 4 is an operational waveform diagram illustrating a three-level modulation method for the digital amplifier of FIG. 2.

[0009] Looking at Fig. 3(a), the comparison unit (30) compares the error signal and the triangle wave signal to generate a comparison pulse signal of opposite phases, and as shown in Fig. 3(b), the output stage (50) outputs first and second output switching signals (OUT1, OUT2) of opposite phases based on the comparison pulse signal of opposite phases.

[0010] Accordingly, OUT2-OUT1 corresponding to the difference between the first and second output switching signals (OUT1, OUT2) is applied to both ends of the low-pass filter, and OUT2-OUT1 corresponds to a two-level PWM signal.

[0011] Looking at Fig. 4(a), the comparison unit (30) is composed of a first comparison unit (30) that compares an error signal and a triangle wave signal, and a second comparison unit (30) that inverts one of the error signal and the triangle wave signal and compares them, thereby generating a comparison pulse signal in a form in which the turn-on sections partially overlap, and as shown in Fig. 4(b), the output stage (50) outputs first and second output switching signals (OUT1, OUT2) in a form in which the high level and the low level partially overlap, based on this comparison pulse signal.

[0012] Accordingly, OUT2-OUT1 corresponding to the difference between the first and second output switching signals (OUT1, OUT2) is applied to both ends of the low-pass filter, and since the high and low levels of the first and second output switching signals (OUT1, OUT2) partially overlap, OUT2-OUT1 forms a three-level PWM signal.

[0013] Compared to FIG. 3, the driving method of FIG. 4 has the advantage of reducing the switching amplitude since OUT2-OUT1 output to the low-pass filter is configured as three levels, and the switching frequency of the waveform of OUT2-OUT1 is doubled compared to the frequency of each of the first and second output switching signals (OUT1, OUT2), thereby reducing the switching ripple of the final output waveform output to the speaker.

[0014] However, the digital amplifier according to the first and second embodiments of the prior art has a structure in which an audio signal is input as an analog input signal (AIN), and thus requires a high-quality digital-to-analog converter (DAC) to obtain an analog signal from audio data, and there is a problem in that the wafer area and the resulting production cost increase when implemented as a semiconductor integrated circuit.

[0015] To improve this, a digital amplifier may consider a structure in which audio signals are input as PWM signals rather than as analog input signals (AIN). This PWM signal, which is input to the input terminal of the digital amplifier as an audio signal, will be referred to as a digital input signal (DIN) hereinafter.

[0016] FIG. 5 is a block diagram and an operating waveform diagram illustrating a third embodiment of a digital amplifier according to the prior art.

[0017] Referring to FIG. 5(a), the digital amplifier according to the third embodiment of the prior art has a similar basic configuration to the first and second embodiments, but differs in that a digital input signal (DIN), which is a PWM signal, is input instead of an analog input signal (AIN).

[0018] However, as shown in Fig. 5(b), since the triangle wave frequency or phase of the triangle wave signal provided from the triangle wave generator (10) is not synchronized with the frequency or phase of the digital input signal (DIN), the PWM pulse signal at the rear end of the comparison unit (30) including the comparison pulse signal becomes faster (PL-fast) or slower (PL-slow) than the digital input signal (DIN), and thus the error between the PWM pulse signal and the digital input signal (DIN) increases, causing a problem in that the distortion of the audio output signal output to the speaker becomes severe.

[0019] Accordingly, the present invention has been devised to solve the problems of the prior art, and the purpose of the present invention is to provide a digital amplifier that can improve the distortion of an output audio signal and enhance the characteristics of an error amplifier by minimizing the pulse error between a digital input signal pulse-width modulated according to audio information and a subsequent PWM pulse signal.

[0020] In addition, another object of the present invention is to provide a digital amplifier that can minimize wafer area and production cost when implemented as a semiconductor integrated circuit.

[0021] The technical problems to be solved by the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the present invention belongs from the description below.

[0022] In order to achieve the above object, according to the present invention, a digital amplifier for correcting pulse errors is provided, which is a digital amplifier configured to amplify a pulse-width modulated (PWM) digital input signal and output a pulse-width modulated output switching signal, comprising: an error amplifier for outputting an error signal for an error between the digital input signal and the output switching signal; a triangle wave generator for outputting a triangle wave signal corresponding to a switching frequency of the output switching signal and as a carrier signal of the pulse-width modulation; and a comparison unit for comparing the error signal with the triangle wave signal and outputting a comparison pulse signal, wherein the triangle wave generator is characterized in that it compares a PWM pulse signal of a rear end of the comparison unit including the comparison pulse signal with the digital input signal, and generates the triangle wave signal to correct an error in phase or frequency between the PWM pulse signal and the digital input signal.

[0023] The above triangle wave generation unit may be configured to include a frequency detection unit that compares the PWM pulse signal with a digital input signal and outputs a control voltage reflecting a phase or frequency error; and a triangle wave oscillation unit that controls oscillation so that the triangle wave signal is generated between preset upper and lower levels, and outputs the triangle wave frequency of the triangle wave signal by varying it according to the control voltage.

[0024] The above triangle wave generating unit further includes a voltage-current conversion unit that outputs a variable current whose size is variable according to the control voltage, and the triangle wave oscillating unit can be configured to vary the triangle wave frequency according to the variable current.

[0025] The frequency detection unit may be configured to include at least one phase detection unit that compares the phase of the PWM pulse signal and the digital input signal and outputs a lagging pulse and a leading pulse, respectively, to indicate whether the phase is lagging or leading; and a pulse-to-voltage conversion unit that varies and outputs the control voltage according to a charge control signal and a discharge control signal input based on the lagging pulse and the leading pulse.

[0026] Each of the one or more phase detection units may be configured to include a reference pulse input terminal into which a reference pulse is input based on the digital input signal or its inverted signal, and a comparison pulse input terminal into which a comparison pulse is input based on the PWM pulse signal or its inverted signal, an edge detection unit that outputs the leading pulse when the phase of the PWM pulse signal is ahead of the digital input signal and outputs the lagging pulse when the phase of the PWM pulse signal is behind the digital input signal; and a reset unit that resets the edge detection unit so that the leading pulse and lagging pulse occur during a phase difference section between the digital input signal and the PWM pulse signal.

[0027] The pulse-voltage conversion unit may be configured to include a conversion capacitor into which the control voltage is charged; a charge switch that receives the ground pulse as the charge control signal and controls the conduction of the conversion charge current to the conversion capacitor according to the charge control signal, thereby controlling the magnitude of the control voltage; and a discharge switch that receives the leading pulse as the discharge control signal and controls the conduction of the conversion discharge current from the conversion capacitor according to the discharge control signal, thereby controlling the magnitude of the control voltage.

[0028] The frequency detection unit may include two phase detection units that detect a phase difference by comparing edges of the reference pulse and the comparison pulse, which are input to each of the reference pulse input terminals and the comparison pulse input terminals, respectively, and one of the two phase detection units may be configured to detect a phase difference based on a rising edge of the reference pulse and the comparison pulse and output the leading pulse or the lagging pulse, and the other of the two phase detection units may be configured to detect a phase difference based on a falling edge of the reference pulse and the comparison pulse and output the leading pulse or the lagging pulse.

[0029] The above charging control signal may be configured to include a ground pulse of each of the two phase detection units, and the above discharging control signal may be configured to include a leading pulse of each of the two phase detection units.

[0030] The variable current may include a variable charging current and a variable discharging current whose sizes are varied by the control voltage, and the voltage-current conversion unit may include an up switch that controls conduction of the variable charging current so that the triangle wave signal rises from the lower limit level to the upper limit level; and a down switch that controls conduction of the variable discharging current so that the triangle wave signal rises from the upper limit level to the lower limit level.

[0031] The above triangle wave oscillation unit may be configured to include a triangle wave capacitor that is charged by the variable charging current and discharged by the variable discharge current to form the triangle wave signal; an upper and lower limit setting unit configured to compare the triangle wave signal with an upper limit reference level and a lower limit reference level and output an upper limit detection signal and a lower limit detection signal, respectively, when the triangle wave signal reaches the upper limit level or the lower limit level; and a latch unit that receives the upper limit detection signal and the lower limit detection signal and conducts the down switch from the upper limit detection signal to the lower limit detection signal, and conducts the up switch from the lower limit detection signal to the upper limit detection signal.

[0032] The above triangle wave signal can have a variable frequency as the magnitudes of the variable charging current and the variable discharging current are varied.

[0033] A switch driving unit that amplifies the voltage and / or current of the comparison pulse signal received from the comparison unit or shifts the voltage level to provide a driving pulse signal for driving an output stage of a subsequent stage; and further includes a switch element that performs a switching operation according to the driving pulse signal, and an output stage that outputs an output switching signal by the switching operation of the switch element, wherein the PWM pulse signal may include any one of the comparison pulse signal, the driving pulse signal, and the output switching signal, or any one of the inversion signals of each of the comparison pulse signal, the driving pulse signal, and the output switching signal.

[0034] According to the present invention, a digital amplifier for correcting pulse errors has the effect of improving the distortion of an output audio signal and enhancing the characteristics of an error amplifier by minimizing the pulse error between a digital input signal pulse-width modulated according to audio information and a subsequent PWM pulse signal.

[0035] In addition, the present invention has the effect of minimizing wafer area and production cost when implemented as a semiconductor integrated circuit.

[0036] FIG. 1 is a block diagram illustrating a first embodiment of a digital amplifier according to the prior art.

[0037] FIG. 2 is a block diagram illustrating a second embodiment of a digital amplifier according to the prior art.

[0038] FIG. 3 is an operational waveform diagram illustrating a two-level modulation method for the digital amplifier of FIG. 2.

[0039] Fig. 4 is an operational waveform diagram illustrating a 3-level modulation method for the digital amplifier of Fig. 2.

[0040] FIG. 5 is a block diagram and an operating waveform diagram illustrating a third embodiment of a digital amplifier according to the prior art.

[0041] Figure 6 is a block diagram illustrating a digital amplifier according to the present invention.

[0042] Fig. 7 is a block diagram showing a triangle wave generating unit of the present invention.

[0043] Fig. 8 is a block diagram illustrating one embodiment of a frequency detection unit in a triangle wave generation unit of the present invention.

[0044] Fig. 9 is a block diagram illustrating another embodiment of a frequency detection unit in a triangle wave generation unit of the present invention.

[0045] FIG. 10 is an operation waveform diagram for explaining the operation of a frequency detection unit according to one embodiment and another embodiment shown in FIGS. 8 and 9.

[0046] Fig. 11 is a circuit diagram showing one embodiment of a voltage-current converter and a triangle wave oscillator in a triangle wave generator of the present invention.

[0047] Preferred embodiments of the present invention are described in detail with reference to the attached drawings. The following detailed description is merely exemplary and merely illustrates preferred embodiments of the present invention.

[0048] Figure 6 is a block diagram illustrating a digital amplifier according to the present invention.

[0049] Referring to FIG. 6, a digital amplifier for correcting a pulse error according to the present invention relates to a digital amplifier configured to amplify a pulse-width modulated (PWM) digital input signal (DIN) and output a pulse-width modulated output switching signal (OUT1, OUT2), and may be configured to include an error amplifier (200) for outputting an error signal (not shown) for an error between the digital input signal (DIN) and the output switching signal (OUT1, OUT2), a triangle wave generator (100) corresponding to the switching frequency of the output switching signal (OUT1, OUT2) and outputting a triangle wave signal (TRI) as a carrier signal of pulse-width modulation, and a comparison unit (300) for comparing the error signal and the triangle wave signal (TRI) and outputting a comparison pulse signal (PL).

[0050] At this time, the triangle wave generation unit (100) is characterized in that it compares the PWM pulse signal at the rear end of the comparison unit (300) including the comparison pulse signal (PL) with the digital input signal (DIN) to generate a triangle wave signal (TRI) to correct the phase or frequency error between the PWM pulse signal and the digital input signal (DIN).

[0051] In addition, the digital amplifier of the present invention may further include a switch driving unit (400) that amplifies at least one of the voltage and current of the comparison pulse signal (PL) received from the comparison unit (300) or shifts the voltage level of the comparison pulse signal (PL) to provide a driving pulse signal (DPL1, DPL2) for driving the output stage (500) of the subsequent stage, and a switch element (not shown in the drawing) that performs a switching operation according to the driving pulse signal (DPL1, DPL2), and an output stage (500) that outputs an output switching signal (OUT1, OUT2) by the switching operation of the switch element.

[0052] Accordingly, the PWM pulse signal compared with the digital input signal (DIN) in the triangle wave generator (100) may include any one of the comparison pulse signal (PL), the driving pulse signal (DPL1, DPL2) and the output switching signal (OUT1, OUT2), or any one of the inverted signals of each of the comparison pulse signal (PL), the driving pulse signal (DPL1, DPL2) and the output switching signal (OUT1, OUT2).

[0053] The digital amplifier of the present invention can be configured not only to receive a pair of digital input signals (DIN) and output a pair of output switching signals (OUT1, OUT2) in a bridge form as shown in FIG. 6, but also to receive a single digital input signal (DIN) and output a single output switching signal (OUT1, OUT2), or to output a pair of output switching signals (OUT1, OUT2) in a bridge form for a single digital input signal (DIN).

[0054] In addition, the digital amplifier of the present invention can be driven by the 2-level or 3-level modulation method described above.

[0055] For convenience of explanation, the digital amplifier of the present invention will be described below as an example of a structure that outputs a pair of output switching signals (OUT1, OUT2) in a bridge form for a pair of digital input signals (DIN), as shown in FIG. 6.

[0056] The error amplifier (200) is a component that amplifies the error between the digital input signal (DIN) and the output switching signals (OUT1, OUT2) and outputs an error signal, and may have an integrator structure that outputs an error signal in which the error between the digital input signal (DIN) and the output switching signals (OUT1, OUT2) is integrated based on the common mode voltage (VCM). Here, the common mode voltage (VCM) may be set to a middle value between the lower limit level (VL) and the upper limit level (VH) of the triangle wave signal (TRI).

[0057] The triangle wave generator (100) is a component that outputs a triangle wave signal (TRI) as a carrier signal of pulse width modulation, and the switching frequency of the output switching signals (OUT1, OUT2) can be determined in response to the triangle wave frequency of the triangle wave signal (TRI). Here, the triangle wave signal (TRI) is a carrier signal for the PWM signal at the rear end of the comparison unit (300), and includes not only a general triangle wave of left-right symmetrical shape but also a sawtooth wave shape.

[0058] The comparison unit (300) is a component that compares an error signal and a triangle wave signal (TRI) and outputs a comparison pulse signal (PL), and outputs a comparison pulse signal (PL) in which the error signal is pulse-width modulated by the triangle wave signal (TRI).

[0059] The switch driving unit (400) is a component provided to drive the switch element of the output stage (500), and amplifies at least one of the voltage and current of the comparison pulse signal (PL) received from the comparison unit (300) to be suitable for driving the switch element, or shifts the voltage level of the comparison pulse signal (PL) to provide a driving pulse signal (DPL1, DPL2) for driving the output stage (500) of the subsequent stage, and the driving pulse signal (DPL1, DPL2) corresponding to the comparison pulse signal (PL) is also a PWM signal, like the comparison pulse signal (PL).

[0060] The output stage (500) is configured to include a switch element that performs a switching operation according to a driving pulse signal (DPL1, DPL2), and outputs an output switching signal (OUT1, OUT2) by the switching operation of the switch element and provides it to a low-pass filter at the subsequent stage. Therefore, the output switching signal (OUT1, OUT2) output in response to the driving pulse signal (DPL1, DPL2) can also be referred to as a PWM signal.

[0061] According to the above configuration, the triangle wave generation unit (100) compares the PWM pulse signal at the rear end of the comparison unit (300) with the digital input signal (DIN), and generates the triangle wave signal (TRI) by varying the frequency in a direction that minimizes the phase or frequency error between the PWM pulse signal and the digital input signal (DIN).

[0062] At this time, the PWM pulse signal compared with the digital input signal (DIN) in the triangle wave generator (100) may be a signal including any one of the comparison pulse signal (PL), the driving pulse signal (DPL1, DPL2), and the output switching signal (OUT1, OUT2) at the rear end of the comparison unit (300) as a pulse width modulated signal according to the error between the digital input signal (DIN) and the output switching signal (OUT1, OUT2).

[0063] Since the triangle wave frequency of the triangle wave signal (TRI) provided from the triangle wave generating unit (100) of the digital amplifier according to the prior art is not exactly synchronized with the frequency of the digital input signal (DIN), the frequency and phase error increases between the PWM pulse signal at the rear end of the comparison unit (300) whose switching frequency is determined by the triangle wave frequency and the digital input signal (DIN), and thus the quality of the audio output signal output to the speaker, i.e., the fidelity (THD, Total Harmonic Distortion) and distortion may be deteriorated.

[0064] Accordingly, the triangle wave generation unit (100) of the present invention is characterized in that it generates the triangle wave signal (TRI) by varying the frequency in a direction that minimizes the phase or frequency error between the PWM pulse signal at the rear end of the comparison unit (300) and the digital input signal (DIN).

[0065] However, for the convenience of explanation, the PWM pulse signal compared with the digital input signal (DIN) in the triangle wave generator (100) will be explained as an example in the case where the comparison pulse signal (PL) is used.

[0066] Figure 7 is a block diagram showing a triangle wave generator (100) of the present invention.

[0067] Referring to FIG. 7, the triangle wave generation unit (100) of the present invention may be configured to include a frequency detection unit (110) that compares a PWM pulse signal and a digital input signal (DIN) to output a control voltage (VC) in which a phase or frequency error is reflected, and a triangle wave oscillation unit (130) that controls oscillation so that a triangle wave signal (TRI) is generated between a preset upper limit level (VH) and a preset lower limit level (VL), and outputs the triangle wave frequency of the triangle wave signal (TRI) by varying it according to the control voltage (VC) of the frequency detection unit (110).

[0068] To this end, the triangle wave generator (100) may further include a voltage-current converter (120) that outputs a variable current whose size is variable according to the control voltage (VC) of the frequency detector (110).

[0069] Accordingly, the triangle wave generator (130) may be configured to operate to vary the triangle wave frequency according to the variable current controlled by the voltage-current converter (120).

[0070] The frequency detection unit (110) may be configured to compare a comparison pulse signal (PL) and a digital input signal (DIN) and output a control voltage (VC) that reflects a frequency error and a phase error resulting therefrom between the two.

[0071] The control voltage (VC) acts as a control signal that controls the triangle wave generator (130) to vary the triangle wave frequency at the rear end, so that the triangle wave generator (100) can be controlled to output a triangle wave signal (TRI) of a triangle wave frequency at which the frequency or phase error between the comparison pulse signal (PL) and the digital input signal (DIN) is minimized.

[0072] The detailed configuration of the frequency detection unit (110), voltage-current conversion unit (120), and triangle wave oscillator unit (130) will be described later.

[0073] FIG. 8 is a block diagram illustrating one embodiment of a frequency detector (110) in a triangle wave generator (100) of the present invention, FIG. 9 is a block diagram illustrating another embodiment of a frequency detector (110), and FIG. 10 is an operation waveform diagram for explaining the operation of a frequency detector (110) according to one embodiment and another embodiment of the frequency detector (110) illustrated in FIGS. 8 and 9.

[0074] Referring to FIGS. 8 and 9, the frequency detection unit (110) may be configured to include a phase detection unit (111) that compares the phases of a comparison pulse signal (PL) and a digital input signal (DIN) and outputs a lag pulse (UP) and a leading pulse (DN) that indicate whether the phase of the comparison pulse signal (PL) is later than that of the digital input signal (DIN) or is earlier than that of the digital input signal (DIN), and a pulse-voltage conversion unit (112) that varies and outputs a control voltage (VC) according to a charge control signal (SC) and a discharge control signal (SD) input based on the lag pulse (UP) and the leading pulse (DN).

[0075] In particular, referring to FIG. 8, a phase detection unit (111) according to an embodiment of a frequency detection unit (110) may be configured to include a component that detects a phase between a digital input signal (DIN) and a comparison pulse signal (PL), and includes a reference pulse input terminal (REF) into which a digital input signal (DIN) is input as a reference pulse and a comparison pulse input terminal (CK) into which a comparison pulse signal (PL) is input as a comparison pulse, an edge detection unit (1111) that outputs a leading pulse (DN) when the phase of the comparison pulse signal (PL) is ahead of the phase of the digital input signal (DIN) and outputs a lagging pulse (UP) when the phase of the comparison pulse signal (PL) is behind the phase of the digital input signal (DIN), and a reset unit (1112) that resets the edge detection unit (1111) so that the leading pulse (DN) and the lagging pulse (UP) occur during a phase difference section between the digital input signal (DIN) and the comparison pulse signal (PL).

[0076] At this time, the signal input as the reference pulse may be, in the case of a bridge output structure, the first digital input signal (DIN1) or the second digital input signal (DIN2) among two digital input signals (DIN), or a signal generated by an inverted signal or a combination of the corresponding signals, and the signal input as the comparison pulse may be, in the case of a bridge output structure, the first comparison pulse signal (PL1) or the second comparison pulse signal (PL2) among two comparison pulse signals (PL), or a signal generated by an inverted signal or a combination of the corresponding signals.

[0077] The edge detection unit (1111) may be configured to include, for example, two D flip-flops that receive a digital input signal (DIN) and a comparison pulse signal (PL) as clocks (CK), are triggered at a rising edge, and output a logic 1 to each output terminal (Q). Here, the edge detection unit (1111) may also be configured to be triggered at a falling edge in addition to a rising edge, but for the convenience of explanation, a rising edge trigger will be described as an example below.

[0078] When the edge detection unit (1111) is triggered by either a digital input signal (DIN) or a comparison pulse signal (PL), a logic 1 is output to the output terminal (Q) of the corresponding edge detection unit (1111), and the output is maintained until the edge detection unit (1111) is triggered by another signal and the reset unit (1112) resets the edge detection unit (1111).

[0079] Through this, the phase detection unit (111) provides a ground pulse (UP) or a leading pulse (DN) having a pulse width corresponding to the phase difference between the digital input signal (DIN) and the comparison pulse signal (PL) as a charge control signal (SC) or a discharge control signal (SD) to the pulse-voltage conversion unit (112) at the subsequent stage.

[0080] The pulse-voltage converter (112) is a component that converts the ground pulse (UP) or leading pulse (DN) provided from the phase detector (111) into a control voltage (VC), and may be configured in the form of a charge pump as shown in FIG. 8, for example.

[0081] Referring to FIG. 8, the pulse-voltage conversion unit (112) may be configured to include a conversion capacitor (Ccp) in which a control voltage (VC) is charged, a charge switch (1121) which receives a ground pulse (UP) as a charge control signal (SC) and controls the conduction of a conversion charge current (Icpc) to the conversion capacitor (Ccp) according to the charge control signal (SC) to control the size of the control voltage (VC), and a discharge switch (1122) which receives a leading pulse (DN) as a discharge control signal (SD) and controls the conduction of a conversion discharge current (Icpd) from the conversion capacitor (Ccp) according to the discharge control signal (SD) to control the size of the control voltage (VC).

[0082] Accordingly, the frequency detection unit (110) of the present invention can compare the phases of a reference pulse input to a reference pulse input terminal (REF) and a comparison pulse input to a comparison pulse input terminal (CK), and control the control voltage (VC) to increase by a lag pulse (UP) when the phase of the comparison pulse is late, and control the control voltage (VC) to decrease by a leading pulse (DN) when the phase of the comparison pulse is early.

[0083] Referring to FIG. 10(a), the operation of the frequency detection unit (110) according to one embodiment is examined. When the phase of the comparison pulse signal (PL) is later than that of the digital input signal (DIN), a ground pulse (UP) is generated as a charge control signal (SC) to increase the control voltage (VC), and when the phase of the comparison pulse signal (PL) is earlier than that of the digital input signal (DIN), a leading pulse (DN) is generated as a discharge control signal (SD) to decrease the control voltage (VC).

[0084] In this way, by using the control voltage (VC) that reflects the phase information of the comparison pulse signal (PL) rather than the digital input signal (DIN), the triangle wave oscillator (130) at the rear end can vary the triangle wave frequency to minimize the phase and frequency deviation between the PWM pulse signal and the digital input signal (DIN).

[0085] However, the frequency detection unit (110) according to one embodiment is configured to generate a ground pulse (UP) or a leading pulse (DN) only for the rising edge (or falling edge) of the input reference pulse and comparison pulse, as shown in FIG. 10(a), but it is also possible to configure it to generate a ground pulse (UP) or a leading pulse (DN) for both the rising and falling edges of the input reference pulse and comparison pulse in order to more precisely vary the control voltage (VC) with higher resolution or to secure faster response characteristics.

[0086] Referring to FIG. 9 regarding another embodiment of the frequency detector (110), a phase detector (111) according to another embodiment of the frequency detector (110) may be configured to include two phase detectors (111) that detect a phase difference by comparing the edges of a reference pulse and a comparison pulse input to each of the reference pulse input terminals (REF) and the comparison pulse input terminal (CK), respectively.

[0087] In particular, referring to FIG. 9(a), a phase detector (111) according to another embodiment of a frequency detector (110) may be configured such that one of the two phase detectors (111) detects a phase difference based on the rising edge of a reference pulse and a comparison pulse and outputs a leading pulse (DN) or a lagging pulse (UP), and the other of the two phase detectors (111) may be configured such that the phase difference is detected based on the falling edge of the reference pulse and a comparison pulse and outputs a leading pulse (DN) or a lagging pulse (UP).

[0088] Referring to FIG. 10(b), the operation of the frequency detection unit (110) of FIG. 9(a) according to another embodiment can be seen that when the phase of the comparison pulse signal (PL) is later than that of the digital input signal (DIN), a ground pulse (UP) as a charge control signal (SC) is generated at both the rising and falling edges of the digital input signal (DIN) to increase the control voltage (VC), and when the phase of the comparison pulse signal (PL) is earlier than that of the digital input signal (DIN), a leading pulse (DN) as a discharge control signal (SD) is generated at both the rising and falling edges of the comparison pulse signal (PL) to decrease the control voltage (VC).

[0089] In this way, the phase detection unit (111) according to another embodiment of the frequency detection unit (110) is configured to generate a ground pulse (UP) or a leading pulse (DN) at both the rising and falling edges of the digital input signal (DIN) or the comparison pulse signal (PL), thereby allowing the control voltage (VC) to be varied more precisely with a higher resolution or with a faster response characteristic.

[0090] In addition, referring to FIG. 9(b), a phase detector (111) according to another embodiment of a frequency detector (110) is configured to include two phase detectors (111) that detect a phase difference by comparing edges of a reference pulse and a comparison pulse, which are input to each of a reference pulse input terminal (REF) and a comparison pulse input terminal (CK), respectively, and wherein one of the two phase detectors (111) is configured to input a first digital input signal (DIN1) and a first comparison pulse signal (PL1) as a reference pulse and a comparison pulse, respectively, and output a leading pulse (DN) or a lagging pulse (UP), and the other of the two phase detectors (111) is configured to input a second digital input signal (DIN1) and a second comparison pulse signal (PL2) as a reference pulse and a comparison pulse, respectively, and output a leading pulse (DN) or a lagging pulse (UP).

[0091] Through this configuration, the phase detection unit (111) of FIG. 9(b) according to another embodiment of the frequency detection unit (110) includes a ground pulse (UP) output from each of the two phase detection units (111) as a charge control signal (SC), and includes a leading pulse (DN) output from each of the two phase detection units (111) as a discharge control signal (SD), so that a plurality of ground pulses (UP) or leading pulses (DN) are generated in one cycle of the digital input signal (DIN) or the comparison pulse signal (PL), so that the control voltage (VC) can be varied more precisely with a higher resolution or with a faster response characteristic.

[0092] Fig. 11 is a circuit diagram showing one embodiment of a voltage-current converter (120) and a triangle wave oscillator (130) in a triangle wave generator (100) of the present invention.

[0093] As described above, the triangle wave generator (100) may be configured to include a triangle wave generator (130) that controls oscillation so that a triangle wave signal (TRI) is generated between preset upper limit levels (VH) and lower limit levels (VL), and outputs the triangle wave frequency of the triangle wave signal (TRI) by varying it according to the control voltage (VC) of the frequency detector (110).

[0094] To this end, the triangle wave generator (100) may further include a voltage-current converter (120) that outputs a variable current whose size is variable according to the control voltage (VC) of the frequency detector (110) between the frequency detector (110) and the triangle wave generator (130).

[0095] Referring to FIG. 11, the voltage-current converter (120) may be configured to include, for example, an up switch (121) that controls the conduction of a variable charge current (Itrc) so that a triangle wave signal (TRI) rises from a lower limit level (VL) to an upper limit level (VH), and a down switch (122) that controls the conduction of a variable discharge current (Itrd) so that the triangle wave signal (TRI) rises from an upper limit level (VH) to a lower limit level (VL).

[0096] In addition, referring to FIG. 11, the triangle wave oscillator (130) may be configured to include, for example, a triangle wave capacitor (Ctr) that is charged by a variable charging current (Itrc) and discharged by a variable discharge current (Itrd) to form a triangle wave signal (TRI), an upper and lower limit setting unit (131) configured to compare the triangle wave signal (TRI) with an upper limit reference level and a lower limit reference level and output an upper limit detection signal and a lower limit detection signal, respectively, when the triangle wave signal (TRI) reaches an upper limit level (VH) or a lower limit level (VL), and a latch unit (132) that receives an upper limit detection signal and a lower limit detection signal and conducts a down switch (122) of a voltage-current converter (120) from an upper limit detection signal to a lower limit detection signal, and conducts an up switch (121) from a lower limit detection signal to an upper limit detection signal.

[0097] Here, the variable charging current (Itrc) and the variable discharging current (Itrd) are configured as a voltage-controlled current source (VCCS) whose size is varied by the control voltage (VC) provided from the frequency detection unit (110), so that as the size of the variable charging current (Itrc) and the variable discharging current (Itrd) is varied by the control voltage (VC), the slope of the triangle wave signal (TRI) is varied, and thus the triangle wave frequency can be varied.

[0098] According to the above configuration, the triangle wave generation unit (100) of the present invention generates a triangle wave signal (TRI) with an increased triangle wave frequency by increasing the control voltage (VC) when the PWM pulse signal is slower than the digital input signal (DIN), and generates a triangle wave signal (TRI) with a decreased triangle wave frequency by decreasing the control voltage (VC) when the PWM pulse signal is faster than the digital input signal (DIN), thereby correcting the phase or frequency error between the digital input signal (DIN) and the PWM pulse signal.

[0099] Furthermore, the digital amplifier of the present invention can improve the characteristics of the error amplifier (200) by reducing the capacitor of the error amplifier (200) that acts as an integrator or setting the bandwidth wide as the phase or frequency error between the digital input signal (DIN) and the PWM pulse signal is minimized.

[0100] The specific configuration of the triangle wave generator (100) described above using the drawing is merely an exemplary implementation example, and it is obvious that a person of ordinary skill in the art can implement it in various forms by exercising his or her ordinary creative ability if the purpose is to detect the phase difference between the digital input signal (DIN) and the PWM pulse signal and to generate a triangle wave signal (TRI) by varying the triangle wave frequency to correct the phase or frequency error.

[0101] Through the above-described configuration, the digital amplifier for correcting pulse errors according to the present invention not only improves the distortion of the output audio signal by minimizing the pulse error between the digital input signal (DIN) pulse-width modulated according to audio information and the PWM pulse signal at the subsequent stage, but also improves the characteristics of the error amplifier (200), and has the effect of minimizing the wafer area and production cost when implemented as a semiconductor integrated circuit.

[0102] While the present invention has been described and illustrated based on preferred embodiments to illustrate the principles of the present invention, the present invention is not limited to the configuration and operation as illustrated and described. It should be understood that the embodiments described above are exemplary in all respects and not restrictive. The scope of the present invention is defined by the following claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

[0103]

[0104] [Explanation of symbols]

[0105] 10, 100: Triangle wave generator

[0106] 110: Frequency detection unit 111: Phase detection unit

[0107] 1111: Edge detection unit 1112: Reset unit

[0108] 112: Pulse-voltage converter 1121 charging switch

[0109] 1122: Discharge switch

[0110] 120: Voltage-current converter 121: Up switch

[0111] 122: Down switch

[0112] 130: Triangle wave generator 131: Upper and lower limit setting section

[0113] 132: Latch section

[0114] 20, 200: Error amplifier 30, 300: Comparator

[0115] 40, 400: Switch driver 50, 500: Output stage

[0116] AIN: Analog input signal DIN, DIN1, DIN2: Digital input signal

[0117] PL, PL1, PL2: Comparison pulse signals DPL1, DPL2: Driving pulse signals

[0118] OUT, OUT1, OUT2: Output switching signals

[0119] VCM: Common Mode Voltage

[0120] VC: Control voltage TRI: Triangle signal

[0121] VH: Upper level VL: Lower level

[0122] UP: Ground pulse DN: Leading pulse

[0123] SC: Charge control signal SD: Discharge control signal

[0124] Icpc: Conversion charge current Icpd: Conversion discharge current

[0125] Itrc: Variable charge current Itrd: Variable discharge current

[0126] Ccp: Conversion capacitor Ctr: Triangle wave capacitor

[0127] REF: Reference pulse input terminal CK: Comparison pulse input terminal

Claims

1. In a digital amplifier configured to amplify a pulse-width modulated (PWM) digital input signal and output a pulse-width modulated output switching signal, An error amplifier that outputs an error signal for an error between the digital input signal and the output switching signal; A triangle wave generator corresponding to the switching frequency of the output switching signal and outputting a triangle wave signal as a carrier signal of the pulse width modulation; and It includes a comparison unit that compares the error signal and the triangle wave signal and outputs a comparison pulse signal, A digital amplifier characterized in that the triangle wave generation unit generates the triangle wave signal by comparing the PWM pulse signal of the rear end of the comparison unit including the comparison pulse signal with the digital input signal to correct the phase or frequency error between the PWM pulse signal and the digital input signal.

2. In paragraph 1, The above triangle wave generator is, A frequency detection unit that compares the PWM pulse signal and the digital input signal and outputs a control voltage reflecting the phase or frequency error; and A digital amplifier characterized by including a triangle wave oscillation unit that controls oscillation to generate the triangle wave signal between preset upper and lower levels, and outputs the triangle wave frequency of the triangle wave signal by varying it according to the control voltage.

3. In paragraph 2, The above triangle wave generator further includes a voltage-current converter that outputs a variable current whose size is variable according to the control voltage, A digital amplifier characterized in that the above triangle wave oscillator is configured to vary the triangle wave frequency according to the variable current.

4. In paragraph 2, The above frequency detection unit, At least one phase detection unit that compares the phase of the PWM pulse signal and the digital input signal and outputs a lag pulse and a leading pulse, respectively, to indicate whether the phase is lag or leading; and A digital amplifier characterized by including a pulse-voltage conversion unit that outputs the control voltage in a variable manner according to a charge control signal and a discharge control signal input based on the ground pulse and the leading pulse.

5. In paragraph 4, Each of the above one or more phase detectors, An edge detection unit having a reference pulse input terminal into which a reference pulse is input based on the digital input signal or its inverted signal and a comparison pulse input terminal into which a comparison pulse is input based on the PWM pulse signal or its inverted signal, and outputting the leading pulse when the phase of the PWM pulse signal is ahead of the digital input signal and outputting the lagging pulse when the phase of the PWM pulse signal is behind the digital input signal; and A digital amplifier characterized by including a reset unit that resets the edge detection unit so that the leading pulse and the ground pulse occur during a phase difference section between the digital input signal and the PWM pulse signal.

6. In paragraph 4, The above pulse-voltage converter, A conversion capacitor charged with the above control voltage; A charging switch that receives the ground pulse as the charging control signal and controls the conduction of the conversion charging current to the conversion capacitor according to the charging control signal, thereby controlling the size of the control voltage; and A digital amplifier characterized by including a discharge switch that receives the above-mentioned pulse as the discharge control signal and controls the conduction of the conversion discharge current from the conversion capacitor according to the discharge control signal, thereby controlling the size of the control voltage.

7. In paragraph 5, The frequency detection unit is configured to include two phase detection units that detect a phase difference by comparing the edges of the reference pulse and the comparison pulse input to each of the reference pulse input terminals and the comparison pulse input terminals, respectively. One of the two phase detection units is configured to detect a phase difference based on the rising edge of the reference pulse and the comparison pulse and output the leading pulse or the lagging pulse, A digital amplifier characterized in that the other of the two phase detection units is configured to detect a phase difference based on the falling edge of the reference pulse and the comparison pulse and output the leading pulse or the lagging pulse.

8. In paragraph 7, The above charging control signal is configured to include a ground pulse of each of the two phase detectors, A digital amplifier characterized in that the discharge control signal is configured to include a leading pulse of each of the two phase detectors.

9. In paragraph 3, The above variable current includes a variable charging current and a variable discharging current whose size is changed by the control voltage, The above voltage-current conversion unit is, An up switch that controls the conduction of the variable charging current so that the triangle wave signal rises from the lower limit level to the upper limit level; and A digital amplifier characterized by including a down switch that controls the conduction of the variable discharge current so that the triangle wave signal rises from the upper limit level to the lower limit level.

10. In paragraph 9, The above triangle wave generator is, A triangle wave capacitor that is charged by the variable charging current and discharged by the variable discharging current to form the triangle wave signal; An upper and lower limit setting unit configured to compare the triangle signal with an upper limit reference level and a lower limit reference level and output an upper limit detection signal and a lower limit detection signal, respectively, when the triangle signal reaches the upper limit level or the lower limit level; and A digital amplifier characterized by including a latch unit that receives the upper limit detection signal and the lower limit detection signal, conducts the down switch from the upper limit detection signal to the lower limit detection signal, and conducts the up switch from the lower limit detection signal to the upper limit detection signal.

11. In paragraph 10, A digital amplifier characterized in that the frequency of the triangle wave signal varies as the magnitudes of the variable charging current and the variable discharging current vary.

12. In paragraph 1, A switch driving unit that amplifies the voltage and / or current of the comparison pulse signal received from the comparison unit or shifts the voltage level to provide a driving pulse signal for driving the output stage of the subsequent stage; and It includes a switch element that performs a switching operation according to the driving pulse signal, and further includes an output stage that outputs an output switching signal by the switching operation of the switch element. A digital amplifier characterized in that the PWM pulse signal includes any one of the comparison pulse signal, the driving pulse signal, and the output switching signal, or any one of the inversion signals of each of the comparison pulse signal, the driving pulse signal, and the output switching signal.

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