Sic composite substrate and method for manufacturing same

Abstract

This method for manufacturing a SiC composite substrate includes: a step of providing a single crystal SiC substrate having a graphene film formed on a main surface; a step of epitaxially growing a single crystal SiC layer on the main surface of the single crystal SiC substrate via the graphene film; a step of peeling the single crystal SiC layer from the graphene film; and a step of laminating the single crystal SiC layer by interposing an adhesive layer containing a metal compound on a main surface of a polycrystalline SiC substrate.

Description

SiC composite substrate and method of manufacturing same

[0001] The present disclosure relates to a SiC composite substrate and a method for manufacturing the same.

[0002] Conventionally, SiC-based devices such as Schottky barrier diodes (SBDs) and metal oxide semiconductor field effect transistors (MOSFETs) have been used for power control applications. Single-crystal SiC substrates on which such SiC-based devices are formed are typically manufactured by a sublimation recrystallization method known as the modified Lely method. However, this method has drawbacks, such as low efficiency in crystal growth and wafer processing, resulting in high manufacturing costs.

[0003] Therefore, in order to reduce the manufacturing cost, there has been provided a technique for producing a SiC composite substrate by growing a polycrystalline SiC substrate on a single-crystal SiC layer by chemical vapor deposition (CVD) or by bonding a single-crystal SiC layer to a polycrystalline SiC substrate (see Patent Documents 1 and 2, and Non-Patent Document 1). On the other hand, there has also been proposed a technique for producing a SiC composite substrate by sandwiching a tungsten film and a silicon film between the surfaces of two SiC semiconductor components and laminating them, and then heat-treating the SiC composite substrate to form a WSi ２ A technique for forming a mixture of the above is disclosed (Patent Document 3).

[0004] International Publication No. 2021 / 020574 International Publication No. 2017 / 047509 Special Publication No. 2003-509843

[0005] IEEE Int. SOI Conf. Proc., Oct 1995, pp. 178-179, Bruel et al

[0006] However, when a polycrystalline SiC substrate is fabricated by CVD, tensile or compressive stress is generated during growth, which can cause the substrate to warp. Furthermore, when a SiC composite substrate is fabricated by bonding, the bonding surfaces must be flattened in advance by chemical mechanical polishing (CMP) or the like.

[0007] The present disclosure has been proposed in view of the above-described circumstances, and aims to provide a SiC composite substrate and a manufacturing method thereof that do not cause warping of the substrate or require flattening of the bonding surfaces.

[0008] In order to solve the above-mentioned problems, the SiC composite substrate of the present disclosure includes a polycrystalline SiC substrate, a single-crystal SiC layer laminated on the polycrystalline SiC substrate, and an adhesive layer containing a metal compound interposed between the polycrystalline SiC substrate and the single-crystal SiC layer.

[0009] The method for manufacturing a SiC composite substrate according to the present disclosure includes the steps of providing a single-crystal SiC substrate having a graphene film formed on a main surface thereof, epitaxially growing a single-crystal SiC layer on the main surface of the single-crystal SiC substrate via the graphene film, peeling the single-crystal SiC layer from the graphene film, and stacking the peeled single-crystal SiC layer on the main surface of a polycrystalline SiC substrate with an adhesive layer containing a metal compound interposed therebetween.

[0010] FIG. 1 is a cross-sectional view of a SiC composite substrate of the present embodiment. FIG. 2 is a cross-sectional view of a SiC composite substrate of Modification 1. FIG. 3 is a cross-sectional view of a SiC composite substrate of Modification 2. FIG. 4A is a process flow diagram (first half) of a method for manufacturing the SiC composite substrate 1 of FIG. 1. FIG. 4B is a process flow diagram (first half) of a method for manufacturing the SiC composite substrate 1 of FIG. 1. FIG. 4C is a process flow diagram (first half) of a method for manufacturing the SiC composite substrate 1 of FIG. 1. FIG. 4D is a process flow diagram (first half) of a method for manufacturing the SiC composite substrate 1 of FIG. 1. FIG. 5A is a process flow diagram (second half) of a method for manufacturing the SiC composite substrate 1 of FIG. 1. FIG. 5B is a process flow diagram (second half) of a method for manufacturing the SiC composite substrate 1 of FIG. 1. FIG. 5C is a process flow diagram (second half) of a method for manufacturing the SiC composite substrate 1 of FIG. 1. FIG. 5D is a process flow diagram (second half) of a method for manufacturing the SiC composite substrate 1 of FIG. 1. 5E is a process flow diagram (second half) of the method for manufacturing the SiC composite substrate 1 of FIG. 1. FIG. 6 is a cross-sectional view illustrating a method for manufacturing the SiC composite substrate of Modification 1. FIG. 7 is a view illustrating a method for manufacturing a single-crystal SiC layer used in the SiC composite substrate of Modification 1. FIG. 8 is a cross-sectional view illustrating a method for manufacturing the SiC composite substrate of Modification 2. FIG. 9 is a cross-sectional view showing components including a single-crystal SiC layer in the manufacturing process of the SiC composite substrate of Modification 2. FIG. 10 is a cross-sectional view of a Schottky barrier diode. FIG. 11 is a cross-sectional view of a trench-gate MOSFET. FIG. 12 is a cross-sectional view of a planar-gate MOSFET.

[0011] [Detailed Description] Hereinafter, embodiments of the SiC composite substrate and its manufacturing method according to the present disclosure will be described in detail with reference to the drawings. The embodiments are comprehensive or specific examples. The numerical values, shapes, materials, components, component installation positions, and connection forms shown in the embodiments are merely examples and are not intended to limit the scope of the present disclosure. Furthermore, among the components in the following embodiments, components that are not recited in the independent claims that represent the highest concepts will be described as optional components. Furthermore, the dimensional proportions in the drawings are exaggerated for the sake of explanation and may differ from the actual proportions. Furthermore, the following embodiments and their variations may include similar components, and similar components will be assigned common reference numerals, and redundant explanations will be omitted.

[0012] 1 is a cross-sectional view showing a SiC composite substrate 1 according to the present embodiment. The SiC composite substrate 1 includes a polycrystalline SiC substrate 11 and a single-crystal SiC layer 13 laminated thereon, and the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13 are bonded together by an adhesive layer 12 interposed between the top surface of the polycrystalline SiC substrate 11 and the bottom surface of the single-crystal SiC layer 13.

[0013] The polycrystalline SiC substrate 11 may be formed by deposition using CVD. The polycrystalline SiC substrate 11 may have a crystal polytype of 4H, or may have other crystal polytypes such as 6H or 3C. The adhesive layer 12 is made of tungsten silicide (WSi), which is a metal compound of metallic tungsten (W) and nonmetallic silicon (Si). ２ As will be described later, the adhesive layer 12 is formed by diffusing and reacting a non-metallic Si layer and a metallic W layer, which are interposed as interface layers between the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13, through heating. ２ The metal alloy layer contains

[0014] Similarly, as will be described later, the single-crystal SiC layer 13 is formed by epitaxially growing the single-crystal SiC substrate surface so as to transfer the crystal structure of the single-crystal SiC substrate surface via a thin film of graphene. The single-crystal SiC layer 13 may have a 4H crystal polytype or other crystal polytypes such as 6H or 3C. The thickness of the single-crystal SiC layer 13 may be 2 μm or more. The defect density of basal plane dislocations in the single-crystal SiC layer 13 is 1×10 １ From 1 x 10 ３ It may be in the range of.

[0015] The polycrystalline SiC substrate 11 and the single-crystal SiC layer 13 are doped with impurities. The doped impurities may be n-type impurities such as nitrogen (N) and phosphorus (P). The concentration of the impurities doped in the polycrystalline SiC substrate 11 is 1×10 １９ cm －３ From 1 x 10 ２０ cm －３ The concentration of the impurity added to the single crystal SiC layer 13 may be in the range of 1×10 １６ cm －３ From 5 x 10 １８ cm －３ It may be in the range of.

[0016] The SiC composite substrate 1 of this embodiment has a WSi layer between the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13. ２ The SiC composite substrate 1 is constructed with an adhesive layer 12 formed of a material such as a silicon dioxide film. Such a SiC composite substrate 1 can be manufactured without warping the substrate or requiring flattening of the bonding surfaces. Therefore, the burden on the single-crystal SiC layer 13 of the SiC composite substrate 1 is small, and a high-quality single-crystal SiC layer 13 with few crystal defects can be ensured.

[0017] 2 is a cross-sectional view showing a SiC composite substrate 2 of Modification 1. The SiC composite substrate 2 of Modification 1 differs from the SiC composite substrate 1 of FIG. 1 , which is composed of a single crystal SiC layer 13 having a single impurity concentration, in that the single crystal SiC layer 13 is composed of a first single crystal SiC layer 13a doped with an impurity at a first concentration and a second single crystal SiC layer 13b doped with an impurity at a second concentration lower than the first concentration, which are stacked in this order. Other components of the SiC composite substrate 2 of Modification 1 are similar to those of the SiC composite substrate of FIG. 1 , and therefore corresponding components are designated by common reference numerals to clarify the correspondence.

[0018] In the SiC composite substrate 2 of the first modification, the first concentration of impurities in the first single-crystal SiC layer 13a is, for example, 10 １８ cm －３ On the other hand, the second concentration of impurities in the second single-crystal SiC layer 13b is, for example, 10 １６ cm －３ The second impurity concentration in the second single crystal SiC layer 13b may be one or more orders of magnitude smaller than the first impurity concentration in the first single crystal SiC layer 13a, so that the second impurity concentration in the second single crystal SiC layer 13b is in the order of magnitude smaller than the first impurity concentration in the first single crystal SiC layer 13a. Note that although the single crystal SiC layer 13 of the SiC composite substrate 2 of Modification 1 is composed of two layers, the first single crystal SiC layer 13a and the second single crystal SiC layer 13b, the single crystal SiC layer 13 may be composed of three or more layers, each having a different impurity concentration. In this case, the impurity concentration in each layer may gradually decrease from the lower layer to the upper layer.

[0019] In SiC composite substrate 2 of Modification 1, single-crystal SiC layer 13 is composed of two layers, namely, first single-crystal SiC layer 13 a and second single-crystal SiC layer 13 b. Therefore, when a semiconductor device is constructed using single-crystal SiC layer 13 as a drift layer, forming two layers with different concentrations in the drift layer can provide a function such as a buffer layer.

[0020] 3 is a cross-sectional view showing a SiC composite substrate 3 of Modification 2. The SiC composite substrate 3 of Modification 2 differs from the SiC composite substrate 1 of FIG. 1 in which the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13 are in contact with the adhesive layer 12 in that a first adhesive layer 18 is interposed between the polycrystalline SiC substrate 11 and the adhesive layer 12, and a second adhesive layer 19 is interposed between the adhesive layer 12 and the single-crystal SiC layer 13. The other configuration of the SiC composite substrate 3 of Modification 2 is similar to that of the SiC composite substrate 1 of FIG. 1, and therefore, corresponding components will be designated by common reference numerals to clarify the correspondence.

[0021] In the SiC composite substrate 3 of Modification 2, the first adhesion layer 18 and the second adhesion layer 19 are made of titanium (Ti). The Ti in the first adhesion layer 18 improves adhesion between the polycrystalline SiC substrate 11 and the adhesive layer 12. Similarly, the Ti in the second adhesion layer 19 improves adhesion between the adhesive layer 12 and the single-crystal SiC layer 13. Note that only one of the first adhesion layer 18 and the second adhesion layer 19 may be present, rather than both. For example, the second adhesion layer 19 may be interposed between the adhesive layer 12 and the single-crystal SiC layer 13, but the polycrystalline SiC substrate 11 and the adhesive layer 12 may be in contact with each other without the first adhesion layer being interposed between them. Note that the first adhesion layer 18 and the second adhesion layer 19 are not limited to Ti, and may be made of molybdenum (Mo), tantalum (Ta), or zirconium (Zr).

[0022] In the SiC composite substrate 3 of the second modification, a first adhesion layer 18 is interposed between the polycrystalline SiC substrate 11 and the adhesive layer 12, and a second adhesion layer 19 is interposed between the adhesive layer 12 and the single-crystal SiC layer 13. This ensures adhesion between the polycrystalline SiC substrate 11 and the adhesive layer 12, and between the single-crystal SiC layer 13 and the adhesive layer 12, ensuring a robust structure that will not peel off even when stress is applied.

[0023] (Method for Manufacturing SiC Composite Substrate) Next, an embodiment of a method for manufacturing a SiC composite substrate will be described. Here, the manufacturing method will be described by taking the SiC composite substrate 1 shown in FIG.

[0024] 4A to 4D are process flow diagrams (first half) of a method for manufacturing the SiC composite substrate 1 of FIG. 1 . FIGS. 4A to 4D show steps for fabricating the single-crystal SiC layer 13 of the SiC composite substrate 1 of FIG. 1 . As shown in FIG. 4A , a single-crystal SiC substrate 21 having a graphene film 22 formed on its main surface is first provided. The single-crystal SiC substrate 21 may be formed by a sublimation method or a solution method. The single-crystal SiC substrate 21 may be, for example, a 4H polytype substrate with a (0001) main surface. However, the single-crystal SiC substrate 21 is not limited to this, and may be of other polytypes such as 6H or 3C, and the main surface may have another crystal plane.

[0025] The graphene film 22 formed on the main surface of the single crystal SiC substrate 21 may be zero layers in which graphene extending two-dimensionally is covalently bonded to atoms on the main surface of the single crystal SiC substrate 21, or may be formed from at most a few layers of graphene. The graphene film 22 may be deposited by CVD or may be formed by pyrolyzing the main surface of the single crystal SiC substrate 21.

[0026] As shown in FIG. 4B , a single-crystal SiC layer 23 is grown by epitaxy on the main surface of a single-crystal SiC substrate 21 via a graphene film 22. Van der Waals forces are exerted on the single-crystal SiC layer 23 from SiC atoms constituting the main surface of the single-crystal SiC substrate 21 via the graphene film 22. As a result, the crystal structure of the main surface of the single-crystal SiC substrate 21 is transferred to the single-crystal SiC layer 23. The single-crystal SiC layer 23 can be formed by epitaxy to a thickness of, for example, 2 μm or more. The defect density of basal plane dislocations in the single-crystal SiC layer 23 is 1×10 １ From 1 x 10 ３ The single crystal SiC layer 23 is doped with an impurity. The doped impurity may be an n-type impurity such as nitrogen (N) or phosphorus (P), and the concentration of the impurity may be in the range of 1×10 １６ cm －３ From 5 x 10 １８ cm －３ It may be in the range of.

[0027] As shown in FIG. 4C , a stress layer 24 is formed on the single-crystal SiC layer 23, and tape 25 is attached to the stress layer 24. The stress layer 24 is made of nickel (Ni) and applies stress to the single-crystal SiC layer 23 so that the single-crystal SiC layer 23 peels off from the graphene film 22. The Ni layer that becomes the stress layer 24 may be formed by vapor deposition or sputtering. Note that the stress layer 24 is not limited to Ni, and may be made of other materials such as silicon nitride (SiN) or diamond-like carbon (DLC). The tape 25 may be a thermal peeling tape that peels off when heated.

[0028] As shown in Fig. 4D, a single-crystal SiC layer 23 formed on a main surface of a single-crystal SiC substrate 21 via a graphene film 22 is peeled off. The two-dimensionally formed graphene film 22 and the single-crystal SiC layer 23 are bonded by van der Waals forces, and stress is applied to the single-crystal SiC layer via a stress layer 24. Therefore, the single-crystal SiC layer 23 can be easily peeled off from the graphene film 22 by applying force to a tape 25 supporting the single-crystal SiC layer via the stress layer 24. The peeled single-crystal SiC layer 23 is supported by the tape 25 via the stress layer 24. This single-crystal SiC layer 23 corresponds to the single-crystal SiC layer 13 of the SiC composite substrate 1 in Fig. 1.

[0029] 5A to 5E are process flow diagrams (second half) of the method for manufacturing the SiC composite substrate 1 of FIG. 1. FIGS. 5A to 5E show the steps of laminating a single-crystal SiC layer 13 on a polycrystalline SiC substrate 11. First, as shown in FIG. 5A, a polycrystalline SiC substrate 11 is provided. The polycrystalline SiC substrate 11 may have a crystalline polytype of 4H, or may have other crystalline polytypes such as 6H or 3C. The polycrystalline SiC substrate 11 may be formed by deposition using CVD. An impurity is added to the polycrystalline SiC substrate 11. The added impurity may be an n-type impurity, similar to the single-crystal SiC layer 23, and the impurity concentration may be 1×10 １９ cm －３ From 5 x 10 ２０ cm －３ It may be in the range of.

[0030] 5B, a W layer 15 and a Si layer 16 are sequentially stacked on the main surface of the polycrystalline SiC substrate 11. The W layer 15 may be deposited by evaporation or sputtering, and the Si layer 16 may be deposited by CVD.

[0031] 5C , a W layer 15 and a Si layer 16 are similarly laminated in this order on the main surface of the single-crystal SiC layer 23 peeled off from the graphene film 22 in FIG. 4D . The W layer 15 may be deposited by vapor deposition or sputtering, and the Si layer 16 may be deposited by CVD. The single-crystal SiC layer 23 is supported by a tape 25 via a Ni layer of the stress layer 24. Then, as shown in FIG. 5D , the main surface of the single-crystal SiC layer 23, on which the W layer 15 and the Si layer 16 are laminated, is arranged so that the main surface faces the main surface of the polycrystalline SiC substrate 11 on which the W layer 15 and the Si layer 16 are laminated.

[0032] 5E , the W layer 15 and the Si layer 16 stacked on the polycrystalline SiC substrate 11 and the single-crystal SiC layer 23, respectively, are placed so that the Si layer 16 faces and contacts each other, and the tape 25 is removed to form the laminate 4. If the tape 25 is a thermal peeling tape, the tape 25 is heated and removed. In the laminate 4, the W layer 15, the Si layer 16, the Si layer 16, and the W layer 15 are stacked between the main surface of the polycrystalline SiC substrate 11 and the main surface of the single-crystal SiC layer 13, from the polycrystalline SiC substrate 11 toward the single-crystal SiC layer 23. The layer interposed between the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13 will be referred to as the interface layer 20.

[0033] Thereafter, the stacked body 4 is heated, and W of the W layer 15 and Si of the Si layer 16 of the interface layer 20 react with each other to form tungsten silicide (WSi ２ The heat treatment causes Si in the Si layer 16 to diffuse into the W layer 15, forming an adhesive layer 12 made of WSi ２ After the adhesive layer 12 is formed, the Ni layer of the stress layer 24 laminated on the single-crystal SiC layer 23 is removed by etching or the like. Through this series of steps, the SiC composite substrate 1 shown in FIG. 1 is obtained. The single-crystal SiC layer 23 in the laminate 4 in FIG. 5E becomes the single-crystal SiC layer 13 in the SiC composite substrate 1 shown in FIG. 1.

[0034] According to the method for manufacturing the SiC composite substrate 1 shown in FIG. 1, W in the W layer 15 of the interface layer 20 reacts with Si in the Si layer 16 to form WSi ２ The polycrystalline SiC substrate 11 and the single-crystal SiC layer 23 are bonded together by forming an adhesive layer 12 made of the above. This allows the SiC composite substrate 1 to be manufactured without warping of the substrate or the need to flatten the bonding surfaces.

[0035] Furthermore, the single crystal SiC layer 13 of the SiC composite substrate 1 is formed by epitaxially growing a graphene film 22 on a single crystal SiC substrate 21, peeling it off, placing it on the polycrystalline SiC substrate 11 with an interface layer 20 interposed therebetween, and then bonding the interface layer 20 to the polycrystalline SiC substrate 11 by heating as the adhesive layer 12. In this way, the single crystal SiC layer 13 is formed by epitaxially growing a graphene film 22 on a single crystal SiC substrate 21, and is bonded to the polycrystalline SiC substrate 11 by heating. Since the single crystal SiC layer 13 is formed by epitaxially growing a graphene film 22 on a single crystal SiC substrate 21 and is not subjected to any processing, the burden on the single crystal SiC layer 13 is small, and a high-quality single crystal SiC layer 13 with few crystal defects can be ensured.

[0036] 6 is a cross-sectional view illustrating a manufacturing method of the SiC composite substrate 2 of the first modification shown in FIG. 2. The manufacturing method of the SiC composite substrate 2 of the first modification uses a single-crystal SiC layer 23 in which a first single-crystal SiC layer 23a containing an impurity doped at a first concentration and a second single-crystal SiC layer 23b containing an impurity doped at a second concentration are stacked, which differs from the manufacturing method of the SiC composite substrate 1 of FIG. 1 shown in FIGS. 4A to 4D and 5A to 5E , which uses a single-crystal SiC layer 23 composed of a single layer. Since the other configurations are the same as those in the manufacturing method of the SiC composite substrate 1 of FIG. 1, the corresponding components will be designated by common reference numerals to clarify the correspondence.

[0037] 6 corresponds to FIG. 5D of the manufacturing process of the SiC composite substrate 1 in FIG. 1, and a main surface of a single-crystal SiC layer 23, similarly formed by laminating a W layer 15 and a Si layer 16, is disposed opposite the main surface of a polycrystalline SiC substrate 11, formed by laminating a W layer 15 and a Si layer 16. The single-crystal SiC layer 23 is formed by laminating a first single-crystal SiC layer 23a and a second single-crystal SiC layer 23b. Note that the stress layer 24 and tape 25 shown in FIG. 5D are omitted from the illustration.

[0038] 1 shown in Fig. 5E, the W layer 15 and the Si layer 16 of the W layer 15 and the Si layer 16 laminated on the polycrystalline SiC substrate 11 and the single-crystal SiC layer 23, respectively, are placed so that they face each other and contact each other, thereby forming an interface layer 20 between the polycrystalline SiC substrate 11 and the single-crystal SiC layer 23. Then, by heating, the W of the W layer 15 and the Si of the Si layer 16 of the interface layer 20 react with each other to form WSi ２ After the adhesive layer 12 is formed, the Ni layer of the stress layer 24 is removed by etching or the like.

[0039] By these steps, the SiC composite substrate 2 of the first modification shown in Fig. 2 is obtained. The single crystal SiC layer 23 in Fig. 6 becomes the single crystal SiC layer 13 in the SiC composite substrate 2 shown in Fig. 2, and the first single crystal SiC layer 23a and the second single crystal SiC layer 23b become the first single crystal SiC layer 13a and the second single crystal SiC layer 13b.

[0040] 7 is a cross-sectional view illustrating a method for manufacturing the single-crystal SiC layer 23 formed by stacking the first single-crystal SiC layer 23a and the second single-crystal SiC layer 23b shown in FIG. 6. The first single-crystal SiC layer 23a, to which an impurity is added at a first concentration, is grown by epitaxy on the main surface of the single-crystal SiC substrate 21, and then the second single-crystal SiC layer 23b, to which an impurity is added at a second concentration, is grown. Here, the first impurity concentration in the first single-crystal SiC layer 23a is, for example, 10 １８ cm －３ The second concentration of impurities in the second single-crystal SiC layer 23b is, for example, 10 １６ cm －３The second impurity concentration of the second single crystal SiC layer 23b may be one or more orders of magnitude smaller than the first impurity concentration of the first single crystal SiC layer 23a, so that the second impurity concentration of the second single crystal SiC layer 23b is in the order of magnitude smaller than the first impurity concentration of the first single crystal SiC layer 23a. The single crystal SiC layer 13 of the SiC composite substrate 2 of Modification 1 may be composed of three or more layers, each having a different impurity concentration. In this case, the impurity concentration of each layer may gradually decrease from the lower layer to the upper layer. Other steps for fabricating the single crystal SiC layer 23 are similar to the steps for fabricating the single crystal SiC layer 23 shown in Figures 4A to 4D.

[0041] Here, a specific example of a method for manufacturing the SiC composite substrate 2 of the first modification in Fig. 2 will be described. First, a 4H single crystal SiC substrate 21 was heated at a high temperature of 1500°C or higher in an argon (Ar) atmosphere at atmospheric pressure, and a graphene film 22 consisting of one or two layers was grown on the main surface by a pyrolysis method. Then, silane (SiH ４ ) and propane (C ３ H ８ ) as a precursor, a single-crystal SiC layer 23 having a thickness of 3 μm was grown on the graphene film 22 by epitaxy. At this time, Ar was used as a carrier gas, and nitrogen gas (N ２ By appropriately controlling the flow rate, the concentration of the impurities added to the single-crystal SiC layer 23 was adjusted to 2×10 of the first single-crystal SiC layer 23 a depending on the distance from the boundary with the graphene film 22. １８ / cm ３ and 5×10 of the second single-crystal SiC layer 23b. １６ / cm ３ It was made to have two regions.

[0042] A 5 μm thick DLC film was formed on the single-crystal SiC layer 23 as the stress layer 24 by plasma CVD, and then adhesive tape 25 was attached to the stress layer 24 to peel the single-crystal SiC layer 23 from the graphene film 22. A 50 nm thick second adhesion layer 19 made of Ti was vapor-deposited on the main surface of the peeled single-crystal SiC layer 23. Meanwhile, 100 nm thick W layers 15 and 500 nm thick Si layers 16 were alternately formed on the main surface of the polycrystalline SiC substrate 11 grown by CVD on a graphite substrate by sputtering, and then a 100 nm thick W layer 15 was further formed. After bonding the two together to form the interface layer 20, the tape 25 was removed, and the interface layer 20 was heated at 1000° C. in an Ar atmosphere to react the W layer 15 and Si layer 16 of the interface layer 20, resulting in a WSi ２ Finally, the DLC film was removed by burning it off by heating at 600° C. or higher in the atmosphere, thereby obtaining the SiC composite substrate 2 of the first modified example shown in FIG.

[0043] 2 , the single-crystal SiC layer 23 is epitaxially grown on the single-crystal SiC substrate 21 via the graphene film 22. This makes it possible to easily fabricate two layers, the first single-crystal SiC layer 13a and the second single-crystal SiC layer 13b, which have different concentrations of added impurities.

[0044] Figure 8 is a cross-sectional view illustrating a method for manufacturing the SiC composite substrate 3 of Modification 2 shown in Figure 3. The method for manufacturing the SiC composite substrate 3 of Modification 2 differs from the method for manufacturing the polycrystalline SiC substrate 11 of Figure 1 in that alternately stacked W layers 15 and Si layers 16 are deposited on the main surface of the polycrystalline SiC substrate 11 with a first adhesion layer 18 made of Ti interposed therebetween, and a second adhesion layer 19 made of Ti is deposited on the main surface of the single-crystal SiC layer 23. Since the other configurations are the same as those in the method for manufacturing the SiC composite substrate 1 of Figure 1, corresponding components are designated by common reference numerals to clarify the correspondence.

[0045] FIG. 8 corresponds to FIG. 5D of the manufacturing process of the SiC composite substrate 1 in FIG. 1 . As shown in FIG. 8 , a main surface of a polycrystalline SiC substrate 11, in which W layers 15 and Si layers 16 are alternately stacked with a first adhesion layer 18 made of Ti interposed therebetween, is disposed so that the main surface of a single-crystal SiC layer 23, in which a second adhesion layer 19 made of Ti is stacked, faces the main surface of the polycrystalline SiC substrate 11. The first adhesion layer 18 and the second adhesion layer 19 are formed on the main surface of the polycrystalline SiC substrate 11 and the main surface of the single-crystal SiC layer 23, respectively. The first adhesion layer 18 and the second adhesion layer 19 may be deposited by vapor deposition or sputtering. The alternately stacked W layers 15 and Si layers 16 are formed on the main surface of the polycrystalline SiC substrate 11 with the first adhesion layer 18 interposed therebetween. The W layer 15 may be deposited by vapor deposition or sputtering, and the Si layer 16 may be deposited by CVD. Here, the W layers 15 and Si layers 16 are alternately stacked so that the W layers 15 face the first adhesion layer 18 and the second adhesion layer 19, respectively, and the W layers 15 are the bottom and top layers.

[0046] 1 shown in Fig. 5E, the polycrystalline SiC substrate 11 is placed with the uppermost W layer 15 of the W layers 15 and Si layers 16 alternately stacked with the first adhesion layer 18 interposed therebetween and the second adhesion layer 19 stacked on the single-crystal SiC layer 23 facing each other, and the tape 25 is removed. Between the main surface of the polycrystalline SiC substrate 11 and the main surface of the single-crystal SiC layer 23, an interface layer 20 is formed from the first adhesion layer 18, the alternately stacked W layers 15 and Si layers 16, and the second adhesion layer 19 in the order from the polycrystalline SiC substrate 11 toward the single-crystal SiC layer 23.

[0047] Then, W of the W layer 15 and Si of the Si layer 16 react with each other in the interface layer 20 by heating to form WSi ２ 8 is formed so as to form an adhesive layer 12 composed of the first adhesive layer 18 and the second adhesive layer 19. As a result, the adhesive layer 12 is formed sandwiched between the first adhesive layer 18 and the second adhesive layer 19. After the adhesive layer 12 is formed, the Ni layer of the stress layer 24 is removed by etching or the like. By these steps, the SiC composite substrate 3 of the second modification in FIG. 3 is obtained. The single crystal SiC layer 23 in FIG. 8 becomes the single crystal SiC layer 13 in the SiC composite substrate 3 in FIG. 3.

[0048] 9 is a cross-sectional view showing a component including a single-crystal SiC layer 23 in a manufacturing process of the SiC composite substrate 3 of Variation 2 of FIG. 3 . This component is a laminate including the single-crystal SiC layer 23 in FIG. 8 . As shown in FIG. 4D , this component is formed by forming a stress layer 24 on the single-crystal SiC layer 23 formed on the main surface of the single-crystal SiC substrate 21 with a graphene film 22 interposed therebetween, applying force to tape 25 attached to the stress layer 24 to peel it off from the graphene film 22, and then depositing a second adhesion layer 19 made of Ti on the main surface of the single-crystal SiC layer 23. Here, the Ti of the second adhesion layer 19 may be thin, for example, may have a thickness of about 100 nm.

[0049] 3, in the manufacturing method of the SiC composite substrate 3 of the second modification example, the stress exerted from the second adhesion layer 19 to the single-crystal SiC layer 23 is small in the components shown in Fig. 9. Therefore, the stress exerted from the stress layer 24 to the single-crystal SiC layer 23 is not canceled by the stress exerted from the second adhesion layer 19 to the single-crystal SiC layer 23, and therefore, peeling of the single-crystal SiC layer 23 from the stress layer 24 is prevented.

[0050] (Semiconductor Device) Next, an embodiment of a semiconductor device will be described. The semiconductor device of this embodiment uses a SiC composite substrate 3 of Modification 2 as shown in FIG. 3 , and is configured such that the polycrystalline SiC substrate 11 of the SiC composite substrate 3 serves as a substrate layer and the single-crystal SiC layer 13 serves as a drift layer. As shown in FIG. 3 , the SiC composite substrate 3 of Modification 2 has a first adhesion layer 18, an adhesive layer 12, and a second adhesion layer 19 interposed between the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13. Therefore, the semiconductor device of this embodiment also has a first adhesion layer 18, an adhesive layer 12, and a second adhesion layer 19 interposed between the substrate layer and the drift layer. Below, examples of electronic devices using the SiC composite substrate 3 will be described, including a Schottky barrier diode (SBD), a trench-gate metal oxide semiconductor field effect transistor (MOSFET), and a planar-gate MOSFET.

[0051] 10 is a cross-sectional view of an SBD 30. The SBD 30 is fabricated using the SiC composite substrate 3 of the second modification shown in FIG. 3. The SBD 30 uses a SiC composite substrate 3 in which a single-crystal SiC layer 13 is laminated on a polycrystalline SiC substrate 11 with a first adhesive layer 18, a bonding layer 12, and a second adhesive layer 19 interposed therebetween. In the SiC composite substrate 3 of the SBD 30, the polycrystalline SiC substrate 11 is, for example, 10 １９ / cm ３ From 10 ２０ / cm ３ High concentration of n in the range ＋ The single crystal SiC layer 13 is doped with, for example, 10 １６ / cm ３ From 10 １７ / cm ３ Low concentration n in the range － The polycrystalline SiC substrate 11 is doped with a metal to form a drift layer. The bottom surface of the polycrystalline SiC substrate 11 is covered with a cathode electrode 31, which is connected to a cathode terminal K.

[0052] The top surface 13c of the single-crystal SiC layer 13 is provided with a contact hole 33 that exposes a part of the single-crystal SiC layer 13 as a body region 32, and a field insulating film 35 is formed in a field region 34 surrounding the body region 32. The field insulating film 35 is made of SiO ２ The field insulating film 35 is made of silicon oxide, but may be made of other insulating materials such as silicon nitride (SiN). An anode electrode 36 is formed on the field insulating film 35 and is connected to an anode terminal A.

[0053] A p-type JTE (junction termination extension) structure 37 is formed in the vicinity of the top surface 13c (surface layer portion) of the single-crystal SiC layer 13 so as to contact the anode electrode 36. The JTE structure 37 is formed along the contour of the contact hole 33 in the field insulating film 35 so as to straddle the inside and outside of the contact hole 33.

[0054] 11 is a cross-sectional view of a trench gate MOSFET 40. The trench gate MOSFET 40 is fabricated using the SiC composite substrate 3 of the second modification shown in FIG. 3. The trench gate MOSFET 40 uses a SiC composite substrate 3 in which a single crystal SiC layer 13 is stacked on a polycrystalline SiC substrate 11 with a first adhesive layer 18, a bonding layer 12, and a second adhesive layer 19 interposed therebetween. In the SiC composite substrate 3 of the trench gate MOSFET 40, the polycrystalline SiC substrate 11 is, for example, 10 １９ / cm ３ From 10 ２０ / cm ３ High concentration of n in the range ＋ The single crystal SiC layer 13 is doped with, for example, 10 １６ / cm ３ From 10 １７ / cm ３ Low concentration n in the range － The bottom surface of the polycrystalline SiC substrate 11 is covered with a drain electrode 41, which is connected to a drain terminal D.

[0055] A p-type body region 42 is formed on the top surface 13c of the single-crystal SiC layer 13. In the single-crystal SiC layer 13, the portion on the polycrystalline SiC substrate 11 side relative to the body region 42 is a lightly doped n-type layer that is maintained as the single-crystal SiC layer 13. － The single-crystal SiC layer 13 has a gate trench 44 formed therein. The gate trench 44 penetrates the body region 42 from the top surface 13c of the single-crystal SiC layer 13, and its deepest portion reaches the drain region 43(13).

[0056] A gate insulating film 45 is formed on the inner surface of the gate trench 44 and on the top surface 13c of the single-crystal SiC layer 13 so as to cover the entire inner surface of the gate trench 44. The inside of the gate insulating film 45 is filled with, for example, polysilicon, thereby embedding a gate electrode 46 in the gate trench 44. A gate terminal G is connected to the gate electrode 46.

[0057] The surface layer of the body region 42 is formed with a highly doped n-type impurity dopant (nPt) that forms part of the side surface of the gate trench 44. ＋ The single-crystal SiC layer 13 has a highly doped p-type source region 47 formed therein. The p-type source region 47 is connected to the body region 42 and extends from the top surface 13c of the single-crystal SiC layer 13 through the source region 47. ＋ A mold body contact region 48 is formed.

[0058] On the single crystal SiC layer 13, SiO ２ An interlayer insulating film 51 made of a material other than silicon dioxide is formed on the source region 47. A source electrode 53 is connected to the source region 47 and the body contact region 48 via a contact hole 52 formed in the interlayer insulating film 51. A source terminal S is connected to the source electrode 53.

[0059] By applying a predetermined voltage (a voltage equal to or greater than the gate threshold voltage) to the gate electrode 46 while a predetermined potential difference is generated between the source electrode 53 and the drain electrode 41 (between the source and drain), a channel can be formed in the body region 42 near the interface with the gate insulating film 45 due to the electric field from the gate electrode 46. This allows a current to flow between the source electrode 53 and the drain electrode 41, turning on the trench-gate MOSFET 40.

[0060] 12 is a cross-sectional view of a planar gate MOSFET 60. The planar gate MOSFET 60 is fabricated using the SiC composite substrate 3 of the second modification shown in FIG. 3. The planar gate MOSFET 60 uses a SiC composite substrate 3 in which a single crystal SiC layer 13 is stacked on a polycrystalline SiC substrate 11 with a first adhesive layer 18, a bonding layer 12, and a second adhesive layer 19 interposed therebetween. In the SiC composite substrate 3 of the planar gate MOSFET 60, the polycrystalline SiC substrate 11 is, for example, 10 １９ / cm ３ From 10 ２０ / cm ３ High concentration of n in the range ＋ The single crystal SiC layer 13 is doped with, for example, 10 １６ / cm ３ From 10 １７ / cm３ Low concentration n in the range － The bottom surface of the polycrystalline SiC substrate 11 is covered with a drain electrode 61, which is connected to a drain terminal D.

[0061] A p-type body region 62 is formed in a well shape on the top surface 13c of the single-crystal SiC layer 13. In the single-crystal SiC layer 13, the portion on the polycrystalline SiC substrate 11 side relative to the body region 62 is formed as a lightly doped n-type layer in which the state of the single-crystal SiC layer 13 is maintained as it is. － The surface layer of the body region 62 is a heavily doped n-type drain region 63 (13). ＋ A source region 64 of the type is formed at a distance from the periphery of the body region 62. Inside the source region 64, a heavily doped p ＋ A body contact region 65 is formed on the source region 64. The body contact region 65 penetrates the source region 64 in the depth direction and is connected to the body region 62.

[0062] A gate insulating film 66 is formed on the top surface 13c of the single-crystal SiC layer 13. The gate insulating film 66 covers a portion of the body region 62 surrounding the source region 64 (the peripheral portion of the body region 62) and the outer periphery of the source region 64. A gate electrode 67 made of, for example, polysilicon is formed on the gate insulating film 66. The gate electrode 67 faces the peripheral portion of the body region 62 with the gate insulating film 66 interposed therebetween. A gate terminal G is connected to the gate electrode 67.

[0063] On the single crystal SiC layer 13, SiO ２ An interlayer insulating film 68 made of a material other than silicon dioxide is formed on the source region 64. A source electrode 72 is connected to the source region 64 and the body contact region 65 via a contact hole 71 formed in the interlayer insulating film 68. A source terminal S is connected to the source electrode 72.

[0064] By applying a predetermined voltage (a voltage equal to or greater than the gate threshold voltage) to the gate electrode 67 while a predetermined potential difference is generated between the source electrode 72 and the drain electrode 61 (between the source and drain), a channel can be formed in the body region 62 near the interface with the gate insulating film 66 due to the electric field from the gate electrode 67. This allows a current to flow between the source electrode 72 and the drain electrode 61, turning the planar gate MOSFET 60 on.

[0065] The semiconductor device of this embodiment is fabricated using SiC composite substrate 3 having high-quality single-crystal SiC layer 13 with few crystal defects. Therefore, even in a semiconductor device having a drift layer configured as single-crystal SiC layer 13, quality degradation caused by lattice defects and the like is suppressed, and characteristics are ensured.

[0066] Although the present disclosure has been described in detail above, it will be apparent to those skilled in the art that the present disclosure is not limited to the embodiments described herein. One or more elements of one embodiment can be combined with one or more elements of another embodiment. The present disclosure can be implemented in modified and altered forms without departing from the spirit and scope of the present disclosure, as defined by the claims. Therefore, the description of the present disclosure is intended to be illustrative and explanatory, and is not intended to be limiting of the present disclosure.

[0067] (Supplementary Notes) The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the Supplementary Notes are given the reference symbols of the corresponding components in the embodiments. The reference symbols are shown as examples to aid understanding, and the components described in each Supplementary Note should not be limited to the components indicated by the reference symbols.

[0068] (Note 1) SiC composite substrate 1 has polycrystalline SiC substrate 11, single-crystal SiC layer 13 laminated on polycrystalline SiC substrate 11, and adhesive layer 12 containing a metal compound interposed between polycrystalline SiC substrate 11 and single-crystal SiC layer 13. SiC composite substrate 1 can be manufactured without warping of the substrate or requiring flattening of the bonding surfaces.

[0069] (Supplementary Note 2) In the SiC composite substrate 1 described in Supplementary Note 1, the metal compound may contain W and Si. ２ can be configured.

[0070] (Supplementary Note 3) In the SiC composite substrate 3 described in Supplementary Note 1 or 2, at least one of a first adhesion layer 18 and a second adhesion layer 19 may be provided between the polycrystalline SiC substrate 11 and the adhesive layer 12 and between the single-crystal SiC layer 13 and the adhesive layer 12. The first adhesion layer 18 improves the adhesion between the polycrystalline SiC substrate 11 and the adhesive layer 12, and the second adhesion layer 19 improves the adhesion between the adhesive layer 12 and the single-crystal SiC layer 13.

[0071] (Appendix 4) In the SiC composite substrate 3 described in Appendix 3, the first adhesion layer 18 and the second adhesion layer 19 may contain Ti. Ti can provide adhesion between the first adhesion layer 18 and the second adhesion layer 19. The first adhesion layer 18 and the second adhesion layer 19 are not limited to this, and may contain at least one of Ti, Mo, Ta, and Zr. (Appendix 5) In the SiC composite substrate 1 described in any one of Appendixes 1 to 4, the thickness of the single crystal SiC layer 13 may be 2 μm or more. The single crystal SiC layer 13 can be grown to a thickness of 2 μm or more by epitaxy. (Appendix 6) In the SiC composite substrate 1 described in any one of Appendixes 1 to 5, the defect density of basal plane dislocations in the single crystal SiC layer 13 is 1×10 １ From 1 x 10 ３ By growing a graphene film on the main surface of the single crystal SiC substrate 21 by epitaxy, the defect density of basal plane dislocations can be reduced.

[0072] (Supplementary Note 7) In the SiC composite substrate 1 according to any one of Supplementary Notes 1 to 6, the concentration of impurities added to the single-crystal SiC layer 13 is 1×10 １６ cm －３ From 5 x 10 １８ cm －３ The impurity concentration can be set to a concentration appropriate for the drift layer of the semiconductor device when the single-crystal SiC layer 13 is grown by epitaxy.

[0073] (Supplementary Note 8) In the SiC composite substrate 1 described in any one of Supplementary Notes 1 to 7, the concentration of the impurity added to the single-crystal SiC layer 13 may be set according to the distance from the boundary with the adhesive layer 12. The concentration of the impurity can be appropriately set according to the distance from the boundary with the adhesive layer 12 when the single-crystal SiC layer 13 is grown by epitaxy.

[0074] (Supplementary Note 9) In the SiC composite substrate 1 described in Supplementary Note 8, the concentration of the impurity added to the single-crystal SiC layer 13 may decrease with increasing distance from the boundary with the adhesive layer 12. By decreasing the impurity concentration with increasing distance from the boundary with the adhesive layer 12, it is possible to appropriately set the change in the impurity concentration in the drift layer of the electronic device.

[0075] (Appendix 10) A method for manufacturing a SiC composite substrate 1 includes the steps of providing a single-crystal SiC substrate 21 having a graphene film 22 formed on a main surface thereof, epitaxially growing a single-crystal SiC layer 23 on the main surface of the single-crystal SiC substrate 21 via the graphene film 22, peeling the single-crystal SiC layer 23 from the graphene film 22, and stacking the single-crystal SiC layer 23 on the main surface of a polycrystalline SiC substrate 11 with an adhesive layer 12 containing a metal compound interposed therebetween. The manufacturing method for a SiC composite substrate 1 allows the substrate to be manufactured without warping or requiring flattening of the bonding surfaces.

[0076] (Supplementary Note 11) In the method for manufacturing the SiC composite substrate 1 described in Supplementary Note 10, the step of growing the single-crystal SiC layer 23 may include adding an impurity to the single-crystal SiC layer 23, and the concentration of the impurity may be set according to the distance from the boundary with the graphene film 22. When the single-crystal SiC layer 23 is grown by epitaxy, the concentration of the impurity can be appropriately set according to the length from the boundary with the graphene film 22.

[0077] (Appendix 12) In the method for manufacturing SiC composite substrate 1 described in Appendix 10 or 11, the step of laminating with adhesive layer 12 interposed therebetween may include the steps of forming interface layer 20 including W layer 15 and Si layer 16 between the main surface of polycrystalline SiC substrate 11 and the main surface of single-crystal SiC layer 23, and heating interface layer 20 to react W layer 15 with Si layer 16 to form a metal alloy layer, thereby forming adhesive layer 12. W of W layer 15 and Si of Si layer 16 can be reacted to form adhesive layer 12 made of a metal compound.

[0078] (Supplementary Note 13) In the method for manufacturing a SiC composite substrate described in Supplementary Note 12, the W layer 15 may contain W, and the Si layer 16 may contain Si. W of the W layer 15 may react with Si of the Si layer 16 to form WSi ２ It can be said that:

[0079] (Appendix 14) In the method for manufacturing SiC composite substrate 1 described in Appendix 12 or 13, the step of forming interface layer 20 may include the steps of depositing W layer 15 and Si layer 16, in order, on the main surface of polycrystalline SiC substrate 11 and the main surface of single-crystal SiC layer 23, respectively, and arranging single-crystal SiC layer 23 so that the main surface thereof faces and contacts the main surface of polycrystalline SiC substrate 11 with the deposited W layer 15 and Si layer 16 interposed therebetween. Interface layer 20 can be formed between the main surface of polycrystalline SiC substrate 11 and the main surface of single-crystal SiC layer 23.

[0080] (Appendix 15) In the method for manufacturing the SiC composite substrate 3 described in Appendix 12 or 13, the step of forming the interface layer 20 may include the steps of depositing a first adhesion layer 18 on the main surface of the polycrystalline SiC substrate 11, alternately depositing W layers 15 and Si layers 16 on the main surface of the polycrystalline SiC substrate 11 with the first adhesion layer 18 interposed therebetween, depositing a second adhesion layer 19 on the main surface of the single-crystal SiC layer 23, and arranging the main surface of the single-crystal SiC layer 23 so that the main surface of the single-crystal SiC layer 23 faces and contacts the main surface of the polycrystalline SiC substrate 11 with the first adhesion layer 18, the W layer 15, the Si layer 16, and the second adhesion layer 19 interposed therebetween. Only the second adhesion layer 19 is deposited on the main surface of the single-crystal SiC layer 23, and stress exerted by the second adhesion layer 19 on the single-crystal SiC layer 23 is small.

[0081] (Appendix 16) In the method for manufacturing the SiC composite substrate 1 described in Appendix 15, the step of alternately depositing the W layer 15 and the Si layer 16 may be performed such that the W layer 15 is in contact with each of the first adhesion layer 18 and the second adhesion layer 19. Ti constituting the first adhesion layer 18 and the second adhesion layer 19 can be solid-dissolved in the W layer 15 and adhere to it.

[0082] (Appendix 17) In the method for manufacturing the SiC composite substrate 1 described in Appendix 15 or 16, the first adhesion layer 18 and the second adhesion layer 19 may contain Ti. Ti can realize the adhesion of the first adhesion layer 18 and the second adhesion layer 19. The first adhesion layer 18 and the second adhesion layer 19 are not limited thereto, and may contain at least one of Ti, Mo, Ta, and Zr.

[0083] (Supplementary Note 18) A semiconductor device is configured as a drift layer using the single-crystal SiC layer 13 of the SiC composite substrate 3 according to any one of Supplementary Notes 1 to 9. The single-crystal SiC layer 13 can form the drift layer of the semiconductor device.

[0084] (Supplementary Note 19) The semiconductor device described in Supplementary Note 18 may include at least one of a Schottky barrier diode, a trench gate MOS, and a planar gate MOS. At least one of a Schottky barrier diode, a trench gate MOS, and a planar gate MOS can be configured using the single-crystal SiC layer 13 of the SiC composite substrate 3 as a drift layer.

[0085] REFERENCE SIGNS LIST 1 SiC composite substrate 11 Polycrystalline SiC substrate 12 Adhesion layer 13 Single crystal SiC layer 15 W layer 16 Si layer 18 First adhesion layer 19 Second adhesion layer 21 Single crystal SiC substrate 22 Graphene film 23 Single crystal SiC layer 24 Stress layer 25 Tape 30 Schottky barrier diode 40 Trench gate type MOS 60 Planar gate type MOS

Claims

1. A SiC composite substrate comprising: a polycrystalline SiC substrate; a single-crystal SiC layer laminated on the polycrystalline SiC substrate; and an adhesive layer containing a metal compound interposed between the polycrystalline SiC substrate and the single-crystal SiC layer.

2. The SiC composite substrate according to claim 1, wherein the metal compound contains W and Si.

3. The SiC composite substrate according to claim 1 or 2, further comprising an adhesion layer interposed between at least one of the polycrystalline SiC substrate and the single-crystal SiC layer and the adhesive layer.

4. The SiC composite substrate according to claim 3, wherein the adhesion layer contains at least one of Ti, Mo, Ta and Zr.

5. A SiC composite substrate according to any one of claims 1 to 4, wherein the concentration of impurities added to the single crystal SiC layer is set according to the distance from the boundary with the adhesive layer.

6. The SiC composite substrate according to claim 5, wherein the concentration of the impurities added to the single crystal SiC layer decreases as the distance from the boundary with the adhesive layer increases.

7. The concentration of impurities added to the single crystal SiC layer is 1×10 １６ cm －３ From 5 x 10 １８ cm －３ The SiC composite substrate according to any one of claims 1 to 6, wherein the range is 8. A method for manufacturing a SiC composite substrate, comprising: providing a single crystal SiC substrate having a graphene film formed on a main surface thereof; epitaxially growing a single crystal SiC layer on the main surface of the single crystal SiC substrate via the graphene film; peeling the single crystal SiC layer from the graphene film; and laminating the single crystal SiC layer on the main surface of a polycrystalline SiC substrate with an adhesive layer containing a metal compound interposed therebetween.

9. A method for manufacturing a SiC composite substrate as described in claim 8, wherein the step of growing the single crystal SiC layer includes adding impurities to the single crystal SiC layer, and the concentration of the impurities is set according to the distance from the boundary with the graphene film.

10. A method for manufacturing a SiC composite substrate as described in claim 8 or 9, wherein the step of laminating with an adhesive layer therebetween includes the steps of: forming an interface layer containing a metal layer and a non-metal layer between the main surface of the polycrystalline SiC substrate and the main surface of the single-crystal SiC layer; and heating the interface layer to cause a reaction between the metal layer and the non-metal layer to form a metal alloy layer, thereby forming the adhesive layer.

11. The method for producing a SiC composite substrate according to claim 10, wherein the metal layer contains W and the non-metal layer contains Si.

12. A method for manufacturing a SiC composite substrate as described in claim 10 or 11, wherein the step of forming the interface layer includes the steps of: depositing the metal layer and the non-metal layer, in order, on the main surface of the polycrystalline SiC substrate and the main surface of the single-crystal SiC layer, respectively; and arranging the main surface of the single-crystal SiC layer so that it faces and contacts the main surface of the polycrystalline SiC substrate, with the deposited metal layer and non-metal layer interposed therebetween.

13. A method for manufacturing a SiC composite substrate as described in claim 10 or 11, wherein the step of forming the interface layer includes the steps of: depositing a first adhesion layer on the main surface of the polycrystalline SiC substrate; alternately depositing the metal layer and the non-metal layer on the main surface of the polycrystalline SiC substrate with the first adhesion layer interposed therebetween; depositing a second adhesion layer on the main surface of the single-crystal SiC substrate; and arranging the main surface of the single-crystal SiC layer so that it faces and contacts the main surface of the polycrystalline SiC substrate with the first adhesion layer, the metal layer, the non-metal layer, and the second adhesion layer interposed therebetween.

14. A method for producing a SiC composite substrate as described in claim 13, wherein the step of alternately depositing the metal layer and the non-metal layer deposits the metal layer so that the metal layer contacts the first adhesion layer and the second adhesion layer, respectively.

15. A method for producing a SiC composite substrate according to claim 13 or 14, wherein the first adhesion layer and the second adhesion layer contain at least one of Ti, Mo, Ta, and Zr.

16. A semiconductor device comprising a single crystal SiC layer of the SiC composite substrate according to any one of claims 1 to 7 as a drift layer.

17. The semiconductor device according to claim 16, comprising at least one of a Schottky barrier diode, a trench gate MOS, and a planar gate MOS.

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