SiC COMPOSITE SUBSTRATE AND METHOD FOR MANUFACTURING SAME

Abstract

This SiC composite substrate (1) comprises: a polycrystalline SiC substrate (11); a single crystal SiC layer (13) laminated over the polycrystalline SiC substrate (11); and an SiC bonding layer (12) that is interposed between the polycrystalline SiC substrate (11) and the single crystal SiC layer (13), bonds the polycrystalline SiC substrate (11) and the single crystal SiC layer (13), and includes SiC crystal grains having an aspect ratio in a range greater than 2 and less than 200 with the longitudinal direction defined as the lamination direction.

Description

SiC composite substrate and method of manufacturing same

[0001] The present disclosure relates to a SiC composite substrate and a method for manufacturing the same.

[0002] Conventionally, SiC-based devices such as Schottky barrier diodes (SBDs) and MOSFETs have been used for power control applications. Single-crystal SiC substrates on which such SiC-based devices are formed are typically manufactured by a sublimation recrystallization method known as the modified Lely method. However, this method suffers from the drawback of low efficiency in crystal growth and wafer processing, resulting in high manufacturing costs. To reduce manufacturing costs, techniques have been proposed for fabricating SiC composite substrates by growing a polycrystalline SiC substrate on a single-crystal SiC layer by chemical vapor deposition (CVD) or by bonding a single-crystal SiC layer to a polycrystalline SiC substrate (see Patent Documents 1 and 2, and Non-Patent Document 1).

[0003] International Publication No. 2021 / 020574 International Publication No. 2017 / 047509

[0004] IEEE Int. SOI Conf. Proc., Oct 1995, pp. 178-179, Bruel et al

[0005] However, when a polycrystalline SiC substrate is fabricated by CVD, tensile or compressive stress is generated during growth, which can cause the substrate to warp. Furthermore, when a SiC composite substrate is fabricated by bonding, the bonding surfaces must be flattened in advance by chemical mechanical polishing (CMP) or the like.

[0006] The present disclosure has been proposed in view of the above-described circumstances, and aims to provide a SiC composite substrate and a manufacturing method thereof that do not cause warping of the substrate or require flattening of the bonding surfaces.

[0007] In order to solve the above-described problems, one aspect of the SiC composite substrate of the present disclosure includes a polycrystalline SiC substrate, a single-crystal SiC layer stacked on the polycrystalline SiC substrate, and a SiC bonding layer interposed between the polycrystalline SiC substrate and the single-crystal SiC layer to bond the polycrystalline SiC substrate and the single-crystal SiC layer, the SiC bonding layer including SiC crystal grains having an aspect ratio in the range of greater than 2 and less than 200 with the stacking direction as the longitudinal direction.

[0008] One aspect of the method for manufacturing a SiC composite substrate of the present disclosure includes the steps of providing a polycrystalline SiC substrate, providing a single-crystal SiC layer, stacking the polycrystalline SiC substrate and the single-crystal SiC layer with an interface layer interposed between a main surface of the polycrystalline SiC substrate and a main surface of the single-crystal SiC layer to form a laminate, each interface layer including at least one Si layer and one C layer, and each C layer including a carbon nanotube film or a graphene film, and heating the laminate to react the Si layer and the C layer of the interface layer and induce SiC crystallization to form a SiC bonding layer.

[0009] FIG. 1 is a cross-sectional view of a SiC composite substrate of the present embodiment. FIG. 2 is a cross-sectional view of a SiC composite substrate of Modification 1. FIG. 3A is a process flow diagram of a method for manufacturing the SiC composite substrate of FIG. 1. FIG. 3B is a process flow diagram of a method for manufacturing the SiC composite substrate of FIG. 1. FIG. 3C is a process flow diagram of a method for manufacturing the SiC composite substrate of FIG. 1. FIG. 3D is a process flow diagram of a method for manufacturing the SiC composite substrate of FIG. 1. FIG. 3E is a process flow diagram of a method for manufacturing the SiC composite substrate of FIG. 1. FIG. 3F is a process flow diagram of a method for manufacturing the SiC composite substrate of FIG. 1. FIG. 3G is a process flow diagram of a method for manufacturing the SiC composite substrate of FIG. 1. FIG. 3H is a process flow diagram of a method for manufacturing the SiC composite substrate of FIG. 1. FIG. 3I is a process flow diagram of a method for manufacturing the SiC composite substrate of FIG. 1. FIG. 3J is a process flow diagram of a method for manufacturing the SiC composite substrate of FIG. 1. FIG. 4A is a process flow diagram of a manufacturing method of Modification 2. FIG. 4B is a process flow diagram of a manufacturing method of Modification 2. FIG. 4C is a process flow diagram of a manufacturing method of Modification 2. Fig. 5 is a diagram showing a manufacturing method of Modification 3. Fig. 6 is a diagram showing a manufacturing method of Modification 4. Fig. 7 is a cross-sectional view of a Schottky barrier diode. Fig. 8 is a cross-sectional view of a trench gate MOSFET. Fig. 9 is a cross-sectional view of a planar gate MOSFET.

[0010] [Detailed Description] Hereinafter, embodiments of the SiC composite substrate and its manufacturing method according to the present disclosure will be described in detail with reference to the drawings. The embodiments are comprehensive or specific examples. The numerical values, shapes, materials, components, component installation positions, and connection forms shown in the embodiments are merely examples and are not intended to limit the scope of the present disclosure. Furthermore, among the components in the following embodiments, components that are not recited in the independent claims that represent the highest concepts will be described as optional components. Furthermore, the dimensional proportions in the drawings are exaggerated for the sake of explanation and may differ from the actual proportions. Furthermore, the following embodiments and their variations may include similar components, and similar components will be assigned common reference numerals, and redundant explanations will be omitted.

[0011] 1 is a cross-sectional view showing a SiC composite substrate 1 according to the present embodiment. The SiC composite substrate 1 includes a polycrystalline SiC substrate 11 and a single-crystal SiC layer 13 laminated thereon, and the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13 are bonded together by a SiC bonding layer 12 interposed between the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13.

[0012] The polycrystalline SiC substrate 11 may be formed by deposition on a graphite substrate by CVD. The single-crystal SiC layer 13 may be formed by epitaxy, transferring the crystalline structure of the surface of the single-crystal SiC substrate to the surface of the single-crystal SiC substrate via a graphene film, and then peeling it off from the graphene film. Alternatively, the single-crystal SiC layer 13 may be formed by implanting hydrogen ions to a predetermined depth from the surface of the single-crystal SiC substrate to form a buried layer, embrittling the layer by heating, and then peeling it off, and then separating the portion from the surface to the buried layer. The crystal polytype of the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13 may be a cubic system such as 3C, or a hexagonal system such as 4H or 6H.

[0013] The SiC bonding layer 12 is formed by Si crystallization of the Si layer included in the interface layer interposed between the laminated polycrystalline SiC substrate 11 and single-crystal SiC layer 13, which reacts with the C layer composed of a carbon nanotube film. In the carbon nanotube film constituting the C layer, each carbon nanotube extends longitudinally in the stacking direction. Therefore, the SiC crystal grains in the SiC bonding layer 12 are aligned in the same direction as the carbon nanotubes, resulting in high linearity and uniformity. The SiC crystal grains obtained by SiC crystallization have an aspect ratio, with the stacking direction as the longitudinal direction, in the range of, for example, greater than 2 and less than 200. However, the aspect ratio of the SiC crystal grains may be greater than 2 and less than 100, greater than 2 and less than 50, or greater than 2 and less than 10.

[0014] The SiC composite substrate 1 shown in Figure 1 is configured by bonding a polycrystalline SiC substrate 11 and a single-crystal SiC layer 13 with a SiC bonding layer 12 interposed between the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13. Therefore, there is no need to planarize the bonding surfaces by chemical mechanical polishing (CMP) or the like prior to bonding the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13. Furthermore, there is no need to amorphize the bonding surfaces by irradiating them with an Ar atomic beam, as in room-temperature bonding. Therefore, the crystallinity of the bonding surfaces with the SiC bonding layer 12 is maintained in the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13.

[0015] In the SiC composite substrate 1, the SiC bonding layer 12 that bonds the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13 is made of SiC. Therefore, the SiC composite substrate 1 can fully withstand high-temperature processes at 2000° C. or higher.

[0016] In the SiC composite substrate 1, the SiC bonding layer 12 is formed by Si crystallization, which occurs when Si in the Si layer included in the interface layer interposed between the laminated polycrystalline SiC substrate 11 and the single-crystal SiC layer 13 reacts with C in the C layer composed of a carbon nanotube film. In the carbon nanotube film constituting the C layer, each carbon nanotube extends longitudinally along the stacking direction and is aligned in the same direction as the carbon nanotubes, resulting in high linearity and uniformity. The SiC crystal grains obtained by SiC crystallization also have a high aspect ratio, with the stacking direction as the longitudinal direction. This suppresses stress generated in the two-dimensional direction in which the SiC bonding layer 12 extends, making warpage less likely to occur after the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13 are bonded by the SiC bonding layer 12.

[0017] Furthermore, in the carbon nanotube film included in the interface layer that will form SiC bonding layer 12, the carbon nanotubes are bonded and firmly bonded to the main surface of single-crystal SiC layer 13 at the atomic level. This results in a good bonding interface with few defects and high adhesion between single-crystal SiC layer 13 and SiC bonding layer 12. This results in a good bonding interface with high adhesion between single-crystal SiC layer 13 and SiC bonding layer 12 in SiC composite substrate 1.

[0018] Figure 2 is a cross-sectional view showing a SiC composite substrate 2 that is a modified example of the SiC composite substrate 1 of Figure 1. The modified SiC composite substrate 2 differs from the SiC composite substrate 1 of Figure 1 in which the SiC bonding layer 12 is composed of SiC crystal grains with an aspect ratio in the range of more than 2 and less than 200, with the lamination direction as the longitudinal direction, in that voids having a diameter of less than 1 nm are dispersed in the SiC bonding layer 12. Since the other configurations of the SiC composite substrate 2 are the same as those of the SiC composite substrate 1 of Figure 1, corresponding components will be assigned the same reference numerals to indicate correspondences.

[0019] In the SiC composite substrate 2, the SiC bonding layer 12 is formed by SiC crystallization caused by a reaction between Si in the Si layer included in the interface layer interposed between the laminated polycrystalline SiC substrate 11 and the single-crystal SiC layer 13 and C in the C layer composed of a graphene film. The graphene film is formed by stacking graphene that spreads two-dimensionally. Therefore, in the SiC bonding layer 12 formed by the reaction of the Si layer and the C layer composed of the graphene film to crystallize SiC, the SiC crystal grains spread in the two-dimensional direction of the SiC bonding layer 12, and voids having a diameter of less than 1 nm are dispersed.

[0020] The SiC bonding layer 12 of the SiC composite substrate 2 is made of an interface layer containing, as a C layer, a graphene film that spreads uniformly in a sheet shape along the main surface of the polycrystalline SiC substrate 11. Therefore, bonding defects are unlikely to occur at the interfaces between the polycrystalline SiC substrate 11 and the SiC bonding layer 12 and between the single-crystal SiC layer 13 and the polycrystalline SiC substrate 11.

[0021] (Method for Manufacturing SiC Composite Substrate) Next, an embodiment of a method for manufacturing a SiC composite substrate will be described. Here, the manufacturing method will be described by taking the SiC composite substrate 1 shown in FIG.

[0022] 3A to 3J are process flow diagrams of a method for manufacturing the SiC composite substrate 1 of FIG. 1. As shown in FIG. 3A, a polycrystalline SiC substrate 11 is provided. The polycrystalline SiC substrate 11 may have a cubic crystal structure such as 3C, or a hexagonal crystal structure such as 4H or 6H. The polycrystalline SiC substrate 11 may be fabricated by deposition on a graphite substrate by CVD. For example, the polycrystalline SiC substrate 11 may have a diameter of 6 inches, a cubic crystal structure such as 3C, and a (000-1) C-plane as its main surface.

[0023] As shown in FIG. 3B , a Si layer 15 is formed on the main surface of the polycrystalline SiC substrate 11. The Si layer 15 is deposited by sputtering to a thickness of, for example, 120 nm. The Si layer 15 may be deposited by vacuum deposition instead of sputtering. In this manner, a first stacked body 3 is obtained in which the Si layer 15 is stacked on the main surface of the polycrystalline SiC substrate 11.

[0024] As shown in FIG. 3C , a single crystal SiC substrate 21 is provided. The single crystal SiC substrate 21 has a main surface that is an Si-face and a back surface opposite the main surface that is a C-face. For example, the single crystal SiC substrate 21 may have a diameter of 6 inches, a hexagonal 4H crystal polytype, and a (0001) crystal polytype on the main surface. Note that the crystal polytype of the single crystal SiC substrate 21 is not limited to 4H, and may also be a cubic crystal system such as 6H or 3C. The single crystal SiC substrate 21 may be formed by a sublimation method or a solution method.

[0025] 3D , a graphene film 22 is formed on the main surface of the single-crystal SiC substrate 21. The graphene film 22 may be formed of zero layers in which graphene extending two-dimensionally is covalently bonded to atoms on the main surface of the single-crystal SiC substrate 21, or may be formed of at most a few layers of graphene. The graphene film 22 may be formed on the main surface of the single-crystal SiC substrate 21 by a pyrolysis method or by CVD.

[0026] 3E, a single-crystal SiC layer 23 is grown by epitaxy on the main surface of a single-crystal SiC substrate 21 via a graphene film 22. Van der Waals forces are exerted on the single-crystal SiC layer 23 from SiC atoms constituting the main surface of the single-crystal SiC substrate 21 via the graphene film 22. Therefore, the crystal structure of the main surface of the single-crystal SiC substrate 21 is transferred to the main surface of the single-crystal SiC layer 23 that faces the main surface of the single-crystal SiC substrate 21 via the graphene film 22. Because the polar plane of the main surface of the single-crystal SiC substrate 21 is the Si-face, the polar plane of the main surface (000-1) of the single-crystal SiC layer 23 is the C-face, and the single-crystal SiC layer 23 is formed to have a diameter of 6 inches and a hexagonal 4H crystal polytype, similar to the single-crystal SiC substrate 21.

[0027] As shown in FIG. 3F , a single-crystal SiC layer 23 formed on a main surface of a single-crystal SiC substrate 21 via a graphene film 22 is peeled off from the graphene film 22. Because the two-dimensionally formed graphene film 22 and the single-crystal SiC layer 23 are bonded by van der Waals forces, the single-crystal SiC layer 23 can be easily peeled off from the graphene film 22. A stress layer made of a Ni layer or the like may be formed on the single-crystal SiC layer 23 so as to apply stress to the single-crystal SiC layer 23, and tape may be attached to the stress layer to support the stress layer. By applying force to the tape, the single-crystal SiC 23 together with the stress layer may be peeled off from the graphene film 22. FIG. 3G shows the single-crystal SiC layer 23 peeled off from the graphene film 22.

[0028] 3H, the single-crystal SiC layer 23 is heated, and a carbon nanotube film 24 is grown by pyrolysis on the C-plane of the main surface of the single-crystal SiC layer 23. The carbon nanotube film 24 is composed of carbon nanotubes extending perpendicularly from the main surface of the single-crystal SiC layer 23. In the carbon nanotube film 24, the carbon nanotubes may be grown to have an aspect ratio of about 10, 50, 100, or 200, with the longitudinal direction being perpendicular to the main surface. For example, a high-frequency induction heating furnace may be used to grow the carbon nanotubes. －２By holding the carbon nanotube film 24 on the main surface of the single-crystal SiC layer 23 in this manner, a second stack 4 is obtained in which the carbon nanotube film 24 is formed on the main surface of the single-crystal SiC layer 23.

[0029] As shown in Fig. 3I, the first laminate 3 and the second laminate 4 are arranged such that the carbon nanotube film 24 of the second laminate 4, which has a carbon nanotube film 24 serving as a C layer formed on the main surface of a single-crystal SiC substrate 21, faces the Si layer 15 of the first laminate 3, which has a Si layer 15 formed on the main surface of a polycrystalline SiC substrate 11. Then, as shown in Fig. 3J, the second laminate 4 is placed on the first laminate 3 so that the surfaces of the Si layer 15 of the first laminate 3 and the surfaces of the carbon nanotube film 24 of the second laminate 4, which face each other, come into contact with each other. This forms a third laminate 5, in which an interface layer 19 formed by stacking the Si layer 15 and the carbon nanotube film 24 of the C layer, is interposed between the laminated polycrystalline SiC substrate 11 and the single-crystal SiC layer 23.

[0030] 3J, Si in Si layer 15 constituting interface layer 19 reacts with C in carbon nanotube film 24 of the C layer to crystallize into SiC, thereby forming SiC bonding layer 12 that is interposed between polycrystalline SiC substrate 11 and single-crystal SiC substrate 21 and bonds polycrystalline SiC substrate 11 and single-crystal SiC substrate 21. For example, third stacked body 5 may be heated at 1100°C for 30 minutes to cause reaction between Si layer 15 and carbon nanotube film 24.

[0031] Because the carbon nanotubes constituting the carbon nanotube film 24 extend perpendicular to the main surface of the polycrystalline SiC substrate 11, the SiC crystal grains formed by crystallization of SiC extend in the stacking direction of the polycrystalline SiC substrate 11 and the single-crystal SiC layer 23. The aspect ratio of the SiC crystal grains in the SiC bonding layer 12, with the stacking direction as the longitudinal direction, is in the range of greater than 2 and less than 200. However, the aspect ratio of the SiC crystal grains constituting the SiC bonding layer 12 may be in the range of greater than 2 and less than 100, greater than 2 and less than 50, or greater than 2 and less than 10.

[0032] In this manner, Si layer 15 of interface layer 19 in third stack 5 is reacted with carbon nanotube film 24 to form SiC bonding layer 12, thereby obtaining SiC composite substrate 1 of Fig. 1. Here, single crystal SiC layer 23 in third stack 5 corresponds to single crystal SiC layer 13 in SiC composite substrate 1 of Fig. 1.

[0033] According to the manufacturing method of the SiC composite substrate 1 of FIG. 1 , as shown in FIG. 3J , the interface layer 19 formed by stacking the carbon nanotube film 24 of the second laminate 4 on the Si layer 15 of the first laminate 3 is heated, causing the Si of the Si layer 15 to react with the C of the carbon nanotube film 24, resulting in SiC crystallization. Therefore, there is no need to planarize the bonding surfaces of the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13 by chemical mechanical polishing (CMP) or the like prior to bonding. Furthermore, there is no need to amorphize the bonding surfaces by irradiating them with an Ar atomic beam, as in room-temperature bonding. In the SiC composite substrate 1 of FIG. 1 , the crystallinity of the bonding surfaces of the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13 with the SiC bonding layer 12 is maintained.

[0034] 3J, in the carbon nanotube film 24 constituting the interface layer 19, each carbon nanotube extends with the stacking direction as its longitudinal direction. The SiC crystal grains obtained by heating the interface layer 19 to crystallize the SiC are also aligned in the same direction as the carbon nanotubes, exhibiting high linearity and uniformity, and have a high aspect ratio with the stacking direction as the longitudinal direction. Therefore, in the SiC bonding layer 12 of the SiC composite substrate 1 shown in FIG. 1, stress generated in the two-dimensional direction in which the SiC bonding layer 12 extends is suppressed, making warping less likely to occur.

[0035] 3H , in carbon nanotube film 24 formed on the C-plane of the main surface of single-crystal SiC layer 23, the carbon nanotubes bond single-crystal SiC layer 13 to the main surface at the atomic level, forming a strong bond. Therefore, as shown in FIG. 3J , even in SiC bonding layer 12 of SiC composite substrate 1 formed by heating interface layer 19 formed by stacking carbon nanotube film 24 of second laminate 4 on Si layer 15 of first laminate 3 to crystallize SiC, a good bonding interface with few defects and high adhesion is obtained between single-crystal SiC layer 13 and SiC bonding layer 12.

[0036] 3E and 3F , in the process of growing a single-crystal SiC layer 23 by epitaxy on a main surface of a single-crystal SiC substrate 21 with a graphene film 22 interposed therebetween and then peeling the single-crystal SiC layer 23 from the graphene film 22 to produce the single-crystal SiC layer 23, the single-crystal SiC substrate 21 having the graphene film 22 formed on its main surface shown in Fig. 3D can be reused. This allows for a reduction in the manufacturing cost of the single-crystal SiC layer 23.

[0037] 4A to 4C are process flow diagrams showing a manufacturing method of Modification 2. The manufacturing method of Modification 2 is used to fabricate the SiC composite substrate 2 of Modification 1 shown in FIG. 2. The manufacturing method of Modification 2 differs from the manufacturing method of SiC composite substrate 1 of FIG. 1 shown in FIGS. 3A to 3J in the steps of FIG. 3B, 3D to 3F, and 3H to 3J. The other steps of FIGS. 3A, 3C, and 3G are also the same in the manufacturing method of Modification 2, and therefore, corresponding components are designated by common reference symbols to indicate the correspondence.

[0038] As shown in Fig. 4A, hydrogen ions are implanted to a predetermined depth from the main surface of the single-crystal SiC substrate 21 provided in the step of Fig. 3A to form a buried layer 21a. When the single-crystal SiC substrate 21 is then heated, pores are formed in the buried layer 21a, making the buried layer 21a embrittled.

[0039] 4B , stress is applied to the main surface of single crystal SiC substrate 21 to peel off embrittled buried layer 21a, and the portion of single crystal SiC substrate 21 from the main surface to the depth of buried layer 21a is separated to form single crystal SiC layer 25. For example, similar to the step of FIG. 3F , a stress layer made of a Ni layer or the like may be formed on the main surface of single crystal SiC substrate 21 so as to apply stress to single crystal SiC substrate 21, tape may be attached to the stress layer to support it, and force may be applied to the tape to peel off the portion of single crystal SiC substrate 21 from the main surface to the depth of buried layer 21a together with the stress layer.

[0040] 4C , in the second modification, instead of forming the Si layer 15 on the main surface of the polycrystalline SiC substrate 11 as shown in FIG. 3B , a carbon nanotube film 17 is formed on the main surface of the C-plane of the polycrystalline SiC substrate 11 to form a fourth stack 6. －２ When the laminate is held at 1500°C for 2 hours in a vacuum of about Pa, carbon nanotubes having a length of 80 nm are grown on the C-plane of the main surface, forming the carbon nanotube film 17. Furthermore, a Si layer 26 is formed on the main surface of the single-crystal SiC layer 25 to form the fifth stack 7. The Si layer 26 is produced in the same process as that for forming the Si layer 15 shown in FIG. 3B. The Si layer 26 may be 200 nm thick.

[0041] 4C , the fourth stack 6 and the fifth stack 7 are arranged such that the Si layer 26 of the fifth stack 7, which has a Si layer 26 formed on the main surface of the single-crystal SiC layer 25, faces the carbon nanotube film 17 of the fourth stack 6, which has a carbon nanotube film 17 serving as a C layer formed on the main surface of the polycrystalline SiC substrate 11. The fifth stack 7 is then placed on the fourth stack 6 so that the surfaces of the carbon nanotube film 17 of the fourth stack 6 and the surfaces of the Si layer 26 of the fifth stack 7, which face each other, come into contact with each other. This results in the polycrystalline SiC substrate 11 and the single-crystal SiC layer 25 being stacked, forming a stack in which an interface layer, made of the carbon nanotube film 17 of the C layer and the Si layer 26, is interposed between the stacked polycrystalline SiC substrate 11 and the single-crystal SiC layer 23.

[0042] When this laminate is heated, the C of the carbon nanotube film 17 constituting the interface layer reacts with the Si of the Si layer 26 to crystallize into SiC, forming a SiC bonding layer 12 interposed between the polycrystalline SiC substrate 11 and the single-crystal SiC layer 25 and bonding the polycrystalline SiC substrate 11 to the single-crystal SiC layer 25. For example, the carbon nanotube film 17 and the Si layer 26 may be reacted by heating the laminate at 1100°C for one hour. In this manner, the SiC composite substrate 1 of FIG. 1 is obtained. Here, the single-crystal SiC layer 25 corresponds to the single-crystal SiC layer 13 of the SiC composite substrate 1 of FIG. 1.

[0043] According to the manufacturing method of Modification 2, hydrogen ions are irradiated from the main surface of single-crystal SiC substrate 21 to form buried layer 21a, and buried layer 21a is then peeled off by heating, thereby peeling off the portion from the main surface to the depth of buried layer 21a to form single-crystal SiC layer 25. Since there is no need to grow single-crystal SiC layer 23 by epitaxy as shown in FIG. 3E , single-crystal SiC layer 25 can be easily produced.

[0044] Furthermore, in carbon nanotube film 17 included in the interface layer that will form SiC bonding layer 12, the carbon nanotubes are bonded and firmly bonded at the atomic level to the main surface of polycrystalline SiC substrate 11. Therefore, a good bonding interface with few defects and high adhesion strength is obtained between polycrystalline SiC substrate 11 and SiC bonding layer 12.

[0045] Fig. 5 is a diagram showing a manufacturing method of Modified Example 3. The manufacturing method of Modified Example 3 is for producing the SiC composite substrate 1 shown in Fig. 1. The manufacturing method of Modified Example 3 differs from the manufacturing method of SiC composite substrate 1 of Fig. 1 shown in Figs. 3A to 3J in the steps of Fig. 3B, Fig. 3I, and Fig. 3J. Since the other steps of Fig. 3A and Figs. 3C to 3H are similar, corresponding components are assigned common reference symbols to indicate correspondence.

[0046] 5, in the third modification, instead of forming the Si layer 15 on the main surface of the polycrystalline SiC substrate 11 as in FIG. 3B, the carbon nanotube film 17 and the Si layer 15 are sequentially laminated on the main surface of the polycrystalline SiC substrate 11 to form the sixth stack 8. Here, the polycrystalline SiC substrate 11 is formed in a 1×10 －２ The carbon nanotube film 17 may be fabricated by holding the substrate at 1500° C. for 1 hour in a vacuum of about 100 Pa to grow carbon nanotubes having a length of 20 nm. The Si layer 15 is formed by the same process as that shown in FIG. 3B. The Si layer 15 may be formed to a thickness of 100 nm.

[0047] 5, the sixth stack 8 and the second stack 4 are arranged so that the carbon nanotube film 24 of the second stack 4, which has a carbon nanotube film 24 formed on the main surface of a single-crystal SiC layer 23, faces the Si layer 15 of the sixth stack 8, which has a carbon nanotube film 17 serving as a C layer and a Si layer 15 laminated in this order on the main surface of the polycrystalline SiC substrate 11. Here, the carbon nanotube film 24 of the second stack 4 is formed in the same manner as in the step of FIG. 3H. For example, a single-crystal SiC substrate 21 having a crystal polytype of 4H is formed in a 1×10 －２ The carbon nanotube film 24 may be formed by growing carbon nanotubes with a length of 20 nm on the C-plane of the main surface (000-1) by holding the substrate at 1500° C. for 1 hour in a vacuum of about Pa.

[0048] The second laminate 4 is placed on the sixth laminate 8 so that the surfaces of the Si layer 15 of the sixth laminate 8 that face each other are in contact with the surfaces of the carbon nanotube film 24 of the sixth laminate 8. In this way, the sixth laminate 8 and the second laminate 4 are stacked, and a laminate is formed in which an interface layer formed by stacking the carbon nanotube film 17, the Si layer 15, and the carbon nanotube film 24 in this order is interposed between the polycrystalline SiC substrate 11 and the single-crystal SiC layer 23.

[0049] When this laminate is heated, the C in the carbon nanotube films 17, 24 constituting the interface layer reacts with the Si in the Si layer 15 to crystallize into SiC, forming a SiC bonding layer 12 that is interposed between the polycrystalline SiC substrate 11 and the single-crystal SiC layer 23 and bonds the polycrystalline SiC substrate 11 to the single-crystal SiC layer 23. For example, the carbon nanotube films 17, 24 may be reacted with the Si layer 15 by heating at 1100°C for 30 minutes. In this manner, the SiC composite substrate 1 shown in FIG. 1 is obtained. Here, the single-crystal SiC layer 23 corresponds to the single-crystal SiC layer 13 of the SiC composite substrate 1 shown in FIG. 1.

[0050] 5 , in the manufacturing method of Modification 3, carbon nanotube film 17 is formed on the main surface of polycrystalline SiC substrate 11, and carbon nanotube film 24 is also formed on the main surface of single-crystal SiC layer 23. In polycrystalline SiC substrate 11, the carbon nanotubes of carbon nanotube film 17 are bonded and firmly bonded to the main surface of polycrystalline SiC substrate 11 at the atomic level. In single-crystal SiC layer 23, the carbon nanotubes of carbon nanotube film 24 are also bonded and firmly bonded to the main surface of single-crystal SiC layer 23 at the atomic level. Therefore, a good bonding interface with few defects and high adhesion is obtained between polycrystalline SiC substrate 11 and single-crystal SiC layer 23.

[0051] Fig. 6 is a diagram showing a manufacturing method of Modified Example 4. The manufacturing method of Modified Example 4 is for producing the SiC composite substrate 2 shown in Fig. 2. The manufacturing method of Modified Example 4 shares the steps from Fig. 3A to Fig. 3G in the manufacturing method of SiC composite substrate 1 of Fig. 1 shown in Fig. 3A to Fig. 3J, and therefore, corresponding components are given common reference symbols to indicate the correspondence.

[0052] In the fourth modification, instead of forming the carbon nanotube film 24 as the C layer on the main surface of the single-crystal SiC substrate 21 as shown in FIGS. 3H to 3J, a graphene film 27 is formed to form the seventh stack 9. The graphene film 27 is formed by stacking graphene that spreads two-dimensionally. The graphene film 27 may be formed to a thickness of 5 nm on the C-face of the main surface (000-1) of a single-crystal SiC layer having a diameter of 4 inches and a crystal polytype of 4H by heating the single-crystal SiC layer 23 of FIG. 3G at 1800° C. for 60 minutes in an Ar atmosphere at atmospheric pressure. Note that the graphene film 27 may be formed in a thickness of 5 nm on the C-face of the main surface (000-1) of a single-crystal SiC layer having a diameter of 4 inches and a crystal polytype of 4H. ２ or an inert gas such as 1×10 －４ A high vacuum of about Pa or less may also be used.

[0053] 6 , the first laminate 3 and the seventh laminate 9 are arranged such that the graphene film 27 of the seventh laminate 9, which has a graphene film 27 serving as a C layer formed on the main surface of a single-crystal SiC layer 23, faces the Si layer 15 of the first laminate 3, which has a Si layer 15 formed on the main surface of a polycrystalline SiC substrate 11. Then, the seventh laminate 9 is placed on the first laminate 3 so that the surfaces of the Si layer 15 of the first laminate 3 and the surfaces of the graphene film 27 of the seventh laminate 9, which face each other, come into contact with each other. In this way, the first laminate 3 and the seventh laminate 9 are stacked, forming a laminate in which an interface layer formed by stacking the Si layer 15 and the graphene film 27 of the C layer is interposed between the polycrystalline SiC substrate 11 and the single-crystal SiC layer 23.

[0054] When this laminate is heated, Si in the Si layer 15 constituting the interface layer reacts with C in the graphene film 27 to form SiC crystallization, forming a SiC bonding layer 12 interposed between the polycrystalline SiC substrate 11 and the single-crystal SiC layer 23 and bonding the polycrystalline SiC substrate 11 and the single-crystal SiC layer 23. For example, the Si layer 15 and the graphene film 27 may be reacted by heating the laminate at 1100°C for 30 minutes. In the SiC bonding layer 12, the SiC crystal grains formed by SiC crystallization expand in two dimensions, dispersing voids with diameters less than 1 nm. In this manner, the SiC composite substrate 2 shown in FIG. 2 is obtained. Here, the single-crystal SiC layer 23 corresponds to the single-crystal SiC layer 13 of the SiC composite substrate 2 shown in FIG. 2.

[0055] 6 , in the manufacturing method of Modification 4, a graphene film 27 of the C layer is formed on the main surface of the single-crystal SiC layer 23. The graphene film 27 spreads uniformly in a sheet shape along the main surface of the polycrystalline SiC substrate 11, and therefore bonding defects are unlikely to occur at the interface after graphene crystallization.

[0056] (Semiconductor Device) Next, an embodiment of a semiconductor device will be described. The semiconductor device of this embodiment uses a SiC composite substrate 1 as shown in FIG. 1 , and is configured such that the polycrystalline SiC substrate 11 of the SiC composite substrate 1 serves as a substrate layer and the single-crystal SiC layer 13 serves as a drift layer. As shown in FIG. 1 , the SiC composite substrate 1 has a SiC bonding layer 12 interposed between the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13. Therefore, the semiconductor device of this embodiment also has a SiC bonding layer 12 interposed between the substrate layer and the drift layer. Below, examples of electronic devices using the SiC composite substrate 1 will be described, including a Schottky barrier diode (SBD), a trench-gate metal oxide semiconductor field effect transistor (MOSFET), and a planar-gate MOSFET.

[0057] 7 is a cross-sectional view of an SBD 30. The SBD 30 is fabricated using the SiC composite substrate 1 shown in FIG. 1. In the SBD 30, in the SiC composite substrate 1, a single-crystal SiC layer 13 is stacked on a polycrystalline SiC substrate 11 with an SiC bonding layer 12 interposed therebetween. The polycrystalline SiC substrate 11 is a high-concentration n ＋ The single-crystal SiC layer 13 is doped with a low concentration of n － The polycrystalline SiC substrate 11 is doped with a metal to form a drift layer. The bottom surface of the polycrystalline SiC substrate 11 is covered with a cathode electrode 31, which is connected to a cathode terminal K.

[0058] The top surface 13a of the single-crystal SiC layer 13 is provided with a contact hole 33 that exposes a part of the single-crystal SiC layer 13 as a body region 32, and a field insulating film 35 is formed in a field region 34 surrounding the body region 32. The field insulating film 35 is made of SiO ２ The field insulating film 35 is made of silicon oxide, but may be made of other insulating materials such as silicon nitride (SiN). An anode electrode 36 is formed on the field insulating film 35 and is connected to an anode terminal A.

[0059] A p-type JTE (junction termination extension) structure 37 is formed in the vicinity of the top surface 13a (surface layer portion) of the single-crystal SiC layer 13 so as to contact the anode electrode 36. The JTE structure 37 is formed along the contour of the contact hole 33 in the field insulating film 35 so as to straddle the inside and outside of the contact hole 33.

[0060] 8 is a cross-sectional view of a trench gate MOSFET 40. The trench gate MOSFET 40 is fabricated using the SiC composite substrate 1 shown in FIG. 1. In the trench gate MOSFET 40, in the SiC composite substrate 1 in which a single crystal SiC layer 13 is stacked on a polycrystalline SiC substrate 11 with an SiC bonding layer 12 interposed therebetween, the polycrystalline SiC substrate 11 is a high concentration n ＋ The single-crystal SiC layer 13 is doped with a low concentration of n －The bottom surface of the polycrystalline SiC substrate 11 is covered with a drain electrode 41, which is connected to a drain terminal D.

[0061] A p-type body region 42 is formed on the top surface 13a of the single-crystal SiC layer 13. In the single-crystal SiC layer 13, the portion on the polycrystalline SiC substrate 11 side relative to the body region 42 is a low-concentration doped n-type layer that is maintained as the single-crystal SiC layer 13. - The single-crystal SiC layer 13 has a gate trench 44 formed therein. The gate trench 44 penetrates the body region 42 from the top surface 13a of the single-crystal SiC layer 13, and its deepest portion reaches the drain region 43(13).

[0062] A gate insulating film 45 is formed on the inner surface of the gate trench 44 and on the top surface 13a of the single-crystal SiC layer 13 so as to cover the entire inner surface of the gate trench 44. The inside of the gate insulating film 45 is filled with, for example, polysilicon, thereby embedding a gate electrode 46 in the gate trench 44. A gate terminal G is connected to the gate electrode 46.

[0063] The surface layer of the body region 42 is formed with a highly doped n-type impurity dopant (nPt) that forms part of the side surface of the gate trench 44. + The single-crystal SiC layer 13 has a highly doped p-type source region 47 formed therein. The p-type source region 47 is connected to the body region 42 and extends from the top surface 13a of the single-crystal SiC layer 13 through the source region 47. + A mold body contact region 48 is formed.

[0064] An interlayer insulating film 51 made of SiO is formed on the single-crystal SiC layer 13. A source electrode 53 is connected to the source region 47 and the body contact region 48 via a contact hole 52 formed in the interlayer insulating film 51. A source terminal S is connected to the source electrode 53.

[0065] By applying a predetermined voltage (a voltage equal to or greater than the gate threshold voltage) to the gate electrode 46 while a predetermined potential difference is generated between the source electrode 53 and the drain electrode 41 (between the source and drain), a channel can be formed in the body region 42 near the interface with the gate insulating film 45 due to the electric field from the gate electrode 46. This allows a current to flow between the source electrode 53 and the drain electrode 41, turning on the trench-gate MOSFET 40.

[0066] 9 is a cross-sectional view of a planar gate MOSFET 60. The planar gate MOSFET 60 is fabricated using the SiC composite substrate 1 shown in FIG. 1. In the planar gate MOSFET 60, in the SiC composite substrate 1 in which a single crystal SiC layer 13 is stacked on a polycrystalline SiC substrate 11 with an SiC bonding layer 12 interposed therebetween, the polycrystalline SiC substrate 11 is a high concentration n ＋ The single-crystal SiC layer 13 is doped with a low concentration of n － The bottom surface of the polycrystalline SiC substrate 11 is covered with a drain electrode 61, which is connected to a drain terminal D.

[0067] A p-type body region 62 is formed in a well shape on the top surface 13a of the single-crystal SiC layer 13. In the single-crystal SiC layer 13, the portion on the polycrystalline SiC substrate 11 side relative to the body region 62 is formed as a lightly doped n-type layer in which the state of the single-crystal SiC layer 13 is maintained as it is. - The surface layer of the body region 62 is a heavily doped n-type drain region 63 (13). + A source region 64 of the type is formed at a distance from the periphery of the body region 62. Inside the source region 64, a heavily doped p + A body contact region 65 is formed on the source region 64. The body contact region 65 penetrates the source region 64 in the depth direction and is connected to the body region 62.

[0068] A gate insulating film 66 is formed on the top surface 13a of the single-crystal SiC layer 13. The gate insulating film 66 covers a portion of the body region 62 surrounding the source region 64 (the peripheral portion of the body region 62) and the outer periphery of the source region 64. A gate electrode 67 made of, for example, polysilicon is formed on the gate insulating film 66. The gate electrode 67 faces the peripheral portion of the body region 62 with the gate insulating film 66 interposed therebetween. A gate terminal G is connected to the gate electrode 67.

[0069] An interlayer insulating film 68 made of SiO is formed on the single-crystal SiC layer 13. A source electrode 72 is connected to the source region 64 and the body contact region 65 via a contact hole 71 formed in the interlayer insulating film 68. A source terminal S is connected to the source electrode 72.

[0070] By applying a predetermined voltage (a voltage equal to or greater than the gate threshold voltage) to the gate electrode 67 while a predetermined potential difference is generated between the source electrode 72 and the drain electrode 61 (between the source and drain), a channel can be formed in the body region 62 near the interface with the gate insulating film 66 due to the electric field from the gate electrode 67. This allows a current to flow between the source electrode 72 and the drain electrode 61, turning the planar gate MOSFET 60 on.

[0071] 1 used in the manufacture of the semiconductor device of this embodiment is configured with a SiC bonding layer 12 interposed between a polycrystalline SiC substrate 11 and a single-crystal SiC layer 13. Therefore, there is no need to planarize the bonding surfaces of the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13 by chemical mechanical polishing (CMP) or the like prior to bonding, and there is no need to amorphize the bonding surfaces by irradiating them with an Ar atomic beam as in room-temperature bonding. Because the crystallinity of the bonding surfaces of the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13 with the SiC bonding layer 12 is maintained, favorable characteristics can be obtained in the semiconductor device.

[0072] In the SiC composite substrate 1 shown in FIG. 1 used in the manufacture of the semiconductor device of this embodiment, the SiC bonding layer 12 interposed between the laminated polycrystalline SiC substrate 11 and single-crystal SiC layer 13 is formed by SiC crystallization caused by a reaction between Si in the Si layer 15 (FIG. 3J) of the interface layer and C in the C layer composed of the carbon nanotube film 24. In the carbon nanotube film 24 constituting the C layer, each carbon nanotube extends longitudinally in the stacking direction and is aligned in the same direction as the carbon nanotubes, resulting in high linearity and uniformity. The SiC crystal grains obtained by SiC crystallization also have a high aspect ratio with the stacking direction as the longitudinal direction. This suppresses stress generated in the two-dimensional direction in which the SiC bonding layer 12 extends, making warpage less likely to occur after bonding the polycrystalline SiC substrate 11 and single-crystal SiC layer 13 together with the SiC bonding layer 12. Therefore, semiconductor devices manufactured using such a SiC composite substrate 1 are also less likely to warp.

[0073] Although the present disclosure has been described in detail above, it will be apparent to those skilled in the art that the present disclosure is not limited to the embodiments described herein. One or more elements of one embodiment can be combined with one or more elements of another embodiment. The present disclosure can be implemented in modified and altered forms without departing from the spirit and scope of the present disclosure, as defined by the claims. Therefore, the description of the present disclosure is intended to be illustrative and explanatory, and is not intended to be limiting of the present disclosure.

[0074] (Supplementary Notes) The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the Supplementary Notes are given the reference symbols of the corresponding components in the embodiments. The reference symbols are shown as examples to aid understanding, and the components described in each Supplementary Note should not be limited to the components indicated by the reference symbols.

[0075] (Note 1) The SiC composite substrate 1 includes a polycrystalline SiC substrate 11, a single-crystal SiC layer 13 stacked on the polycrystalline SiC substrate 11, and a SiC bonding layer 12 interposed between the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13 to bond the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13, the SiC bonding layer 12 containing SiC crystal grains with an aspect ratio greater than 2 and smaller than 200, with the stacking direction as the longitudinal direction. The SiC crystal grains in the SiC bonding layer 12 are aligned in the stacking direction with high linearity and uniformity, so that the SiC composite substrate 1 does not warp and the bonding surfaces do not require planarization.

[0076] (Supplementary Note 2) In the SiC composite substrate 1 described in Supplementary Note 1, the aspect ratio may be in the range of greater than 2 and less than 100. The SiC crystal grains in the SiC bonding layer 12 are aligned in the stacking direction and have high linearity and uniformity, so that the SiC composite substrate 1 does not warp and the bonding surfaces do not need to be flattened.

[0077] (Supplementary Note 3) In the SiC composite substrate 1 described in Supplementary Note 2, the aspect ratio may be in the range of greater than 2 and less than 50. The SiC crystal grains in the SiC bonding layer 12 are aligned in the stacking direction and have high linearity and uniformity, so that the SiC composite substrate 1 does not warp and the bonding surfaces do not need to be flattened.

[0078] (Supplementary Note 4) In the SiC composite substrate 1 described in Supplementary Note 3, the aspect ratio may be in the range of greater than 2 and less than 10. The SiC crystal grains in the SiC bonding layer 12 are aligned in the stacking direction and have high linearity and uniformity, so that the SiC composite substrate 1 does not warp and the bonding surfaces do not need to be flattened.

[0079] (Supplementary Note 5) In the SiC composite substrate 1 described in any one of Supplementary Notes 1 to 4, the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13 may each include any of the crystal polytypes of cubic 3C and hexagonal 4H and 6H. The crystal polytypes of the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13 can be selected arbitrarily.

[0080] (Supplementary Note 6) In the SiC composite substrate 1 described in any one of Supplementary Notes 1 to 5, at least one of the main surfaces of the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13 may include a polar Si-face or a polar C-face. A carbon nanotube film can be formed on the C-face by pyrolysis, and a carbon nanotube film or a graphene film can be formed on the Si-face and the C-face.

[0081] (Supplementary Note 7) The SiC composite substrate 2 includes a polycrystalline SiC substrate 11, a single-crystal SiC layer 13 laminated on the polycrystalline SiC substrate 11, and a SiC bonding layer 12 interposed between the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13 to bond the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13, the SiC bonding layer 12 having dispersed therein vacancies having a diameter of less than 1 nm. The graphene film used to fabricate the SiC bonding layer 12 can be fabricated by a variety of methods, which can reduce the burden of manufacturing the SiC composite substrate 2.

[0082] (Appendix 8) A method for manufacturing a SiC composite substrate includes the steps of providing a polycrystalline SiC substrate 11, providing a single-crystal SiC layer 23, stacking the polycrystalline SiC substrate 11 and the single-crystal SiC layer 23 with an interface layer 19 interposed between a main surface of the polycrystalline SiC substrate 11 and a main surface of the single-crystal SiC layer 23 to form a third stacked body 5, the interface layer 19 including at least one Si layer and one C layer, each including a carbon nanotube film or a graphene film, and heating the third stacked body 5 to react the Si layer and the C layer of the interface layer 19 and induce SiC crystallization to form a SiC bonding layer 12. There is no need to planarize the bonding surfaces of the polycrystalline SiC substrate 11 and the single-crystal SiC layer 23 by chemical mechanical polishing (CMP) or the like prior to bonding. Furthermore, there is no need to amorphize the bonding surfaces by irradiating them with an Ar atomic beam, as in room-temperature bonding. Therefore, in the SiC composite substrate 1, the crystallinity is maintained at the bonding surface between the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13 and the SiC bonding layer.

[0083] (Supplementary Note 9) In the method for manufacturing a SiC composite substrate described in Supplementary Note 8, the step of providing the single-crystal SiC layer 23 may include a step of growing the single-crystal SiC layer 23 on the main surface of the single-crystal SiC substrate 21 via the graphene film 22 by an epitaxy method, and a step of peeling off the formed single-crystal SiC layer 23 from the graphene film 22. The single-crystal SiC substrate 21 having the graphene film 22 formed on its main surface can be used repeatedly.

[0084] (Supplementary Note 10) In the method for manufacturing a SiC composite substrate described in Supplementary Note 8, the step of providing single-crystal SiC layer 23 may include the steps of implanting hydrogen ions to a predetermined depth from the main surface of single-crystal SiC substrate 21 to form buried layer 21 a, heating single-crystal SiC substrate 21 on which buried layer 21 a has been formed to embrittle buried layer 21 a, and separating a portion of single-crystal SiC substrate 21 from the main surface to the depth of the embrittlement of buried layer 21 a to obtain single-crystal SiC layer 23. Since there is no need to grow single-crystal SiC layer 23 by epitaxy, single-crystal SiC layer 23 can be easily produced.

[0085] (Appendix 11) In the method for manufacturing SiC composite substrate 1 according to any one of Appendices 8 to 10, the step of forming third stacked body 5 may include the steps of forming a C layer on a first main surface among the main surface of polycrystalline SiC substrate 11 and the main surface of single-crystal SiC layer 23, and forming a Si layer on a second main surface among the main surface of polycrystalline SiC substrate 11 and the main surface of single-crystal SiC layer 23. The surfaces on which the Si layer and the C layer are formed can be arbitrarily selected from the main surface of polycrystalline SiC substrate 11 and the main surface of single-crystal SiC layer 23.

[0086] (Supplementary Note 12) In the method for manufacturing SiC composite substrate 1 described in Supplementary Note 11, the first main surface may be a C-plane, and the step of forming a C layer on the first main surface may include the step of forming a carbon nanotube film on the first main surface by a pyrolysis method. SiC crystal grains in SiC bonding layer 12 formed as a C layer using a carbon nanotube film are aligned in the stacking direction and have high linearity and uniformity, so that warping of SiC composite substrate 1 does not occur, and flattening of the bonding surfaces is not required.

[0087] (Supplementary Note 13) In the method for manufacturing SiC composite substrate 1 described in Supplementary Note 12, the step of forming a C layer on the first main surface may include the step of forming a graphene film on the first main surface by a pyrolysis method. The graphene film can be formed by heating polycrystalline SiC substrate 11 or single-crystal SiC layer 23.

[0088] (Supplementary Note 14) In the method for manufacturing SiC composite substrate 1 described in Supplementary Note 12, the step of forming a C layer on the first main surface may include the step of forming a graphene film on the first main surface by chemical vapor deposition. Chemical vapor deposition (CVD) makes it easy to set the properties, film thickness, etc. of the graphene film.

[0089] (Supplementary Note 15) In the method for manufacturing SiC composite substrate 1 described in Supplementary Note 13 or 14, the step of forming the Si layer on the second main surface may deposit each Si layer by a sputtering method. By using a sputtering method, the properties and film thickness of the Si film can be easily set.

[0090] (Supplementary Note 16) In the method for manufacturing SiC composite substrate 1 according to Supplementary Note 13 or 14, the step of forming the Si layer on the second main surface may deposit each Si layer by vacuum deposition. Vacuum deposition allows for rapid formation of the Si film.

[0091] (Appendix 17) In the method for manufacturing SiC composite substrate 1 according to any one of Appendices 8 to 10, the main surface of polycrystalline SiC substrate 11 and the main surface of single-crystal SiC layer 23 may each be a C-plane, and the step of forming the laminate may include a step of forming a carbon nanotube film by pyrolysis on each of the main surface of polycrystalline SiC substrate 11 and the main surface of single-crystal SiC layer 23. SiC crystal grains in SiC bonding layer 12 formed using the C layer as a carbon nanotube film are aligned in the stacking direction and are highly linear and uniform, so that warping of SiC composite substrate 1 does not occur and flattening of the bonding surfaces is not required.

[0092] (Appendix 18) A semiconductor device is configured using the single-crystal SiC layer 13 of the SiC composite substrate 1 described in any one of Appendices 1 to 7 as a drift layer. In the SiC composite substrate 1, it is not necessary to planarize the bonding surfaces of the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13 by chemical mechanical polishing (CMP) or the like prior to bonding, and it is also not necessary to amorphize the bonding surfaces by irradiating them with an Ar atomic beam as in room-temperature bonding. Therefore, the crystallinity of the bonding surfaces of the polycrystalline SiC substrate 11 and the single-crystal SiC layer 13 with the SiC bonding layer 12 is maintained, and good characteristics can be obtained in the semiconductor device.

[0093] (Supplementary Note 19) The semiconductor device described in Supplementary Note 18 may include at least one of a Schottky barrier diode, a trench gate MOS, and a planar gate MOS. Various semiconductor devices such as a Schottky barrier diode, a trench gate MOS, and a planar gate MOS can be configured.

Claims

1. A SiC composite substrate comprising: a polycrystalline SiC substrate; a single-crystal SiC layer laminated on the polycrystalline SiC substrate; and a SiC bonding layer interposed between the polycrystalline SiC substrate and the single-crystal SiC layer to bond the polycrystalline SiC substrate and the single-crystal SiC layer, the SiC bonding layer containing SiC crystal grains having an aspect ratio in the range of greater than 2 and less than 200, with the lamination direction as the longitudinal direction.

2. The SiC composite substrate according to claim 1, wherein the polycrystalline SiC substrate and the single crystal SiC layer each contain either one of the cubic 3C and hexagonal 4H and 6H crystal polytypes.

3. The SiC composite substrate according to claim 1 or 2, wherein at least one of the main surfaces of the polycrystalline SiC substrate and the single-crystal SiC layer includes a polar Si-face or C-face.

4. A SiC composite substrate comprising: a polycrystalline SiC substrate; a single-crystal SiC layer laminated on the polycrystalline SiC substrate; and a SiC bonding layer interposed between the polycrystalline SiC substrate and the single-crystal SiC layer to bond the polycrystalline SiC substrate and the single-crystal SiC layer, the SiC bonding layer having dispersed voids having a diameter of less than 1 nm.

5. A method for manufacturing a SiC composite substrate, comprising: providing a polycrystalline SiC substrate; providing a single-crystal SiC layer; stacking the polycrystalline SiC substrate and the single-crystal SiC layer with an interface layer interposed between a main surface of the polycrystalline SiC substrate and a main surface of the single-crystal SiC layer to form a laminate, the interface layer each including at least one Si layer and one C layer, and each C layer including a carbon nanotube film or a graphene film; and heating the laminate to react the Si layer and the C layer of the interface layer and induce SiC crystallization to form a SiC bonding layer.

6. The method for producing a SiC composite substrate according to claim 5, wherein the step of providing the single-crystal SiC layer comprises: forming the single-crystal SiC layer by epitaxy on a main surface of a single-crystal SiC substrate via a graphene film; and peeling the formed single-crystal SiC layer from the graphene film.

7. A method for manufacturing a SiC composite substrate according to claim 5, wherein the step of providing the single crystal SiC layer comprises the steps of: implanting hydrogen ions to a predetermined depth from the main surface of the single crystal SiC substrate to form a buried layer; heating the single crystal SiC substrate on which the buried layer has been formed to embrittle the buried layer; and separating the portion of the single crystal SiC substrate from the main surface to the depth of the buried layer, with the embrittlement of the buried layer, to provide the single crystal SiC layer.

8. A method for manufacturing a SiC composite substrate according to any one of claims 5 to 7, wherein the step of forming the laminate includes the steps of: forming the C layer on a first main surface among the main surface of the polycrystalline SiC substrate and the main surface of the single-crystal SiC layer; and forming the Si layer on a second main surface among the main surface of the polycrystalline SiC substrate and the main surface of the single-crystal SiC layer.

9. A method for manufacturing a SiC composite substrate as described in claim 8, wherein the first main surface is a C-plane, and the step of forming the C layer on the first main surface includes a step of forming a carbon nanotube film on the first main surface by a thermal decomposition method.

10. A method for producing a SiC composite substrate as described in claim 9, wherein the step of forming the C layer on the first main surface includes a step of forming the graphene film on the first main surface by a thermal decomposition method.

11. A method for producing a SiC composite substrate as described in claim 9, wherein the step of forming the C layer on the first main surface includes a step of forming the graphene film on the first main surface by chemical vapor deposition.

12. A method for producing a SiC composite substrate according to claim 8 or 9, wherein the step of forming the Si layer on the second main surface deposits each Si layer by sputtering or vacuum deposition.

13. A method for manufacturing a SiC composite substrate according to any one of claims 5 to 7, wherein the main surface of the polycrystalline SiC substrate and the main surface of the single-crystal SiC layer are each a C-plane, and the step of forming the laminate includes a step of forming a carbon nanotube film on each of the main surface of the polycrystalline SiC substrate and the main surface of the single-crystal SiC layer by a thermal decomposition method.

14. A semiconductor device comprising a single crystal SiC layer of the SiC composite substrate according to any one of claims 1 to 4 as a drift layer.

15. The semiconductor device according to claim 14, comprising at least one of a Schottky barrier diode, a trench gate MOS, and a planar gate MOS.

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