Printed circuit board design device, printed circuit board design method, and printed circuit board design program

Abstract

This printed circuit board design device (20) is provided with: a board graph creation unit (26) that creates a board graph representing the components and connections between the components included in a designed board; a circuit block graph creation unit (28) that creates a circuit block graph representing the components and connections between the components included in a circuit block included in a new board; a subgraph extraction unit (29) that performs a search using, as a starting node, a node, which is among a plurality of nodes included in the board graph, for a component of the same type as a specific component included in the circuit block, and thereby extracts a plurality of subgraphs, each including the starting node, from the board graph; a feature extraction unit (30) that uses a trained model to extract a feature of the circuit block graph from information representing the circuit block graph and extract a feature of the subgraph from information representing the subgraph; and a similarity calculation unit (31) that calculates the similarity between the feature of the circuit block graph and the feature of each subgraph.

Description

Printed circuit board design device, printed circuit board design method, and printed circuit board design program

[0001] The present disclosure relates to a printed circuit board design device, a printed circuit board design method, and a printed circuit board design program.

[0002] Conventionally, design devices have been known that can place components that are desired to be placed close to each other on a printed circuit board so that the performance or characteristics of the electronic circuit can be fully demonstrated. For example, a design device described in Patent Document 1 includes a knowledge pattern storage unit that stores conditions for components to be placed close to each other on the printed circuit board as a knowledge pattern, a printed circuit board design information storage unit that stores components to be placed on the printed circuit board and wiring information between the components, a group classification unit that determines whether each component stored in the printed circuit board design information storage unit satisfies the knowledge pattern stored in the knowledge pattern storage unit based on the wiring information, and classifies a group of components that satisfy the knowledge pattern into one group, and a placement determination unit that regards a group of components classified into one group as one placement element and determines the placement on the printed circuit board. The placement of components other than the group is based on the connection information in the printed circuit board design information storage unit.

[0003] Japanese Patent Application Publication No. 7-200655

[0004] The printed circuit board design method described in Patent Document 1 requires determining the conditions for components to be arranged closely together on the printed circuit board, which requires the knowledge or know-how of an experienced printed circuit board designer.

[0005] An object of the present disclosure is to provide a printed circuit board design device, a printed circuit board design method, and a printed circuit board design program that are capable of designing a printed circuit board without requiring the knowledge or know-how of an experienced printed circuit board designer.

[0006] The printed circuit board design apparatus disclosed herein comprises a board graph creation unit that creates a board graph representing the components included in a designed board and the connections between the components; a circuit block graph creation unit that creates a circuit block graph that represents the components included in a circuit block included in a new board and the connections between the components; a subgraph extraction unit that searches for a node of a component of the same type as a specific component included in the circuit block from among multiple nodes included in the board graph, sets the node of the searched component as a starting node, and extracts multiple subgraphs including the starting node from the board graph; a feature extraction unit that uses a trained model to extract features of the circuit block graph from information representing the circuit block graph and extracts features of the subgraph from information representing the subgraph; and a similarity calculation unit that calculates the similarity between the features of the circuit block graph and the features of each subgraph.

[0007] According to the present disclosure, it is possible to design a new board by reusing data from previous designs, so that a printed circuit board can be designed without the knowledge or know-how of an experienced printed circuit board designer. In addition, it is possible to improve the efficiency of printed circuit board design and to standardize the quality of printed circuit boards.

[0008] 1 is a diagram showing the configuration of the learning device 10 of the first embodiment. FIG. 2 is a flowchart showing the procedure of learning processing by the learning device 10 of the first embodiment. FIG. 3 is a diagram showing an example of a circuit board graph. FIG. 4 is a diagram showing attribute vectors of nodes. FIG. 5 is a diagram showing a first example of similarity setting. FIG. 6 is a diagram showing a second example of similarity setting. FIG. 7 is a diagram showing a third example of similarity setting. FIG. 8 is a diagram showing a fourth example of similarity setting. FIG. 9 is a diagram showing an example of the configuration of a graph neural network of the first embodiment. FIG. 10 is a diagram showing the configuration of a printed circuit board design device 20. FIG. 11 is a flowchart showing the procedure of printed circuit board design by the printed circuit board design device 20 of the first embodiment. FIG. 11 is a diagram showing an example of circuit blocks of a new board. FIG. 12 is a diagram showing an example of a netlist of circuit blocks of a new board. FIG. 13 is a diagram showing a circuit block graph of a new board. FIG. 14 is a diagram showing an example of a board graph. FIG. 15 is a diagram showing an example of a subgraph G(1,1). FIG. 16 is a diagram showing an example of a subgraph G(1,2). 1 is a diagram showing an example of a subgraph G(1,3). 2 is a diagram showing an example of a subgraph G(1,4). 3 is a flowchart showing a procedure for printed circuit board design by the printed circuit board design device 20 of the second embodiment. 4 is a flowchart showing a procedure for printed circuit board design by the printed circuit board design device 20 of the third embodiment. 5 is a diagram showing the configuration of a graph neural network of the fourth embodiment. 6 is a diagram showing example data related to subgraph G1. 7 is a diagram showing example data related to subgraph G2. 8 is a diagram showing subgraph G1, a feature matrix M3 of subgraph G1, subgraph G2, and a feature matrix M3 of subgraph G2. 9 is a flowchart showing a procedure for printed circuit board design by the printed circuit board design device 20 of the fourth embodiment. 10 is a diagram showing the configuration of a graph neural network of the fifth embodiment. 11 is a diagram showing the hardware configuration of the learning device 10. 12 is a diagram showing the hardware configuration of the printed circuit board design device 20.

[0009] Hereinafter, embodiments will be described with reference to the drawings. First Embodiment (Printed Circuit Board Design Apparatus) Fig. 1 is a diagram showing the configuration of a learning apparatus 10 according to the first embodiment.

[0010] The learning device 10 includes an input device 11, a display device 12, a designed board data storage unit 13, a learned model storage unit 14, a board graph creation unit 15, a subgraph extraction unit 16, a similarity setting unit 17, a learning data creation unit 18, a learning data storage unit 41, and a model generation unit 19.

[0011] The input device 11 receives input from a board designer (user), and the display device 12 displays a screen required for board design.

[0012] The designed board data storage unit 13 stores data on previously designed boards. The board data includes component information, pin information, wiring information, a netlist, and the like.

[0013] A netlist represents the connection relationships between components. Component information includes component names, component attributes, and component positions (X and Y coordinates). Component attributes include the component model number (product number), component type, shape type, width, height, and number of pins. Component types include resistors, ICs, and capacitors. Shape types include rectangular parallelepipeds and cylinders.

[0014] The pin information includes the pin name, the pin position (X coordinate, Y coordinate), and the mounting type. The mounting type indicates surface mounting, insertion mounting, etc. The mounting type may also indicate the soldering type (hot air method, condensation method, heater method, light heating method, or soldering iron method).

[0015] The wiring information includes the wiring name, wiring attribute, wiring path, wiring width, etc. The wiring attribute includes the wiring type, the number of connection pins, the frequency of the signal to be transmitted, the voltage to be transmitted, etc. The wiring type indicates whether the wiring transmits a power supply voltage, a ground voltage, or a signal.

[0016] The board graph creator 15 uses data on the designed board to create a graph (board graph) that represents the components included in the designed board and the connections between the components. The graph includes nodes that represent components, pins, and wiring, and edges that represent the connections between the nodes.

[0017] The subgraph extraction unit 16 extracts subgraphs included in the board graph from the board graph.

[0018] The similarity setting unit 17 sets the similarity between two subgraphs. The similarity can be set automatically, or a value input by the designer to the input device 11 can be used.

[0019] The learning data creating unit 18 creates learning data for generating a model. The learning data storage unit 41 stores the learning data created by the learning data creating unit 18.

[0020] The model generation unit 19 uses the learning data stored in the learning data storage unit 41 to generate a trained model that generates a feature vector of an N-dimensional subgraph from information representing the subgraph through metric learning.

[0021] The trained model storage unit 14 stores the trained model generated by the model generation unit 19.

[0022] (Learning Process) FIG. 2 is a flowchart showing the procedure of the learning process performed by the learning device 10 of the first embodiment.

[0023] In step S101, the board graph creation unit 15 uses the designed data in the designed data storage unit 13 to create a board graph for the designed board.

[0024] 3 is a diagram showing an example of a board graph. The board graph has nodes and edges. The nodes include component nodes, pin nodes, and wiring nodes. Component nodes and pin nodes are connected by edges. Pin nodes and wiring nodes are connected by edges.

[0025] 4 is a diagram showing the attribute vector of a node. The 0th to 2nd elements of the attribute vector of a node represent the node type. If the node is a component node, the 0th, 1st, and 2nd elements are 1, 0, and 0, respectively. If the node is a pin node, the 0th, 1st, and 2nd elements are 0, 1, and 0, respectively. If the node is a wiring node, the 0th, 1st, and 2nd elements are 0, 0, and 1, respectively.

[0026] The third, fourth, fifth, sixth, and seventh elements of the attribute vector of a part node are values ​​representing the width, height, number of pins, part type, and shape type. The attribute vector of a part node may include at least one of the third, fourth, fifth, sixth, and seventh elements.

[0027] The third, fourth, and fifth elements of the attribute vector of the pin node are values ​​representing the X coordinate, Y coordinate, and implementation type. The attribute vector of the pin node may include at least one of the third, fourth, and fifth elements.

[0028] The third, fourth, fifth, and sixth elements of the attribute vector of the wiring node are values ​​representing the wiring type, the number of connection pins, the frequency of the signal to be transmitted, and the voltage to be transmitted. The attribute vector of the wiring node may include at least one of the third, fourth, fifth, and sixth elements.

[0029] In step S102, the subgraph extraction unit 16 extracts multiple subgraphs from the board graph of the designed board. Each subgraph includes a parent component node and one or more child component nodes that are directly or indirectly connected to the parent component node. The parent component is, for example, a component whose component type is an IC or a connector.

[0030] In step S103, the similarity setting unit 17 sets the similarity between two subgraphs among the plurality of subgraphs extracted in step S102.

[0031] For example, if the conditions that the component types of the parent component nodes of the two subgraphs match and the difference in width is within a certain value and the difference in height is within a certain value are not satisfied, the similarity setting unit 17 can set the similarity to 0. If the conditions that the component types of the parent component nodes of the two subgraphs match and the difference in width is within a certain value and the difference in height is within a certain value are satisfied, the similarity setting unit 17 can set the similarity to the proportion of the component nodes of the two subgraphs that match in component types and have a difference in width and a difference in height within a certain value.

[0032] 5 is a diagram showing a first example of similarity setting. As shown in FIG. 5, subgraphs of the same circuit have a similarity of "1".

[0033] 6 shows a second example of similarity setting. In the example of Fig. 6, the component types of the parent components (ICs) of the two subgraphs match, but the conditions that the difference in width and the difference in height are within a certain value are not met, so the similarity is set to "0".

[0034] 7 is a diagram showing a third example of similarity setting. In the example of FIG. 7, the component types of the parent components (ICs) of the two subgraphs match, and the conditions that the difference in width and the difference in height are within a certain value are met. The number of component nodes in subgraph G1 is three (one IC and two capacitors), and the number of component nodes in subgraph G2 is four (one IC and three capacitors). In subgraphs G1 and G2, the types of the three components match, and the difference in width and the difference in height are within a certain value. Therefore, the similarity is set to "0.75" (= 3 / 4).

[0035] 8 is a diagram showing a fourth example of similarity setting. In the example of FIG. 8, the component types of the parent components (ICs) of the two subgraphs match, and the conditions that the difference in width and height are within a certain value are met. The number of component nodes in subgraph G1 is three (one IC and two capacitors), and the number of component nodes in subgraph G2 is three (one IC and two capacitors). In subgraphs G1 and G2, the two component types match, and the difference in width and height are within a certain value. This is because the size of one capacitor in subgraph G2 is larger than the corresponding capacitor in subgraph G1. Therefore, the similarity is set to "0.66" (= 2 / 3).

[0036] The method for setting the similarity between graphs is not limited to the above-described method. For example, similarity may be set using attributes of not only component nodes but also pin nodes and wiring nodes.

[0037] In step S104, the learning data creation unit 18 creates learning data consisting of information representing two of the multiple subgraphs and the similarity between the two subgraphs, and stores the data in the learning data storage unit 41. The information representing the subgraphs includes an attribute vector of each node included in the subgraph and an adjacency matrix that defines the adjacency relationship between each node.

[0038] In step S105, the model generation unit 19 uses the training data stored in the training data storage unit 41 to generate a trained model that generates a feature vector of an N-dimensional subgraph from information representing the subgraph by distance learning. The model generation unit 19 performs distance learning so as to reduce the error between the COS similarity between a first feature vector generated from information representing a first subgraph and a second feature vector generated from information representing a second subgraph, and the similarity set in step S103. For example, mean squared error can be used as the loss function. The model generation unit 19 generates a graph neural network as a trained model by distance learning. The model generation unit 19 stores the generated trained model in the trained model storage unit 14.

[0039] FIG. 9 is a diagram illustrating an example of the configuration of a graph neural network according to the first embodiment.

[0040] The graph neural network includes a first GCN (Graph Convolution Network) layer LY1, which is an input layer, a second GCN layer LY2, a third GCN layer LY3, and a pooling layer LY4, which is an output layer.

[0041] The first, second, and third GCN layers LY1, LY2, and LY3 are used to update node features while taking into account the relationships between nodes in the graph structure data. The first, second, and third GCN layers LY1, LY2, and LY3 aggregate information from neighboring nodes. Through this process, structural and local characteristics of the entire graph are encoded. The pooling layer LY4 calculates the graph-wide average of the node features obtained through the first, second, and third GCN layers LY1, LY2, and LY3. This outputs a representative feature representation of the entire graph. This averaging process allows comparison between graphs of different sizes and shapes.

[0042] The configuration of the graph neural network is not limited to that shown in Fig. 9. The number of GGCN layers may be increased or decreased. Dropout layers or Linear layers may be added.

[0043] (Board Design) FIG. 10 is a diagram showing the configuration of a printed circuit board design device 20. As shown in FIG.

[0044] The printed circuit board design device 20 includes an input device 21, a display device 22, a designed board data storage unit 23, a learned model storage unit 24, a new board data storage unit 25, a board graph creation unit 26, a circuit block creation unit 27, a circuit block graph creation unit 28, a subgraph extraction unit 29, a feature extraction unit 30, a similarity calculation unit 31, and a new board layout design unit 32.

[0045] The input device 21 receives input from a board designer (user), and the display device 22 displays a screen required for board design.

[0046] The designed board data storage unit 23 stores data on previously designed boards, similar to the designed board data storage unit 13 of the learning device 10.

[0047] The trained model storage unit 24 stores the trained model created by the learning device 10.

[0048] The new board data storage unit 25 stores data on new boards. The data on new boards includes component information, wiring information, a netlist, and the like for the new board, similar to the data on designed boards.

[0049] Similar to board graph creation unit 15 of learning device 10, board graph creation unit 26 uses data on the designed board to create a graph (board graph) representing the components included in the designed board and the connections between the components. The graph includes nodes representing components, pins, and wiring, and edges representing the connections between the nodes.

[0050] The circuit block creation unit 27 creates a circuit block for the new board. The circuit block includes a parent component and a child component that is directly or indirectly connected to the parent component.

[0051] The circuit block graph creating unit 28 creates a circuit block graph that represents the components included in the circuit block created by the circuit block creating unit 27 and the connections between the components.

[0052] The subgraph extraction unit 29 searches for nodes of components of the same type as a specific component included in the circuit block from among the multiple nodes included in the board graph, and sets the node of the component found as the starting node, and extracts multiple subgraphs from the board graph that include the starting node and have a number of nodes equal to or less than the number of nodes in the circuit block graph.

[0053] The feature extraction unit 30 extracts features of the circuit block graph from the information representing the circuit block graph and extracts features of the subgraph from the information representing the subgraph, using the trained model stored in the trained model storage unit 24. The information representing the circuit block graph includes an attribute vector of each node included in the circuit block graph and an adjacency matrix that defines the adjacency relationships of each node. The information representing the subgraph includes an attribute vector of each node included in the subgraph and an adjacency matrix that defines the adjacency relationships of each node.

[0054] The similarity calculation unit 31 calculates the similarity between the characteristics of the circuit block graph and the characteristics of each subgraph.

[0055] The new board layout design unit 32 selects a subgraph from among the multiple subgraphs based on the calculated similarity. The new board layout design unit 32 can determine the positions of components, pins, and wires within the circuit block using information about the nodes in the selected subgraph. The new board layout design unit 32 can determine the position of the entire circuit block based on the positions within the designed board of all nodes included in the selected subgraph.

[0056] FIG. 11 is a flowchart showing the procedure for designing a printed circuit board by the printed circuit board design device 20 of the first embodiment.

[0057] In step S201, the circuit block creation unit 27 creates a circuit block for a new board. The circuit block for the new board includes a parent component and a child component connected directly or indirectly to the parent component. The component type of the parent component is an IC, a connector, or the like.

[0058] FIG. 12 is a diagram showing an example of a circuit block of a new board. FIG. 13 is a diagram showing an example of a netlist of the circuit block of a new board. As shown in FIG. 12, the circuit block includes a parent component, IC1, and child components, R1, C1, and C2. IC1 has three pins. As shown in FIG. 13, a wire W1 connects pin P1 of IC1 to pin P4 of C1. A wire W2 connects pin P2 of IC1 to pin P5 of R1. A wire W3 connects pin P3 of IC1 to pin P6 of C2.

[0059] In step S202, the circuit block graph creation unit 28 creates a graph of the circuit blocks (circuit block graph) of the new board.

[0060] Figure 14 is a diagram showing the circuit block graph of a new board. The number of nodes M in the circuit block graph of the new board is 13. As shown in Figure 14, the nodes of pins P1, P2, and P3 of IC1 are connected to the node of component IC1. The node of pin P4 of component C1 is connected to the node of component C1. The node of pin P4 and the node of pin P1 are connected by a node of wiring W1. The node of pin P5 of component R1 is connected to the node of component R1. The node of pin P5 and the node of pin P2 are connected by a node of wiring W2. The node of pin P6 of component C2 is connected to the node of component C2. The node of pin P6 and the node of pin P3 are connected by a node of wiring W3.

[0061] In step S203, the board graph creation unit 26 uses the data in the designed board data storage unit 23 to create a board graph for the designed board.

[0062] Fig. 15 is a diagram showing an example of a board graph. Fig. 15 shows a portion of the board graph. The component nodes include nodes IC1, IC2, IC3, IC7, R1, R2, R3, R5, R7, C1, C3, C5, and C8.

[0063] In step S204, the subgraph extraction unit 29 searches for nodes (starting nodes) of the same component type as the parent component included in the circuit block graph of the new board. It is assumed that L starting nodes ND(1), ND(2), ... ND(L) are searched for.

[0064] In step S205, the subgraph extraction unit 29 extracts, from the substrate graph, for each of the L starting nodes ND(i), a plurality of subgraphs G(i, j) including the starting node and having two or more and M or less nodes.

[0065] Assume that the parent component of the circuit block graph of the new board is IC. Assume that a node of the same component type, IC1, is searched for from the board graph. Below, we will explain the subgraph when the starting node ND(1) is IC1.

[0066] 16 is a diagram showing an example of subgraph G(1,1). Subgraph G(1,1) includes component nodes IC1, C1, R5, and R2. Subgraph G(1,1) also includes pin nodes for these components and wiring nodes between the two pins. The number of nodes in subgraph G(1,1) is 13 (=M).

[0067] 17 is a diagram showing an example of subgraph G(1,2). Subgraph G(1,2) includes component nodes IC1, C5, and R3. Subgraph G(1,2) also includes pin nodes for these components and wiring nodes between the two pins. The number of nodes in subgraph G(1,2) is 9 (<M).

[0068] 18 is a diagram showing an example of subgraph G(1,3). Subgraph G(1,3) includes component nodes IC1, C1, and R1. Subgraph G(1,3) also includes pin nodes for these components and wiring nodes between the two pins. The number of nodes in subgraph G(1,3) is 9<(M).

[0069] 19 is a diagram showing an example of subgraph G(1,4). Subgraph G(1,4) includes component nodes IC1, C1, R5, and C5. Subgraph G(1,4) also includes pin nodes for these components and wiring nodes between the two pins. The number of nodes in subgraph G(1,4) is 13 (=M).

[0070] In step S206, the feature extraction unit 30 inputs information representing the circuit block graph of the new board into the trained model stored in the trained model storage unit 24, and obtains a feature vector V1 of the N-dimensional circuit block graph of the new board output from the trained model. The information representing the circuit block graph includes an attribute vector of each node included in the circuit block graph and an adjacency matrix that defines the adjacency relationships of each node.

[0071] In step S207, the feature extraction unit 30 inputs information representing the subgraph G(i, j) to the trained model stored in the trained model storage unit 24, and obtains a feature vector V2(i, j) of the N-dimensional subgraph output from the trained model. The information representing the subgraph G(i, j) includes an attribute vector of each node included in the subgraph G(i, j) and an adjacency matrix that defines the adjacency relationships of each node.

[0072] In step S208, the similarity calculation unit 31 calculates the COS similarity between the feature vector V1 of the circuit block graph output from the output layer (pooling layer LY4) of the graph neural network when information representing the circuit block graph of the new board is input to the input layer (first GCN layer LY1) of the graph neural network, and the feature vector V2(i, j) of the subgraph G(i, j) output from the output layer (pooling layer LY4) of the graph neural network when information representing the subgraph is input to the input layer (first GCN layer LY1) of the graph neural network.

[0073] In step S209, the similarity calculation unit 31 displays the calculation results of the COS similarity on the display device 22. For example, the similarity calculation unit 31 may extract subgraphs having a predetermined number of feature vectors V2 from among those with high COS similarity, and display information about the nodes of these subgraphs or a part of the circuit diagram of the designed board that includes these subgraphs.

[0074] In step S210, the new board layout design unit 32 determines the layout of the circuit blocks of the new board within the new board based on the layout of the extracted subgraph within the designed board. The new board layout design unit 32 determines the positions of the components, pins, and wires within the circuit blocks of the new board based on the positions of the components, pins, and wires represented by the nodes of the extracted subgraph.

[0075] (Effect) As a method for designing a new board using data from previously designed boards, a method that applies a graph isomorphism problem or a subgraph isomorphism determination problem can be considered instead of the method of this embodiment. However, the subgraph isomorphism determination problem is known to be NP-complete, and designers are forced to wait for long periods of time for calculations, especially when designing large-scale circuits or considering complex circuit structures. As a result, it becomes difficult to design quickly and efficiently.

[0076] Furthermore, design support systems are required to have the flexibility to determine whether circuits with different constants or part numbers are similar during the design process. However, methods based on matching searches such as subgraph detection have difficulty providing similarity search functions that allow for such subtle differences, which limits the use of past design data.

[0077] In this embodiment, a similar region estimation method for electric circuits using a graph neural network enables calculations to be performed in a realistic calculation time and enables flexible circuit search.

[0078] Second Embodiment Fig. 20 is a flowchart showing the procedure for designing a printed circuit board by a printed circuit board design device 20 according to a second embodiment. The flowchart in Fig. 20 differs from the flowchart in Fig. 11 according to the first embodiment in that the flowchart in Fig. 20 includes step S204A instead of step S204.

[0079] In step S204A, the subgraph extraction unit 29 searches for nodes that are of the same component type as a parent component included in the circuit block graph of the new board and whose size difference from that parent component is equal to or less than a predetermined value. The size difference may be equal to or less than a first predetermined value in width and a second predetermined value in height.

[0080] <Third embodiment> Fig. 21 is a flowchart showing the procedure for designing a printed circuit board by a printed circuit board design device 20 of a third embodiment. The flowchart of Fig. 21 differs from the flowchart of Fig. 11 of the first embodiment in that the flowchart of Fig. 21 includes step S205B instead of step S205.

[0081] In step S205B, the subgraph extraction unit 29 extracts from the board graph, for each of the L starting nodes ND(i), a plurality of subgraphs G(i,j) each having two or more and M or less nodes, each including the starting node and excluding one or more excluded nodes. The excluded nodes are wiring nodes connected to ground and nodes lower than those wiring nodes. The lower nodes of a wiring node are nodes that are further away from the parent component than the wiring node.

[0082] Fourth Embodiment FIG. 22 is a diagram showing the configuration of a graph neural network according to a fourth embodiment.

[0083] Information representing a graph is input to the first GCN layer LY1, which is the input layer. The feature matrix M1 output from the first GCN layer LY1 is input to the second GCN layer LY2. The feature matrix M2 output from the second GCN layer LY2 is input to the third GCN layer LY3. The feature matrix M3 output from the third GCN layer LY3, which is the layer immediately before the output layer, is input to the pooling layer LY4. An N-dimensional feature vector representing the features of the graph is output from the output layer (pooling layer LY4).

[0084] Next, an example of how a subgraph is processed by a graph neural network will be described. In the following description, for ease of understanding, the subgraph will be described as including only part nodes.

[0085] 23A is a diagram showing an example of a subgraph G1. The subgraph G1 includes nodes A, B, C, D, E, and F.

[0086] FIG. 23(b) is a diagram showing the attribute vectors of nodes A, B, C, D, E, and F input to the input layer (first GCN layer LY1) of the graph neural network.

[0087] Fig. 23(c) is a diagram showing the feature matrix M1 output from the first GCN layer LY1, and Fig. 23(d) is a diagram showing the feature matrix M3 output from the third GCN layer LY3.

[0088] The first row of the feature matrices M1 and M3 represents the characteristics of node A and the characteristics of the connection relationships between nodes surrounding node A. The second row of the feature matrices M1 and M3 represents the characteristics of node B and the characteristics of the connection relationships between nodes surrounding node B. The third row of the feature matrices M1 and M3 represents the characteristics of node C and the characteristics of the connection relationships between nodes surrounding node C. The fourth row of the feature matrices M1 and M3 represents the characteristics of node D and the characteristics of the connection relationships between nodes surrounding node D. The fifth row of the feature matrices M1 and M3 represents the characteristics of node E and the characteristics of the connection relationships between nodes surrounding node E. The sixth row of the feature matrices M1 and M3 represents the characteristics of node F and the characteristics of the connection relationships between nodes surrounding node F. The feature matrix M2 output from the second GCN layer LY2 is similar, so its description will be omitted.

[0089] 23(e) is a diagram showing a feature vector output from pooling layer LY4. FIG. 24(a) is a diagram showing an example of subgraph G2. Subgraph G2 includes nodes X, Y, Z, and W.

[0090] Fig. 24(b) is a diagram showing the feature matrix M3 output from the third GCN layer LY3, and Fig. 24(c) is a diagram showing the feature vectors output from the pooling layer LY4.

[0091] The similarity between the subgraph G1 and the subgraph G2 can be calculated by the COS similarity between the feature vector in Fig. 23(e) and the feature vector in Fig. 24(c). This also applies to the first to third embodiments.

[0092] In this embodiment, the similarity calculation unit 31 can identify the correspondence between the nodes of the subgraph G1 and the nodes of the subgraph G2 by using the feature matrix M3 of FIG. 23(d) and the feature matrix M3 of FIG. 24(b).

[0093] FIG. 25 is a diagram showing subgraph G1, feature matrix M3 of subgraph G1, subgraph G2, and feature matrix M3 of subgraph G2.

[0094] An example of a method for identifying which node in subgraph G2 corresponds to which node in subgraph G1 will be described below.

[0095] The vector in the first row of feature matrix M3 of subgraph G1 represents the feature of node A. The similarity calculation unit 31 searches for a vector that has the greatest COS similarity with the vector in the first row from among the vectors in the first to fourth rows of feature matrix M3 of subgraph G2. For example, if the vector in the second row of feature matrix M3 of subgraph G2 has the greatest COS similarity, the similarity calculation unit 31 determines that node A and node Y correspond to each other.

[0096] Next, the vector in the second row of the feature matrix M3 of subgraph G1 represents the feature of node B. The similarity calculation unit 31 searches for the vector with the greatest COS similarity with the vector in the second row from among the vectors in the first, third, and fourth rows of the feature matrix M3 of subgraph G2. For example, if the vector in the third row of the feature matrix M3 of subgraph G2 has the greatest COS similarity, the similarity calculation unit 31 determines that node B corresponds to node Z. Thereafter, the similarity calculation unit 31 similarly determines which nodes in subgraph G2 correspond to nodes C and D in subgraph G1.

[0097] The method for identifying the correspondence between nodes is not limited to the above. For example, a combination that minimizes the sum of squares of errors between corresponding vectors may be selected.

[0098] Fig. 26 is a flowchart showing the procedure for designing a printed circuit board by the printed circuit board design device 20 of the fourth embodiment. The flowchart of Fig. 26 differs from the flowchart of Fig. 11 of the first embodiment in that the flowchart of Fig. 26 includes step S2081C and step S209C instead of step S209.

[0099] In step S2081C, the similarity calculation unit 31 identifies nodes of the subgraph corresponding to nodes of the circuit block graph, using the feature matrix M3 of the circuit block graph output from the layer immediately before the output layer (third GCN layer LY3) of the graph neural network when information representing a circuit block graph is input to the input layer (first GCN layer LY1) of the graph neural network, and the feature matrix M3 of the subgraph output from the layer immediately before the output layer (third GCN layer LY3) of the graph neural network when information representing a subgraph is input to the input layer (first GCN layer LY1) of the graph neural network. Specific examples of the identification method are as described above.

[0100] In step S209C, the similarity calculation unit 31 displays the calculation results of the COS similarity and the correspondence between the nodes of the two graphs on the display device 22. For example, the similarity calculation unit 31 may extract subgraphs having a predetermined number of feature vectors V2 from among those with high COS similarity, and display information about the nodes of these subgraphs or parts of the circuit diagram that include these subgraphs. Furthermore, the similarity calculation unit 31 may display nodes of the subgraphs that correspond to nodes of the circuit block graph.

[0101] Fifth Embodiment In the above-described embodiment, the similarity calculation unit 31 calculated the COS similarity between the feature vector of the circuit block graph output from the pooling layer, which is the output layer of the graph neural network, when information representing a circuit block graph is input to the input layer (first GCN layer LY1) of the graph neural network, and the feature vector of the subgraph output from the pooling layer, which is the output layer of the graph neural network, when information representing a subgraph is input to the input layer (first GCN layer LY1) of the graph neural network.

[0102] 27 is a diagram showing the configuration of a graph neural network according to the fifth embodiment. In this embodiment, the graph neural network does not include a pooling layer LY4, and the third GCN layer LY3 is the output layer. In this embodiment, the similarity calculation unit 31 calculates the COS similarity using the feature matrix M3 output from the third GCN layer LY3.

[0103] The number of rows in the feature matrix M3 varies depending on the number of nodes in the graph input to the graph neural network. The more nodes in the graph input to the graph neural network, the more rows in the feature matrix M3. Specifically, when the number of nodes in the graph input to the graph neural network is K, the number of rows in the feature matrix M3 is K.

[0104] The similarity calculation unit 31 executes the following processing when, when information representing a circuit block graph is input to the input layer (first GCN layer LY1) of the graph neural network, the number of rows in the feature matrix M3(A) of the circuit block graph output from the third GCN layer LY3, which is the output layer of the graph neural network, is NA, and when, when information representing a subgraph is input to the input layer (first GCN layer LY1) of the graph neural network, the number of rows in the feature matrix M3(B) of the subgraph output from the third GCN layer LY3, which is the output layer of the graph neural network, is NB.

[0105] When NA > NB, the similarity calculation unit 31 generates a feature matrix M31(B) with number of rows NB by padding the feature matrix M3(B) with number of rows NB, and sets M31(A) = M3(A). When NA < NB, the similarity calculation unit 31 generates a feature matrix M31(A) with number of rows NB by padding the feature matrix M3(A) with number of rows NA, and sets M31(B) = M3(B). When NA = NB, the similarity calculation unit 31 sets M31(A) = M3(A) and M31(B) = M3(B). The padding can be 0, an arbitrary value, the average, or the median.

[0106] The similarity calculation unit 31 calculates the COS similarity between the vector in the i-th row of the feature matrix M31(A) and the vector in the i-th row of the feature matrix M31(B), where i = 1 to RN. The similarity calculation unit 31 calculates the average value of the RN calculated COS similarities as the similarity between the circuit block graph and the subgraph.

[0107] <Modification of the Fifth Embodiment> The similarity calculation unit 31 sets the maximum number of rows in the feature matrix M3 generated from all graphs input to the graph neural network to RN. For feature matrices M3 generated from the graphs input to the graph neural network that do not have RN rows, the similarity calculation unit 31 extends the number of rows to RN by padding. The padding can use 0, any value, the average, or the median.

[0108] When information representing a circuit block graph is input to the input layer (first GCN layer LY1) of the graph neural network, if the number of rows of the feature matrix M3(A) of the circuit block graph output from the third GCN layer LY3, which is the output layer of the graph neural network, is not RN, the similarity calculation unit 31 performs padding processing to generate a feature matrix M31(A) with the number of rows RN. If the number of rows of the feature matrix M3(A) is RN, then M31(A) = M3(A).

[0109] When information representing a subgraph is input to the input layer (first GCN layer LY1) of the graph neural network, if the number of rows of the feature matrix M3(B) of the subgraph output from the third GCN layer LY3, which is the output layer of the graph neural network, is not RN, the similarity calculation unit 31 performs padding processing to generate a feature matrix M31(B) with the number of rows RN. If the number of rows of the feature matrix M3(B) is RN, then M31(B) = M3(B).

[0110] The similarity calculation unit 31 calculates the COS similarity between the vector in the i-th row of the feature matrix M31(A) and the vector in the i-th row of the feature matrix M31(B), where i = 1 to RN. The similarity calculation unit 31 calculates the average value of the RN calculated COS similarities as the similarity between the circuit block graph and the subgraph.

[0111] (Hardware Configuration) FIG. 28 is a diagram showing the hardware configuration of the learning device 10.

[0112] The learning device 10 can be realized by a known personal computer or the like. The learning device 10 includes a processor 100, a display device 12 such as an LCD display, an input device 11 such as a keyboard and a mouse, an internal storage device 400 such as memory, an external storage device 500 such as a hard disk or portable recording medium, and a communication device 600. The input device 11 accepts input from a designer. The communication device 600 can receive learning programs and data from an external device via the Internet or the like. The external storage device 500 can store the learning programs and data. The internal storage device 400 stores the learning programs and data transferred from the communication device 600 or the external storage device 500. The processor 100 executes the learning program stored in the internal storage device 400. This executes processing according to the flowchart of FIG. 2.

[0113] FIG. 29 is a diagram showing the hardware configuration of the printed circuit board design device 20. The printed circuit board design device 20 can be realized using a known personal computer or the like. The printed circuit board design device 20 includes a processor 100A, a display device 22 such as an LCD display, an input device 21 such as a keyboard and a mouse, an internal storage device 400A such as a memory, an external storage device 500A such as a hard disk or portable recording medium, and a communication device 600A. The input device 21 accepts input from a designer. The communication device 600A can receive a printed circuit board design program and data from an external device via the Internet or the like. The external storage device 500A can store the printed circuit board design program and data. The internal storage device 400A stores the printed circuit board design program and data transferred from the communication device 600A or the external storage device 500A. The processor 100A executes the printed circuit board design program stored in the internal storage device 400A. This executes processing according to the flowchart of FIG. 11.

[0114] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0115] 10 Learning device, 11, 21 Input device, 12, 22 Display device, 13, 23 Designed board data storage unit, 14, 24 Learned model storage unit, 15, 26 Board graph creation unit, 16, 29 Subgraph extraction unit, 17 Similarity setting unit, 18 Learning data creation unit, 19 Model generation unit, 20 Printed circuit board design device, 25 New board data storage unit, 27 Circuit block creation unit, 28 Circuit block graph creation unit, 30 Feature extraction unit, 31 Similarity calculation unit, 32 New board layout design unit, 41 Learning data storage unit, 100, 100A Processor, 400, 400A Internal storage device, 500, 500A External storage device, 600, 600A Communication device.

Claims

1. A printed circuit board design device comprising: a board graph creation unit that creates a board graph representing components included in a designed board and the connections between said components; a circuit block graph creation unit that creates a circuit block graph that represents components included in circuit blocks included in a new board and the connections between said components; a subgraph extraction unit that searches, from multiple nodes included in the board graph, for nodes of the same type as a specific component included in the circuit block, and uses the node of the searched component as a starting node to extract multiple subgraphs including the starting node from the board graph; a feature extraction unit that uses a trained model to extract features of the circuit block graph from information representing the circuit block graph, and extracts features of the subgraphs from information representing the subgraphs; and a similarity calculation unit that calculates the similarity between the features of the circuit block graph and the features of each of the subgraphs.

2. The printed circuit board design device according to claim 1, wherein the subgraph extraction unit extracts a plurality of subgraphs from the board graph that include the starting node and have a number of nodes equal to or less than the number of nodes in the circuit block graph.

3. The printed circuit board design device according to claim 1, wherein the nodes of the board graph and the circuit block graph include component nodes, component pin nodes, and wiring nodes.

4. The printed circuit board design device according to claim 3, wherein the component node has at least one attribute selected from the group consisting of size, number of pins, component type, and shape type.

5. The printed circuit board design device according to claim 3, wherein the pin nodes of the component have at least one attribute of a position and a mounting type.

6. The printed circuit board design device according to claim 3, wherein the wiring nodes have at least one attribute of wiring type, number of connection pins, frequency of a signal to be transmitted, and voltage to be transmitted.

7. A printed circuit board design device as described in claim 1, wherein the subgraph extraction unit searches for a node of a component that is the same type as a specific component included in the circuit block and whose size differs from that of the specific component by a predetermined value or less from the multiple nodes included in the board graph.

8. The printed circuit board design device according to claim 1, wherein said subgraph extraction unit extracts a subgraph that does not include a node of a wiring connected to ground and a lower node of said wiring node.

9. The printed circuit board design device according to claim 1, wherein the trained model is a graph neural network.

10. The printed circuit board design device according to claim 9, wherein the trained model is generated by metric learning.

11. The printed circuit board design device of claim 10, wherein the similarity calculation unit calculates, as the similarity, the COS similarity between a feature vector of the circuit block graph output from the output layer of the graph neural network when information representing the circuit block graph is input to the input layer of the graph neural network, and a feature vector of the subgraph output from the output layer of the graph neural network when information representing the subgraph is input to the input layer of the graph neural network.

12. The printed circuit board design device of claim 11, wherein the similarity calculation unit, when information representing the circuit block graph is input to the input layer of the graph neural network, uses a feature matrix of the circuit block graph output from the layer immediately preceding the output layer of the graph neural network, and when information representing the subgraph is input to the input layer of the graph neural network, uses a feature matrix of the subgraph output from the layer immediately preceding the output layer of the graph neural network to identify nodes of the subgraph that correspond to nodes of the circuit block graph.

13. The printed circuit board design device of claim 10, wherein the similarity calculation unit calculates, as the similarity, the average value of COS similarities between each row of a feature matrix of the circuit block graph output from the output layer of the graph neural network when information representing the circuit block graph is input to the input layer of the graph neural network, and each row of a feature matrix of the subgraph output from the output layer of the graph neural network when information representing the subgraph is input to the input layer of the graph neural network.

14. The printed circuit board design device according to claim 13, wherein the similarity calculation unit calculates the COS similarity of each row of the feature matrix of the circuit block graph and the feature matrix of the subgraph after expanding the rows of either or both of the feature matrix of the circuit block graph and the subgraph by padding processing.

15. A printed circuit board design method comprising the steps of: creating a board graph representing components included in a designed board and the connections between said components; creating a circuit block graph representing components included in a circuit block included in a new board and the connections between said components; searching for a node of a component of the same type as a specific component included in said circuit block from among multiple nodes included in said board graph, setting the node of the searched component as a starting node, and extracting multiple subgraphs including said starting node from said board graph; using a trained model, extracting features of said circuit block graph from information representing said circuit block graph, and extracting features of said subgraphs from information representing said subgraphs; and calculating the similarity between the features of said circuit block graph and the features of each of said subgraphs.

16. A printed circuit board design program that causes a computer to execute the following steps: creating a board graph that represents the components included in a designed board and the connections between said components; creating a circuit block graph that represents the components included in a circuit block included in a new board and the connections between said components; searching for a node of a component of the same type as a specific component included in the circuit block from among multiple nodes included in the board graph, setting the node of the searched component as a starting node, and extracting multiple subgraphs that include the starting node from the board graph; using a trained model, extracting features of the circuit block graph from information representing the circuit block graph, and extracting features of the subgraphs from information representing the subgraphs; and calculating the similarity between the features of the circuit block graph and the features of each of the subgraphs.

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