Semiconductor device

Abstract

The present invention improves learning accuracy in a semiconductor device that performs machine learning.　This semiconductor device includes a prescribed number of memory cells, a driver, and a control circuit. In the semiconductor device, the driver supplies a write pulse to each of the memory cells. Further, the control circuit sequentially performs course tuning for controlling, to a prescribed value, a statistical amount of a change amount of the reciprocal of the impedance of the memory cell for each write pulse, and fine tuning for controlling the statistical amount to a value smaller than the prescribed value.

Description

Semiconductor Devices

[0001] The present technology relates to a semiconductor device, and more particularly to a semiconductor device that performs a product-sum operation.

[0002] Conventionally, artificial intelligence (AI) chips have mainly used product-sum operations using static random access memory (SRAM). However, this configuration consumes a lot of power due to data exchange with peripheral memory when performing learning and inference using programs. Therefore, the use of analog AI, spiking neural networks (SNN), neuromorphic computing, and the like is desired. For example, devices have been proposed that use analog non-volatile memory (NVM) such as resistive RAM (ReRAM) for product-sum operations instead of SRAM (see, for example, Non-Patent Document 1).

[0003] Ruibo Ai, et al., Multilevel resistive switching and synaptic behaviors in MnO-based memristor, Current Applied Physics Volume 41, September 2022, Pages 123-130.

[0004] The above-mentioned conventional technology aims to improve computing performance by using analog NVM instead of SRAM. However, in the above-mentioned conventional technology, if the characteristics of the storage elements in the NVM are not ideal, it becomes difficult to adjust the conductance of the storage elements to a target value. For example, while it is ideal for the amount of change in conductance to be constant per write pulse, this is not the case in reality. Therefore, when the conductance is adjusted up or down around the target value, the average conductance value may deviate from the target value. This results in a problem of reduced learning accuracy in machine learning.

[0005] The present technology was developed in light of these circumstances, and aims to improve the learning accuracy in semiconductor devices that perform machine learning.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is a semiconductor device including a predetermined number of memory cells, a driver that supplies a write pulse to each of the memory cells, and a control circuit that sequentially performs coarse tuning to control a statistic of the reciprocal of the change in impedance of the memory cell for each write pulse to a predetermined value and fine tuning to control the statistic to a value smaller than the predetermined value, thereby improving learning accuracy.

[0007] In this first aspect, each of the memory cells may be provided with a first storage element and a second storage element, thereby providing an effect that the statistics of the amount of change in the reciprocal of the impedance becomes variable.

[0008] In the first aspect, the first memory element and the second memory element may be different in at least one of area and length, thereby providing an effect that the statistics of the amount of change in the reciprocal of the impedance becomes variable.

[0009] In the first aspect, the first storage element and the second storage element may be of different types, thereby providing an effect that the statistics of the amount of change in the reciprocal of the impedance becomes variable.

[0010] In the first aspect, the first memory element and the second memory element may be resistance change elements, thereby providing an effect of adjusting the conductance.

[0011] In addition, in this first aspect, the first memory element and the second memory element may be variable capacitance elements, thereby providing an effect that the capacitance value is adjusted.

[0012] In this first aspect, the driver may include a first driver that supplies a first write pulse, and a second driver that supplies a second write pulse that is different from the first write pulse in at least one of a voltage absolute value and a pulse width, thereby achieving the effect of making the areas and lengths of the first and second memory elements uniform.

[0013] In this first aspect, each of the memory cells may further include a third storage element, thereby providing an effect that the statistics of the amount of change in the reciprocal of the impedance can be adjusted in more stages.

[0014] In the first aspect, one end of the first memory element may be connected to a first signal line, one end of the second memory element may be connected to a second signal line, and the other ends of the first memory element and the second memory element may be commonly connected to a third signal line, thereby providing an effect that the amount of change in the reciprocal of the impedance is adjusted by switching the connection destinations of the first signal line and the second signal line.

[0015] In addition, in this first aspect, the first memory element and the second memory element may be disposed between a wiring layer in which the first signal line and the second signal line are wired and a wiring layer in which the third signal line is wired, thereby reducing manufacturing costs.

[0016] In addition, in this first aspect, the first memory element may be arranged between a first wiring layer in which the first signal line is wired and a third wiring layer in which the third signal line is wired, and the second memory element may be arranged between a second wiring layer in which the second signal line is wired and the third wiring layer, thereby providing an effect of reducing the mounting area.

[0017] In this first aspect, the control circuit may calculate the loss every time the reciprocal of the impedance is updated, and start the fine tuning when the loss is saturated, thereby providing an effect that the reciprocal of the impedance is finely adjusted when the loss is saturated.

[0018] In this first aspect, the control circuit may acquire the updated reciprocal of the impedance each time the reciprocal of the impedance is updated, and start the fine tuning when the reciprocal of the impedance is saturated. This brings about an effect that when the reciprocal of the impedance is saturated, the value of the reciprocal of the impedance is finely adjusted.

[0019] In addition, in this first aspect, each of the memory cells may be provided with a predetermined number of first memory elements and a number of second memory elements that does not correspond to the predetermined number, one end of each of the first memory elements may be connected to a first signal line, one end of each of the second memory elements may be connected to a second signal line, and the other ends of each of the first memory elements and the second memory elements may be connected in common to a third signal line, thereby reducing manufacturing costs.

[0020] In this first aspect, each of the memory cells may be provided with one storage element, and the driver may sequentially supply a first write pulse and a second write pulse that differ in at least one of voltage absolute value and pulse width, thereby reducing the circuit size.

[0021] 1 is a block diagram showing an example of a configuration of a semiconductor device according to a first embodiment of the present technology. FIG. 2 is a circuit diagram showing example configurations of a memory cell array, a switching circuit, a vertical driver, a horizontal driver, and a column ADC (Analog to Digital Converter) according to the first embodiment of the present technology. FIG. 3 is a block diagram showing an example of a configuration of a control circuit according to the first embodiment of the present technology. FIG. 4 is a diagram showing an example of a control method of a control circuit during inference according to the first embodiment of the present technology. FIG. 5 is a diagram showing an example of a control method of a control circuit during learning according to the first embodiment of the present technology. FIG. 6 is a diagram showing an example of a waveform of a write pulse according to the first embodiment of the present technology. FIG. 7 is a perspective view showing an example of a memory element according to the first embodiment of the present technology. FIG. 8 is an example of an equivalent circuit of a memory cell according to the first embodiment of the present technology. FIG. 9 is a perspective view showing an example of an arrangement of memory elements according to the first embodiment of the present technology. FIG. 10 is a flowchart showing an example of an operation of a semiconductor device according to the first embodiment of the present technology. FIG. 11 is a graph showing an example of ideal resistance change characteristics of a memory element used in a product-sum operation and resistance change characteristics of a ReRAM. FIG. 12 is a diagram showing an example of resistance change characteristics and an equivalent circuit according to the first embodiment of the present technology. FIG. 13 is a graph showing an example of a change in conductance in a comparative example and the first embodiment of the present technology. 10 is a diagram showing an example of measurement of the average conductance and σ in a comparative example and a first embodiment of the present technology. FIG. 11 is a diagram showing an example of accuracy for each device in a comparative example and a first embodiment of the present technology. FIG. 12 is a perspective view showing an example of a memory element in a second embodiment of the present technology. FIG. 13 is a circuit diagram showing an example of configurations of a vertical driver, a switching circuit, and a memory cell in a second embodiment of the present technology. FIG. 14 is a circuit diagram showing an example of configurations of a vertical driver, a selector, and a memory cell in a third embodiment of the present technology. FIG. 15 is a perspective view showing an example of a memory element in a third embodiment of the present technology. FIG. 16 is a perspective view showing another example of a memory element in a third embodiment of the present technology. FIG. 17 is an example of an equivalent circuit of a memory cell in a third embodiment of the present technology. FIG. 18 is a perspective view showing an example of a memory element in a fourth embodiment of the present technology. FIG. 19 is a circuit diagram showing an example of configurations of a vertical driver, a selector, and a memory cell in a fourth embodiment of the present technology.13 is a circuit diagram showing an example of the configuration of a vertical drive unit, a selector, and a memory cell according to a fifth embodiment of the present technology. FIG. 14 is a diagram showing an example of a schematic configuration of an IoT system 9000 to which the technology according to the present disclosure can be applied.

[0022] Hereinafter, modes for implementing the present technology (hereinafter referred to as embodiments) will be described. The descriptions will be made in the following order: 1. First embodiment (an example in which coarse and fine tuning are performed in sequence) 2. Second embodiment (an example in which two write pulses with different voltages or the like are supplied and coarse and fine tuning are performed in sequence) 3. Third embodiment (an example in which three memory elements are provided in a memory cell and coarse and fine tuning are performed in sequence) 4. Fourth embodiment (an example in which a plurality of memory elements connected in parallel and one memory element are provided in a memory cell and coarse and fine tuning are performed in sequence) 5. Fifth embodiment (an example in which one memory element is provided in a memory cell and coarse and fine tuning are performed in sequence) 6. Application examples

[0023] 1 is a block diagram showing a configuration example of a semiconductor device 100 according to a first embodiment of the present technology. The semiconductor device 100 is a device that performs machine learning, and includes a memory cell array 110, a switching circuit 130, a switching circuit 140, a vertical drive unit 150, a horizontal drive unit 160, a column ADC 170, a control circuit 180, and an input / output unit 190. In the memory cell array 110, a predetermined number of memory cells (not shown) are arranged in a two-dimensional lattice pattern.

[0024] The switching circuit 130 switches the connection destination of the signal lines wired in the horizontal direction within the memory cell array 110. The vertical drive unit 150 drives the memory cells row by row via the switching circuit 130.

[0025] The switching circuit 140 switches the connection destination of signal lines wired vertically within the memory cell array 110. The horizontal drive unit 160 drives the memory cells on a column-by-column basis. The column ADC 170 converts analog current signals from the memory cell array 110 into digital signals for each column and supplies them to the control circuit 180 as read data.

[0026] The control circuit 180 controls the switching circuit 130, the switching circuit 140, the vertical drive unit 150, and the horizontal drive unit 160. Details of the control by the control circuit 180 will be described later. The input / output unit 190 transmits and receives data to and from the outside.

[0027] FIG. 2 is a circuit diagram showing an example configuration of each of the memory cell array 110, the switching circuits 130 and 140, the vertical drive unit 150, the horizontal drive unit 160, and the column ADC 170 according to the first embodiment of the present technology.

[0028] In the memory cell array 110, a predetermined number of memory cells 120 are arranged in a two-dimensional lattice. Each of the memory cells 120 is provided with a memory element 121 and a memory element 122. For example, a resistance change element in a ReRAM is used as these memory elements 121 and 122. In the memory cell array 110, signal lines 111 and 112 are wired in the horizontal direction for each row, and a signal line 113 is wired in the vertical direction for each column. One end of the memory element 121 is connected to the signal line 111, and one end of the memory element 122 is connected to the signal line 112. The other ends of the memory elements 121 and 122 are connected in common to the signal line 113.

[0029] The memory elements 121 and 122 are examples of the first memory element and the second memory element set forth in the claims, and the signal lines 111, 112, and 113 are examples of the first signal line, the second signal line, and the third signal line set forth in the claims.

[0030] The vertical drive section 150 is provided with a driver 151 for each row. The driver 151 generates a pulse signal under the control of the control circuit 180 and supplies it to the corresponding row via the switching circuit 130.

[0031] The switching circuit 130 is provided with a selector 131 for each row. The selector 131 connects at least one of the signal lines 111 and 112 to the driver 151 in accordance with a selection signal SELv from the control circuit 180. The selection signal SELv includes selection signals SELvx and SELvy.

[0032] The column ADC 170 is provided with an ADC 171 for each column. The ADC 171 converts a current signal from the corresponding column into a digital signal and supplies it to the control circuit 180 as read data RD.

[0033] The horizontal drive unit 160 is provided with a driver 161 for each column. The driver 161 generates a pulse signal under the control of the control circuit 180 and supplies it to the corresponding column via the switching circuit 140.

[0034] A pulse consisting of a pulse signal from driver 151 and a pulse signal from driver 151 is used to write to memory cell 120. This pulse is hereinafter referred to as a "write" pulse.

[0035] The switching circuit 140 is provided with a selector 141 for each column. The selector 141 connects the signal line 113 to one of the driver 161 and the ADC 171 in accordance with a switching signal SELh from the control circuit 180.

[0036] The driver 151 and the driver 161 supply write pulses to adjust the conductance (in other words, the inverse of the impedance) of the memory cell 120. In machine learning, the conductance is used as a weight for the input value to the neuron. The conductance value increases or decreases depending on the polarity of the voltage of the write pulse. Furthermore, the write pulse is supplied multiple times as necessary. The absolute voltage value and pulse width of each write pulse are assumed to be the same, for example. Furthermore, the statistics (such as the average) of the amount of change in the conductance of the memory cell 120 for each write pulse are assumed to be variable.

[0037] The selector 131 also includes, for example, nMOS transistors 132 and 133. The nMOS transistor 132 opens and closes the path between the driver 151 and the signal line 112 in accordance with a selection signal SELvx. The nMOS transistor 133 opens and closes the path between the driver 151 and the signal line 111 in accordance with a selection signal SELvy.

[0038] The control circuit 180 repeatedly performs learning and inference in machine learning. In learning, the weights (i.e., the conductance of the memory cell 120) are adjusted by the write pulse, but as described above, the statistics of the conductance change amount for each write pulse are variable. For example, the statistics of the conductance change amount can be changed in two stages, and the process of controlling this value to the larger value is hereinafter referred to as "coarse tuning." On the other hand, the process of controlling the statistics of the change amount to a value smaller than the coarse tuning value is hereinafter referred to as "fine tuning."

[0039] For example, the statistics (such as the average) of the amount of change in conductance of the storage element 121 for each write pulse is set to a value different from that of the storage element 122. Here, the amount of change indicates the amount of increase or decrease, and the statistics of the amount of change indicates, for example, the statistics of the amount of increase and the absolute value of the amount of decrease. For example, the statistics of the amount of change in conductance of the storage element 121 is 0.8 G, and the statistics of the amount of change in conductance of the storage element 122 is 0.2 G.

[0040] When performing coarse tuning, the control circuit 180 sets both the selection signals SELvx and SELvy to a high level, for example. The control circuit 180 also causes the drivers 151 and 161 to supply write pulses and controls the selector 141 to connect the signal line 113 to the driver 161. By these controls, the storage elements 121 and 122 are connected in parallel in the memory cell 120, and the amount of change in their combined conductance is 1.0 G.

[0041] When performing fine tuning, the control circuit 180 sets only one of the selection signals SELvx and SELvy to a high level and the other to a low level. For example, the selection signal SELvx is controlled to a high level and the selection signal SELvy to a low level. The control circuit 180 also controls the drivers 151 and 161 to supply write pulses and controls the selector 141 to connect the signal line 113 to the driver 161. With these controls, only the memory element 122 in the memory cell 120 is connected to the driver 151, and the statistical amount of change in the conductance of the memory cell 120 is 0.2 G.

[0042] When performing inference, the control circuit 180 sets both the selection signals SELvx and SELvy to a high level. The control circuit 180 also causes the driver 151 to supply a read pulse and controls the selector 141 to connect the signal line 113 to the ADC 171. Through these controls, a current signal corresponding to the product of the conductance of the memory cell 120 and the voltage of the read pulse flows for each column.

[0043] 3 is a block diagram showing an example of the configuration of the control circuit 180 according to the first embodiment of the present technology. The control circuit 180 includes a weight setting update unit 181, a prediction unit 182, a loss calculation unit 183, and a determination unit 184.

[0044] The weight setting update unit 181 initializes and updates the conductance (i.e., weight) of each memory cell 120. The weight setting update unit 181 first starts coarse tuning. In coarse tuning, the weight setting update unit 181 controls the vertical drive unit 150, the horizontal drive unit 160, and the switching circuits 130 and 140 to supply write pulses and initialize the weights. In coarse tuning, the statistics of the amount of change in conductance for each write pulse is set to a predetermined value (e.g., 1.0 G).

[0045] The prediction unit 182 obtains a predicted value when the weight is initially set or each time the weight is updated. The prediction unit 182 controls the vertical drive unit 150, the switching circuit 130, the switching circuit 140, and the column ADC 170 to supply a read pulse and read the read data RD. The prediction unit 182 supplies the value indicated by the read data RD to the loss calculation unit 183 as a predicted value y. The predicted value y is expressed by the following equation, for example: y=f ｗ (x) ...Equation 1 In the above equation, x is the input value to the neuron, and f ｗ (x) denotes the function used in the neuron, and w denotes the weight.

[0046] The loss calculation unit 183 calculates the loss Δ based on the predicted value. The loss calculation unit 183 acquires the correct answer value Y and the learning rate α from the input / output unit 190, calculates the loss Δ using the following formula, for example, and supplies it to the weight setting update unit 181 and the determination unit 184. Δ=α∇L(w) Formula 2

[0047] In Equation 2, ∇ denotes total differential. Furthermore, L(w) is a loss function, which is expressed by the following equation, for example: L(w)=(Y−y) ２ ...Formula 3

[0048] The determination unit 184 determines whether the loss Δ is saturated. For example, the determination unit 184 obtains thresholds Th1, Th2, and Th3 from the input / output unit 190, and determines whether the following formula is true: Δ<Th1 (Formula 4)

[0049] If Equation 4 holds, the determining unit 184 determines that the loss Δ is saturated. The determining unit 184 supplies the determination result to the weight setting update unit 181.

[0050] If the loss Δ is not saturated, the weight setting update unit 181 updates the weight using, for example, the following equation: w ｔ＋１ =w ｔ -Δ ... Equation 5 In the above equation, t (t is an integer) is the number of times of learning, and w ｔ denotes the weight of the tth time.

[0051] On the other hand, when the loss Δ is saturated, the weight setting update unit 181 starts fine tuning. In fine tuning, the statistics of the change in conductance (weight) for each write pulse is set to a value (e.g., 0.2 G) smaller than that in coarse tuning. In fine tuning, weight updating (in other words, learning), acquisition of predicted values, and loss calculation (in other words, inference) are also repeatedly performed in sequence.

[0052] Then, every time the loss Δ is calculated in fine tuning, the determining unit 184 determines whether any of the following formulas is true: Δ<Th2 (Formula 6) t>Th3 (Formula 7)

[0053] In Equation 6, the threshold value Th2 is set to, for example, a value equal to or less than Th1. If neither Equation 6 nor Equation 7 holds, the weight setting update unit 181 continues updating the weights. On the other hand, if Equation 6 or Equation 7 holds, the weight setting update unit 181 ends updating (learning) the weights.

[0054] When the learning is completed, the control circuit 180 outputs various data to the input / output unit 190. For example, a notification that the learning is completed and the final conductance value are output.

[0055] 4 is a diagram illustrating an example of a control method of the control circuit 180 during inference according to the first embodiment of the present technology. As illustrated in the diagram, the control circuit 180 controls the driver 151 to supply a read pulse, and controls the selector 141 to connect the ADC 171 to the signal line 113.

[0056] The voltage of the readout pulse for row i (i is an integer) is x ｉ and the value of the current signal in the jth column (j is an integer) is expressed as y ｊ The conductance (weight) of the memory cell 120 in the i-th row and j-th column is w ｉｊ Then, y ｊ is expressed by the following formula, for example:

[0057] As shown in the figure, the semiconductor device 100 executes a product-sum operation using an analog circuit, thereby improving computing performance compared to when an SRAM is used.

[0058] 5 is a diagram showing an example of a control method of the control circuit 180 during learning in the first embodiment of the present technology. As illustrated in the diagram, the control circuit 180 controls the selector 131 to connect the signal lines 111 and 112 to the driver 151 in coarse tuning, and controls the selector 141 to connect the driver 161 to the signal line 113. Note that in fine tuning, one of the signal lines 111 and 112 is connected to the driver 151.

[0059] For each row, the driver 151 supplies a voltage x ｉ For each column, the driver 161 supplies a pulse signal of voltage σ ｊ A pulse signal is supplied.

[0060] 6 is a diagram showing an example of a write pulse waveform according to the first embodiment of the present technology. In the diagram, "a" shows a write pulse waveform when the conductance is updated, and "b" shows a write pulse waveform when the conductance is not updated. As shown in "a" and "b" as examples, the write pulse includes a pulse signal from the row driver 151 and a pulse signal from the column driver 161.

[0061] As shown in FIG. 1A, when the conductance is increased, for example, the row driver 151 applies a positive voltage x ｉ The column driver 161 supplies a pulse signal of a negative voltage σ ｊ When the conductance is to be decreased, the row driver 151 supplies a pulse signal of negative voltage, and the column driver 161 supplies a pulse signal of positive voltage.

[0062] Also, as illustrated in FIG. 1B, when the conductance is not updated, for example, the row-side driver 151 applies a positive voltage x ｉ , and the column-side driver 161 does not supply a pulse signal.

[0063] [Configuration Example of Memory Element] Fig. 7 is a perspective view showing an example of memory elements 121 and 122 according to the first embodiment of the present technology. As illustrated in Fig. 7A, the area of ​​the memory element 121 is different from the area of ​​the memory element 122, but the memory elements 121 and 122 are the same type and have the same length. Here, the areas of the memory elements 121 and 122 correspond to the cross-sectional area of ​​the element when observed from the direction from the row-side terminal connected to the signal line 111 or 112 to the column-side terminal connected to the signal line 113. Furthermore, the lengths of the memory elements 121 and 122 correspond to the distance between the row-side terminal and the column-side terminal.

[0064] Alternatively, as shown in FIG. 1B, the length of the memory element 121 is different from the length of the memory element 122, and the memory elements 121 and 122 are the same type and have the same area.

[0065] The memory element 121 may have a configuration different from that of the memory element 122 in both area and length.

[0066] Alternatively, as illustrated in c in the figure, the type of the memory element 121 is different from the type of the memory element 122. For example, the memory element 121 is a memory element in a ReRAM, and the memory element 122 is a memory element in a PCM (Phase Change Memory).

[0067] As illustrated in a and b in the figure, by providing memory elements 121 and 122 that are different in either area or length, the amount of change in conductance of memory element 121 for each write pulse will be a different value from that of memory element 122. Also, as illustrated in c in the figure, even when memory elements 121 and 122 are different types, the amount of change in conductance of memory element 121 for each write pulse will be a different value from that of memory element 122.

[0068] As described above, in coarse tuning, the conductance of memory cell 120 is the sum of the conductances of storage elements 121 and 122, and in fine tuning, the conductance of memory cell 120 is the value of storage element 122. Therefore, by using the configuration a, b, or c in the figure, it is possible to increase the difference in the amount of change in conductance between coarse tuning and fine tuning.

[0069] 8 is an example of an equivalent circuit of the memory cell 120 according to the first embodiment of the present technology. As illustrated in FIG. 8A, resistance change elements such as those in a ReRAM are used as the memory elements 121 and 122.

[0070] As shown in FIG. 1B, variable capacitance elements may be used as the storage elements 121 and 122. As the variable capacitance elements, for example, MOS capacitors or ferroelectric capacitors may be used.

[0071] When a variable capacitance element is used, the capacitance, which is the reciprocal of the capacitive reactance (in other words, the impedance) of the memory cell, is used as the weight.

[0072] FIG. 9 is a perspective view showing an example of the arrangement of the memory elements 121 and 122 according to the first embodiment of the present technology.

[0073] For example, as illustrated in FIG. 1A, the memory elements 121 and 122 are arranged in the same layer. Specifically, the memory elements 121 and 122 are arranged between the wiring layer 115 on which the signal lines 111 and 112 are wired and the wiring layer 116 on which the signal line 113 is wired.

[0074] Alternatively, as illustrated in FIG. 1B, the memory elements 121 and 122 are arranged on different layers. Specifically, the memory element 121 is arranged between the wiring layer 115 in which the signal line 111 is arranged and the wiring layer 116 in which the signal line 113 is arranged. The memory element 122 is arranged between the wiring layer 117 in which the signal line 112 is arranged and the wiring layer 116.

[0075] The wiring layer 115 is an example of a first wiring layer as defined in the claims, the wiring layer 117 is an example of a second wiring layer as defined in the claims, and the wiring layer 116 is an example of a third wiring layer as defined in the claims.

[0076] In the layout of a in the same figure, the mounting area is increased compared to b in the same figure, but the manufacturing cost is reduced. On the other hand, in the layout of b in the same figure, the manufacturing cost is increased compared to a in the same figure, but the mounting area is reduced.

[0077] 10 is a flowchart showing an example of the operation of the semiconductor device 100 according to the first embodiment of the present technology. This operation is started, for example, when a predetermined application for performing machine learning is executed.

[0078] The control circuit 180 in the semiconductor device 100 first performs coarse tuning setup, in which the weights are set to initial values, and the statistics of the amount of change in conductance (weight) for each write pulse is set to a predetermined value (e.g., 1.0 G) (step S901).

[0079] The control circuit 180 then obtains the predicted value (step S902) and calculates the loss Δ (step S903). The control circuit 180 determines whether the loss Δ is less than a threshold Th1 (step S904). If the loss Δ is greater than or equal to the threshold Th1 (step S904: No), the control circuit 180 controls the matrix driver to update the weights (step S905) and repeatedly executes steps S902 and subsequent steps.

[0080] On the other hand, if the loss Δ is less than the threshold Th1 (step S904: Yes), the control circuit 180 performs fine tuning, in which the statistics of the change in conductance (weight) for each write pulse is set to a smaller value (e.g., 0.2 G) than that in coarse tuning (step S906).

[0081] The control circuit 180 then obtains the predicted value (step S907) and calculates the loss Δ (step S908). The control circuit 180 determines whether the loss Δ is less than a threshold Th2 or whether the number of learning iterations t is greater than a threshold Th3 (step S909). If the loss Δ is greater than or equal to the threshold Th2 and the number of learning iterations t is less than or equal to the threshold Th3 (step S909: No), the control circuit 180 controls the matrix driver to update the weights (step S910) and repeatedly executes steps S907 and subsequent steps.

[0082] On the other hand, if the loss Δ is less than the threshold Th2 or the number of learning times t is greater than the threshold Th3 (step S909: Yes), the control circuit 180 ends the machine learning.

[0083] Note that the control circuit 180 starts fine tuning when the loss Δ becomes less than the threshold value Th1, in other words, when the loss Δ becomes saturated, but this configuration is not limiting. The control circuit 180 can also acquire the updated conductance each time the conductance (i.e., the weight) is updated, and start fine tuning when the updated conductance becomes saturated. Whether the conductance has become saturated is determined, for example, by whether the number of times the conductance has fluctuated around the target value corresponding to the correct value exceeds a predetermined number.

[0084] The control circuit 180 can also initiate fine tuning when the loss Δ is saturated or when the conductance is saturated.

[0085] Here, a configuration in which only one ReRAM storage element is arranged for each memory cell is assumed as a comparative example, and the problems with this comparative example will be described.

[0086] 11 is a graph showing an example of the ideal resistance change characteristic of a memory element used in a product-sum operation and the resistance change characteristic of a ReRAM. In the figure, a indicates the ideal resistance change characteristic, and b indicates the resistance change characteristic of a ReRAM. The vertical axes of a and b in the figure indicate the conductance of the memory element, and the horizontal axis indicates the number of write pulses.

[0087] Regarding the measurement conditions, the initial value of the conductance is set to the minimum value Gｍｉｎ The driver repeatedly supplies write pulses to increase the conductance. ｍａｘ Then, the driver applies a write pulse with the polarity reversed to the conductance minimum G ｍｉｎ Repeatedly supply until the concentration is reduced to .

[0088] As shown in the example of a in the same figure, ideally, the absolute value of the change in conductance for each write pulse (in other words, the slope of the graph) is constant when the conductance is increased and when the conductance is decreased.

[0089] However, as shown in FIG. 1B, in an actual ReRAM, the amount of change in conductance for each write pulse is not constant. In FIG. 1B, when the conductance is increased, the maximum value G ｍａｘ The closer to , the smaller the absolute value of the change (slope) becomes. When the conductance is reduced, the minimum value G ｍｉｎ The difference in absolute value of the change (slope) between increasing the conductance and decreasing the conductance is the maximum value G ｍａｘ or minimum value G ｍｉｎ The closer it gets to G, the larger it becomes. ｍａｘ and the minimum value G ｍｉｎ It reaches a minimum near the middle of

[0090] Therefore, in the comparative example, the target value G of the conductance corresponding to the correct value ｔａｇ The maximum value G ｍａｘ If you set it to a value close to the target value G ｔａｇ When the conductance is increased or decreased near the target value G ｔａｇ may not be reached.

[0091] To solve this problem, in the first embodiment, storage elements 121 and 122 are provided for each memory cell 120 .

[0092] 12A is a graph showing the resistance change characteristics according to the first embodiment of the present technology. The vertical axis of the graph A shows the conductance of the memory cell 120, and the horizontal axis shows the number of write pulses. The solid curve shows the resistance change characteristics in coarse tuning, and the dashed line shows the resistance change characteristics in fine tuning.

[0093] As illustrated in FIG. 1B, in coarse tuning, memory elements 121 and 122 are connected in parallel between row driver 151 and column driver 161. On the other hand, as illustrated in FIG. 1C, in fine tuning, only memory element 122 is connected between driver 151 and driver 161. For example, the statistics (averages, etc.) of the amounts of change in conductance of memory elements 121 and 122 for each write pulse are set to 0.8 G and 0.2 G, respectively.

[0094] In this case, the average change in conductance is 1.0 G in coarse tuning and 0.2 G in fine tuning.

[0095] Here, the average change in conductance is calculated by, for example, setting the conductance to the minimum value G ｍｉｎ to maximum value G ｍａｘ and then the minimum value G ｍｉｎ 4 shows the average of the absolute values ​​of the increase and decrease for each write pulse when the voltage is decreased to .

[0096] As shown in b and c in the figure, by switching the connections of the storage elements 121 and 122, the resistance change characteristics of the memory cell 120 can be switched as shown in a in the figure.

[0097] 13 is a graph showing an example of conductance fluctuation in a comparative example and the first embodiment of the present technology. In the figure, a shows an example of conductance fluctuation in the comparative example, and b shows an example of conductance fluctuation in the first embodiment. The vertical axes of a and b in the figure indicate the conductance of the memory cell 120, and the horizontal axes indicate the number of write pulses. Furthermore, it is assumed that a ReRAM memory element is used, and the target value of the conductance corresponding to the correct value is set to 0.8, and this target value is set to the maximum value G ｍａｘ The value should be close to .

[0098] As shown in a and b in the figure, in the ReRAM, the conductance changes rapidly at first, but then the change slows down. Therefore, near the target value, the increase in conductance per write pulse is small, and the decrease is large.

[0099] In the comparative example, as shown in a in the figure, when the conductance exceeds the target value, the control circuit 180 reduces the conductance, but too quickly, resulting in a decrease far below the target value. The control circuit 180 then increases the conductance to return it to the target value, but the increase is small, requiring multiple write pulses. This behavior is repeated, so the average conductance value is lower than the target value. For example, the average conductance during the repeated behavior in the comparative example is 0.769. Also, the variance, σ ２ The square root σ of this is 0.031.

[0100] In contrast, the control circuit 180 of the first embodiment starts coarse tuning and increases or decreases the conductance 17 times. After the loss Δ reaches saturation, the control circuit 180 switches to fine tuning and reduces the statistics of the amount of change in conductance. This results in the average conductance being closer to the target value than in the comparative example. Therefore, the learning accuracy can be improved compared to the comparative example.

[0101] For example, if the statistical value of the amount of change in fine tuning is 20% of that in coarse tuning, the average conductance is 0.795. Also, σ is 0.006, and the variation is about 1 / 5 of that in the comparative example.

[0102] 14 is a diagram showing an example of measurement of the average conductance and σ in a comparative example and the first embodiment of the present technology. The vertical axis in the figure represents the average conductance, and the horizontal axis represents σ, which is the square root of the variance of the conductance. Gray circles represent plots of measured values ​​in the first embodiment. White circles represent plots of measured values ​​in the comparative example. The target value of conductance is set to 0.8. As illustrated in the figure, in the first embodiment, the average is closer to the target value than in the comparative example, and σ (in other words, the variance) is also smaller.

[0103] In the first embodiment, the combination of the statistics of the conductance changes of the storage elements 122 and 121 is not limited to 0.8 G and 0.2 G. In the figure, in addition to 0.8 G and 0.2 G, measurements were performed for each combination, with the values ​​set to 0.1 G and 0.9 G, 0.3 G and 0.7 G, and 0.5 G and 0.5 G. The greater the difference in the conductance changes, the closer the average is to the target value and the smaller σ becomes. However, since differences in the conductance changes may increase manufacturing costs, the combination is selected taking into account the required accuracy.

[0104] 15 is a diagram illustrating an example of accuracy for each device in the comparative example and the first embodiment of the present technology. In the drawing, a circle indicates high learning accuracy, and an x ​​indicates low learning accuracy.

[0105] When a device with ideal resistance change characteristics is used, high learning accuracy can be achieved in both the comparative example and the first embodiment.

[0106] However, in the ReRAM, as described above, the absolute value of the change in conductance for each write pulse differs between when the conductance is increased and when the conductance is decreased. However, the absolute values ​​of the increase in the conductance when the conductance is increased and the decrease in the conductance when the conductance is decreased are the maximum value G ｍａｘ and the minimum value G ｍｉｎ The gradient of the arrow in the figure indicates the amount of change in conductance near the middle.

[0107] Furthermore, in PCM, the absolute values ​​of the increase and decrease in conductance are never the same in the regions where the conductance increases and decreases.

[0108] When using ReRAM or PCM, the learning accuracy decreases in the comparative example. In contrast, in the first embodiment, since it is possible to switch from coarse tuning to fine tuning, high learning accuracy can be achieved even when using ReRAM or PCM.

[0109] As described above, according to the first embodiment of the present technology, the control circuit 180 performs coarse tuning and fine tuning in sequence, and therefore, the learning accuracy can be improved compared to the comparative example.

[0110] 2. Second Embodiment In the first embodiment described above, memory cells 120 are provided with memory elements 121 and 122 that are different in area, length, and type. However, this configuration may make manufacturing more difficult and increase manufacturing costs compared to when memory elements 121 and 122 are the same in area, length, and type. Semiconductor device 100 in this second embodiment differs from the first embodiment in that two write pulses that differ in at least one of voltage absolute value and pulse width are supplied to memory elements 121 and 122.

[0111] 16 is a perspective view showing an example of memory elements 121 and 122 according to the second embodiment of the present technology. The memory elements 121 and 122 according to the second embodiment differ from those according to the first embodiment in that they have the same area, length, and type (e.g., ReRAM).

[0112] The control circuit 180 supplies two write pulses, which differ in at least one of the voltage absolute value and the pulse width, to the storage elements 121 and 122. Here, the voltage of the write pulse indicates the difference between the voltage of the pulse signal on the row side and the voltage of the pulse signal on the column side.

[0113] For example, the absolute voltage value of the write pulse to the memory element 122 is set to a value smaller than that of the write pulse to the memory element 121. As a result, the statistics of the amount of change in conductance of the memory element 121 for each write pulse is controlled to a value different from that of the memory element 122.

[0114] FIG. 17 is a circuit diagram showing an example configuration of the vertical drive section 150, the switching circuit 130, and the memory cell 120 according to the second embodiment of the present technology.

[0115] In the second embodiment, the vertical drive section 150 is provided with drivers 151 and 152 for each row, and the switching circuit 130 is provided with nMOS transistors 132, 133, and 134 for each row.

[0116] The nMOS transistor 132 opens and closes a path between the driver 151 and the signal line 112 in accordance with a selection signal SELvx. The nMOS transistor 134 opens and closes a path between the driver 152 and the signal line 111 in accordance with a selection signal SELvy.

[0117] The nMOS transistor 133 opens and closes the path between the signal line 112 and the connection point between the driver 152 and the nMOS transistor 134 in accordance with the selection signal SELvy.

[0118] Driver 151 supplies a pulse signal of a predetermined voltage. Driver 152 has a driving force higher than that of driver 151 and supplies a pulse signal of a higher voltage than driver 151. The pulse signals of drivers 151 and 152 have the same pulse width. Drivers 151 and 152 are examples of the first driver and second driver set forth in the claims.

[0119] When performing coarse tuning, the control circuit 180 sets both of the selection signals SELvx and SELvy to a high level, for example.

[0120] When fine tuning is performed, the control circuit 180 sets, for example, the selection signal SELvx to a high level and the selection signal SELvy to a low level. When inference is performed, the control circuit 180 sets both the selection signals SELvx and SELvy to a high level.

[0121] The amount of change in conductance for each write pulse varies depending on the voltage and pulse width of the write pulse, so that the statistics of the amount of change in conductance in fine tuning are controlled to a smaller value than in coarse tuning.

[0122] In the figure, drivers 151 and 152 supply two pulse signals with the same pulse width but different absolute voltage values ​​of the write pulses, but this configuration is not limiting. Drivers 151 and 152 can also supply two pulse signals with the same absolute voltage value but different pulse widths. Drivers 151 and 152 can also supply two pulse signals with different absolute voltage values ​​and different pulse widths.

[0123] As shown in the figure, the drivers 151 and 152 supply two pulse signals that differ in at least one of the voltage absolute value and the pulse width, so that the memory elements 121 and 122 can be made the same in area, length, and type, as described above, which makes manufacturing easier and reduces manufacturing costs compared to the first embodiment.

[0124] As described above, according to the second embodiment of the present technology, the drivers 151 and 152 supply two pulse signals that are different in at least one of the voltage absolute value and the pulse width, so that the memory elements 121 and 122 can be made the same in area, length, and type, thereby reducing manufacturing costs.

[0125] 3. Third Embodiment In the first embodiment described above, two memory elements are provided for each memory cell 120, but three or more memory elements may be provided for each memory cell 120. The semiconductor device 100 in this third embodiment differs from the first embodiment in that three memory elements are provided for each memory cell 120.

[0126] 18 is a circuit diagram showing a configuration example of a vertical drive unit 150, a selector 131, and a memory cell 120 according to the third embodiment of the present technology. The memory cell 120 according to the third embodiment further includes a memory element 123 in addition to memory elements 121 and 122. In the memory cell array 110, signal lines 111, 112, and 113 are wired in the horizontal direction for each row, and a signal line 114 is wired in the vertical direction for each column. One end of the memory element 121 is connected to the signal line 111, one end of the memory element 122 is connected to the signal line 112, and one end of the memory element 123 is connected to the signal line 113. The other ends of the memory elements 121, 122, and 123 are commonly connected to the signal line 114.

[0127] Furthermore, in the selector 131 of the third embodiment, an nMOS transistor 134 is further arranged in addition to the nMOS transistors 132 and 133. The nMOS transistor 132 opens and closes the path between the driver 151 and the signal line 113 in accordance with the selection signal SELvx. The nMOS transistor 133 opens and closes the path between the driver 151 and the signal line 112 in accordance with the selection signal SELvy. The nMOS transistor 134 opens and closes the path between the driver 151 and the signal line 111 in accordance with the selection signal SELvz.

[0128] For example, the control circuit 180 sets all of the selection signals SELvx, SELvy, and SELvz to a high level in coarse tuning, and sets some of them to a high level and the rest to a low level in fine tuning.

[0129] As shown in the figure, since memory elements 121, 122, and 123 are provided for each memory cell 120, the amount of change in conductance can be controlled in more stages than in the first embodiment.

[0130] 19 is a perspective view showing an example of memory elements 121, 122, and 123 according to the third embodiment of the present technology. As shown in a in the figure, the memory elements 121, 122, and 123 have different areas and are the same type and length.

[0131] Alternatively, as shown in FIG. 1B, the memory elements 121, 122, and 123 have different lengths but the same type and area.

[0132] Alternatively, as illustrated in c in the figure, the types of the memory elements 121, 122, and 123 are different. For example, a memory element in a ReRAM is used as the memory element 121, and a memory element in a PCM is used as the memory element 122. A memory element in a STT (Spin Transfer Torque)-MRAM (Magnetoresistive RAM) is used as the memory element 123.

[0133] Alternatively, as illustrated in d in the figure, the areas, lengths, and types of the memory elements 121, 122, and 123 are the same. In this case, as in the second embodiment, three write pulses that differ in at least one of voltage absolute value and pulse width are supplied to the memory elements 121, 122, and 123. For example, the voltage absolute value of the write pulse to the memory element 122 is set to a medium value that is smaller than the voltage absolute value of the write pulse to the memory element 121. Furthermore, the voltage absolute value of the write pulse to the memory element 123 is set to a value even smaller than the voltage absolute value of the write pulse to the memory element 122.

[0134] Furthermore, the configurations illustrated as a, b, c, and d in the figure can be combined in any manner.

[0135] For example, as illustrated in FIG. 20, both storage elements 121 and 122 may be ReRAM storage elements, storage element 123 may be a PCM storage element, and the areas of storage elements 121 and 122 may be different.

[0136] 21 is an example of an equivalent circuit of a memory cell 120 according to the third embodiment of the present technology. As illustrated in FIG. 21 a, resistance change elements such as those in a ReRAM are used as memory elements 121, 122, and 123.

[0137] As shown in FIG. 1B, variable capacitance elements (such as MOS capacitors) can also be used as the storage elements 121, 122, and 123.

[0138] Furthermore, four or more storage elements may be provided within the memory cell 120 .

[0139] As described above, according to the third embodiment of the present technology, since the memory cells 120 are provided with the storage elements 121, 122, and 123, the amount of change in conductance can be controlled in more stages than in the first embodiment.

[0140] 4. Fourth Embodiment In the first embodiment described above, a plurality of memory elements with different areas, lengths, and types were provided for each memory cell 120, but this configuration may increase manufacturing costs compared to when memory elements with the same area and length are provided. The semiconductor device 100 in this fourth embodiment differs from the first embodiment in that a plurality of memory elements connected in parallel to a signal line 111 and a memory element connected to a signal line 112 are provided within the memory cell 120.

[0141] 22 is a perspective view showing an example of a memory element according to the fourth embodiment of the present technology. In the fourth embodiment, memory cells 120 are provided with memory elements 121-1 to 121-8 and a memory element 122. These nine memory elements have the same area, length, and type (e.g., ReARM).

[0142] 23 is a circuit diagram showing a configuration example of the vertical drive unit 150, the selector 131, and the memory cell 120 according to the fourth embodiment of the present technology. In the memory cell 120, one end of each of the storage elements 121-1 to 121-8 is commonly connected to a signal line 111. One end of the storage element 122 is connected to a signal line 112. The other ends of the storage elements 121-1 to 121-8 and the storage element 122 are commonly connected to a signal line 113.

[0143] For example, the statistical value of the change in the individual conductance of nine storage elements in response to a write pulse is 1.0 G. In this case, the change in the combined conductance of a group of eight storage elements connected in parallel between signal lines 111 and 113 is 8.0 G, which is a different value from that of storage element 122. Therefore, even if the area, length, and type of each storage element are the same, coarse tuning and fine tuning can be achieved. This reduces manufacturing costs.

[0144] Although the number of memory elements connected between signal lines 111 and 113 is eight and the number of memory elements connected between signal lines 112 and 113 is one, the numbers of memory elements may be different and are not limited to the combination of 8 and 1. For example, the number of memory elements connected between signal lines 111 and 113 may be seven, and the number of memory elements connected between signal lines 112 and 113 may be two.

[0145] The memory elements 121-1 to 121-8 are an example of a first memory element set forth in the claims, and the memory element 122 is an example of a second memory element set forth in the claims.

[0146] As described above, according to the fourth embodiment of the present technology, the memory elements 121-1 to 121-8 are connected in parallel between the signal lines 111 and 113, and the memory element 122 is connected to the signal lines 112 and 113. Therefore, even if the memory elements have the same area, length, and type, it is possible to achieve coarse tuning and fine tuning, and it is possible to reduce manufacturing costs.

[0147] 5. Fifth Embodiment In the first embodiment described above, memory elements 121 and 122 are provided for each memory cell 120, but this configuration increases the circuit size compared to when one memory element is provided for each memory cell 120. Semiconductor device 100 in this fifth embodiment differs from the first embodiment in that one memory element is provided for each memory cell 120 and two write pulses that differ in at least one of voltage absolute value and pulse width are supplied.

[0148] 24 is a circuit diagram showing a configuration example of a vertical drive unit 150, a selector 131, and a memory cell 120 according to a fifth embodiment of the present technology. The memory cell 120 according to the fifth embodiment differs from that according to the first embodiment in that only a memory element 121 is arranged therein. The vertical drive unit 150 according to the fifth embodiment also differs from that according to the first embodiment in that a driver 152 is further provided for each row in addition to the driver 151. Furthermore, only a signal line 111 is wired for each row within the memory cell array 110.

[0149] Furthermore, the nMOS transistor 132 opens and closes the path between the driver 152 and the signal line 111 in accordance with the selection signal SELvx, and the nMOS transistor 133 opens and closes the path between the driver 151 and the signal line 111 in accordance with the selection signal SELvy. Furthermore, the driver 152 has a higher driving force than the driver 151, and can supply a pulse signal with a higher voltage than the driver 151.

[0150] The control circuit 180 sets only the selection signal SELvx to a high level in coarse tuning to supply a high-voltage pulse signal, and sets only the selection signal SELvy to a high level in fine tuning to supply a low-voltage pulse signal.

[0151] The control circuit 180 can also switch only the pulse width instead of the absolute voltage value, or can switch both the absolute voltage value and the pulse width.

[0152] By having the control circuit 180 sequentially supply two pulse signals that differ in at least one of voltage absolute value and pulse width, it is possible to achieve coarse tuning and fine tuning even with only one memory element per memory cell 120. This allows the circuit scale to be reduced.

[0153] As described above, according to the fifth embodiment of the present technology, the control circuit 180 sequentially supplies two pulse signals that differ in at least one of voltage absolute value and pulse width, thereby enabling coarse tuning and fine tuning to be achieved even with one memory element per memory cell 120, and reducing the circuit size.

[0154] 6. Application Examples The technology disclosed herein can be applied to a technology called IoT (Internet of things), which is the so-called "Internet of Things." IoT is a system in which an IoT device 9100, which is a "thing," is connected to other IoT devices 9003, the Internet, a cloud 9005, etc., and mutually controls them by exchanging information. IoT can be used in various industries, such as agriculture, housing, automobiles, manufacturing, distribution, and energy.

[0155] FIG. 25 is a diagram showing an example of a schematic configuration of an IoT system 9000 to which the technology of the present disclosure can be applied.

[0156] The IoT device 9001 includes various sensors such as a temperature sensor, a humidity sensor, an illuminance sensor, an acceleration sensor, a distance sensor, an image sensor, a gas sensor, and a motion sensor. The IoT device 9001 may also include terminals such as smartphones, mobile phones, wearable devices, and game consoles. The IoT device 9001 is powered by an AC power source, a DC power source, a battery, a contactless power supply, or so-called energy harvesting. The IoT device 9001 can communicate via wired, wireless, or near-field wireless communication. Suitable communication methods include 3G / LTE (registered trademark), Wi-Fi (registered trademark), IEEE 802.15.4, Bluetooth (registered trademark), Zigbee (registered trademark), and Z-Wave. The IoT device 9001 may communicate by switching between multiple of these communication methods.

[0157] The IoT devices 9001 may form one-to-one, star-shaped, tree-shaped, or mesh-shaped networks. The IoT devices 9001 may be connected to an external cloud 9005 directly or through a gateway 9002. Addresses are assigned to the IoT devices 9001 using IPv4, IPv6, 6LoWPAN, or the like. Data collected from the IoT devices 9001 is transmitted to other IoT devices 9003, servers 9004, clouds 9005, or the like. The timing and frequency of data transmission from the IoT devices 9001 are suitably adjusted, and the data may be compressed before transmission. Such data may be used as is, or may be analyzed by a computer 9008 using various methods such as statistical analysis, machine learning, data mining, cluster analysis, discriminant analysis, combinatorial analysis, and time series analysis. By utilizing such data, various services such as control, warning, monitoring, visualization, automation, and optimization can be provided.

[0158] The technology disclosed herein can also be applied to devices and services related to homes. IoT devices 9001 in homes include washing machines, dryers, microwave ovens, dishwashers, refrigerators, ovens, rice cookers, cooking appliances, gas appliances, fire alarms, thermostats, air conditioners, televisions, recorders, audio equipment, lighting equipment, water heaters, hot water heaters, vacuum cleaners, fans, air purifiers, security cameras, locks, door / shutter operating devices, sprinklers, toilets, thermometers, scales, blood pressure monitors, etc. The IoT devices 9001 may also include solar cells, fuel cells, storage batteries, gas meters, power meters, and distribution boards.

[0159] A low-power communication method is desirable for the IoT device 9001 in the home. The IoT device 9001 may communicate via Wi-Fi indoors and 3G / LTE (registered trademark) outdoors. An external server 9006 for controlling the IoT device may be installed on the cloud 9005 to control the IoT device 9001. The IoT device 9001 transmits data such as the status of the home appliances, temperature, humidity, power usage, and the presence or absence of people and animals inside and outside the home. The data transmitted from the home appliances is stored in the external server 9006 via the cloud 9005. New services are provided based on this data. Such an IoT device 9001 can be controlled by voice using voice recognition technology.

[0160] In addition, by sending information directly from various home appliances to a television, the status of the appliances can be visualized. Furthermore, various sensors can determine whether an occupant is present and send data to air conditioners, lights, etc., so that they can be turned on and off. Furthermore, advertisements can be displayed via the Internet on the displays attached to the various home appliances.

[0161] An example of an IoT system 9000 to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be suitably applied to the computer 9008 and the IoT device 9001 among the configurations described above. Specifically, the semiconductor device 100 in FIG. 1 can be applied to the computer 9008 or the IoT device 9001. By applying the technology according to the present disclosure to the computer 9008 or the IoT device 9001, the accuracy of machine learning on the cloud side and the edge side can be improved.

[0162] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist thereof.

[0163] The processing procedures described in the above embodiments may be considered as a method having a series of these procedures, or as a program for causing a computer to execute the series of procedures, or as a recording medium for storing the program. Examples of such a recording medium include a CD (Compact Disc), an MD (MiniDisc), a DVD (Digital Versatile Disc), a memory card, and a Blu-ray (registered trademark) Disc.

[0164] The effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0165] The present technology may also be configured as follows: (1) A semiconductor device comprising: a predetermined number of memory cells; a driver that supplies a write pulse to each of the memory cells; and a control circuit that sequentially performs coarse tuning to control a statistic of a change in the reciprocal of the impedance of the memory cell for each write pulse to a predetermined value and fine tuning to control the statistic to a value smaller than the predetermined value. (2) The semiconductor device according to (1), wherein each of the memory cells is provided with a first memory element and a second memory element. (3) The semiconductor device according to (2), wherein the first memory element and the second memory element differ in at least one of area and length. (4) The semiconductor device according to (2) or (3), wherein the first memory element and the second memory element are different types. (5) The semiconductor device according to any of (2) to (4), wherein the first memory element and the second memory element are resistance change elements. (6) The semiconductor device according to any of (2) to (4), wherein the first memory element and the second memory element are variable capacitance elements. (7) The semiconductor device according to any one of (2) to (6), wherein the driver includes a first driver that supplies a first write pulse and a second driver that supplies a second write pulse that differs from the first write pulse in at least one of a voltage absolute value and a pulse width. (8) The semiconductor device according to (2), wherein each of the memory cells is further provided with a third memory element. (9) The semiconductor device according to any one of (2) to (8), wherein one end of the first memory element is connected to a first signal line, one end of the second memory element is connected to a second signal line, and the other ends of the first memory element and the second memory element are commonly connected to a third signal line. (10) The semiconductor device according to (9), wherein the first memory element and the second memory element are arranged between a wiring layer in which the first signal line and the second signal line are wired in the same layer and a wiring layer in which the third signal line is wired. (11) The semiconductor device described in (9) above, wherein the first memory element is arranged between a first wiring layer in which the first signal line is wired and a third wiring layer in which the third signal line is wired, and the second memory element is arranged between a second wiring layer in which the second signal line is wired and the third wiring layer.(12) The semiconductor device according to any one of (1) to (11), wherein the control circuit calculates a loss each time the inverse of the impedance is updated, and starts the fine tuning when the loss is saturated. (13) The semiconductor device according to any one of (1) to (12), wherein the control circuit acquires the updated inverse of the impedance each time the inverse of the impedance is updated, and starts the fine tuning when the inverse is saturated. (14) The semiconductor device according to (1), wherein each of the memory cells is provided with a predetermined number of first memory elements and a number of second memory elements not corresponding to the predetermined number, wherein one end of each of the first memory elements is connected to a first signal line, one end of each of the second memory elements is connected to a second signal line, and the other ends of each of the first memory elements and the second memory elements are connected in common to a third signal line. (15) The semiconductor device according to (1), wherein each of the memory cells is provided with one memory element, and the driver sequentially supplies first write pulses and second write pulses that differ in at least one of voltage absolute value and pulse width.

[0166] 100 semiconductor device 110 memory cell array 115, 116, 117 wiring layer 120 memory cell 121, 121-1 to 121-8, 122, 123 storage element 130, 140 switching circuit 131, 141 selector 132, 133, 134 nMOS transistor 150 vertical drive unit 151, 152, 161 driver 160 horizontal drive unit 170 column ADC 171 ADC 180 control circuit 181 weight setting update unit 182 prediction unit 183 loss calculation unit 184 determination unit 190 input / output unit 9001 IoT device 9008 computer

Claims

1. A semiconductor device comprising: a predetermined number of memory cells; a driver that supplies a write pulse to each of the memory cells; and a control circuit that sequentially performs coarse tuning to control a statistic of the reciprocal of the change in impedance of the memory cell for each write pulse to a predetermined value, and fine tuning to control the statistic to a value smaller than the predetermined value.

2. The semiconductor device according to claim 1, wherein each of said memory cells is provided with a first memory element and a second memory element.

3. The semiconductor device according to claim 2, wherein the first memory element and the second memory element differ in at least one of area and length.

4. The semiconductor device according to claim 2, wherein the first memory element and the second memory element are different types.

5. The semiconductor device according to claim 2, wherein the first memory element and the second memory element are resistance change elements.

6. The semiconductor device according to claim 2, wherein the first memory element and the second memory element are variable capacitance elements.

7. The semiconductor device according to claim 2, wherein the drivers include a first driver that supplies a first write pulse, and a second driver that supplies a second write pulse that differs from the first write pulse in at least one of voltage absolute value and pulse width.

8. The semiconductor device according to claim 2, wherein each of said memory cells is further provided with a third memory element.

9. The semiconductor device according to claim 2, wherein one end of the first memory element is connected to a first signal line, one end of the second memory element is connected to a second signal line, and the other ends of the first memory element and the second memory element are commonly connected to a third signal line.

10. The semiconductor device according to claim 9, wherein the first memory element and the second memory element are arranged between a wiring layer in which the first signal line and the second signal line are wired in the same layer and a wiring layer in which the third signal line is wired.

11. A semiconductor device according to claim 9, wherein the first memory element is arranged between a first wiring layer in which the first signal line is wired and a third wiring layer in which the third signal line is wired, and the second memory element is arranged between a second wiring layer in which the second signal line is wired and the third wiring layer.

12. The semiconductor device according to claim 1, wherein the control circuit calculates the loss each time the inverse of the impedance is updated, and starts the fine tuning when the loss is saturated.

13. The semiconductor device according to claim 1, wherein the control circuit acquires the updated reciprocal of the impedance each time the reciprocal is updated, and starts the fine tuning when the reciprocal is saturated.

14. A semiconductor device according to claim 1, wherein each of the memory cells is provided with a predetermined number of first memory elements and a number of second memory elements not corresponding to the predetermined number, one end of each of the first memory elements is connected to a first signal line, one end of each of the second memory elements is connected to a second signal line, and the other ends of each of the first memory elements and the second memory elements are commonly connected to a third signal line.

15. The semiconductor device according to claim 1, wherein each of the memory cells is provided with one storage element, and the driver sequentially supplies a first write pulse and a second write pulse that differ in at least one of voltage absolute value and pulse width.

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