Heterojunction cell preparation method

Abstract

The present invention relates to the technical field of solar cell preparation, and specifically provides a heterojunction cell preparation method and a heterojunction cell. The heterojunction cell preparation method comprises: providing a semiconductor substrate layer, at least one side of the semiconductor substrate layer being provided with a damage layer; performing first texturing treatment on the semiconductor substrate layer to remove some damage from the damage layer, such that the surface of the side of the semiconductor substrate layer having the damage layer forms an inverted pyramid textured surface, the inverted pyramid textured surface comprising a plurality of first microstructural units; and, after the first texturing treatment, performing second texturing treatment on the side of the semiconductor substrate layer where the inverted pyramid textured surface is formed, so as to form a plurality of second pyramids on the surfaces of the first microstructural units of the inverted pyramid textured surface, and remove remaining damage from the damage layer. The heterojunction cell preparation method of the present invention enables prepared cells to have high fill factors at low costs.

Description

Method for preparing heterojunction cell

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410837632.7, filed on June 26, 2024, the contents of which are incorporated herein in their entirety. TECHNICAL FIELD

[0003] The present application relates to the technical field of solar cell preparation, in particular to a method for preparing a heterojunction cell. BACKGROUND

[0004] In the preparation process of a heterojunction cell, texturing is the first step of the production process, which is usually formed by etching the surface of a silicon substrate with an alkaline etching solution. Generally, a positive pyramid textured surface structure is formed, i.e., a textured surface composed of positive pyramid-shaped microstructure units and the structure surface between them. The microstructure units of the positive pyramid textured surface structure are relatively loose, and the incident light can usually be reflected only twice, so the heterojunction cell cannot make better use of the incident light. The microstructure units of the inverted pyramid textured surface structure are relatively continuous and compact, forming inverted pyramid voids. Such a textured surface structure has a better light-trapping structure, and the incident light can be reflected three times or even more, which is more suitable for a heterojunction solar cell.

[0005] Currently, the inverted pyramid textured surface structure texturing method includes: using the holes or lines in the damage layer of the silicon substrate to form an inverted pyramid structure textured surface by hole expansion. Among them, using the damage layer of the silicon substrate to expand the hole can reduce the cost. However, since the hole expansion method is mainly lateral etching with less vertical etching, it is only convenient to expand the hole to form the void between the inverted pyramids, and the lines in the damage layer are enlarged to become larger lines, which are difficult to completely remove and also difficult to form microstructure units that are beneficial to reflection. The defects and impurities caused by the damage layer remaining on the surface of the silicon substrate will affect the fill factor of the heterojunction cell, resulting in unsatisfactory performance. The performance of the existing heterojunction cell still has room for improvement.

[0006] Therefore, there is an urgent need to propose a method for preparing a heterojunction cell to solve the above problems. SUMMARY

[0007] Therefore, the technical problem to be solved by the present application is to solve the problem of unsatisfactory performance of the inverted pyramid textured surface structure of the heterojunction cell caused by the hole expansion texturing process in the prior art.

[0008] The first aspect of the present application provides a preparation method of a heterojunction cell, comprising the steps of: providing a semiconductor substrate layer; at least one side of the semiconductor substrate layer having a damage layer; further comprising the steps of: performing a first texturing treatment on the semiconductor substrate layer to remove part of the damage in the damage layer, so that the surface of the semiconductor substrate layer on the side of the damage layer forms an inverted pyramid texture; the inverted pyramid texture comprises a plurality of first microstructure units, and the gaps between the first microstructure units form inverted pyramid-shaped voids; wherein the first texturing treatment uses a first treatment liquid containing a first nucleating agent and a first masking agent, and the content of the first nucleating agent is less than that of the first masking agent; after the first texturing treatment, a second texturing treatment is performed on the side of the semiconductor substrate layer where the inverted pyramid texture is formed, to form a plurality of second pyramids on the surface of the first microstructure units and remove the remaining damage in the damage layer; wherein the second texturing treatment uses a second treatment liquid containing a second nucleating agent and a second masking agent, and the content of the second nucleating agent is greater than that of the second masking agent.

[0009] Optionally, the damage in the damage layer includes pores and lines;

[0010] During the first texturing treatment, the pores are expanded to form inverted pyramid-shaped voids, and part of the adjacent inverted pyramid-shaped voids forms the first microstructure units;

[0011] During the second texturing treatment, the lines are removed.

[0012] Optionally, the damage in the damage layer includes pores and lines;

[0013] During the first texturing treatment, part of the pores are treated to form inverted pyramid-shaped voids, part of the lines are removed, and part of the adjacent inverted pyramid-shaped voids forms the first microstructure units;

[0014] During the second texturing treatment, another part of the pores are treated, another part of the lines are removed, and part of the adjacent inverted pyramid-shaped voids forms the first microstructure units;

[0015] The first texturing treatment removes less lines than the second texturing treatment, and the first texturing treatment treats more pores than the second texturing treatment.

[0016] Optionally, during the first texturing treatment, a reticular self-masking film is formed on at least one side of the surface of the semiconductor substrate layer.

[0017] Optionally, the first processing solution comprises an alkali solution, the alkali solution comprises KOH solution or NaOH solution, and the solute in the alkali solution accounts for 1.0%-4.0% of the mass percentage of the alkali solution; the temperature of the first texturing treatment is 70-90℃, and the time is 240-600s.

[0018] Optionally, the first nucleation agent comprises isopropyl alcohol, and the first mask agent comprises sodium silicate; the mass fraction of the first nucleation agent in the first processing solution is 0.006%-0.045%; and / or, the mass fraction of the first mask agent in the first processing solution is 0.03%-0.225%.

[0019] Optionally, the second processing solution comprises an alkali solution, the alkali solution comprises KOH solution or NaOH solution, and the solute in the alkali solution accounts for 0.1%-2.0% of the mass percentage of the alkali solution; the temperature of the second texturing treatment is 70-90℃, and the time is 180-400s.

[0020] Optionally, the second nucleation agent comprises isopropyl alcohol, and the second mask agent comprises sodium silicate; the mass fraction of the second nucleation agent in the second processing solution is 0.01%-0.12%; and / or, the mass fraction of the second mask agent in the second processing solution is 0.002%-0.024%.

[0021] Optionally, the method further comprises: after the second texturing treatment, performing a cleaning treatment on the semiconductor substrate layer to remove residual processing solution on the surface of the semiconductor substrate layer; and the cleaning treatment on the semiconductor substrate layer comprises a wet chemical cleaning method.

[0022] Optionally, the size of the first microstructure unit is greater than the size of the second pyramid.

[0023] The second aspect of the present application provides a heterojunction cell prepared by the preparation method of the first aspect of the present application.

[0024] The third aspect of the present application provides a heterojunction cell, comprising:

[0025] a semiconductor substrate layer, at least one side surface of the semiconductor substrate layer having an inverted-pyramid texture, the inverted-pyramid texture comprising a plurality of first microstructure units, and the gaps between the first microstructure units forming inverted-pyramid-shaped voids;

[0026] the surface of the first microstructure unit has a plurality of second pyramids.

[0027] The present application has the following beneficial effects:

[0028] Since the material of the semiconductor substrate layer is usually single crystal silicon, the arrangement spacing of the single crystal silicon crystal in each crystal direction is different, and generally, the single crystal silicon exists (100), (111), and (110) crystal planes. The etching rates of the crystal directions are different, and the etching rates of the crystal directions change obviously under different environments. Specifically, in the process of the first texturing treatment, because the content of the first mask agent is higher than that of the first nucleating agent in the first treatment solution, the first mask agent covers part of the crystal directions and the surface of the semiconductor substrate layer that should participate in etching originally. The texturing solution can penetrate into the damage area of the surface of the semiconductor substrate layer that is not covered, and the inverted pyramid texture is preferentially formed on the surface of the damage layer of the semiconductor substrate layer. The inverted pyramid texture includes a plurality of first microstructure units, and the gaps between the first microstructure units form inverted pyramid-shaped voids. In the process of forming the inverted pyramid texture, the uncovered damage area is removed. After the first texturing treatment, the second texturing treatment is performed on one side of the inverted pyramid texture to form a plurality of second pyramids on the surface of the first microstructure units surrounding the inverted pyramid texture. Specifically, in the process of the second texturing treatment, the content of the second nucleating agent is higher than that of the second mask agent in the second treatment solution, and the second nucleating agent can form independent nucleation points on the surface of the first microstructure units. The nucleation points can improve the reaction rate of the semiconductor substrate layer and the texturing solution, which is conducive to the rapid formation of the second pyramids, i.e., the normal pyramids. In the process of forming the second pyramids, the texturing solution does not cover the crystal directions and the surface, and can effectively remove the remaining damage in the damage layer, i.e., the damage layer of the covered area in the first texturing treatment. Therefore, after the second texturing treatment, all the damage layers are removed. In this way, an additional step of removing the damage layer is not needed, and the process flow is more simple. After the above-mentioned first texturing treatment and second texturing treatment, the damage layer on the surface of the semiconductor substrate layer can be completely removed, and the fill factor of the heterojunction cell is improved. Specifically, compared with the heterojunction cell that only undergoes one texturing treatment, the fill factor is increased by at least 0.18%. The method of the present disclosure does not use metal-assisted etching, the waste liquid has been treated, and pollution is not easy to form. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings needed to be used in the description of the specific embodiments or the prior art. Obviously, the drawings described below are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0030] FIG. 1 is a flowchart of a method for preparing a heterojunction cell according to an embodiment of the present application;

[0031] FIG. 2 is a structural schematic diagram of a semiconductor substrate layer after a first texturing treatment according to an embodiment of the present application;

[0032] Fig. 3 is a schematic diagram of the structure of the semiconductor substrate layer after the second texturing treatment in the embodiment of the present application;

[0033] Fig. 4 is a schematic diagram of the structure of the heterojunction cell in the embodiment of the present application;

[0034] Fig. 5 is a schematic diagram of the structure of the semiconductor substrate layer under scanning electron microscope (SEM) in the embodiment of the present application.

[0035] Legend: 1 - semiconductor substrate layer; 2 - first microstructure unit; 3 - second pyramid; 4 - intrinsic semiconductor layer; 5 - doped semiconductor layer; 6 - transparent conductive film; 7 - gate line electrode. DETAILED DESCRIPTION

[0036] The technical solutions of the present application will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0037] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0038] In conjunction with reference to Figs. 1 to 5, the embodiment of the present application provides a preparation method of a heterojunction cell, comprising the steps of:

[0039] S1: providing a semiconductor substrate layer; at least one side of the semiconductor substrate layer has a damage layer;

[0040] Further comprising the steps of:

[0041] S2: performing a first texturing treatment on the semiconductor substrate layer to remove part of the damage in the damage layer, so that the surface of the semiconductor substrate layer on the side of the damage layer forms an inverted-pyramid textured surface; the inverted-pyramid textured surface comprises a plurality of first microstructure units, and the gaps between the first microstructure units constitute inverted-pyramid-shaped voids; wherein the first texturing treatment uses a first treatment liquid containing a first nucleating agent and a first masking agent, and the content of the first nucleating agent is less than the content of the first masking agent;

[0042] S3: after the first texturing treatment, performing a second texturing treatment on the side of the semiconductor substrate layer where the inverted-pyramid textured surface is formed, to form a plurality of second pyramids on the surface of the first microstructure units and remove the remaining damage in the damage layer;

[0043] The second texturing treatment adopts a second treatment liquid containing a second nucleation agent and a second mask agent, and the content of the second nucleation agent is greater than that of the second mask agent.

[0044] In a standard process for preparing a heterojunction cell, a damage layer is formed on the surface of the semiconductor substrate layer in the process of cutting a silicon raw material to form the semiconductor substrate layer, and a rough polishing process is performed on the surface of the semiconductor substrate layer.

[0045] In the present embodiment, the damage layer formed on at least one side of the semiconductor substrate layer during the cutting of the silicon raw material is utilized, and specifically, the damage layer is used as a starting point to perform the first texturing treatment on at least one side of the semiconductor substrate layer 1, and the rough polishing process is omitted. Since the material of the semiconductor substrate layer 1 is usually monocrystalline silicon, the arrangement spacing of the monocrystalline silicon crystal in each crystal direction is different, and generally, the monocrystalline silicon has (100), (111), and (110) crystal planes, the etching rates of each crystal direction are different, and the etching rates of each crystal direction will change significantly under different environments. Specifically, during the first texturing treatment, because the content of the first masking agent is higher than that of the first nucleating agent in the first treatment solution, the first masking agent will cover part of the crystal direction and surface of the semiconductor substrate layer that should have participated in the etching originally, and the texturing solution can penetrate into the damaged area of the surface of the semiconductor substrate layer that is not covered, and preferentially form inverted pyramid textures on the surface of the damage layer of the semiconductor substrate layer 1 (see FIG. 2 or FIG. 5), and the inverted pyramid textures include a plurality of first microstructure units 2; and during the formation of the inverted pyramid textures, the uncovered damaged area is removed; after the first texturing treatment, a second texturing treatment is performed on one side of the inverted pyramid textures to form a plurality of second pyramids 3 (see FIG. 3 or FIG. 5) on the surface of the first microstructure units 2 surrounding the inverted pyramid textures; specifically, during the second texturing treatment, the content of the second nucleating agent is higher than that of the second masking agent in the second treatment solution, and the second nucleating agent can form independent nucleation points on the surface of the first microstructure units 2, which can improve the reaction rate of the semiconductor substrate layer 1 with the texturing solution and facilitate the rapid formation of the second pyramids 3, i.e., the normal pyramids; during the formation of the second pyramids 3, the texturing solution does not cover the crystal direction and surface of the semiconductor substrate layer, and can effectively remove the remaining damage in the damage layer, i.e., the damage layer in the covered area during the first texturing treatment, and therefore, after the second texturing treatment, all of the damage layer is removed, so that an additional step of removing the damage layer is not required, and the process flow is more simple. After the above-mentioned first texturing treatment and second texturing treatment, the damage layer on the surface of the semiconductor substrate layer 1 can be completely removed, the fill factor of the heterojunction cell is improved, and compared with the heterojunction cell that only undergoes one texturing treatment, the fill factor is at least improved by 0.18%.

[0046] It should be noted that in the present embodiment, the first treatment liquid and the second treatment liquid both include alkaline solution, and the alkaline solution components and additive components in the two treatment liquids are the same, but the percentages are different, which affects the reaction rate with the surface of the semiconductor substrate layer 1. Specifically, in the present embodiment, by controlling the process parameters of the first texturing treatment and the second texturing treatment, adjusting the alkaline solution concentration, additive component content, and texturing time and temperature, the texturing treatment obtains different sizes and different shapes of the first microstructure unit 2 and the second pyramid 3. In one embodiment, the first treatment liquid includes an alkaline solution, and the alkaline solution includes a KOH solution or a NaOH solution, and the mass percentage of the solute in the alkaline solution is 1.0%-4.0%, for example, 1.0%, 2.0%, 2.3%, 2.5%, 3.0%, or 4.0%, or a range formed by any two of them.

[0047] It should be noted that "at least one side of the semiconductor substrate layer has a damage layer" means that one side or both sides of the semiconductor substrate layer has a damage layer, specifically, the light-receiving surface (front surface) and / or the back surface (back surface) of the semiconductor substrate layer has a damage layer. After steps S2 and S3, the light-receiving surface (front surface) and / or the back surface (back surface) of the semiconductor substrate layer has an inverted pyramid texture, which includes a plurality of first microstructure units, and the gaps between the first microstructure units form inverted pyramid-shaped voids; on the surface of the first microstructure unit, a plurality of second pyramids are formed; wherein the "light-receiving surface" is the surface on which sunlight is incident, and the "back surface" is the surface opposite to the light-receiving surface.

[0048] In one embodiment, the temperature of the first texturing treatment is greater than the temperature of the second texturing treatment.

[0049] In one embodiment, the time of the first texturing treatment is greater than the time of the second texturing treatment.

[0050] In one embodiment, the alkaline solution concentration of the first texturing treatment is greater than the alkaline solution concentration of the second texturing treatment.

[0051] In one embodiment, the concentration of the first nucleation agent in the first treatment liquid is less than the concentration of the second nucleation agent in the second treatment liquid.

[0052] In one embodiment, the concentration of the first mask agent in the first treatment liquid is greater than the concentration of the second mask agent in the second treatment liquid.

[0053] Further, the first nucleation agent comprises isopropyl alcohol, and the first mask agent comprises sodium silicate; the mass fraction of the first nucleation agent in the first treatment solution is 0.006%-0.045%, for example, 0.006%, 0.01%, 0.03% or 0.045%, or a range formed by any two of them; and / or, the mass fraction of the first mask agent in the first treatment solution is 0.03%-0.225%, for example, 0.03%, 0.08%, 0.15% or 0.225%, or a range formed by any two of them, and the content of the first nucleation agent in the first treatment solution is less than the content of the first mask agent. Since the surface of the semiconductor substrate layer is relatively flat before the first texturing treatment, in the first texturing treatment, due to the relatively high content of the mask agent compared to the content of the nucleation agent, a network-like self-mask is formed on at least one side surface of the semiconductor substrate layer 1, and the etching rate of the portion of the semiconductor substrate layer covered by the network-like self-mask is less than the etching rate of the portion not covered by the network-like self-mask. Therefore, as the first texturing treatment time increases, the first microstructure unit structure is formed on at least one side surface of the semiconductor substrate layer 1, and the gap between the first microstructure units constitutes a reverse pyramid-shaped void, that is, the semiconductor substrate layer 1 forms a reverse pyramid textured structure.

[0054] Those skilled in the art can understand that the size of the first microstructure unit 2 formed as needed adjusts the operating parameters of the first texturing treatment, such as the type of texturing solution, the texturing time, etc.

[0055] In this embodiment, the temperature of the first texturing treatment is 70°C-90°C, for example, 70°C, 80°C or 90°C, or a range formed by any two of them. In the first texturing treatment, the temperature does not exceed 90°C, which makes it easy to control the etching rate, the structure of the first microstructure unit 2 formed is relatively optimal, and the topography has high integrity; the temperature is not less than 70°C, which makes the etching rate relatively high.

[0056] In this embodiment, the time of the first texturing treatment is 240s-600s, for example, 240s, 260s, 300s, 350s, 400s, 450s, 500s, 550s or 600s, or a range formed by any two of them. The time of the first texturing treatment should not be too long or too short. If the time of the first texturing treatment is too long, it will cause excessive consumption of the thickness of the semiconductor substrate layer; if the time of the first texturing treatment is too short, the light trapping ability of the first microstructure unit 2 will be affected.

[0057] The height of the first microstructure unit 2 after the first texturing treatment is 1-8 μm, for example, 1 μm, 1.3 μm, 1.8 μm, 2.7 μm, 2.9 μm, 3.2 μm, 3.5 μm, 4 μm, 4.2 μm, 4.5 μm, 4.8 μm, 5 μm, 5.3 μm, 5.7 μm, 6 μm, 6.6 μm, 6.8 μm, 7 μm, 7.2 μm, 7.5 μm, 8 μm, or a range defined by any two of them. The height of the first microstructure unit 2 refers to the distance from the top to the bottom surface of the first microstructure unit. The bottom surface of the first microstructure unit refers to the cross section of the inverted pyramid in the direction parallel to the layer surface of the substrate layer, where the tip of the inverted pyramid is located. If there are multiple cross sections, the one closest to the top of the first microstructure unit is used. The height of each first microstructure unit 2 can be the same or different. The width of the first microstructure unit 2 is 1-8 μm, for example, 1 μm, 1.5 μm, 1.8 μm, 2.1 μm, 2.4 μm, 2.7 μm, 3.5 μm, 4 μm, 4.2 μm, 4.5 μm, 4.8 μm, 5 μm, 5.3 μm, 5.7 μm, 6 μm, 6.6 μm, 6.8 μm, 7 μm, 7.2 μm, 7.5 μm, 8 μm, or a range defined by any two of them. The width of the first microstructure unit 2 refers to the largest dimension of the bottom surface of the first microstructure unit. The definition of the bottom surface of the first microstructure unit is the same as above. The width of each first microstructure unit 2 can be the same or different.

[0058] In one embodiment, the second processing liquid comprises an alkali solution, which comprises KOH solution or NaOH solution. The solute in the alkali solution accounts for 0.1-2.0% of the mass percentage of the alkali solution, for example, 0.1%, 0.5%, 0.6%, 0.7%, 1.0%, 1.5%, or 2.0%, or a range defined by any two of them. With the alkali solution in the above concentration range, the etching rate of the semiconductor substrate layer 1 is anisotropic. It can be understood that, due to the different densities of covalent bonds on the crystal faces of the semiconductor substrate layer 1, the crystal faces in the direction of which the covalent bonds are tighter are connected more tightly, and are less likely to react with the alkali solution, so the etching rate in the direction perpendicular to the crystal face is relatively slow. Therefore, the etching rates in different directions are different. According to this principle, the semiconductor substrate layer 1 in a specific crystal direction is placed in the alkali solution in the above concentration for the second texturing treatment, so as to produce the second pyramid 3, and the second pyramid 3 is a positive pyramid texturing structure.

[0059] Further, the second nucleation agent comprises isopropyl alcohol, and the second mask agent comprises sodium silicate; the mass fraction of the second nucleation agent in the second treatment solution is 0.01%-0.12%, for example, can be 0.01%, 0.04%, 0.08% or 0.12%, or a range formed by any two of them; and / or, the mass fraction of the second mask agent in the second treatment solution is 0.002%-0.024%, for example, can be 0.002%, 0.008%, 0.012%, 0.018%, 0.0024% or 0.024%, or a range formed by any two of them, and the content of the second nucleation agent in the first treatment solution is greater than the content of the second mask agent. In the process of the second texturing treatment, the nucleation agent forms independent nucleation points on the surface of the first microstructure unit 2 of the inverted pyramid texture, and the nucleation points can improve the reaction rate of the semiconductor substrate layer 1 with the alkali solution, which is beneficial to the rapid formation of the second pyramid 3.

[0060] The person skilled in the art can understand that the size of the second pyramid 3 formed according to the need adjusts the operation parameters of the second texturing treatment, such as the type of texturing solution, texturing time, etc.

[0061] In the embodiment, the temperature of the second texturing treatment is 70-90°C, for example, 70°C, 75°C, 80°C, 85°C or 90°C, or a range formed by any two of them. In the second texturing treatment, the temperature is not more than 90°C, so that the etching rate is easy to control, the structure of the second pyramid 3 formed is relatively optimal, and the morphology completeness is high; the temperature is not less than 70°C, so that the etching rate is relatively high.

[0062] In the embodiment, the time of the second texturing treatment is 180-400s, for example, 180s, 200s, 250s, 300s, 350s or 400s, or a range formed by any two of them. The time of the second texturing treatment should not be too long or too short, if the time of the second texturing treatment is too long, it will cause the excessive consumption of the thickness of the second pyramid 3; if the time of the second texturing treatment is too short, the light trapping ability of the second pyramid 3 will be affected.

[0063] After the first texturing process, the height of the second pyramids 3 is 0.2-1.5 μm, for example, 0.2 μm, 0.7 μm, 0.8 μm, 1.1 μm, 1.3 μm, 1.5 μm, or a range defined by any two of them. The height of the second pyramids 3 refers to the distance from the top to the bottom of the second pyramids. The width of the second pyramids 3 is 0.2-1.5 μm, for example, 0.2 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.1 μm, 1.5 μm, or a range defined by any two of them. The width of the second pyramids 3 refers to the largest dimension of the bottom of the second pyramids. It can be understood that the masking agent in the texturing process can form a mask on the surface of the semiconductor substrate layer 1 to enhance the etching effect of the area outside the mask to expand the hole to form inverted pyramidal texture; the nucleation agent in the texturing process is to form independent nucleation points to facilitate the formation of the positive pyramids. Therefore, in order to obtain the structure of the present application, i.e., the second pyramids on the surface of the first microstructure units of the inverted pyramidal texture, the content of the masking agent in the first processing solution needs to be controlled to be more, and the content of the nucleation agent in the second processing solution needs to be controlled to be more.

[0064] The inverted pyramidal texture includes a plurality of first microstructure units; a plurality of second pyramids form a positive pyramidal texture on the surface of the first microstructure units of the inverted pyramidal texture. The inverted pyramidal texture refers to a texture with mainly inverted pyramidal voids; the inverted pyramidal void refers to a void with a shape of a tip pointing downward and a flared bottom pointing upward. The positive pyramidal texture refers to a texture continuously formed by positive pyramidal structures; the positive pyramidal structure refers to a three-dimensional structure with a wide bottom and a tip at the top. Forming the positive pyramidal texture on the surface of the first microstructure units of the inverted pyramidal texture can further improve the light trapping ability of the surface of the semiconductor substrate layer 1, so that the heterojunction cell can better utilize the incident light, thereby improving the conversion efficiency of the heterojunction cell. Specifically, compared with the heterojunction cell subjected to only one texturing process, the conversion efficiency is improved by at least 0.42%.

[0065] In one embodiment, the material of the semiconductor substrate layer 1 includes silicon. In other embodiments, the material of the semiconductor substrate layer is other semiconductor materials, such as silicon germanium. The material of the semiconductor substrate layer can also be other semiconductor materials.

[0066] The damages in the damage layer include holes and lines, in the process of the first texturing treatment, the holes are enlarged to form inverted pyramid voids, and the parts between adjacent inverted pyramid voids form the first microstructure units; in the process of the second texturing treatment, the remaining lines are removed. Since the damage layer has holes, in the process of the first texturing treatment, the texturing solution can enter the holes and serve as a starting point to form inverted pyramid textures on the surface of the semiconductor substrate layer by enlarging the holes, which is more operable. By changing and adjusting the texturing parameters, in the process of the second texturing treatment, the lines are removed, and finally all the damages in the damage layer are removed.

[0067] In one embodiment, in the process of the first texturing treatment, a part of the holes are processed to form inverted pyramid voids, the parts between adjacent inverted pyramid voids form the first microstructure units, and a part of the lines are removed; in the process of the second texturing treatment, another part of the holes are processed, the parts between adjacent inverted pyramid voids form the first microstructure units, and another part of the lines are removed; the lines removed by the first texturing treatment are less than the lines removed by the second texturing treatment, and the holes processed by the first texturing treatment are more than the holes processed by the second texturing treatment.

[0068] It needs to be understood that, in the process of the first texturing treatment, since the content of the mask in the texturing solution is relatively large compared with the nucleating agent, the mask covers part of the crystal orientation and surface of the semiconductor substrate layer that should have participated in the etching originally, and most of the texturing solution enters the holes for the enlargement, which makes the damage layer on the covered surface of the semiconductor substrate layer unable to be completely removed, i.e., the removal of the lines in the damage layer is small; in the second texturing treatment, the content of the mask in the texturing solution is small compared with the nucleating agent, which can be ignored, and will not cover the above-mentioned crystal orientation and surface, so that the texturing solution further forms the etching effect on the unremoved damage layer to remove the lines while forming the second pyramid, so that the damages in the damage layer are completely removed after the second texturing treatment.

[0069] In one embodiment, the size of the first microstructure unit 2 is larger than the size of the second pyramid 3, and the second pyramid is embedded into the surface of the first microstructure unit 2 of the inverted pyramid suede, so that the surface of the first microstructure unit forms an irregular jagged structure. Since the inverted pyramid suede is formed by a plurality of first microstructure units, the inverted pyramid suede has better light trapping capability, and the incident light can be reflected three times or even more on its surface, so that the heterojunction cell can utilize more incident light, thereby improving the conversion efficiency of the heterojunction cell and making a stronger contribution to the conversion efficiency of the heterojunction cell. A plurality of second pyramids form a positive pyramid suede, and the incident light can be reflected twice on the surface thereof, so that the heterojunction cell can also utilize part of the incident light, thereby making a certain contribution to the conversion efficiency of the heterojunction cell. Therefore, by embedding the second pyramid 3 into the surface of the first microstructure unit 2 of the inverted pyramid suede, the light trapping performance of the suede of the semiconductor substrate layer 1 is better, and the conversion efficiency of the heterojunction cell is higher. Specifically, compared with the heterojunction cell subjected to only one texturing treatment, the conversion efficiency is increased by at least 0.42%.

[0070] It can be understood that the alkali solution reacts with the surface of the semiconductor substrate layer during the texturing treatment and plays a role of corrosion, and therefore, in order to achieve that the size of the first microstructure unit 2 is larger than the size of the second pyramid 3, the mass percentage of the solute of the alkali solution included in the first treatment solution is obviously larger than the mass percentage of the solute of the alkali solution included in the second treatment solution.

[0071] The preparation method of the heterojunction cell further includes: after the second texturing treatment, performing a cleaning treatment on the semiconductor substrate layer 1. The purpose of the cleaning treatment is to remove the residual texturing treatment solution on the surface of the semiconductor substrate layer 1, so as to obtain a clean semiconductor substrate layer 1.

[0072] In the embodiment, the process of performing the cleaning treatment on the semiconductor substrate layer 1 includes a wet chemical cleaning method. The wet chemical cleaning method is a conventional RCA standard cleaning method in the field, and will not be described in detail in the present application.

[0073] The preparation method of the heterojunction cell further includes: forming an intrinsic semiconductor layer 4 on at least one side surface of the semiconductor substrate layer 1; forming a doped semiconductor layer 5 on the side surface of the intrinsic semiconductor layer 4 away from the semiconductor substrate layer 1; forming a transparent conductive film 6 on the side surface of the doped semiconductor layer 5 away from the semiconductor substrate layer 1; and forming a grid electrode 7 on the side surface of the transparent conductive film 6 away from the semiconductor substrate layer 1.

[0074] The embodiment of the present application provides a kind of heterojunction battery, reference Figure 3, comprising: semiconductor substrate layer 1;The at least one side surface of the semiconductor substrate layer 1 has a plurality of inverted-pyramid-shaped void inverted-pyramid surface;The inverted-pyramid surface includes a plurality of first microstructure units 2;A plurality of second pyramids 3 are located on the surface of the first microstructure unit 2 surrounding the inverted-pyramid-shaped void.

[0075] In the embodiment, the size of the first microstructure unit 2 is greater than the size of the second pyramid 3, and the second pyramid is embedded in the surface of the first microstructure unit 2 of the inverted-pyramid surface, so that the surface of the first microstructure unit forms an irregular jagged structure. Since a plurality of first microstructure units 2 form an inverted-pyramid surface, the inverted-pyramid surface has better light trapping capability, and the incident light can be reflected three times or more on its surface, so that the heterojunction battery can utilize more incident light, thereby improving the conversion efficiency of the heterojunction battery. The second pyramid 3 forms a positive-pyramid surface, and the incident light can be reflected twice on its surface, so that the heterojunction battery can also utilize part of the incident light, thereby contributing to the improvement of the conversion efficiency of the heterojunction battery. Therefore, by embedding the second pyramid 3 in the surface structure of the first microstructure unit 2, the light trapping performance of the surface of the semiconductor substrate layer 1 is better, and the conversion efficiency of the heterojunction battery is higher. Specifically, compared with a heterojunction battery that only undergoes one texturing process, the conversion efficiency is improved by at least 0.42%.

[0076] In one embodiment, the height of the first microstructure unit 2 is 1 μm-8 μm, for example, 1 μm, 1.3 μm, 1.8 μm, 2.7 μm, 2.9 μm, 3.2 μm, 3.5 μm, 4 μm, 4.2 μm, 4.5 μm, 4.8 μm, 5 μm, 5.3 μm, 5.7 μm, 6 μm, 6.6 μm, 6.8 μm, 7 μm, 7.2 μm, 7.5 μm, 8 μm, or a range formed by any two of them, or a range formed by any two of them. The "height of the first microstructure unit 2" refers to the distance from the top of the first microstructure unit to the bottom surface. The "bottom surface of the first microstructure unit" refers to the cross section in the direction parallel to the layer surface of the substrate layer where the tip of the inverted-pyramid adjacent to the first microstructure unit is located. If there are multiple cross sections, the cross section closest to the top of the first microstructure unit is used. The height of each first microstructure unit 2 can be the same or different. If the height of the first microstructure unit 2 is too high, the subsequent process matching will be difficult. If the height of the first microstructure unit 2 is too low, the effect of forming the second pyramid will be weakened.

[0077] The width of the first microstructure unit 2 is 1-8 μm, for example, 1 μm, 1.5 μm, 1.8 μm, 2.1 μm, 2.4 μm, 2.7 μm, 3.5 μm, 4 μm, 4.2 μm, 4.5 μm, 4.8 μm, 5 μm, 5.3 μm, 5.7 μm, 6 μm, 6.6 μm, 6.8 μm, 7 μm, 7.2 μm, 7.5 μm, 8 μm, or a range defined by any two of them. The width of the first microstructure unit 2 refers to the maximum dimension of the bottom surface of the first microstructure unit, which is defined as above, and the width of each first microstructure unit 2 can be the same or different. If the width of the first microstructure unit 2 is too large, it is difficult to form regular first microstructure units. If the width of the first microstructure unit 2 is too small, it is difficult to form second pyramids on the surface of the first microstructure unit surrounding the inverted-pyramid-shaped gap, and the effect of improving the fill factor of the heterojunction cell by texturing is poor.

[0078] In one embodiment, the height of the second pyramid 3 is 0.2-1.5 μm, for example, 0.2 μm, 0.7 μm, 0.8 μm, 1.1 μm, 1.3 μm, 1.5 μm, or a range defined by any two of them. The height of the second pyramid 3 refers to the distance from the top to the bottom of the second pyramid. If the height of the second pyramid 3 is too high, the structure of the first microstructure unit 2 is easily damaged. If the height of the second pyramid 3 is too low, the light-trapping ability of the surface of the semiconductor substrate layer 1 is weakened.

[0079] The width of the second pyramid 3 is 0.2-1.5 μm, for example, 0.2 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.1 μm, 1.5 μm, or a range defined by any two of them. The width of the second pyramid 3 refers to the maximum dimension of the bottom of the second pyramid. If the width of the second pyramid 3 is too large, the number of second pyramids formed is too small, and the light-trapping ability of the surface of the semiconductor substrate layer 1 is weakened. If the width of the second pyramid 3 is too small, the passivation effect on the semiconductor substrate layer 1 is poor.

[0080] In one embodiment, referring to FIG. 4, the heterojunction cell further comprises: an intrinsic semiconductor layer 4 located on at least one side surface of the semiconductor substrate layer 1; a doped semiconductor layer 5 located on the side surface of the intrinsic semiconductor layer 4 away from the semiconductor substrate layer 1; a transparent conductive film 6 located on the side surface of the doped semiconductor layer 5 away from the semiconductor substrate layer 1; and a grid electrode 7 located on the side surface of the transparent conductive film 6 away from the semiconductor substrate layer 1.

[0081] One embodiment of the present application provides a heterojunction cell prepared by the preparation method of the present application, the structure of which is shown in FIGS. 3 and 4.

[0082] In the following examples and comparative examples, the measurement method of each parameter is as follows:

[0083] 1. Test method of microstructure size

[0084] The size of the microstructure is determined by the following method:

[0085] Scanning electron microscope (SEM) observation method: place the sample to be measured on the electron microscope sample stage, image under the condition of acceleration voltage of 5-30 kV, select representative area image, and directly measure the size parameters of the target structure using the instrument matching analysis software (NanoMeasure).

[0086] 2. Size statistical method of microstructure unit and second pyramid

[0087] The size of the microstructure unit and the second pyramid can be determined by the following statistical method:

[0088] The measurement of the height or width of the microstructure unit is as follows: select an observation area of 50x50 μm 2 on the sample surface, randomly position 10 microstructure units, measure the size, and take the arithmetic mean as the final height or width size;

[0089] The measurement of the height or width of the second pyramid is as follows: select an observation area of 10x10 μm 2 on the sample surface, randomly position 10 second pyramid structures, measure the size, and take the arithmetic mean as the final height or width size.

[0090] Note: Randomly selected points should avoid edge defect areas to ensure that the data represents the center characteristics of the structure.

[0091] 3. Test method of solar cell electrical performance

[0092] The test of short-circuit current, short-circuit current density (Jsc), fill factor (FF), and conversion efficiency (η) is carried out according to IEC 60904-1:2020 standard, which specifically includes:

[0093] (1) Standard test conditions (STC): irradiance 1000 W / m 2 , spectrum AM 1.5G, cell temperature 25±1℃;

[0094] (2) Short-circuit current density (Jsc): The short-circuit current is read directly by a four-probe source meter (Keysight B2900A) by illuminating the cell surface with a programmable solar simulator (Newport Oriel Class AAA) and dividing by the active illuminated area of the cell;

[0095] (3) Fill factor (FF) and conversion efficiency (η): By measuring the I-V characteristic curve of the cell, the following formula is used to calculate:

[0096] where P max is the maximum output power, V oc is the open-circuit voltage, and P in is the incident light power.

[0097] Example 1

[0098] Example 1 uses the above preparation method of the heterojunction cell to prepare and obtain a heterojunction cell, specifically:

[0099] The first treatment solution includes a NaOH solution, and the mass percentage of NaOH solute in the NaOH solution is 2.5%; the first treatment solution also includes an isopropyl alcohol solution, and the mass percentage of isopropyl alcohol solute in the isopropyl alcohol solution is 1.0%, the mass fraction of isopropyl alcohol in the first treatment solution is 0.006%, and the first treatment solution also contains sodium silicate, and the mass fraction of sodium silicate in the first treatment solution is 0.03%.

[0100] The temperature of the first texturing treatment is 82°C, and the time is 500s.

[0101] After the first texturing treatment, the etching amount of the semiconductor substrate layer 1 is 0.24g, the height of the first microstructure unit 2 is 3.2μm, and the width of the first microstructure unit 2 is 2.4μm.

[0102] The second treatment solution includes a NaOH solution, and the mass percentage of NaOH solute in the NaOH solution is 0.7%; the second treatment solution also includes an isopropyl alcohol solution, and the mass percentage of isopropyl alcohol solute in the isopropyl alcohol solution is 0.4%, the mass fraction of isopropyl alcohol in the second treatment solution is 0.01%, and the second treatment solution also contains sodium silicate, and the mass fraction of sodium silicate in the second treatment solution is 0.002%.

[0103] The temperature of the second texturing treatment is 75°C, and the time is 240s.

[0104] After the second texturing treatment, the etching amount of the semiconductor substrate layer 1 is 0.08g, the height of the second pyramid 3 is 1.3μm, and the width of the second pyramid 3 is 1μm.

[0105] The one side (front side) of the semiconductor substrate layer 1 has a plurality of inverted-pyramid-shaped voids of inverted-pyramid-shaped roughening; the inverted-pyramid-shaped roughening comprises a plurality of first microstructure units 2; a plurality of second pyramids 3 are located on the surface of the first microstructure units 2 surrounding the inverted-pyramid-shaped voids.

[0106] Embodiment 2

[0107] Embodiment 2 adopts the preparation method of the heterojunction cell described above to prepare a heterojunction cell, specifically:

[0108] The first treatment solution comprises a NaOH solution, and the mass percentage of NaOH solute in the NaOH solution is 2.3%; the first treatment solution further comprises an isopropyl alcohol solution, and the mass percentage of isopropyl alcohol solute in the isopropyl alcohol solution is 0.8%, the mass fraction of isopropyl alcohol in the first treatment solution is 0.045%, and the first treatment solution further contains sodium silicate, and the mass fraction of sodium silicate in the first treatment solution is 0.225%.

[0109] The temperature of the first roughening treatment is 82°C, and the time is 480s.

[0110] After the first roughening treatment, the etching amount of the semiconductor substrate layer 1 is 0.22g, the height of the first microstructure unit 2 is 2.9μm, and the width of the first microstructure unit 2 is 2.1μm.

[0111] The second treatment solution comprises a NaOH solution, and the mass percentage of NaOH solute in the NaOH solution is 0.6%; the second treatment solution further comprises an isopropyl alcohol solution, and the mass percentage of isopropyl alcohol solute in the isopropyl alcohol solution is 0.4%, the mass fraction of isopropyl alcohol in the second treatment solution is 0.12%, and the second treatment solution further contains sodium silicate, and the mass fraction of sodium silicate in the second treatment solution is 0.024%.

[0112] The temperature of the second roughening treatment is 75°C, and the time is 210s.

[0113] After the second roughening treatment, the etching amount of the semiconductor substrate layer 1 is 0.07g, the height of the second pyramid 3 is 1.1μm, and the width of the second pyramid 3 is 0.9μm.

[0114] The two sides of the semiconductor substrate layer 1 both have a plurality of inverted-pyramid-shaped voids of inverted-pyramid-shaped roughening; the inverted-pyramid-shaped roughening comprises a plurality of first microstructure units 2; a plurality of second pyramids 3 are located on the surface of the first microstructure units 2 surrounding the inverted-pyramid-shaped voids.

[0115] Comparative Example 1

[0116] Comparative Example 1 provides a preparation method of a heterojunction cell, comprising:

[0117] providing a semiconductor substrate layer;

[0118] performing a first texturing treatment on one side (front side) of the semiconductor substrate layer, so that the one side surface of the semiconductor substrate layer forms an inverted pyramid texture. The texturing treatment adopts the same process and parameters as the first texturing treatment of Example 1.

[0119] Comparative Example 2

[0120] Comparative Example 2 provides a preparation method of a heterojunction cell, comprising:

[0121] providing a semiconductor substrate layer;

[0122] performing a first texturing treatment on both sides of the semiconductor substrate layer, so that the two side surfaces of the semiconductor substrate layer form an inverted pyramid texture. The texturing treatment adopts the same process and parameters as the first texturing treatment of Example 2.

[0123] The heterojunction cells prepared by the preparation methods of the heterojunction cells provided in Examples 1-2 and Comparative Examples 1-2 are tested for performance, and the following data is obtained:

[0124] Table 1

[0125] The electrical performance of the heterojunction cell includes the conversion efficiency, open circuit voltage, short circuit current, and fill factor of the heterojunction cell. The conversion efficiency of the heterojunction cell obtained by the preparation method of the heterojunction cell provided by the present application is increased to 25.1626%, 25.1728%; the short circuit current is increased to 10.8944A, 10.8888A; the short circuit current density is increased to 39.7185mA / cm 2 , 39.7388mA / cm 2 ; the fill factor is increased to 84.6511%, 84.7090%.

[0126] The present application is different from the prior art which only performs a texturing process on the semiconductor substrate layer 1 once, but utilizes the damage layer formed on at least one side of the semiconductor substrate layer 1 in the process of cutting the silicon raw material to perform a first texturing process on at least one side of the semiconductor substrate layer 1 to form inverted pyramid textures on the surface of the semiconductor substrate layer 1; after the first texturing process, a second texturing process is performed on at least one side of the semiconductor substrate layer 1 to form a plurality of second pyramids 3 on the surface of the first microstructure units 2 of the inverted pyramid textures. After the above-mentioned first and second texturing processes, the damage layer on the surface of the semiconductor substrate layer 1 can be completely removed, and the fill factor of the heterojunction cell is improved, specifically, the fill factor is at least improved by 0.18% compared with the heterojunction cell which only performs a texturing process once. In addition, the plurality of first microstructure units 2 form inverted pyramid textures, and the plurality of second pyramids 3 form positive pyramid textures. Forming a plurality of second pyramids 3 on the surface of the first microstructure units 2 can improve the light trapping capability of the surface of the semiconductor substrate layer 1, so that the heterojunction cell can better utilize incident light, and thus the conversion efficiency of the heterojunction cell is improved. Specifically, the conversion efficiency is at least improved by 0.42% compared with the heterojunction cell which only performs a texturing process once.

[0127] Obviously, the above-mentioned embodiments are only examples for clearly illustrating the present application, and are not intended to limit the embodiments. Based on the above-mentioned description, other different forms of changes or variations can be made by those skilled in the art. All the embodiments do not need to be exhausted, and the obvious changes or variations derived therefrom are still within the protection scope of the present application.

Claims

1. A method for preparing a heterojunction cell, comprising the steps of: providing a semiconductor substrate layer; at least one side of the semiconductor substrate layer having a damage layer; further comprising the steps of: performing a first texturing treatment on the semiconductor substrate layer to remove part of the damage in the damage layer, so that the semiconductor substrate layer has a surface on the side of the damage layer forming an inverted pyramid texture; the inverted pyramid texture comprises a plurality of first microstructure units, and the gaps between the first microstructure units form inverted pyramid-shaped voids; wherein the first texturing treatment uses a first treatment solution containing a first nucleating agent and a first masking agent, and the content of the first nucleating agent is less than the content of the first masking agent; performing a second texturing treatment on the side of the semiconductor substrate layer forming the inverted pyramid texture after the first texturing treatment, to form a plurality of second pyramids on the surface of the first microstructure units and remove the remaining damage in the damage layer; wherein the second texturing treatment uses a second treatment solution containing a second nucleating agent and a second masking agent, and the content of the second nucleating agent is greater than the content of the second masking agent. 2.The method for preparing a heterojunction cell according to claim 1, wherein the damage in the damage layer comprises pores and lines; in the process of the first texturing treatment, the pores are expanded to form inverted pyramid-shaped voids, and part of the adjacent inverted pyramid-shaped voids forms the first microstructure units; in the process of the second texturing treatment, the lines are removed. characterized in that 3.The method for preparing a heterojunction cell according to claim 1, wherein the damage in the damage layer comprises pores and lines; in the process of the first texturing treatment, part of the pores are treated to form inverted pyramid-shaped voids, part of the lines are removed, and the part between adjacent inverted pyramid-shaped voids forms the first microstructure units; in the process of the second texturing treatment, another part of the pores are treated to form inverted pyramid-shaped voids, another part of the lines are removed, and the part between adjacent inverted pyramid-shaped voids forms the first microstructure units; the first texturing treatment removes less lines than the second texturing treatment, and the first texturing treatment treats more pores than the second texturing treatment. 4.The method for preparing a heterojunction cell according to any one of claims 1-3, wherein in the process of the first texturing treatment, a reticular self-masking film is formed on at least one side of the surface of the semiconductor substrate layer. 5.The method for preparing a heterojunction cell according to any one of claims 1-4, wherein the first treatment solution comprises an alkali solution, the alkali solution comprises a KOH solution or a NaOH solution, and the mass percentage of the solute in the alkali solution is 1.0%-4.0%; the temperature of the first texturing treatment is 70℃-90℃, and the time is 240s-600s. 6.The method for preparing a heterojunction cell according to any one of claims 1-5, wherein ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The first nucleation agent comprises isopropyl alcohol, and the first mask agent comprises sodium silicate. The mass fraction of the first nucleation agent in the first treatment solution is 0.006%-0.045%; and / or, The mass fraction of the first mask agent in the first treatment solution is 0.03%-0.225%.

7. The preparation method of the heterojunction cell according to any one of claims 1-6, wherein, The second treatment solution comprises an alkali solution, and the alkali solution comprises a KOH solution or a NaOH solution; the mass percentage of the solute in the alkali solution is 0.1%-2.0%; the temperature of the second texturing treatment is 70-90°C, and the time is 180-400s.

8. The preparation method of the heterojunction cell according to any one of claims 1-7, wherein, The second nucleation agent comprises isopropyl alcohol, and the second mask agent comprises sodium silicate. The mass fraction of the second nucleation agent in the second treatment solution is 0.01%-0.12%; and / or, The mass fraction of the second mask agent in the second treatment solution is 0.002%-0.024%.

9. The method of producing a heterojunction cell according to any one of claims 1 to 8, wherein Further comprising: After the second texturing treatment, the semiconductor substrate layer is subjected to a cleaning treatment to remove the residual treatment solution on the surface of the semiconductor substrate layer; The process of the cleaning treatment of the semiconductor substrate layer comprises a wet chemical cleaning method.

10. The method of producing a heterojunction cell according to any one of claims 1 to 9, wherein The size of the first microstructure unit is greater than the size of the second pyramid.

11. The heterojunction cell prepared by the preparation method according to any one of claims 1-10.

12. A heterojunction cell comprising: A semiconductor substrate layer, wherein at least one side surface of the semiconductor substrate layer has an inverted-pyramid texture, and the inverted-pyramid texture comprises a plurality of first microstructure units, and the gaps between the first microstructure units form inverted-pyramid-shaped voids. The surface of the first microstructure unit has a plurality of second pyramids.

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