Display panel and display device comprising same

Abstract

A display panel, comprising a semiconductor layer. The semiconductor layer comprises a plurality of first semiconductor patterns. The display panel further comprises a source driving circuit, a plurality of sub-pixels, a plurality of data lines, a plurality of demultiplexer circuits, and a plurality of input signal lines. The plurality of sub-pixels are arranged in multiple rows and columns, wherein the sub-pixels in a same column emit light of the same color. One data line is connected to at least one column of sub-pixels. Each demultiplexer circuit comprises a plurality of sub-demultiplexer circuits; each sub-demultiplexer circuit comprises a plurality of transistors; and channels, first electrodes, and second electrodes of the plurality of transistors are all arranged in a same first semiconductor pattern. One sub-demultiplexer circuit is connected to at least two data lines; and in addition, at least two columns of sub-pixels connected to at least two data lines emit light of the same color and are not adjacent to each other, and at least two data lines connected to sub-pixels emitting light of different colors are crossed. The input signal lines are located on the side of the plurality of demultiplexer circuits away from a display area. One input signal line is connected to the source driving circuit and one demultiplexer circuit.

Description

Display panel and display device thereof

[0001] The present application claims priority to the Chinese patent application No. 202410876291.4, filed on July 01, 2024, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of display, and in particular, to a display panel and a display device thereof. BACKGROUND

[0003] With the continuous progress of display technology, virtual reality (VR) and augmented reality (AR) technologies have entered our lives more and more and brought us a whole new experience. Among them, the display principle of VR / AR is based on the fact that the images seen by the left and right eyes are different. After the human eye obtains this information with differences, it produces a stereoscopic effect in the mind. SUMMARY

[0004] In one aspect, a display panel is provided. The display panel has a display area and a peripheral area located at least one side of the display area, and includes a semiconductor layer, the semiconductor layer includes a plurality of first semiconductor patterns, and the plurality of first semiconductor patterns are arranged at intervals in the peripheral area.

[0005] The display panel further includes a source driving circuit, a plurality of sub-pixels, a plurality of data lines, a plurality of multiplexing circuits, and a plurality of input signal lines. The source driving circuit is arranged in the peripheral area. The plurality of sub-pixels are arranged in the display area and arranged in a plurality of rows and a plurality of columns. Each row includes at least two sub-pixels arranged along a first direction, and each column includes at least two sub-pixels arranged along a second direction, the first direction intersects the second direction. Wherein, the sub-pixels in the same column have the same light-emitting color.

[0006] The plurality of data lines are arranged in the display area and extend to the peripheral area. One of the data lines is connected to at least one column of the sub-pixels. The plurality of multiplexing circuits are arranged in the peripheral area. The multiplexing circuits include a plurality of sub-multiplexing circuits, and each of the sub-multiplexing circuits includes a plurality of transistors, the channel, the first electrode and the second electrode of which are arranged in the same first semiconductor pattern. One of the sub-multiplexing circuits is connected to at least two of the data lines, and the at least two columns of the sub-pixels connected by the at least two data lines have the same light-emitting color. The at least two columns of the sub-pixels are not adjacent, and at least two data lines connected to the sub-pixels with different light-emitting colors intersect. The input signal line is arranged in the peripheral area and is located on the side of the plurality of multiplexing circuits away from the display area. One of the input signal lines is connected to the source driving circuit and one of the multiplexing circuits.

[0007] In some embodiments, the plurality of sub-pixels include first, second and third sub-pixels with different light-emitting colors. In the first direction, one row of the sub-pixels is arranged in a sequence of the first, second and third sub-pixels in a cycle. The data lines connected to the first, second and third sub-pixels are first, second and third data lines, respectively.

[0008] The plurality of sub-multiplexing circuits include first, second and third sub-multiplexing circuits, which are connected to the first, second and third data lines, respectively. In the first direction, the plurality of sub-multiplexing circuits are arranged in a sequence of the first, second and third sub-multiplexing circuits.

[0009] In some embodiments, the display panel further includes a plurality of conductive layers arranged on one side of the semiconductor layer. The plurality of data lines include first and second data lines.

[0010] The first data line includes a first, a second and a third wire segment connected in sequence. The first and third wire segments are located in the same conductive layer, and the first wire segment is connected to the sub-multiplexing circuit. The first and second wire segments are located in different conductive layers. The second data line is located in the same conductive layer as the first wire segment. The orthogonal projection of the second wire segment on the semiconductor layer intersects with the orthogonal projection of the second data line on the semiconductor layer.

[0011] In some embodiments, the first type of data line has a length of wire equal to a length of wire of the second type of data line in the peripheral region.

[0012] In some embodiments, the first type of data line includes at least two first sub-segments and at least one second sub-segment, the first sub-segments extending in the second direction. The second sub-segment extends in the first direction. And, the second sub-segment is connected to the first sub-segments alternately.

[0013] The second type of data line includes at least two third sub-segments and at least one fourth sub-segment, the third sub-segments extending in the second direction. The fourth sub-segment extends in the first direction. And, the fourth sub-segment is connected to the third sub-segments alternately. The sum of the lengths of wire of the at least one second sub-segment is equal to the sum of the lengths of wire of the at least one fourth sub-segment.

[0014] In some embodiments, the semiconductor layer further includes a second semiconductor pattern, the second semiconductor pattern surrounding the plurality of first semiconductor patterns, the display panel further includes a first voltage signal line, the first voltage signal line disposed in the peripheral region and connected to the second semiconductor pattern. The first voltage signal line surrounds the plurality of multiplexing circuits, and the second sub-segment and the fourth sub-segment are located on a side of the first voltage signal line close to the display region.

[0015] In some embodiments, the first wire segment, the second wire segment and the third wire segment each include a first sub-segment extending in the second direction, the second type of data line includes a third sub-segment extending in the second direction. The distance between the first sub-segment of the first wire segment and the third sub-segment of the second type of data line is greater than the distance between the first sub-segment of the second wire segment and the third sub-segment of the second type of data line. And / or, the distance between the first sub-segment of the third wire segment and the third sub-segment of the second type of data line is greater than the distance between the first sub-segment of the second wire segment and the third sub-segment of the second type of data line.

[0016] In some embodiments, the sub-multiplexing circuit includes two transistors, the first poles of the two transistors are connected to the input signal line, and the second poles are respectively connected to one of the data lines.

[0017] The third data line close to the second sub-multiplexing circuit crosses the second data line close to the third sub-multiplexing circuit and the first data line close to the third sub-multiplexing circuit respectively; and / or, the first data line close to the second sub-multiplexing circuit crosses the second data line close to the first sub-multiplexing circuit and the third data line close to the second sub-multiplexing circuit respectively.

[0018] In some embodiments, the plurality of first semiconductor patterns are arranged in a plurality of rows and a plurality of columns, each row comprising at least two first semiconductor patterns arranged along the first direction, and each column comprising at least two first semiconductor patterns arranged along the second direction. The first semiconductor pattern comprises two transistor channels, a first electrode and a second electrode, the first electrode and the second electrode being located on opposite sides of the channels along the first direction, and the first electrodes of the two transistors being connected.

[0019] The display panel further comprises gate lines, control signal lines and output signal lines. The gate lines are disposed in the peripheral region and extend along the second direction. Two gate lines overlap with two channels of a column of the first semiconductor patterns, respectively. The control signal lines are disposed in the peripheral region and extend along the first direction. One control signal line is connected with one gate line of the plurality of gate lines corresponding to each multiplexing circuit. The output signal lines are disposed in the peripheral region and extend along the second direction. The data lines are connected with the output signal lines, and two output signal lines are connected with two second electrodes of a column of the first semiconductor patterns, respectively.

[0020] In some embodiments, the semiconductor layer further comprises a second semiconductor pattern surrounding the plurality of first semiconductor patterns, the display panel comprises a plurality of conductive layers, and the display panel further comprises a first voltage signal line disposed in the peripheral region and connected with the second semiconductor pattern. The first voltage signal line surrounds the plurality of multiplexing circuits and is located at a conductive layer of the plurality of conductive layers closest to the semiconductor layer.

[0021] In some embodiments, the input signal lines comprise a plurality of first connection lines and second connection lines, the plurality of first connection lines being disposed in an area surrounded by the first voltage signal line. The first connection lines extend along the second direction and are located at a conductive layer of the plurality of conductive layers closest to the semiconductor layer. One first connection line is connected with a first electrode of a column of the first semiconductor patterns. The second connection lines are connected with the plurality of first connection lines, and the second connection lines are connected with the source driver circuit across the first voltage signal line.

[0022] In some embodiments, the second connection lines comprise a first bus line, a second bus line and a plurality of first branch lines. The first bus line extends along the second direction and is connected with the source driver circuit. The second bus line extends along the first direction and is connected with the first bus line. The second bus line is located at a side of the first voltage signal line away from the display region. The plurality of first branch lines are connected with the second bus line, and one first connection line is connected with one first branch line.

[0023] In some embodiments, the control signal line and the first connection line are located in different conductive layers, and at least one conductive layer is arranged between the control signal line and the first connection line. And / or, the control signal line and the output signal line are located in different conductive layers, and at least one conductive layer is arranged between the control signal line and the output signal line.

[0024] In some embodiments, the gate line is arranged on a side of the semiconductor layer away from the control signal line. The control signal line includes a first main wire segment and a first overlap portion. The first main wire segment extends along the first direction and overlaps the first semiconductor pattern. The first overlap portion is arranged on a side of the first main wire segment and at least partially beyond the first semiconductor pattern. The portion of the first overlap portion beyond the first semiconductor pattern is connected to the gate line.

[0025] In some embodiments, the first main wire segment of each of the plurality of control signal lines overlaps the gate line. In the second direction, the gap on both sides of the first semiconductor pattern of the semiconductor layer is a first gap. The first main wire segments of two control signal lines overlap the same first semiconductor pattern, and the first overlap portion is arranged on a side of the first main wire segment close to the nearest first gap.

[0026] In some embodiments, the display panel further includes a transfer line extending along the second direction. One of the transfer lines is connected to one of the gate lines between a plurality of the first semiconductor patterns in the same column, and the control signal line is connected to the transfer line.

[0027] In some embodiments, the display panel includes a plurality of conductive layers. In a direction away from the semiconductor layer, the plurality of conductive layers includes a first conductive layer, a second conductive layer, and a third conductive layer in sequence. The transfer line is located in the first conductive layer, and the control signal line is located in the third conductive layer. The display panel further includes a transfer pad arranged in the second conductive layer and connected to the transfer line and the control signal line.

[0028] In some embodiments, the display panel further includes a plurality of insulating layers including a first insulating layer and a second insulating layer. The first insulating layer is arranged between the first conductive layer and the second conductive layer. The first insulating layer is provided with a first connection via, and the transfer pad is in electrical contact with the transfer line through the first connection via. The number of first connection vias is greater than or equal to 8. The second insulating layer is arranged between the second conductive layer and the third conductive layer. The second insulating layer is provided with a second connection via, and the control signal line is in electrical contact with the transfer pad through the second connection via. The number of second connection vias is greater than or equal to 8.

[0029] In some embodiments, the adapter wire includes a second main wire segment, a second bridging portion, and a third bridging portion. The second main wire segment extends along the second direction. The second bridging portion is disposed on at least one side of the second main wire segment. The second bridging portion is connected with the gate line. The third bridging portion is disposed on at least one side of the second main wire segment. The third bridging portion is connected with the gate line and the adapter pad.

[0030] In another aspect, a display device is provided. The display device includes a display panel and a circuit board as described in any of the above embodiments, and the circuit board is connected with the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings described in the following description are only some drawings of the embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0032] FIG. 1 is a structural diagram of a display device according to some embodiments;

[0033] FIG. 2 is a structural diagram of another display device according to some embodiments;

[0034] FIG. 3A is a structural diagram of a display panel and a flexible circuit board of a display device according to some embodiments;

[0035] FIG. 3B is a structural diagram of a main body portion of a first bracket of a display device according to some embodiments;

[0036] FIG. 3C is a structural diagram of a second bracket of a display device according to some embodiments;

[0037] FIG. 4 is a structural diagram of a display panel according to some embodiments;

[0038] FIG. 5 is a structural diagram of another display panel according to some embodiments;

[0039] FIG. 6 is a top view of a semiconductor layer and a multilayer metal layer stack of a display panel according to some embodiments;

[0040] FIG. 7 is a sectional view along section line D-D in FIG. 6;

[0041] FIG. 8 is a top view of a semiconductor layer of a display panel according to some embodiments;

[0042] FIG. 9 is a circuit schematic diagram of signal transmission of a demultiplexing circuit of a display panel according to some embodiments;

[0043] FIG. 10 is a top view of a sub-distribution circuit of a display panel according to some embodiments;

[0044] FIG. 11 is a structural diagram of a connection of a demultiplexing circuit and a data line of a display panel according to some embodiments;

[0045] FIG. 12 is a top view of a first metal layer of a display panel according to some embodiments;

[0046] FIG. 13 is a top view of a fourth metal layer of a display panel according to some embodiments;

[0047] FIG. 14 is a top view of a second metal layer of a display panel according to some embodiments;

[0048] FIG. 15 is a top view of a third metal layer of a display panel according to some embodiments;

[0049] FIG. 16 is a structural diagram of a jumper wire of a display panel according to some embodiments;

[0050] FIG. 17 is a timing diagram of a demultiplexing circuit of a display panel according to some embodiments. DETAILED DESCRIPTION

[0051] The technical solutions in some embodiments of the present disclosure will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0052] Unless the context clearly requires otherwise, throughout the description and the claims, the term "comprise," and variations thereof (e.g., "comprises" and "comprising"), will be construed to be inclusive in a manner consistent with the term's plain meaning, namely, "including but not limited to." In describing the description, the terms "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," are not necessarily referring to the same embodiment or example. Furthermore, the above terms are not necessarily mutually exclusive. Throughout the description and claims, the meaning of "a," "an," and "the" includes singular and plural referents unless the context clearly dictates otherwise.

[0053] Hereinafter, the terms "first" and "second" are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0054] In describing some embodiments, "coupled" and "connected," and variations thereof, can be used. The term "connected" should be interpreted broadly, for example, "connected" can be fixedly connected, or detachably connected, or integrated; can be directly connected, or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components have direct physical contact or electrical contact. The term "coupled" or "coupling" can also refer to two or more components that do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0055] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C," and includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0056] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0057] As used herein, the term "if' is, optionally, interpreted as meaning "when" or "while" or "in response to a determination" or "in response to a detection of, as the context suggests. Similarly, the phrase "if determined," or "if [stated condition or event] is detected," is, optionally, interpreted as meaning "upon a determination" or "in response to a determination" or "upon a detection of [stated condition or event]" or "in response to a detection of [stated condition or event]," as the context suggests.

[0058] Use of "adapted to" or "configured to" herein means open and inclusive language that does not exclude devices that are adapted to or configured to perform additional tasks or steps.

[0059] Additionally, use of "based on" means open and inclusive, as a process, step, calculation, or other action "based on" one or more stated conditions or values can be based on additional conditions or values beyond those stated.

[0060] "About," "approximately," or "substantially" as used herein includes the stated value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art to be within the scope of what is claimed while considering the measurement in question and the error associated with that measurement (i.e., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0061] "Parallel," "perpendicular," "equal" as used herein include the stated condition and conditions that approximate the stated condition within an acceptable range of deviation, where the acceptable range of deviation is as determined by one of ordinary skill in the art considering the measurement in question and the error associated with that measurement (i.e., limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where the acceptable range of deviation for near parallel can be, for example, within 5°; "perpendicular" includes absolute perpendicular and near perpendicular, where the acceptable range of deviation for near perpendicular can also be, for example, within 5°. "Equal" includes absolute equality and near equality, where the acceptable range of deviation for near equality can be, for example, a difference between the two that is less than or equal to 5% of either.

[0062] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0063] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of exemplary embodiments.

[0064] In this specification, unless defined otherwise, all terms used herein including technical terms and scientific terms have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure pertains. It will be further understood that the terms, e.g., those defined in a generally used dictionary, should not be interpreted as being ideal or overly formal meanings.

[0065] In the present disclosure, terms such as "lower", "below", "upper" and "above" are used to explain the relative positional association of components shown in the drawings. The terms can be relative concepts and described based on the direction indicated in the drawings, or based on the order of process steps formed, but are not limited thereto.

[0066] The term "opposite" means that a first element can be directly or indirectly opposite to a second element. In the case where a third element is interposed between the first element and the second element, although still opposite to each other, the first element and the second element can be understood as indirectly opposite to each other.

[0067] In the embodiments of the present disclosure, the transistor employed can be a thin film transistor (TFT), a metal oxide semiconductor (MOS), or other switching devices with the same characteristics, and the embodiments of the present disclosure are described by taking the thin film transistor as an example.

[0068] In embodiments of the present disclosure, the control electrode of each thin film transistor is the gate electrode of the transistor, the first electrode is one of the source electrode and the drain electrode of the thin film transistor, and the second electrode is the other of the source electrode and the drain electrode of the thin film transistor. Since the source electrode and the drain electrode of the thin film transistor can be symmetrical in structure, the source electrode and the drain electrode of the thin film transistor can be indistinguishable in structure, that is, the first electrode and the second electrode of the thin film transistor in embodiments of the present disclosure can be indistinguishable in structure. For example, when the transistor is a P-type transistor, the first electrode of the transistor is the source electrode, and the second electrode of the transistor is the drain electrode; for example, when the transistor is an N-type transistor, the first electrode of the transistor is the drain electrode, and the second electrode of the transistor is the source electrode.

[0069] In embodiments of the present disclosure, the capacitor can be a capacitor device separately manufactured by a process, for example, a capacitor device realized by manufacturing a special capacitor electrode, each capacitor electrode of the capacitor can be realized by a metal layer, a semiconductor layer (for example, doped polysilicon), or the like. The capacitor can also be a parasitic capacitor between transistors, or realized by a transistor itself and other devices, lines, or the like, or realized by using a parasitic capacitor between lines of a circuit itself.

[0070] In embodiments of the present disclosure, the nodes such as the first node, the second node, and the third node do not represent actual components, but represent the convergence points of relevant electrical connections in a circuit diagram, that is, these nodes are nodes equivalent to the convergence points of relevant electrical connections in a circuit diagram.

[0071] In addition, in the circuit provided by embodiments of the present disclosure, the transistors are all taken as P-type transistors for example. It should be noted that embodiments of the present disclosure include but are not limited to this. For example, one or more transistors in the circuit provided by embodiments of the present disclosure can also adopt N-type transistors, as long as each electrode of the selected type of transistor is connected according to the corresponding electrode of the corresponding transistor in embodiments of the present disclosure, and the corresponding voltage terminal provides the corresponding high level or low level.

[0072] In embodiments of the present disclosure, the "low level" refers to a voltage capable of turning on the operated P-type transistor included therein, and incapable of turning on the operated N-type transistor included therein (that is, the N-type transistor is turned off). Correspondingly, the "high level" refers to a voltage incapable of turning on the operated P-type transistor included therein (that is, the P-type transistor is turned off), and capable of turning on the operated N-type transistor included therein.

[0073] As shown in FIG. 1, some embodiments of the present disclosure provide a display device 1000, which can be any device that displays images whether in motion (e.g., video) or stationary (e.g., still images) and whether textual or pictorial.

[0074] Exemplarily, referring to FIG. 1 and FIG. 2, the display device 1000 can be a wearable device, a personal digital assistant (PDA), a clock, a global positioning system (GPS) receiver / navigator, a virtual reality (VR) device, an augmented reality (AR) device, a mixed reality (MR) device, an extended reality (XR), a sighting device, a range finder, or the like display product or component with high pixel density.

[0075] FIG. 1 and FIG. 2 show structural schematic diagrams of two wearable devices. For example, as shown in FIG. 1 and FIG. 2, the display device 1000 can be a VR glasses shown in FIG. 1 or FIG. 2.

[0076] It should be noted that according to different application scenarios, the display device 1000 can be a flat display device, a curved display device, and a folding display device, and the shape of the display surface of the display device 1000 can be any one of a circle, an ellipse, a polygon, or an irregular figure.

[0077] Hereinafter, some embodiments of the present disclosure will be illustratively described taking the display device 1000 as the VR glasses shown in FIG. 2 as an example.

[0078] In some embodiments, referring to FIG. 3A, the display device 1000 includes a display panel 100, and the display device 1000 can include one or more display panels 100. Exemplarily, as shown in FIG. 3A, the display device 1000 includes two display panels 100, and the two display panels 100 are arranged in mirror symmetry.

[0079] Exemplarily, the display panel 100 can be a silicon-based Micro OLED display panel. The silicon-based Micro OLED display panel not only has ultra-high pixel density (greater than or equal to 3000 PPI), but also has advantages of high brightness, high color gamut, high color depth, high refresh rate, and the like, and thus is widely applied to various smart products, and especially has a wide and irreplaceable application prospect in the virtual reality field which emphasizes immersive experience.

[0080] Hereinafter, some embodiments of the present disclosure will be illustratively described taking the display panel 100 as a silicon-based Micro OLED display panel as an example.

[0081] In some embodiments, referring to FIG. 3A, the display device 1000 can further include flexible circuit boards 200 and a driving board and other electronic accessories.

[0082] As shown in FIG. 3A, the display panel 100 and the flexible circuit board 200 are connected, and the flexible circuit board 200 is provided with a connection interface 2-1 (also referred to as a connector) for electrical connection with external circuits. The shape and size of the flexible circuit board 200 can be determined according to actual design, for example, the shape of the flexible circuit board 200 can be rectangular or L-shaped, and a rectangular shape is taken as an example for illustration in FIG. 3A.

[0083] As shown in FIGS. 2 and 3A, the driving board can be arranged at the position of the first mark 1-1, the second mark 1-2 or the third mark 1-3 in FIG. 2, and the driving board is electrically connected with the two flexible circuit boards 200 respectively to transmit display signals to the two display panels 100 to control the images displayed by the two display panels 100. For example, the driving board can be arranged at the first mark 1-1 in FIG. 2 to maintain the balance of the device. At this time, the two flexible circuit boards 200 can be electrically connected with the driving board arranged at the position of the first mark 1-1.

[0084] In some embodiments, referring to FIGS. 2, 3B and 3C, the display device 1000 can further include a first support 300 and a second support 400.

[0085] As shown in FIGS. 2, 3B and 3C, the first support 300 is configured to be wearable, and in the case where the wearable device is glasses, the first support 300 includes a main body part 3-1 and a temple 3-2 connected with the main body part 3-1. The main body part 3-1 includes a connecting piece 3-11 and two mounting frames 3-12, and the connecting piece 3-11 connects the two mounting frames 3-12. The mounting frames 3-12 are used to connect the second support 400 to fix the display panel 100 (see FIG. 3A).

[0086] For example, referring to FIGS. 3B and 3C, the mounting frames 3-12 are provided with a first mounting piece 3-13 and a second mounting piece 3-14, the second support 400 is provided with a third mounting piece 4-1 and a fourth mounting piece 4-2, the first mounting piece 3-13 is mounted and fixed with the fourth mounting piece 4-2, and the second mounting piece 3-14 is mounted and fixed with the third mounting piece 4-1.

[0087] In addition, the two flexible circuit boards 200 can be arranged in central symmetry with the geometric center of the main body part 3-1 of the first support 300 as the symmetry point. In addition, the geometric centers of the display areas A of the two display panels 100 can be located on the same straight line as the geometric center of the main body part 3-1 of the second support. In this way, when the user uses the device, the field of view center of the left eye of the user and the field of view center of the right eye of the user are located in the same straight line, which can improve the user experience.

[0088] In some embodiments, referring to FIGS. 2 and 3A, the display device 1000 can further include two wire harnesses 500 connected with the two flexible circuit boards 200 respectively, and the two wire harnesses 500 can be combined into one wire harness through the assembly 600, for example, to be electrically connected with external devices.

[0089] In some embodiments, referring to FIG. 4, the display panel 100 has a display area A and a peripheral area B arranged on at least one side of the display area A. In FIG. 4, the peripheral area B is arranged around the display area A as an example.

[0090] The display area A is an area for displaying images, and the display area A is configured to arrange a plurality of sub-pixels P, which can be understood as the smallest light-emitting unit in the display panel 100. The peripheral area B is an area for not displaying images, and is configured to arrange a driving circuit, for example, a gate driving circuit 101 and a source driving circuit 102.

[0091] For example, as shown in FIG. 4, the display area A is provided with a plurality of sub-pixels P, and the plurality of sub-pixels P are arranged in multiple rows and multiple columns, each row includes at least two sub-pixels P arranged along a first direction X, and each column includes at least two sub-pixels P arranged along a second direction Y.

[0092] It should be noted that the first direction X is the row direction of the arrangement of the plurality of sub-pixels P, and the second direction Y is the column direction of the arrangement of the plurality of sub-pixels P. The first direction X and the second direction Y intersect, for example, the first direction X and the second direction Y are perpendicular.

[0093] For example, as shown in FIG. 4, the plurality of sub-pixels P can include a plurality of sub-pixels P with different light-emitting colors. For example, the plurality of sub-pixels P includes a first sub-pixel P1, a second sub-pixel P2 and a third sub-pixel P3, and the light-emitting colors of the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 are three primary colors, for example, the light-emitting color of the first sub-pixel P1 is red, the light-emitting color of the second sub-pixel P2 is green, and the light-emitting color of the third sub-pixel P3 is blue.

[0094] For example, the light-emitting color of the first sub-pixel P1 is red, the light-emitting color of the second sub-pixel P2 is green, and the light-emitting color of the third sub-pixel P3 is blue.

[0095] On this basis, as shown in FIG. 4, the arrangement mode of the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 is not unique. Exemplarily, along the first direction X, a row of sub-pixels P are arranged in the order of the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 in turn, forming a standard RGB arrangement.

[0096] Exemplarily, the arrangement mode of the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 is taken as the standard RGB arrangement, and some embodiments of the present disclosure are schematically described below.

[0097] In some embodiments, as shown in FIG. 4, the display panel 100 can further include a plurality of scanning signal lines 10 and a plurality of data lines 20. The scanning signal lines 10 are arranged in the display area A and extend to the peripheral area B along the first direction X; the plurality of scanning signal lines 10 are arranged along the second direction Y at intervals. The data lines 20 are arranged in the display area A and extend to the peripheral area B along the second direction Y; the plurality of data lines 20 are arranged along the first direction X at intervals.

[0098] On this basis, the display panel 100 can further include a gate drive circuit 101 and a source drive circuit 102. The gate drive circuit 101 can be connected with a row of sub-pixels P through the scanning signal lines 10, and the source drive circuit 102 can be connected with a column of sub-pixels P through the data lines 20. Along the first direction X, the gate drive circuit 101 can be arranged on one side of the display area A, and drive a plurality of rows of sub-pixels P from one side of the display area A. Alternatively, along the first direction X, the gate drive circuit 101 can be arranged on opposite sides of the display area A, and drive a plurality of rows of sub-pixels P from both sides of the display area A. FIG. 4 is taken as an example for schematically illustrating that the gate drive circuit 101 is arranged on opposite sides of the display area A.

[0099] It should be understood that all the circuits located in the peripheral area B can be integrated on the display panel 100, for example, the gate drive circuit 101 and the source drive circuit 102 are both integrated on the display panel 100, without the need for binding. Alternatively, part of the circuits located in the peripheral area B are integrated on the display panel 100, and the other part of the circuits are arranged on the display panel 100 through a binding process. For example, the gate drive circuit 101 is integrated on the display panel 100, and the source drive circuit 102 is packaged in a chip and bound to the display panel 100.

[0100] Exemplarily, the gate drive circuit 101 is integrated on the display panel 100, and the source drive circuit 102 is packaged in a chip and bound to the display panel 100, and some embodiments of the present disclosure are schematically described below.

[0101] The source driving circuit 102 refers to a chip for transmitting data signals to the plurality of data lines 20. In order to reduce the cost of the source driving circuit 102, a multiplexer (MUX) can be arranged in the peripheral area B to reduce the number of output signals of the source driving circuit 102, thereby reducing the cost of the source driving circuit 102 and the manufacturing cost of the display panel 100.

[0102] As shown in FIGS. 4 and 5, the display panel 100 further includes a plurality of multiplexers 30 and a plurality of input signal lines 40, which are arranged in the peripheral area B.

[0103] In the second direction Y, the multiplexers 30 are arranged on one side of the display area A, and the input signal lines 40 are at least partially arranged on the side of the multiplexers 30 away from the display area A and connected to the multiplexers 30. One input signal line 40 is connected to the source driving circuit 102 and one multiplexer 30, and one multiplexer 30 is connected to the plurality of data lines 20.

[0104] At this time, the multiplexers 30 are configured to transmit the data signals transmitted by the input signal lines 40 to the plurality of data lines 20 connected to the multiplexers 30 in time division manner, so as to reduce the number of circuit traces (input signal lines 40) connected to the source driving circuit 102, thereby reducing the fan-out area of the circuit traces (input signal lines 40), reducing the area occupied by the lower frame of the display panel 100, and reducing the cost of the source driving circuit 102.

[0105] The multiplexers 30 and the source driving circuit 102 can be arranged on opposite sides of the display area A, or the multiplexers 30 and the source driving circuit 102 can be arranged on the same side of the display area A.

[0106] Hereinafter, some embodiments of the present disclosure will be described by way of example with the multiplexers 30 and the source driving circuit 102 arranged on the same side of the display area A, and the multiplexers 30 and the source driving circuit 102 can also be arranged on opposite sides of the display area A as long as the same technical idea is applied.

[0107] In some embodiments, referring to FIGS. 6 and 7, the display panel 100 includes a substrate 110 and a semiconductor layer ACT, which can be embedded in the substrate 110 or arranged on the substrate 110. In FIG. 6, the semiconductor layer ACT is embedded in the substrate 110 by way of example. In combination with FIGS. 5, 7 and 8, the semiconductor layer ACT includes a plurality of first semiconductor patterns 50, which are arranged in the peripheral area B in a spaced manner.

[0108] The material of the substrate 110 and the semiconductor layer ACT1 includes at least one of single crystal silicon, amorphous silicon, polycrystalline silicon, and silicon oxide. For example, the material of the substrate 110 and the semiconductor layer ACT1 includes single crystal silicon, which is conducive to the display panel 100 forming an ultra-high pixel density (greater than or equal to 3000 PPI).

[0109] On this basis, as shown in FIGS. 6, 9, and 10, the multiplexing circuit 30 includes a plurality of sub-distribution circuits 31, the sub-distribution circuit 31 includes a plurality of transistors 310, and the channel 313, the first electrode 311, and the second electrode 312 of the plurality of transistors 310 are all arranged on the same first semiconductor pattern 50.

[0110] The transistor 310 can be a thin film transistor (TFT), a metal oxide semiconductor (MOS), or other switching devices with the same characteristics. In the embodiments of the present disclosure, the thin film transistor is taken as an example for illustration. The transistor 310 can be a top gate structure, a bottom gate structure, or a double gate structure, and in the embodiments of the present disclosure, the transistor 310 with a bottom gate structure is taken as an example for illustration.

[0111] In some related technologies, the plurality of data lines connected to the plurality of transistors of the same sub-distribution circuit have different light-emitting colors of the connected plurality of columns of sub-pixels. When the display device is lit for testing, vertical stripe display defects occur, resulting in poor uniformity of the display image.

[0112] The inventor has found that in the plurality of transistors of the same sub-distribution circuit, one transistor is turned on, and in the process of transmitting the data signal to the connected data line, the other transistors generate a leakage current, causing crosstalk of the data signals transmitted by different transistors, resulting in abnormal data writing of the sub-pixels, and thus vertical stripe display defects occur, resulting in poor uniformity of the display image.

[0113] Based on this, referring to FIGS. 4, 9, and 10, some embodiments of the present disclosure provide that in the display panel 100, the plurality of data lines 20 connected to one sub-distribution circuit 31 have the same light-emitting color of the connected sub-pixels P; that is, the transistors 310 arranged on the same first semiconductor pattern 50 have the same light-emitting color of the plurality of columns of sub-pixels P connected through the data lines 20.

[0114] That is, the same sub-distribution circuit 31 is connected to the plurality of columns of sub-pixels P with the same light-emitting color through the plurality of data lines 20. Compared with the related technologies, the display panel 100 provided by some embodiments of the present disclosure reduces the difference between the data signals transmitted by the plurality of data lines 20 connected to the same sub-distribution circuit 31.

[0115] At this time, in the process of turning on the plurality of transistors 310 of the same sub-distribution circuit 31 respectively to transmit different data signals to the connected data lines 20, the crosstalk between the data signals transmitted by the plurality of data lines 20 can be reduced due to the reduction of the difference of the data signals transmitted by the data lines 20, so as to reduce the deviation of the data signals received by the plurality of columns of sub-pixels P, improve the vertical stripe display defect, improve the uniformity of the display picture, and improve the display effect.

[0116] For the convenience of description, the data lines 20 connected with the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 respectively are referred to as the first data line 21, the second data line 22 and the third data line 23.

[0117] In some embodiments, referring to FIGS. 6, 9 and 11, the plurality of sub-distribution circuits 31 includes a first sub-distribution circuit 301, a second sub-distribution circuit 302 and a third sub-distribution circuit 303, and the first sub-distribution circuit 301, the second sub-distribution circuit 302 and the third sub-distribution circuit 303 are connected with the first data line 21, the second data line 22 and the third data line 23 respectively. And, along the first direction X, the plurality of sub-distribution circuits 31 are arranged in the order of the first sub-distribution circuit 301, the second sub-distribution circuit 302 and the third sub-distribution circuit 303.

[0118] In this way, the arrangement mode of the first sub-distribution circuit 301, the second sub-distribution circuit 302 and the third sub-distribution circuit 303 is consistent with the arrangement mode of the corresponding first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3, which is conducive to the connection of each sub-distribution circuit 31 with the corresponding data line 20, reduces the length of the data line 20, and the circuit arrangement is more regular.

[0119] In addition, the plurality of columns of sub-pixels P with the same light-emitting color connected with the same sub-distribution circuit 31 are not adjacent. At this time, at least two data lines 20 connected with the sub-pixels P with different light-emitting colors intersect.

[0120] On this basis, referring to FIGS. 6, 7 and 11, the plurality of data lines 20 includes a first type of data line 210 and a second type of data line 220, the first type of data line 210 and the second type of data line 220 are connected with the sub-pixels P with different light-emitting colors, and the first type of data line 210 and the second type of data line 220 intersect.

[0121] The first type of data line 210 includes a first wire segment 211, a second wire segment 212 and a third wire segment 213 connected in sequence, the first wire segment 211 is connected with the sub-distribution circuit 31, the second wire segment 212 is projected on the semiconductor layer ACT, and the projection of the second wire segment 212 on the semiconductor layer ACT intersects with the projection of the second type of data line 220 on the semiconductor layer ACT, and the third wire segment 213 is connected with the sub-pixel P.

[0122] Exemplarily, as shown in FIG. 7, FIG. 8, FIG. 9, FIG. 10 and FIG. 11, the sub-distribution circuit 31 includes two transistors 310, the first electrode 311 of which is connected with the input signal line 40, and the second electrode 312 of which is connected with a data line 20 respectively.

[0123] At this time, the two first data lines 21 connected with the first sub-distribution circuit 301, for example, the first data line 21 closer to the second sub-distribution circuit 302 can be the first type data line 210, and the first data line 21 farther away from the second sub-distribution circuit 302 can be the second type data line 220. The two second data lines 22 connected with the second sub-distribution circuit 302, for example, can both be the second type data line 220. The two third data lines 23 connected with the third sub-distribution circuit 303, for example, the third data line 23 closer to the second sub-distribution circuit 302 can be the first type data line 210, and the third data line 23 farther away from the second sub-distribution circuit 302 can be the second type data line 220.

[0124] On this basis, as shown in FIG. 6, FIG. 9 and FIG. 11, the third data line 23 closer to the second sub-distribution circuit 302 crosses the second data line 22 closer to the third sub-distribution circuit 303, and the first data line 21 closer to the third sub-distribution circuit 303 respectively. And / or, the first data line 21 closer to the second sub-distribution circuit 302 crosses the second data line 22 closer to the first sub-distribution circuit 301, and the third data line 23 closer to the second sub-distribution circuit 302 respectively. In this way, among the plurality of data lines 20 connected with the three sub-distribution circuits 31, only the first data line 21 and the third data line 23 need to be cross-connected, the cross-line design is less, the structure is simple, the cross-line process can be reduced, the process flow can be simplified, and the preparation cost can be reduced.

[0125] Hereinafter, some embodiments of the present disclosure will be described illustratively taking the sub-distribution circuit 31 including two transistors 310 as an example.

[0126] In addition, referring to FIG. 6 and FIG. 7, the display panel 100 further includes a plurality of conductive layers M, which are arranged on one side of the semiconductor layer ACT. Moreover, the first trace segment 211, the third trace segment 213 and the second type data line 220 are located in the same conductive layer M, and the first trace segment 211 and the second trace segment 212 are located in different conductive layers M. That is, the second type data line 220 and the second trace segment 212 are located in different conductive layers M, so as to avoid the first type data line 210 and the second type data line 220 from being short-circuited.

[0127] Exemplarily, as shown in FIG. 6, FIG. 11, FIG. 12 and FIG. 13, the multilayer conductive layer M comprises, in sequence, the first conductive layer M1, the second conductive layer M2, the third conductive layer M3 and the fourth conductive layer M4 in the direction away from the semiconductor layer ACT. At this time, the first trace segment 211, the third trace segment 213 and the second type data line 220 can be located in the fourth conductive layer M4, for example, and the second trace segment 212 can be located in the first conductive layer M1, for example.

[0128] In addition, the multilayer conductive layer M can further comprise a fifth conductive layer located on the side of the fourth conductive layer M4 away from the semiconductor layer ACT. At this time, the second trace segment 212 can be located in the fifth conductive layer, for example, so that the distance between the second trace segment 212 and the first trace segment 211 and the third trace segment 213 is closer, facilitating the connection design between the first trace segment 211, the second trace segment 212 and the third trace segment 213.

[0129] In some embodiments, as shown in FIG. 9, in the peripheral area B, the trace length of the first type data line 210 is equal to the trace length of the second type data line 220, so that the impedance of the first type data line 210 and the second type data line 220 in the peripheral area B is substantially equal, reducing the difference in voltage drop of the data signals inputted into the sub-pixels P by the first type data line 210 and the second type data line 220, thereby improving the uniformity of the display picture.

[0130] In addition, in the peripheral area B, the trace width of the first type data line 210 and the trace width of the second type data line 220 are both greater than or equal to 1 μm, so as to reduce the impedance of the first type data line 210 and the second type data line 220 in the peripheral area B, and improve the increase of impedance due to the increase of trace length.

[0131] Exemplarily, as shown in FIG. 9, the first type data line 210 comprises at least two first sub-segments 214 and at least one second sub-segment 215, the first sub-segment 214 extends along the second direction Y, and the second sub-segment 215 extends along the first direction X. Moreover, the second sub-segment 215 and the first sub-segment 214 are alternately connected. The second type data line 220 comprises at least two third sub-segments 221 and at least one fourth sub-segment 222, the third sub-segment 221 extends along the second direction Y, and the fourth sub-segment 222 extends along the first direction X. Moreover, the fourth sub-segment 222 and the third sub-segment 221 are alternately connected. At this time, the sum of the trace lengths of all the second sub-segments 215 is equal to the sum of the trace lengths of all the fourth sub-segments 222, so that the trace lengths of the first type data line 210 and the second type data line 220 in the peripheral area B are equal, and a single data is controlled, which facilitates to reduce the process difficulty and improve the production efficiency.

[0132] In some embodiments, as shown in FIG. 11, the first wire segment 211, the second wire segment 212 and the third wire segment 213 each include a first sub-segment 214 extending along the second direction Y, and the second type of data line 220 includes a third sub-segment 221 extending along the second direction Y.

[0133] In some embodiments, as shown in FIG. 11, the first wire segment 211, the second wire segment 212 and the third wire segment 213 each include a first sub-segment 214 extending along the second direction Y, and the second type of data line 220 includes a third sub-segment 221 extending along the second direction Y.

[0134] In some embodiments, as shown in FIG. 8, the semiconductor layer ACT further includes a second semiconductor pattern 60 surrounding the plurality of first semiconductor patterns 50. In FIG. 8, only the portions of the second semiconductor pattern 60 located on the sides of the first semiconductor patterns 50 close to and away from the display area A are shown.

[0135] On this basis, as shown in FIGS. 6, 8 and 12, the display panel 100 further includes a first voltage signal line 70 disposed in the peripheral area B and connected to the second semiconductor pattern 60 to serve as an isolation function and reduce the risk of leakage current.

[0136] It should be noted that the first voltage signal line 70 is configured to transmit a constant voltage signal, for example, connected to the positive pole of a power supply or directly grounded, for example, the first voltage signal line 70 provides a constant voltage of 8V.

[0137] In addition, as shown in FIGS. 6 and 9, the first voltage signal line 70 surrounds the plurality of demultiplexing circuits 30, and the second sub-segment 215 and the fourth sub-segment 222 are located on the side of the first voltage signal line 70 close to the display area A. The space on the side of the first voltage signal line 70 close to the display area A is large, which is conducive to the wire design of the data line 20 and reduces the process difficulty.

[0138] In addition, the distance between the second sub-section 215, the fourth sub-section 222 and the first voltage signal line 70 can be designed to be relatively long, so as to reduce the coupling capacitance between signals. For example, the distance between the second sub-section 215, the fourth sub-section 222 and the first voltage signal line 70 can be greater than or equal to 1 μm, so as to reduce the coupling capacitance between the second sub-section 215, the fourth sub-section 222 and the first voltage signal line 70. In addition, the distance between the second sub-section 215 and the fourth sub-section 222 can be greater than or equal to 1 μm, so as to reduce the coupling capacitance between the second sub-section 215 and the fourth sub-section 222.

[0139] In some embodiments, referring to FIGS. 6 and 12, the first voltage signal line 70 is located at the conductive layer M closest to the semiconductor layer ACT.

[0140] For example, as shown in FIGS. 6 and 12, along the direction away from the semiconductor layer ACT, the multi-layer conductive layer M includes the first conductive layer M1, the second conductive layer M2, the third conductive layer M3 and the fourth conductive layer M4 in sequence. At this time, the first voltage signal line 70 can be located at the first conductive layer M1, so that the distance between the first voltage signal line 70 and the semiconductor layer ACT is relatively short, which is beneficial to the design of the connection between the first voltage signal line 70 and the second semiconductor pattern 60.

[0141] In some embodiments, referring to FIG. 8, the plurality of first semiconductor patterns 50 are arranged in multiple rows and multiple columns, each row includes at least two first semiconductor patterns 50 arranged along the first direction X, and each column includes at least two first semiconductor patterns 50 arranged along the second direction Y.

[0142] In this case, the first semiconductor pattern 50 includes the channel 313, the first electrode 311 and the second electrode 312 of the two transistors 310, along the first direction X, the first electrode 311 and the second electrode 312 are located at opposite sides of the channel 313, and the first electrodes 311 of the two transistors 310 are connected.

[0143] In the following, some embodiments of the present disclosure will be described illustratively by taking a multiplexing circuit 30 including three rows and three columns of first semiconductor patterns 50 as an example.

[0144] In this case, the three transistors 310 connected to one data line 20 are arranged along the second direction Y, which can reduce the size of the multiplexing circuit 30 along the first direction X, which is beneficial to improve the pixel density, so that the distance between the pixels P can reach 6.42 μm. In addition, the three transistors 310 connected to one data line 20 are arranged in parallel, which is equivalent to increasing the width-length ratio of the transistor 310, improving the saturation current and improving the response speed.

[0145] That is, three transistors 310 connected to one data line 20 are arranged in the second direction Y and are connected in parallel, so that a higher pixel density (for example, 3956 PPI) and a higher response speed can be achieved even if the width-length ratio of each transistor 310 is relatively small. For example, the width-length ratio of three transistors 310 connected to one data line 20 is 5 / 1, 1 / 1 and 1 / 1 respectively, and the three transistors 310 are connected in parallel, which is equivalent to a transistor with a width-length ratio of 15 / 1, so that the saturation current is larger and the response speed is faster.

[0146] In addition, in the same sub-distribution circuit 31, the first electrodes 311 of the two transistors 310 can be connected by a wire to transmit the data signal, so as to simplify the circuit and reduce the cost.

[0147] For example, referring to FIG. 9, the input signal line 40 includes a plurality of first connection lines 41 and second connection lines 42, and the first connection lines 41 are arranged in the area surrounded by the first voltage signal line 70. In addition, the first connection lines 41 extend in the second direction Y, and one first connection line 41 is connected to the first electrodes 311 of the two transistors 310 in one column of the first semiconductor patterns 50 to transmit data signals to the two transistors 310.

[0148] For example, as shown in FIGS. 6, 10 and 12, the first connection lines 41 can be located in the conductive layer M closest to the semiconductor layer ACT. For example, in the direction away from the semiconductor layer ACT, the plurality of conductive layers M include a first conductive layer M1, a second conductive layer M2, a third conductive layer M3 and a fourth conductive layer M4 in sequence. At this time, the first connection lines 41 can be located in the first conductive layer M1, so that the distance between the first connection lines 41 and the first electrodes 311 of the semiconductor layer ACT is relatively short, which is beneficial to the connection design between the first voltage signal line 70 and the first electrodes 311.

[0149] On this basis, the plurality of first connection lines 41 are connected to the second connection lines 42, and the second connection lines 42 are connected to the source electrode drive circuit 102 across the first voltage signal line 70. In addition, the second connection lines 42 and the first connection lines 41 are located in different conductive layers M1, and the second connection lines 42 and the first voltage signal line 70 are located in different conductive layers M1, so as to avoid short circuit between the second connection lines 42 and the first voltage signal line 70.

[0150] For example, as shown in FIGS. 6 and 14, in the direction away from the semiconductor layer ACT, the plurality of conductive layers M include a first conductive layer M1, a second conductive layer M2, a third conductive layer M3 and a fourth conductive layer M4 in sequence. At this time, the second connection lines 42 can be located in the second conductive layer M2, so that the distance between the second connection lines 42 and the first connection lines 41 is relatively short, which is beneficial to the connection design between the second connection lines 42 and the first connection lines 41.

[0151] In some embodiments, as shown in FIG. 6 and FIG. 14, the second connection line 42 includes a first bus line 421, a second bus line 422, and a plurality of first branch lines 423. The first bus line 421 extends along the second direction Y and is connected with the source driving circuit 102. The second bus line 422 extends along the first direction X and is connected with the first bus line 421. The second bus line 422 is located at a side of the first voltage signal line 70 away from the display area A. The plurality of first branch lines 423 are connected with the second bus line 422. One first connection line 41 is connected with one first branch line 423.

[0152] In this case, the second bus line 422 is located at a side of the first voltage signal line 70 away from the display area A. This can reduce the overlapping area between the second bus line 422 and the first voltage signal line 70, reduce the overlapping area between the second connection line 42 and the first semiconductor pattern 50, and increase the distance between the second bus line 422 and the control signal line 80 (see below) and the output signal line 90 (see below), which is conducive to reducing the coupling capacitance between the second connection line 42 and the first voltage signal line 70, the first semiconductor pattern 50, and the control signal line 80 (see below) and the output signal line 90 (see below).

[0153] The distance between the above-mentioned second bus line 422 and the first voltage signal line 70 is greater than or equal to 2 μm, which further reduces the coupling capacitance between the second bus line 422 and the first voltage signal line 70, and the coupling capacitance between the second bus line 422 and the control signal line 80 (see below) and the output signal line 90 (see below).

[0154] The width of the above-mentioned second connection line 42 is greater than or equal to 2 μm, which reduces the impedance of the second connection line 42 and improves the increase in impedance due to the increase in the length of the second connection line 42.

[0155] In some embodiments, referring to FIG. 6 and FIG. 10, the display panel 100 further includes a gate line 71, a plurality of control signal lines 80, and an output signal line 90.

[0156] As shown in FIG. 6, FIG. 8, and FIG. 10, the gate line 71 is disposed in the peripheral area B and extends along the second direction Y. Two gate lines 71 overlap with two channels 313 of one column of first semiconductor patterns 50, respectively, to serve as the gate electrode of the transistor 310 to control the conduction and cutoff of the channel 313.

[0157] As shown in FIG. 6 and FIG. 10, the control signal line 80 is disposed in the peripheral area B and extends along the first direction X. One control signal line 80 is connected with one gate line 71 of the plurality of gate lines 71 corresponding to each multiplexing circuit 30 to transmit a control signal to the gate line 71.

[0158] As shown in FIG. 6 and FIG. 10, the output signal lines 90 are arranged in the peripheral area B and extend along the second direction Y. Among them, the data lines 20 are connected with the output signal lines 90, and two output signal lines 90 are respectively connected with two second electrodes 312 of a column of the first semiconductor patterns 50 to output data signals.

[0159] In this case, the control signal lines 80 can cross the first semiconductor patterns 50 and intersect with all the output signal lines 90, so that the coupling capacitances of the output signal lines 90 and the control signal lines 80 are consistent, the difference of the coupling capacitances of the output signal lines 90 is reduced, the brightness difference of the sub-pixels P in different columns is caused, and the uniformity of the display brightness is improved.

[0160] In some embodiments, referring to FIG. 6, FIG. 10, FIG. 12 and FIG. 15, the control signal lines 80 and the output signal lines 90 are located in different conductive layers M to avoid short circuit. At least one conductive layer M is arranged between the control signal lines 80 and the output signal lines 90 to reduce the coupling capacitance between the control signal lines 80 and the output signal lines 90.

[0161] For example, as shown in FIG. 6, FIG. 12 and FIG. 15, along the direction away from the semiconductor layer ACT, the multi-layer conductive layers M include the first conductive layer M1, the second conductive layer M2, the third conductive layer M3 and the fourth conductive layer M4 in sequence. Among them, the output signal lines 90 are located in the first conductive layer M1, and the control signal lines 80 are located in the third conductive layer M3 or the fourth conductive layer M4, so that the distance between the output signal lines 90 and the control signal lines 80 is far, which is beneficial to reduce the coupling capacitance between the control signal lines 80 and the output signal lines 90, thereby reducing the rising and falling time of the data signal transmission, increasing the effective charging time, and facilitating the improvement of the refresh rate.

[0162] In some embodiments, referring to FIG. 6, FIG. 10, FIG. 12 and FIG. 15, the control signal lines 80 and the first connection lines 41 are located in different conductive layers M, and at least one conductive layer M is arranged between the control signal lines 80 and the first connection lines 41.

[0163] For example, as shown in FIG. 6, FIG. 12 and FIG. 15, along the direction away from the semiconductor layer ACT, the multi-layer conductive layers M include the first conductive layer M1, the second conductive layer M2, the third conductive layer M3 and the fourth conductive layer M4 in sequence. Among them, the first connection lines 41 are located in the first conductive layer M1, and the control signal lines 80 are located in the third conductive layer M3 or the fourth conductive layer M4, so that the distance between the first connection lines 41 and the control signal lines 80 is far, which is beneficial to reduce the coupling capacitance between the control signal lines 80 and the first connection lines 41, thereby reducing the rising and falling time of the data signal transmission, increasing the effective charging time, and facilitating the improvement of the refresh rate.

[0164] In some embodiments, referring to FIGS. 6, 10 and 15, the gate lines 71 are disposed on the side of the semiconductor layer ACT away from the control signal lines 80. The control signal lines 80 include the first main wire segments 81 and the first overlap portions 82, the first main wire segments 81 extend along the first direction X, and the first main wire segments 81 of the plurality of control signal lines 80 all overlap the gate lines 71, so that the first main wire segments 81 and the gate lines 71 are located in different layers, which is conducive to increasing the width of the first main wire segments 81 and improving the signal transmission delay.

[0165] In addition, the first main wire segments 81 also overlap the first semiconductor patterns 50, and the first main wire segments 81 are located in the first semiconductor patterns 50 along the second direction Y. The first overlap portions 82 are disposed on one side of the first main wire segments 81 and at least partially beyond the first semiconductor patterns 50. The portion of the first overlap portions 82 beyond the first semiconductor patterns 50 is connected to the gate lines 71.

[0166] For example, referring to FIGS. 6, 8, 10 and 15, along the second direction Y, the gap between the first semiconductor patterns 50 of the semiconductor layer ACT is the first gap G1, the first main wire segments 81 of the two control signal lines 80 overlap the same first semiconductor pattern 50, and the first overlap portions 82 are located on the side of the first main wire segments 81 close to the nearest first gap G1, so that the first overlap portions 82 can be connected to the corresponding gate lines 71 at the nearest first gap G1, respectively, which can avoid the crossing of the wire of the plurality of control signal lines 80, regularize the circuit wire, and simplify the structure.

[0167] The width of the above-mentioned first main wire segments 81 is greater than or equal to 1 μm, so as to reduce the wire resistance of the control signal lines 80. The pitch of the above-mentioned first main wire segments is greater than or equal to 1 μm, so as to reduce the coupling capacitance between different control signal lines 80.

[0168] On this basis, as shown in FIGS. 6, 10 and 12, the display panel 100 further includes the adapter lines 91, the adapter lines 91 extend along the second direction Y and are connected to the control signal lines 80. One adapter line 91 is connected to one gate line 71 between the plurality of first semiconductor patterns 50 in the same column, so as to transmit the control signal, reduce the difference between the plurality of transistors 310 connected in parallel to the control signal, and reduce the voltage drop of the control signal transmission.

[0169] Along the first direction X, the interval between the above-mentioned transition line 91 and the adjacent first connection line 41 is equal to the interval between the transition line 91 and the adjacent output signal line 90, so that the coupling capacitances between the transition line 91 and the adjacent first connection line 41 and output signal line 90 are substantially equal, which reduces the difference in coupling capacitances between different transition lines 91 and the first connection line 41 and the output signal line 90, resulting in the difference in the sufficient degree of opening of each transistor 310, thereby improving the uniformity of display brightness.

[0170] In some embodiments, referring to FIGS. 6, 12 and 15, along the direction away from the semiconductor layer ACT, the multilayer conductive layer M includes the first conductive layer M1, the second conductive layer M2 and the third conductive layer M3 in sequence. At this time, the transition line 91 can be located in the first conductive layer M1, and the control signal line 80 can be located in the third conductive layer M3, so that the distance between the transition line 91 and the gate line 71 is closer, which is beneficial to the connection design between the transition line 91 and the gate line 71. In addition, the distance between the transition line 91 and the control signal line 80 is closer, which is beneficial to the connection design between the second connection line 42 and the first connection line 41.

[0171] At the same time, the distance between the first connection line 41 and the control signal line 80 is farther, and the distance between the output signal line 90 and the control signal line 80 is farther, which is beneficial to reducing the coupling capacitances between the control signal line 80 and the first connection line 41 and the output signal line 90, and is beneficial to the improvement of the refresh rate.

[0172] On this basis, as shown in FIGS. 6, 10 and 14, the display panel 100 further includes a transition pad 92, the transition pad 92 is arranged in the second conductive layer M2 and connected with the transition line 91 and the control signal line 80, so as to avoid the problem that the process difficulty is increased due to the too deep depth of the connection via, and the control signal line 80 is disconnected in the connection via.

[0173] In some embodiments, referring to FIG. 7, the display panel 100 further includes a multilayer insulating layer ILD, the multilayer insulating layer ILD includes a first insulating layer ILD1 and a second insulating layer ILD2, the first insulating layer ILD1 is arranged between the first conductive layer M1 and the second conductive layer M2, and the second insulating layer ILD2 is arranged between the second conductive layer M2 and the third conductive layer M3.

[0174] It should be noted that the multilayer insulating layer ILD can further include a third insulating layer ILD3 located between the first conductive layer M1 and the substrate 110, etc.

[0175] As shown in FIG. 7 and FIG. 10, the first insulating layer ILD1 is provided with first connection vias 901, and the transfer pads 92 are in electrical contact with the transfer lines 91 through the first connection vias 901. The number of the first connection vias 901 is greater than or equal to 8, so as to improve the connection stability of the transfer pads 92 and the transfer lines 91. In FIG. 10, the number of the first connection vias 901 is taken as an example of 10.

[0176] As shown in FIG. 7 and FIG. 10, the second insulating layer ILD2 is provided with second connection vias 902, and the control signal lines 80 are in electrical contact with the transfer pads 92 through the second connection vias 902. The number of the second connection vias 902 is greater than or equal to 8, so as to improve the connection stability of the control signal lines 80 and the transfer pads 92. In FIG. 10, the number of the second connection vias 902 is taken as an example of 10.

[0177] In some embodiments, referring to FIG. 10 and FIG. 16, the transfer line 91 includes a second main wire segment 911, a second overlap portion 912 and a third overlap portion 913, and the second main wire segment 911 extends along the second direction Y. The second overlap portion 912 is arranged on at least one side of the second main wire segment 911, and the second overlap portion 912 is connected with the gate line 71. The third overlap portion 913 is arranged on at least one side of the second main wire segment 911, and the third overlap portion 913 is connected with the gate line 71 and the transfer pad 92 to receive the control signal. In this way, in the case that the connection stability of the control signal line 80 and the transfer line 91 and the connection stability of the transfer line 91 and the first semiconductor pattern 50 are high, the wire width of the second main wire segment 911 can be set to be relatively narrow, so as to reduce the coupling capacitance,

[0178] FIG. 17 is a timing diagram of the multiplexing circuit according to some embodiments. In the following, the timing of the multiplexing circuit according to some embodiments of the present disclosure is exemplarily described in combination with FIG. 9 and FIG. 17. In FIG. 9, the multiplexing circuit 30 is taken as an example in which the multiplexing circuit 30 is connected with 6 data lines 20. In FIG. 17, DATA represents the data signal output by the source driving circuit 102.

[0179] In order to facilitate the description, the 6 transistors 310 arranged in sequence along the first direction X in one multiplexing circuit 30 are respectively referred to as a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6.

[0180] In addition, the data lines 20 connected with the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are respectively referred to as a first data line 201, a second data line 202, a third data line 203, a fourth data line 204, a fifth data line 205 and a sixth data line 206.

[0181] And, the control signal lines 80 respectively controlling the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are called a first control signal line 810, a second control signal line 820, a third control signal line 830, a fourth control signal line 840, a fifth control signal line 850 and a sixth control signal line 860.

[0182] As shown in FIG. 9 and FIG. 17, in the first stage S1, the first control signal line 810, the second control signal line 820, the third control signal line 830, the fourth control signal line 840, the fifth control signal line 850 and the sixth control signal line 860 all output low level, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned on.

[0183] At this time, one input signal line 40 outputs the reference voltage to the six output signal lines 90, and the six output signal lines 90 respectively transmit the reference voltage to the six data lines 20, so as to write the reference voltage into the pixels P.

[0184] It should be noted that the reference voltage can be located between the voltage of the data signal corresponding to the maximum gray scale written into the pixel P and the voltage of the data signal corresponding to the minimum gray scale written into the pixel P and the minimum value, so that in the subsequent process of writing the data signal of the target gray scale, the pixel P can quickly write the data signal of the target gray scale, thereby reducing the rising and falling time of the data signal of the target gray scale, increasing the effective charging time, and facilitating the improvement of the refresh rate.

[0185] As shown in FIG. 9 and FIG. 17, in the second stage S2, the first control signal line 810 outputs low level, the second control signal line 820, the third control signal line 830, the fourth control signal line 840, the fifth control signal line 850 and the sixth control signal line 860 all output high level, the first transistor T1 is turned on, and the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned off.

[0186] At this time, one input signal line 40 outputs the first data signal to the first data line 201, so as to write the first data signal into the column of pixels P.

[0187] As shown in FIG. 9 and FIG. 17, in the third stage S3, the second control signal line 820 outputs low level, the first control signal line 810, the third control signal line 830, the fourth control signal line 840, the fifth control signal line 850 and the sixth control signal line 860 all output high level, the second transistor T2 is turned on, and the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned off.

[0188] At this time, the input signal line 40 outputs the second data signal to the second data line 202 to write the second data signal into the column of pixels P.

[0189] As shown in FIGS. 9 and 17, in the fourth stage S4, the third control signal line 830 outputs a low level, the first control signal line 810, the second control signal line 820, the fourth control signal line 840, the fifth control signal line 850, and the sixth control signal line 860 each output a high level, the third transistor T3 is turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0190] At this time, the input signal line 40 outputs the third data signal to the third data line 203 to write the third data signal into the column of pixels P.

[0191] As shown in FIGS. 9 and 17, in the fifth stage S5, the fourth control signal line 840 outputs a low level, the first control signal line 810, the second control signal line 820, the third control signal line 830, the fifth control signal line 850, and the sixth control signal line 860 each output a high level, the fourth transistor T4 is turned on, and the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0192] At this time, the input signal line 40 outputs the fourth data signal to the fourth data line 204 to write the fourth data signal into the column of pixels P.

[0193] As shown in FIGS. 9 and 17, in the sixth stage S6, the fifth control signal line 850 outputs a low level, the first control signal line 810, the second control signal line 820, the third control signal line 830, the fourth control signal line 840, and the sixth control signal line 860 each output a high level, the fifth transistor T5 is turned on, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 are turned off.

[0194] At this time, the input signal line 40 outputs the fifth data signal to the fifth data line 205 to write the fifth data signal into the column of pixels P.

[0195] As shown in FIGS. 9 and 17, in the seventh stage S7, the sixth control signal line 860 outputs a low level, the first control signal line 810, the second control signal line 820, the third control signal line 830, the fourth control signal line 840, and the fifth control signal line 850 each output a high level, the sixth transistor T6 is turned on, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned off.

[0196] At this time, an input signal line 40 outputs a sixth data signal to the sixth data line 206 to write the sixth data signal into a column of pixels P.

[0197] Based on the above, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are controlled to be turned on and turned off in sequence through the first control signal line 810, the second control signal line 820, the third control signal line 830, the fourth control signal line 840, the fifth control signal line 850 and the sixth control signal line 860, so that the six columns of pixels respectively receive the corresponding data signals.

[0198] In the description of the present specification, a specific feature, structure, material or characteristic can be combined in any one or more embodiments or examples in a suitable manner.

[0199] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art should be covered in the protection scope of the present disclosure within the technical range disclosed by the present disclosure, and any person skilled in the art should be covered in the protection scope of the present disclosure within the technical range disclosed by the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display panel having a display area and a peripheral area located at least one side of the display area, the display panel comprising a semiconductor layer, the semiconductor layer comprising a plurality of first semiconductor patterns, the plurality of first semiconductor patterns being spaced apart in the peripheral area; the display panel further comprising: a source driving circuit disposed in the peripheral area; a plurality of sub-pixels disposed in the display area and arranged in a plurality of rows and a plurality of columns, each row comprising at least two sub-pixels arranged in a first direction, and each column comprising at least two sub-pixels arranged in a second direction, the first direction intersecting the second direction, wherein the sub-pixels in the same column have the same light-emitting color; a plurality of data lines disposed in the display area and extending to the peripheral area, one data line being connected to at least one column of sub-pixels; a plurality of demultiplexing circuits disposed in the peripheral area, the demultiplexing circuit comprising a plurality of sub-demultiplexing circuits, each sub-demultiplexing circuit comprising a plurality of transistors, the channel, the first electrode and the second electrode of the plurality of transistors being disposed in the same first semiconductor pattern, wherein one sub-demultiplexing circuit is connected to at least two data lines, the at least two data lines being connected to at least two columns of sub-pixels having the same light-emitting color, the at least two columns of sub-pixels being non-adjacent, and at least two data lines connected to sub-pixels having different light-emitting colors intersecting each other; a plurality of input signal lines disposed in the peripheral area and located on a side of the plurality of demultiplexing circuits away from the display area, one input signal line being connected to the source driving circuit and one demultiplexing circuit.

2. The display panel of claim 1, wherein, The plurality of sub-pixels comprises first, second and third sub-pixels having different light-emitting colors, and in the first direction, one row of sub-pixels is arranged in a sequence of the first, second and third sub-pixels in turn, the data lines connected to the first, second and third sub-pixels being first, second and third data lines, respectively. The plurality of sub-demultiplexing circuits comprises first, second and third sub-demultiplexing circuits, the first, second and third sub-demultiplexing circuits being connected to the first, second and third data lines, respectively, and in the first direction, the plurality of sub-demultiplexing circuits are arranged in the sequence of the first, second and third sub-demultiplexing circuits in turn. 3.The display panel of claim 2, further comprising a plurality of conductive layers disposed on one side of the semiconductor layer, the plurality of data lines comprising: first-type data lines comprising a first wire segment, a second wire segment and a third wire segment connected in turn, the first wire segment and the third wire segment being located in the same conductive layer, and the first wire segment being connected to the sub-demultiplexing circuit, the first wire segment and the second wire segment being located in different conductive layers. The second type of data line is in the same conductive layer as the first routing segment, and a projection of the second routing segment on the semiconductor layer intersects a projection of the second type of data line on the semiconductor layer.

4. The display panel of claim 3, wherein, In the peripheral area, the routing length of the first type of data line is equal to the routing length of the second type of data line.

5. The display panel of claim 4, wherein, The first type of data line includes: At least two first sub-segments extending in the second direction; At least one second sub-segment extending in the first direction; and the second sub-segment is alternately connected with the first sub-segment; The second type of data line includes: At least two third sub-segments extending in the second direction; At least one fourth sub-segment extending in the first direction; and the fourth sub-segment is alternately connected with the third sub-segment; the sum of the routing lengths of the at least one second sub-segment is equal to the sum of the routing lengths of the at least one fourth sub-segment.

6. The display panel of claim 5, wherein, The semiconductor layer further includes a second semiconductor pattern surrounding the plurality of first semiconductor patterns, and the display panel further includes: A first voltage signal line is arranged in the peripheral area and connected with the second semiconductor pattern; the first voltage signal line surrounds the plurality of multiplexing circuits, and the second sub-segment and the fourth sub-segment are located on one side of the first voltage signal line close to the display area.

7. The display panel according to any one of claims 3 to 6, wherein The first routing segment, the second routing segment and the third routing segment each include a first sub-segment extending in the second direction, and the second type of data line includes a third sub-segment extending in the second direction; The distance between the first sub-segment of the first routing segment and the third sub-segment of the second type of data line is greater than the distance between the first sub-segment of the second routing segment and the third sub-segment of the second type of data line; and / or, the distance between the first sub-segment of the third routing segment and the third sub-segment of the second type of data line is greater than the distance between the first sub-segment of the second routing segment and the third sub-segment of the second type of data line.

8. The display panel according to any one of claims 3 to 7, wherein The sub-distribution circuit includes two transistors, the first electrode of the two transistors is connected with the input signal line, and the second electrode is respectively connected with one of the data lines; The third data line close to the second sub-distribution circuit crosses the second data line close to the third sub-distribution circuit and the first data line close to the third sub-distribution circuit, respectively; and / or, the first data line close to the second sub-distribution circuit crosses the second data line close to the first sub-distribution circuit and the third data line close to the second sub-distribution circuit, respectively.

9. The display panel according to any one of claims 1 to 8, wherein, The plurality of first semiconductor patterns are arranged in multiple rows and multiple columns, each row includes at least two first semiconductor patterns arranged in the first direction, and each column includes at least two first semiconductor patterns arranged in the second direction; the first semiconductor pattern includes two transistor channels, a first electrode and a second electrode, in the first direction, the first electrode and the second electrode are located on opposite sides of the channel, and the first electrodes of the two transistors are connected; The display panel further includes: Gate lines are disposed in the peripheral area and extend along the second direction; two of the gate lines overlap two channels of a column of the first semiconductor patterns respectively; A plurality of control signal lines are disposed in the peripheral area and extend along the first direction; one of the control signal lines is connected with one of the gate lines corresponding to each of the plurality of demultiplexing circuits; Output signal lines are disposed in the peripheral area and extend along the second direction; the data lines are connected with the output signal lines, and two of the output signal lines are connected with two second poles of a column of the first semiconductor patterns respectively.

10. The display panel of claim 9, wherein, The semiconductor layer further comprises second semiconductor patterns surrounding the plurality of first semiconductor patterns, and the display panel comprises a plurality of conductive layers, and further comprises: first voltage signal lines disposed in the peripheral area and connected with the second semiconductor patterns; the first voltage signal lines surround the plurality of demultiplexing circuits and are located in the conductive layer closest to the semiconductor layer among the plurality of conductive layers.

11. The display panel of claim 10, wherein, The input signal lines comprise: A plurality of first connection lines are disposed in the area surrounded by the first voltage signal lines; the first connection lines extend along the second direction and are located in the conductive layer closest to the semiconductor layer among the plurality of conductive layers; one of the first connection lines is connected with a first pole of a column of the first semiconductor patterns; Second connection lines are connected with the plurality of first connection lines, and the second connection lines are connected with the source driving circuit across the first voltage signal lines.

12. The display panel of claim 11, wherein, The second connection lines comprise: First buses extending along the second direction and connected with the source driving circuit; Second buses extending along the first direction and connected with the first buses; the second buses are located on the side of the first voltage signal lines away from the display area; A plurality of first branch lines are connected with the second buses; and one of the first connection lines is connected with one of the first branch lines.

13. The display panel of claim 11 or 12, wherein, The control signal lines and the first connection lines are located in different conductive layers, and at least one conductive layer is arranged between the control signal lines and the first connection lines; and / or, The control signal lines and the output signal lines are located in different conductive layers, and at least one conductive layer is arranged between the control signal lines and the output signal lines.

14. The display panel according to any one of claims 9 to 13, wherein The gate lines are disposed on the side of the semiconductor layer away from the control signal lines; the control signal lines comprise: First main wire segments extending along the first direction and overlapping the first semiconductor patterns; First lap joints disposed on the side of the first main wire segments and at least partially beyond the first semiconductor patterns; the part of the first lap joints beyond the first semiconductor patterns is connected with the gate lines.

15. The display panel of claim 14, wherein, First main wire segments of the plurality of control signal lines all overlap the gate lines; Along the second direction, the gap on both sides of the first semiconductor patterns of the semiconductor layer is a first gap; the first main wire segments of two of the control signal lines overlap the same first semiconductor pattern, and the first lap joint is located on the side of the first main wire segment closest to the nearest first gap.

16. The display panel of claim 14 or 15, further comprising: a plurality of adapter lines extending in the second direction; and one of the adapter lines is connected to one of the gate lines between a plurality of the first semiconductor patterns in the same column; the control signal line is connected to the adapter line.

17. The display panel of claim 16, comprising a plurality of conductive layers in a direction away from the semiconductor layer, the plurality of conductive layers comprising a first conductive layer, a second conductive layer, and a third conductive layer in sequence; the adapter line is located in the first conductive layer, and the control signal line is located in the third conductive layer. The display panel further comprises an adapter pad, the adapter pad is arranged in the second conductive layer, and is connected to the adapter line and the control signal line.

18. The display panel of claim 17, further comprising a plurality of insulating layers, the plurality of insulating layers comprising: a first insulating layer arranged between the first conductive layer and the second conductive layer; the first insulating layer is provided with a first connection via, the adapter pad is in electrical contact with the adapter line through the first connection via; the number of the first connection via is greater than or equal to 8; a second insulating layer arranged between the second conductive layer and the third conductive layer; the second insulating layer is provided with a second connection via, the control signal line is in electrical contact with the adapter pad through the second connection via; the number of the second connection via is greater than or equal to 8.

19. The display panel of claim 18, wherein, The adapter line comprises: a second main wire segment extending in the second direction; a second lap portion arranged on at least one side of the second main wire segment; the second lap portion is connected to the gate line; a third lap portion arranged on at least one side of the second main wire segment; the third lap portion is connected to the gate line and the adapter pad.

20. A display device, comprising: the display panel of any one of claims 1-19; a circuit board connected to the display panel.

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