Static random access memory and electronic device

Abstract

A static random access memory (SRAM) (300) and an electronic device, which solve the problem of how to balance the power consumption and area of a SRAM. The SRAM (300) comprises a global bit line, a local bit line, a gating unit (500), and a first memory region (310) and a second memory region (320) which are arranged in a first direction, wherein the gating unit (500) is arranged between the first memory region (310) and the second memory region (320); the first memory region (310) comprises a plurality of first memory cells (400a) and a first dummy cell (311) which is arranged adjacent to the gating unit (500), the second memory region (320) comprises a plurality of second memory cells (400b) and a second dummy cell (312) which is arranged adjacent to the gating unit (500), and the local bit line is connected to the plurality of first memory cells (400a) or the plurality of second memory cells (400b); and the gating unit (500) is connected to the global bit line and the local bit line. The SRAM (300) can be used as a cache in a circuit system.

Description

Static random access memory device and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202411292944.0, filed on September 13, 2024, and entitled "Static random access memory device and electronic device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of semiconductor technology, and in particular to a static random access memory device and an electronic device. BACKGROUND

[0003] With the rapid development of information technology, people's requirements for low power consumption of chips are also getting higher and higher. Low power consumption chips not only meet the requirements of green development, but also for portable products, low power consumption chips can prolong their endurance. And static random access memory (SRAM) as an important part of most chips, its power consumption directly determines the overall power consumption of the chip.

[0004] Especially in today's rapid development of artificial intelligence technology, in the scene of applying artificial intelligence, a large amount of weight data stored in SRAM needs to be frequently read out for calculation, so reducing the read power consumption of SRAM becomes particularly important.

[0005] At the same time, the area of the chip is also an important indicator affecting the competitiveness of the product. And SRAM occupies a large proportion of the area in the whole chip. Therefore, in order to reduce the area of SRAM, the fixed structural characteristics of the storage unit in SRAM can be used, the circuit and layout of the storage unit are designed skillfully, and unique design rules different from conventional logic circuits are used to realize close arrangement, so as to reduce the area of SRAM.

[0006] However, in some designs, there is a conflict between reducing the power consumption of SRAM and reducing the area of SRAM, therefore, how to balance the power consumption and area of SRAM is a technical problem to be solved. SUMMARY

[0007] The present application provides a static random access memory device and an electronic device to solve the problem of how to balance the power consumption and area of SRAM.

[0008] To achieve the above purpose, the technical scheme adopted by the embodiments of the present application is as follows:

[0009] In a first aspect, the embodiments of the present application provide a static random access memory device, which comprises a first storage area, a second storage area, a gating unit, a local bit line and a global bit line. The first storage area comprises a plurality of first storage units and a first dummy unit arranged along a first direction, and the second storage area comprises a plurality of second storage units and a second dummy unit arranged along the first direction, the first direction being the arrangement direction of the first storage area and the second storage area; the gating unit is arranged between the first dummy unit and the second dummy unit; the local bit line is connected with the plurality of first storage units or the plurality of second storage units; the global bit line is connected with the local bit line through the gating unit; wherein the first dummy unit and the first storage unit each comprise a plurality of transistors, and the number of the transistors included is equal, and the arrangement of the plurality of transistors of each of the plurality of first storage units and the first dummy unit changes periodically according to the arrangement order of the plurality of first storage units and the first dummy unit; the second dummy unit and the second storage unit each comprise a plurality of transistors, and the number of the transistors included is equal, and the arrangement of the plurality of transistors of each of the second dummy unit and the plurality of second storage units changes periodically according to the arrangement order of the second dummy unit and the plurality of second storage units.

[0010] Since the gating transistor of the gating unit can selectively turn on the connection between the global bit line and the local bit line, when reading and writing the first storage unit of the first storage area or the second storage unit of the second storage area, only the local bit line corresponding to one of the plurality of storage areas is turned on, the number of storage units connected by the local bit line is reduced, the load of the bit line is reduced, and thus the power consumption of the static random access memory device can be reduced.

[0011] In addition, since the arrangement of the plurality of transistors in each of the plurality of first storage units and the first dummy unit varies periodically according to the arrangement order of the plurality of first storage units and the first dummy unit, the first dummy unit can adopt the same design rule as the first storage unit, i.e., the same design rule as the first storage unit, and similarly, the second dummy unit can also adopt the same design rule as the second storage unit. Since the selection unit is arranged adjacent to the first dummy unit and the second dummy unit, and the first dummy unit and the second dummy unit do not implement the storage function, the connection relationship between the plurality of transistors in the first dummy unit and the plurality of transistors in the second dummy unit is not limited. Thus, the first dummy unit and the second dummy unit adopting the compact arrangement design rule can be used to make the selection unit meet the compact arrangement design rule and simultaneously connect the local bit line and the global bit line. Therefore, the first storage area, the second storage area and the selection unit can all adopt the compact arrangement rule, that is, the bit line load of the static random access memory device can be reduced while avoiding the design rule of the logic circuit, i.e., avoiding the introduction of a buffer module between the device designed according to the logic circuit design rule and the storage unit to increase the area. Therefore, the power consumption of the static random access memory device can be reduced while avoiding a significant increase in the area.

[0012] In a possible implementation of the first aspect, the connection between the plurality of transistors in the first dummy unit is the same as the connection between the plurality of transistors in the second dummy unit. In this way, when the first dummy unit and the second dummy unit are arranged using the same design rule, it is beneficial to simplify the arrangement of the plurality of transistors in the first dummy unit and the second dummy unit.

[0013] In a possible implementation of the first aspect, the gate of the plurality of transistors in the first dummy unit and the gate of the plurality of transistors in the second dummy unit are connected to the same potential, for example, both are connected to a low potential, which is a potential lower than the power supply voltage of the static random access memory device. In this way, the plurality of transistors in the first dummy unit and the second dummy unit can only be used to meet the design rule, and do not play a role in the working process of the static random access memory device, thereby reducing the design complexity and ensuring the production yield of the normal storage unit adjacent to the dummy unit.

[0014] In a possible implementation of the first aspect, the static random access memory device comprises an N-well arranged in a first direction, and a first region and a second region on two sides of the N-well along a second direction perpendicular to the first direction; a number of transistors of the first memory cells arranged in the N-well, the first region and the second region is equal to a number of transistors of the first dummy cells arranged in the N-well, the first region and the second region respectively; and a number of transistors of the second memory cells arranged in the N-well, the first region and the second region is equal to a number of transistors of the second dummy cells arranged in the N-well, the first region and the second region respectively. In this way, the transistors of the first dummy cells arranged in the N-well, the first region and the second region can all use the same design rule as the transistors of the first memory cells arranged in the corresponding region, and the transistors of the second dummy cells arranged in the N-well, the first region and the second region can all use the same design rule as the transistors of the second memory cells arranged in the corresponding region. In addition, the gate control unit is arranged between the first dummy cells and the second dummy cells, and since the first dummy cells and the second dummy cells are not used to implement the storage function, the first dummy cells, the second dummy cells can be flexibly arranged, so that the gate control unit also meets the design rule.

[0015] In a possible implementation of the first aspect, a number of transistors of any one of the plurality of first memory cells and the first dummy cells arranged in the first region and the second region is equal; the plurality of first memory cells and the first dummy cells arranged in the first region are arranged in the first direction in sequence, and a first electrode of one of any two adjacent transistors and a second electrode of the other transistor share one electrode; and the plurality of first memory cells and the first dummy cells arranged in the second region are arranged in the first direction in sequence, and a first electrode of one of any two adjacent transistors and a second electrode of the other transistor share one electrode. A number of transistors of any one of the plurality of second memory cells and the second dummy cells arranged in the first region and the second region is equal; the plurality of second memory cells and the second dummy cells arranged in the first region are arranged in sequence, and a first electrode of one of any two adjacent transistors and a second electrode of the other transistor share one electrode; and the plurality of second memory cells and the second dummy cells arranged in the second region are arranged in sequence, and a first electrode of one of any two adjacent transistors and a second electrode of the other transistor share one electrode. In this way, the adjacent transistors of the first memory cells and the first dummy cells arranged in the first region and the second region can improve the storage density by sharing one electrode, and the adjacent transistors of the second memory cells and the second dummy cells arranged in the first region and the second region can improve the storage density by sharing one electrode.

[0016] In a possible implementation of the first aspect, one of any two adjacent ones of the plurality of first storage units and the first dummy unit comprises a first P-type transistor, and the other one comprises a second P-type transistor, a first electrode of one of the first P-type transistor and the second P-type transistor and a second electrode of the other one share one electrode, wherein the first P-type transistor and the second P-type transistor are the two closest transistors arranged in the N-well for the any two adjacent ones of the plurality of first storage units and the first dummy unit; one of any two adjacent ones of the second dummy unit and the plurality of second storage units comprises a third P-type transistor, and the other one comprises a fourth P-type transistor, a first electrode of one of the third P-type transistor and the fourth P-type transistor and a second electrode of the other one share one electrode, wherein the third P-type transistor and the fourth P-type transistor are the two closest transistors arranged in the N-well for the any two adjacent ones of the plurality of first storage units and the first dummy unit. In this way, the transistors arranged in the N-well can also improve the storage density by sharing one electrode.

[0017] In a possible implementation of the first aspect, the static random access memory device further comprises a region selection line, the gating unit comprises a first gating subunit and a second gating subunit arranged along the first direction, the first gating subunit comprises a first gating transistor, the second gating subunit comprises a second gating transistor, the local bit line comprises a first local bit line and a second local bit line, and the global bit line comprises a first global bit line and a second global bit line; a gate of the first gating transistor is connected to the region selection line, a first electrode of the first gating transistor is connected to the first local bit line, and a second electrode of the first gating transistor is connected to the first global bit line; a gate of the second gating transistor is connected to the region selection line, a first electrode of the second gating transistor is connected to the second global bit line, and a second electrode of the second gating transistor is connected to the second local bit line. In this way, the first gating transistor and the second gating transistor are arranged in the first gating subunit and the second gating subunit arranged along the first direction respectively, which can reduce mutual interference generated when the first gating transistor and the second gating transistor are arranged, and is conducive to making the first gating transistor and the second gating transistor meet the design rules. Moreover, the first gating transistor and the second gating transistor are simultaneously controlled by the region selection line, so that a specific storage region can be selected by the region selection line.

[0018] In a possible implementation of the first aspect, the first gating subunit further comprises a plurality of first dummy transistors, the plurality of first dummy transistors are arranged in the first region and the second region, the first gating transistor is arranged in the first region, and a sum of a number of the first dummy transistors arranged in the first region and a number of the first gating transistors arranged in the first region is equal to a number of the first dummy transistors arranged in the second region; the second gating subunit further comprises a plurality of second dummy transistors, the plurality of second dummy transistors are arranged in the first region and the second region, the second gating transistor is arranged in the second region, and a sum of a number of the second dummy transistors arranged in the second region and a number of the second gating transistors arranged in the second region is equal to a number of the second dummy transistors arranged in the first region. In this way, the number of the transistors arranged in the first region and the second region by the first gating subunit is the same, and the number of the transistors arranged in the first region and the second region by the second gating subunit is the same, so that the transistors can be symmetrically arranged with respect to the N-well, and the design rule of close arrangement is facilitated.

[0019] In a possible implementation of the first aspect, the number of the first dummy transistors arranged in the second region is equal to a number of the transistors of the first storage unit arranged in the second region; and the number of the second dummy transistors arranged in the first region is equal to a number of the transistors of the second storage unit arranged in the first region. Because the number of the transistors of the first dummy unit arranged in the second region is equal to the number of the transistors of the first storage unit arranged in the second region, the number of the first dummy transistors arranged in the second region is also equal to the number of the transistors of the first storage unit arranged in the second region, so the number of the transistors arranged in the second region by the first gating subunit is equal to the number of the transistors of the first storage unit arranged in the second region; and because a sum of the number of the first dummy transistors arranged in the first region and the number of the first gating transistors arranged in the first region is equal to the number of the first dummy transistors arranged in the second region, the number of the transistors arranged in the first region by the first gating subunit is equal to the number of the transistors of the first storage unit arranged in the second region. Similarly, the number of the transistors arranged in the first region and the second region by the second gating subunit is equal to the number of the transistors of the second storage unit arranged in the first region and the second region respectively. In this way, the arrangement of the transistors arranged in the first region and the second region by the first gating subunit can correspond to the arrangement of the transistors arranged in the first region and the second region by the first storage unit respectively, and the arrangement of the transistors arranged in the first region and the second region by the second gating subunit can correspond to the arrangement of the transistors arranged in the first region and the second region by the second storage unit respectively, so that the first gating subunit and the second gating subunit can adopt the design rule of close arrangement.

[0020] In a possible implementation manner of the first aspect, in the first region or the second region, a first dummy transistor of the first gating subunit is arranged adjacent to a transistor of the first dummy unit, and a first electrode of the transistor of the first dummy unit shares an electrode with a second electrode of the first dummy transistor; in the first region or the second region, a second dummy transistor of the second gating subunit is arranged adjacent to a transistor of the second dummy unit, and a first electrode of the transistor of the second dummy unit shares an electrode with a second electrode of the second dummy transistor. In this way, the first dummy transistor can facilitate the first gating subunit and the first dummy unit to adopt a closely arranged design rule by sharing an electrode with the adjacent transistor, and the second dummy transistor can facilitate the second gating subunit and the second dummy unit to adopt a closely arranged design rule by sharing an electrode with the adjacent transistor.

[0021] In a possible implementation manner of the first aspect, in the first region, a first electrode of the first gating transistor shares an electrode with a second electrode of a transistor of the first dummy unit adjacent to the first gating transistor, and a second electrode of the first gating transistor shares an electrode with a first electrode of the first dummy transistor adjacent to the first gating transistor; in the second region, a first electrode of the second gating transistor shares an electrode with a second electrode of the first dummy transistor adjacent to the second gating transistor, and a second electrode of the second gating transistor shares an electrode with a second electrode of the second dummy transistor adjacent to the second gating transistor. In this way, the first gating transistor can facilitate the first gating subunit and the first dummy unit to adopt a closely arranged design rule by sharing an electrode with the adjacent transistor, and the second gating transistor can facilitate the second gating subunit and the second dummy unit to adopt a closely arranged design rule by sharing an electrode with the adjacent transistor.

[0022] In a possible implementation manner of the first aspect, the first gating subunit further comprises a third gating transistor, and the second gating subunit further comprises a fourth gating transistor; a gate electrode of the third gating transistor is connected to a region selection line, a first electrode of the third gating transistor is connected to a first local bit line, and a second electrode of the third gating transistor is connected to a first global bit line; a gate electrode of the fourth gating transistor is connected to the region selection line, a first electrode of the fourth gating transistor is connected to a second local bit line, and a second electrode of the fourth gating transistor is connected to a second global bit line. In this way, the impedance between the first global bit line and the first local bit line can be reduced, the power consumption of the static random access memory device can be further reduced, and the read / write speed can be improved.

[0023] In a possible implementation manner of the first aspect, the region selection line is arranged to extend along the second direction to connect part of the gate electrode of the first gating transistor and part of the gate electrode of the second gating transistor. In this way, the arrangement of the region selection line can be facilitated, so that the first gating transistor and the second gating transistor can be simultaneously controlled to be turned off or turned on by the region selection line.

[0024] In a second aspect, the present application provides an electronic device, which comprises a circuit board and the static random access memory device as any one of the first aspect, and the static random access memory device is arranged on the circuit board. Since the electronic device adopts the static random access memory device which can reduce power consumption while avoiding a significant increase in area, the electronic device can also reduce the impact of arranging the static random access memory device while reducing the power consumption of the static random access memory device. BRIEF DESCRIPTION OF DRAWINGS

[0025] FIG. 1 is a block diagram of an electronic device according to an embodiment of the present application;

[0026] FIG. 2 is a schematic diagram of a static random access memory device according to the related art;

[0027] FIG. 3 is a circuit schematic diagram of a memory cell according to the related art;

[0028] FIG. 4 is a schematic diagram of another static random access memory device according to the related art;

[0029] FIG. 5 is a schematic diagram of another static random access memory device according to the related art;

[0030] FIG. 6 is a circuit schematic diagram of a static random access memory device according to an embodiment of the present application;

[0031] FIG. 7 is a layout design diagram of a static random access memory device according to an embodiment of the present application;

[0032] FIG. 8 is an architecture diagram of a possible static random access memory device according to an embodiment of the present application. DETAILED DESCRIPTION

[0033] Unless otherwise defined, technical or scientific terms used in the present application should have the same meaning as commonly understood by one of ordinary skill in the art. The terms "first", "second", "third", and the like as used in the specification and claims of the present application do not denote any order, quantity, or importance, but are used to distinguish different components. Thus, a feature with "first", "second", or "third" designation can explicitly or implicitly include one or more of the feature. In the description of the embodiments of the present application, unless otherwise stated, "a plurality of" means two or more.

[0034] The orientation terms such as "left", "right", "upper", and "lower" are defined with respect to the orientation of the device shown in the drawings, and it should be understood that these directional terms are relative concepts, which are used for relative description and clarification, and can be changed accordingly according to the orientation of the chip or semiconductor package structure.

[0035] Unless otherwise required by context, the term "including" as used herein is to be interpreted as open, inclusive, meaning "including, but not limited to". The description herein of any aspect or embodiment of the application using terms such as "one embodiment", "an embodiment", or "some embodiments" or "some examples" or "one example" or "some implementations" or "one implementation" etc. does not necessarily refer to the same embodiment or example, although it can. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments or examples. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting.

[0036] Referring to FIG. 1, FIG. 1 is a block diagram of an electronic device 20 according to an embodiment of the present application. The electronic device 20 can be a mobile phone, a computer (e.g., a tablet computer, a notebook computer), a personal digital assistant (PDA), a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a charging household small appliance (e.g., a soybean milk machine, a sweeping robot), a drone, a radar, an aerospace device, and a vehicle-mounted device, etc. different types of user equipment or terminal devices, or a network device such as a base station. The embodiments of the present application do not specially limit the specific form of the electronic device.

[0037] The electronic device 20 can include a circuit board 200, a bus 205, and a system on chip (SoC) 210 connected with the bus 205. The bus 205 and the system on chip 210 can be disposed on the circuit board 200. The system on chip 210 can be used to process data, such as data of an application program, image data, and temporary data for caching. In an embodiment, the system on chip 210 can include one or more processors 211, such as an application processor (AP) for processing data of an application program, and a graphics processing unit (GPU) for processing image data. The processor 211 can include a computing module and a first level cache (Cache L1) for caching high-speed data, and the computing module and the first level cache can be disposed on the same die. The system on chip 210 can further include more caches, such as a second level cache (Cache L2), a third level cache (Cache L3), a fourth level cache (Cache L4), and the like. It can be understood that one or more of the second level cache (Cache L2), the third level cache (Cache L3), and the fourth level cache (Cache L4) can be independently disposed from the processor 211, that is, the second level cache (Cache L2), the third level cache (Cache L3), and the fourth level cache (Cache L4) can be disposed outside the processor 211 and interact with the first level cache (Cache L1) through a data bus in the system on chip 210. At this time, the bus 205 can be connected with the data bus in the system on chip 210 through a data interface (not shown in FIG. 1).

[0038] The electronic device 200 can further include a storage device 220 connected with the system on chip 210 through the bus 205. The storage device 220 can also be disposed on the circuit board. The storage device 220 can also be a cache, and the storage device 220 can be disposed on the circuit board 200 through a slot and can interact with the caches in the system on chip 210 through the bus 205. The storage capacity of the storage device 220 is generally larger than that of the caches in the system on chip 210, but the speed of transmitting data with the processor 211 is slower than that of the caches in the system on chip 210.

[0039] The application also provides a static random access memory device, which can be the caches shown in FIG. 1 or the storage device 220.

[0040] Please refer to FIG. 2, which is a schematic diagram of a static random access memory device 300 in the prior art. The static random access memory device 300 includes a plurality of memory cells 400 and peripheral circuits connected to the memory cells 400 to control the reading and writing of the memory cells 400. For example, please refer to FIG. 3, which is a circuit schematic diagram of a memory cell 400 in the prior art. A memory cell 400 can include a pair of access transistors TA0, TA1, a pair of drive transistors TD0, TD1, and a pair of load transistors TL0, TL1. The gates of the pair of access transistors TA0, TA1 are connected to the same word line WL, and the reading and writing of the memory cell 400 can be controlled through the word line WL. The pair of access transistors TA0, TA1 and the pair of drive transistors TD0, TD1 can be N-type metal-oxide-semiconductor (NMOS) transistors, and the pair of load transistors TL0, TL1 can be P-type metal-oxide-semiconductor (PMOS) transistors.

[0041] In the static random access memory device 300, the plurality of memory cells 400 can be arranged in an array. Each row of memory cells 400 is connected to a word line, for example, the first row of memory cells 400 is connected to the word line WL1, and the 256th row of memory cells 400 is connected to the word line WL256. Each column of memory cells 400 is connected to the same pair of bit lines BL, BLB. It can be understood that when reading and writing the memory cells 400, a memory cell 400 can be selected through a word line and a pair of bit lines BL, BLB, and then the memory cell 400 can be read and written. In order to increase the storage density of the static random access memory device 300, a large number of memory cells 400 are connected to a pair of bit lines BL, BLB, for example, 256 memory cells 400 are connected to a pair of bit lines BL, BLB in FIG. 2. The more memory cells 400 connected to a bit line, the greater the load on the bit line. In the process of reading and writing the static random access memory device 300, a pair of bit lines BL, BLB connected to the selected memory cell 400 needs to be charged and discharged. The greater the load on the bit line, the greater the dynamic power consumption caused by charging and discharging the bit line during the reading and writing process. In addition, the power consumption consumed by charging and discharging the bit line can account for more than half of the total power consumption of the static random access memory device 300. Therefore, the greater the load on the bit line, the greater the total power consumption of the static random access memory device 300.

[0042] Referring to FIG. 4 and FIG. 3, FIG. 4 is a schematic diagram of another static random access memory device 300 in the related art. The static random access memory device 300 in FIG. 4 is different from the static random access memory device 300 in FIG. 2 in that local peripheral circuits are inserted in the column direction of the static random access memory device 300. In FIG. 4, the static random access memory device 300 includes local peripheral circuits and global peripheral circuits, the local peripheral circuits are connected to the outside of the static random access memory device 300 through the global peripheral circuits, and the local peripheral circuits divide the static random access memory device 300 into a plurality of memory areas in the column direction, for example, the static random access memory device 300 is divided into memory area 1 to memory area 4 in FIG. 4 by two local peripheral circuits, so that the bit lines of each column of memory cells 400 are also divided into bit lines BL1 to BL4. When reading data, the local peripheral circuits can respectively select the bit lines corresponding to the memory areas on both sides to perform read and write operations. Thus, the number of memory cells 400 connected by any one of the bit lines BL1 to BL4 is reduced by a factor of two, thereby reducing the load of the bit lines, and thus the power consumption of the static random access memory device 300 can be reduced.

[0043] However, since the local peripheral circuits are inserted in the column direction of the static random access memory device 300, the area of the static random access memory device 300 is increased. In addition, when constructing the circuit, the local peripheral circuits need to use the design rules of conventional logic circuits, while the memory cells of the static random access memory device 300 use the design rules of dense arrangement, and the circuits constructed by the two kinds of design rules cannot be directly adjacent, otherwise problems may occur in the preparation process and the finished product. Therefore, a buffer module needs to be designed between the local peripheral circuits and the memory cells. The introduction of the buffer module and the local peripheral circuits increases the area of the static random access memory device 300, for example, the area of the static random access memory device 300 will be increased by more than 45%, which is not conducive to improving the storage density of the static random access memory device 300.

[0044] Please refer to Fig. 5, and in combination with Fig. 3 and Fig. 4, Fig. 5 is a schematic diagram of another static random access memory device 300 in the related art. The static random access memory device 300 in Fig. 5 is different from the static random access memory device 300 in Fig. 3 in that the bit lines BL, BLB of the static random access memory device 300 are divided into multiple local bit lines LBL, LBLB (only one segment is shown in Fig. 5), each local bit line LBL is connected to a global bit line GBL through a pass transistor TS, each local bit line LBLB is connected to a global bit line GBLB through a pass transistor TS, and the pass transistor TS is controlled by a global word line GWL to be turned on or not. In this way, the storage area can be divided into multiple storage areas, and each storage area can be smaller. When reading and writing, the global word line GWL controls the pass transistor TS corresponding to the storage area that needs to be read or written to be turned on, and one of the multiple local word lines LWL in the storage area is selected to select the storage cell, so that the reading and writing operation of the storage cell can be realized. Therefore, since the bit lines are divided into multiple local bit lines LBL, LBLB, and the number of storage cells 400 on the bit lines does not change, the number of storage cells 400 connected to the local bit lines LBL, LBLB can be reduced, that is, the load of the local bit lines LBL, LBLB is reduced, so the power consumption of the static random access memory device 300 can be reduced.

[0045] Similarly, the pass transistor TS also needs to be constructed using the design rules of the conventional logic circuit, and the storage cells of the static random access memory device 300 adopt the design rules of dense arrangement, and the circuits constructed by the two kinds of design rules cannot be directly adjacent. Therefore, a buffer module needs to be designed between the pass transistor TS and the storage cell. The introduction of the buffer module will also cause a huge area overhead. For example, when the static random access memory device 300 in Fig. 2 is divided into 4 storage areas, the area of the static random access memory device 300 will increase by more than 25%.

[0046] Please refer to Fig. 6-7, Fig. 6 is a circuit schematic diagram of a static random access memory device 300 provided by an embodiment of the present application, and Fig. 7 is a layout design diagram of a static random access memory device 300 provided by an embodiment of the present application. The static random access memory device 300 can include a first storage area 310, a second storage area 320, a pass unit 500, a global bit line GBL and a local bit line LB. The first storage area 310 and the second storage area 320 can include arrayed storage cells 400. For the convenience of description, the arrangement direction of the first storage area 310 and the second storage area 320 is the first direction X, and the second direction Y intersects the first direction X, for example, the second direction Y is perpendicular to the first direction X.

[0047] The first storage region 310 includes a first dummy cell 311 and a plurality of first storage cells 400a, which are arranged in the first direction X in sequence. The first dummy cell 311 is arranged at one side of the plurality of first storage cells 400a close to the second storage region 320. The first dummy cell 311 can include a plurality of transistors T1-T6, and the first storage cell 400a can also include a plurality of transistors T. Moreover, the number of transistors included in the first dummy cell 311 and the first storage cell 400a is equal, for example, the first dummy cell 311 and the first storage cell 400a each include six transistors. The first storage cell 400a can be a storage cell as shown in FIG. 3, but the present application does not make any limitation in this regard.

[0048] In addition, according to the arrangement order of the plurality of first storage cells 400a and the first dummy cell 311, the arrangement of the plurality of transistors in each of the plurality of first storage cells 400a and the first dummy cell 311 changes periodically, and the period of the arrangement change is not limited, for example, it can be one cell, two cells, three cells, etc., where the cell refers to one first storage cell 400a or one first dummy cell 311. Since the plurality of first storage cells 400a and the first dummy cell 311 are arranged in the first direction X in sequence, the first dummy cell 311 is arranged after the plurality of first storage cells 400a in the first direction X. Understandably, since the first storage cell 400a and the first dummy cell 311 each include a plurality of transistors, in the finished static random access memory device 300, there is a certain positional relationship between the plurality of transistors, which is the arrangement of the plurality of transistors. Exemplarily, referring to FIG. 7, for a first dummy cell 311 including six transistors T1-T6, the six transistors T1-T6 can be arranged in four rows in the second direction Y, each row is arranged in the first direction X, the first row and the fourth row each include two transistors, the second row and the third row each include one transistor, and the transistors in the second row and the transistors in the third row are arranged staggered in the second direction Y. For example, the transistors T2 and T1 are arranged in the first row in the first direction X in sequence, the transistors T3 and T4 are arranged in the fourth row in the first direction X in sequence, the transistor T5 is arranged in the second row, and the transistor T6 is arranged in the third row; and the transistor T5 and the transistor T6 are arranged staggered in the second direction Y, the transistors T2, T5 and T3 are arranged in alignment in the second direction Y, and the transistors T1, T6 and T4 are arranged in alignment in the second direction Y.

[0049] The second storage area 320 includes a second dummy cell 312 and a plurality of second storage cells 400b, which are arranged in sequence along the first direction X. It can be understood that the second dummy cell 312 is arranged at one side of the plurality of second storage cells 400b close to the first storage area 310. Thus, the first dummy cell 311 is arranged between the plurality of first storage cells 400a and the plurality of second storage cells 400b, and the second dummy cell 312 is also arranged between the plurality of first storage cells 400a and the plurality of second storage cells 400b. The second dummy cell 312 can include a plurality of transistors T15-T20, and the second storage cell 400b can also include a plurality of transistors T. Moreover, the number of transistors included in the second dummy cell 312 and the second storage cell 400b can be equal, for example, the second dummy cell 312 and the second storage cell 400b each include 6 transistors. The second storage cell 400b can also be a storage cell as shown in FIG. 3, but the present application does not make any limitation in this regard.

[0050] Similarly, according to the arrangement order of the second dummy cell 312 and the plurality of second storage cells 400b, the arrangement of the plurality of transistors in each of the second dummy cell 312 and the plurality of second storage cells 400b changes periodically, and the period of the arrangement change is not limited, for example, it can be 1 cell, 2 cells, 3 cells, etc. Since the second dummy cell 312 and the plurality of second storage cells 400b are arranged in sequence along the first direction X, along the first direction X, the second dummy cell 312 is arranged before the plurality of second storage cells 400b. It can be understood that since the second dummy cell 312 and the second storage cell 400b each include a plurality of transistors, in the completed static random access memory device 300, there is a certain positional relationship between the plurality of transistors, which is the arrangement of the plurality of transistors. Exemplarily, please continue to refer to FIG. 7, for a second dummy cell 312 including 6 transistors T15-T20, the 6 transistors T15-T20 can be arranged in 4 rows along the second direction Y, each row is arranged along the first direction X, the first row and the fourth row each include two transistors, the second row and the third row each include one transistor, and the transistors in the second row and the transistors in the third row are arranged staggered in the second direction Y. For example, the transistors T15 and T16 are arranged in sequence along the first direction X in the first row, the transistors T18 and T17 are arranged in sequence along the first direction X in the fourth row, the transistor T19 is arranged in the second row, and the transistor T20 is arranged in the third row; and the transistors T19, T20 and T15 are arranged staggered in the second direction Y, the transistors T15, T20 and T18 are arranged in alignment in the second direction Y, and the transistors T16, T19 and T17 are arranged in alignment in the second direction Y.

[0051] The gating unit 500 is disposed between the first storage area 310 and the second storage area 320, and the gating unit 500 is disposed adjacent to the first dummy unit 311 and the second dummy unit 312. Thus, the first dummy unit 311, the gating unit 500 and the second dummy unit 312 are also arranged in sequence along the first direction X, that is, the first dummy unit 311, the gating unit 500 and the second dummy unit 312 are arranged along a straight line, and the extension direction of the straight line is the first direction X. The gating unit 500 can be used to connect the local bit line LB and the global bit line GB. That is, the local bit line LB is connected with the global bit line GB through the gating unit 500.

[0052] The local bit line LB can be connected with the first storage unit 400a or the second storage unit 400b. That is, the first storage area 310 and the second storage area 320 correspond to different local bit lines LB. Exemplarily, the local bit line LB can be connected with a plurality of first storage units 400a (only one first storage unit 400a is shown in FIG. 6) in the first storage area 310, and the local bit line LB is also connected with a plurality of second storage units 400b (only one second storage unit 400b is shown in FIG. 6) in the second storage area 320. In this way, the storage unit 400 in the storage area corresponding to the local bit line LB can be selected by the local bit line LB to perform read / write operation. For example, after selecting the local bit line LB connected with the first storage unit 400a and the word line WL connected with the first storage unit 400a, the read / write operation can be performed on the first storage unit 400a in the first storage area 310.

[0053] The global bit line GB can be connected with the local bit line LB through the gating unit 500. It can be understood that the end of the global bit line GB not connected with the gating unit 500 can be connected to a peripheral circuit (not shown in FIG. 6). The gating unit 500 can selectively conduct the connection between the global bit line GB and the local bit line LB, so that when the storage unit 400 is read / written, only the local bit line corresponding to the storage area in the plurality of storage areas can be conducted, thereby reducing the number of storage units 400 connected by the local bit line, reducing the load of the bit line, and thus the power consumption of the static random access memory device 300 can be reduced.

[0054] In addition, since the arrangement of the plurality of transistors in each of the plurality of first storage units 400a and the first dummy unit 311 varies periodically according to the arrangement order of the plurality of first storage units 400a and the first dummy unit 311, the first dummy unit 311 can adopt the same design rule as the first storage unit 400a, i.e., the design rule of the closely arranged storage unit 400; similarly, the second dummy unit 312 can also adopt the same design rule as the second storage unit 400b. Since the selection unit 500 is arranged adjacent to the first dummy unit 311 and the second dummy unit 312, and the first dummy unit 311 and the second dummy unit 312 do not implement the storage function, the connection relationship between the plurality of transistors of the first dummy unit 311 and the connection relationship between the plurality of transistors of the second dummy unit 312 are not limited. Thus, the first dummy unit 311 and the second dummy unit 312 can be used to make the selection unit 500 meet the design rule of the closely arranged storage unit 400 while making the selection unit 500 connect the local bit line LB and the global bit line GB. Thus, the first storage area 310, the second storage area 320 and the selection unit 500 can all adopt the design rule of the closely arranged storage unit 400, that is, the different design rule introduced by the logic circuit can be avoided while reducing the bit line load of the static random access memory device 300, and the buffer module introduced between the logic circuit and the storage unit 400 can be avoided. Therefore, the static random access memory device 300 can reduce power consumption while avoiding a significant increase in area.

[0055] It can be understood that the first storage unit 400a of the first storage area 310 and the second storage unit 400b of the second storage area 320 can be the same, that is, the number of transistors of the first storage unit 400a and the number of transistors of the second storage unit 400b are the same, and the arrangement of the plurality of transistors of each of the plurality of first storage units 400a can be the same as the arrangement of the plurality of transistors of each of the plurality of second storage units 400b. For example, the plurality of transistors of the first storage unit 400a can have two arrangements, and the plurality of transistors of the second storage unit 400b can also have two arrangements, the two arrangements of the plurality of transistors of the first storage unit 400a are the same as the two arrangements of the plurality of transistors of the second storage unit 400b, and the periodic variation law of the two arrangements of the plurality of transistors of the first storage unit 400a is also the same as the periodic variation law of the two arrangements of the plurality of transistors of the second storage unit 400b.

[0056] In some embodiments, due to the periodic change of the arrangement of the plurality of transistors of each of the first storage unit 400a and the first dummy unit 311, the arrangement of the plurality of transistors of the first dummy unit 311 is one of the possible arrangements of the plurality of transistors of the first storage unit 400a; similarly, the arrangement of the plurality of transistors of the second dummy unit 312 is one of the possible arrangements of the plurality of transistors of the second storage unit 400b. Since the first storage unit 400a and the second storage unit 400b can be identical, the arrangement of the plurality of transistors of the second dummy unit 312 can be identical to or different from the arrangement of the plurality of transistors of the first dummy unit 311; at different times, the arrangement of the plurality of transistors of the second dummy unit 312 and the arrangement of the plurality of transistors of the first dummy unit 311 are both one of the periodically changed arrangements. Understandably, regardless of which case, the connection between the plurality of transistors of the first dummy unit 311 can be identical to the connection between the plurality of transistors of the second dummy unit 312, so that when the first dummy unit 311 and the second dummy unit 312 are set by using the same design rule, it is beneficial to simplify the arrangement of the plurality of transistors of the first dummy unit 311 and the second dummy unit 312.

[0057] For example, the gates of the plurality of transistors of the first dummy unit 311 and the gates of the plurality of transistors of the second dummy unit 312 can be connected to the same potential. Therefore, the plurality of transistors in the first dummy unit 311 and the second dummy unit 312 can only be used to meet the design rule, thereby reducing the design complexity and facilitating the selection unit 500 to meet the design rule.

[0058] For example, in the first dummy unit 311, the gates of the transistors T1-T6 can be connected to a low potential. For example, the gate of the transistor T5 and the gate of the transistor T6 are connected to the same low potential line VSS, and the gates of the transistors T1-T4 are connected to another low potential line VSS. In addition, the first electrode of the transistor T1 and the first electrode of the transistor T2 are connected to the gate of the transistor T2, and the second electrode of the transistor T1 and the second electrode of the transistor T2 are also connected to the gate of the transistor T2; the first electrode of the transistor T5 can be connected to a power supply line VDD, and the second electrode of the transistor T5 can be suspended; the first electrodes of the transistors T3, T4 and T6 can be connected to a local bit line LBLB1, and the second electrodes of the transistors T3, T4 and T6 are connected to each other. Understandably, the first electrode refers to one of the source electrode or the drain electrode of the transistor, and the second electrode refers to the other of the source electrode or the drain electrode of the transistor. Similarly, the second dummy unit 312 can also have the same connection mode, which will not be described herein.

[0059] In some embodiments, the static random access memory device 300 can further comprise a block select line SWL, which can be used to control the selection unit 500 to turn on or turn off.

[0060] For example, the selection unit 500 can comprise a first selection subunit 510 and a second selection subunit 520 arranged along the first direction X, the first selection subunit 510 can comprise a first selection transistor T10, the second selection subunit 520 can comprise a second selection transistor T14, the local bit line LB can comprise a first local bit line LBL1 and a second local bit line LBLB1, and the global bit line GB can comprise a first global bit line GBL and a second global bit line GBLB. The first local bit line LBL1 and the second local bit line LBLB1 are connected with the first storage unit 400a in the first storage block 310.

[0061] The gate of the first selection transistor T10 can be connected with the block select line SWL, the first pole of the first selection transistor T10 can be connected with the first local bit line LBL1, and the second pole of the first selection transistor T10 can be connected with the first global bit line GBL; the gate of the second selection transistor T14 can be connected with the block select line SWL, the first pole of the second selection transistor T14 can be connected with the second local bit line LBLB1, and the second pole of the second selection transistor T14 can be connected with the second global bit line GBLB (as shown in FIG. 6 and FIG. 7).

[0062] It can be understood that the local bit line LB can also comprise a third local bit line LBL2 and a fourth local bit line LBLB2, which can be connected with the first global bit line GBL and the second global bit line GBLB through another selection unit 500. The another selection unit 500 refers to the selection unit 500 other than the selection unit 500 connected with the first local bit line LBL1 and the second local bit line LBLB1.

[0063] Please continue to refer to FIG. 7 and combine with FIG. 6, the static random access memory device 300 further comprises N-well NW arranged along the first direction X, and the first region A1 and the second region A2 on both sides of the N-well NW along the second direction Y. It can be understood that the transistors of the storage unit 400 can comprise P-type transistors, which can be arranged in the N-well NW. Therefore, the first dummy unit 311 and the second dummy unit 312 can also comprise transistors arranged in the N-well NW. In addition, the first storage unit 400a, the first dummy unit 311, the selection unit 500, the second dummy unit 312 and the second storage unit 400b are arranged along the first direction X, that is, the first storage unit 400a, the first dummy unit 311, the selection unit 500, the second dummy unit 312 and the second storage unit 400b can comprise transistors arranged in the first region A1 and the second region A2.

[0064] In some embodiments, the number of transistors in which the first storage unit 400a is disposed in the N-well NW, the first region A1 and the second region A2 is equal to the number of transistors in which the first dummy unit 311 is disposed in the N-well NW, the first region A1 and the second region A2, respectively. That is, the number of transistors in which the first storage unit 400a is disposed in the N-well NW is equal to the number of transistors in which the first dummy unit 311 is disposed in the N-well NW, respectively, the number of transistors in which the first storage unit 400a is disposed in the first region A1 is equal to the number of transistors in which the first dummy unit 311 is disposed in the first region A1, respectively, and the number of transistors in which the first storage unit 400a is disposed in the second region A2 is equal to the number of transistors in which the first dummy unit 311 is disposed in the second region A2, respectively. Thus, the transistors of the first dummy unit 311 in the N-well NW, the first region A1 and the second region A2 can have the same arrangement rule as the transistors of the first storage unit 400a in the N-well NW, the first region A1 and the second region A2, respectively, so as to facilitate the first dummy unit 311 to meet the design rule of the first storage unit 400a.

[0065] The number of transistors in which the second storage unit 400b is disposed in the N-well NW, the first region A1 and the second region A2 is equal to the number of transistors in which the second dummy unit 312 is disposed in the N-well NW, the first region A1 and the second region A2, respectively. In this way, the second dummy unit 312 can meet the design rule of the second storage unit 400b.

[0066] Exemplarily, the number of transistors in which any one of the plurality of first storage units 400a and the first dummy unit 311 is disposed in the first region A1 and the second region A2 is equal. That is, the number of transistors in which the first storage unit 400a is disposed in the first region A1 and the second region A2 is equal, and the number of transistors in which the first dummy unit 311 is disposed in the first region A1 and the second region A2 is equal. For example, the number of transistors in which the first dummy unit 311 is disposed in the first region A1 and the second region A2 is both two, and the transistors disposed in the first region A1 or the second region A2 can be arranged along the first direction X. In this way, the transistors in the first region A1 and the second region A2 can be symmetrically disposed with respect to the N-well NW, thereby facilitating the implementation of the design rule of close arrangement.

[0067] The transistors in which the plurality of first storage units 400a and the first dummy unit 311 are disposed in the first region A1 are arranged in the first direction X in sequence, and one of the first electrodes of any two adjacent transistors shares one electrode with the second electrode of the other. The transistors in which the plurality of first storage units 400a and the first dummy unit 311 are disposed in the second region A2 are arranged in the first direction in sequence, and one of the first electrodes of any two adjacent transistors shares one electrode with the second electrode of the other. In this way, the transistors in which the plurality of first storage units 400a and the first dummy unit 311 are disposed in the first region A1 and the second region A2 can be arranged densely, so that the first dummy unit 311 can achieve a design rule of close arrangement.

[0068] Similarly, the number of transistors in which any of the second dummy unit 312 and the plurality of second storage units 400b are disposed in the first region A1 and the second region A2 is equal. The transistors in which the plurality of second storage units 400b and the second dummy unit 312 are disposed in the first region A1 are arranged in sequence, and one of the first electrodes of any two adjacent transistors shares one electrode with the second electrode of the other; the transistors in which the plurality of second storage units 400b and the second dummy unit 312 are disposed in the second region A2 are arranged in sequence, and one of the first electrodes of any two adjacent transistors shares one electrode with the second electrode of the other. In this way, the transistors in which the plurality of second storage units 400b and the second dummy unit 312 are disposed in the first region A1 and the second region A2 can be arranged densely, so that the second dummy unit 312 can achieve a design rule of close arrangement.

[0069] As described above, the plurality of first storage units 400a and the first dummy unit 311 can include transistors disposed in the N-well NW, and it can be understood that the transistors disposed in the N-well NW can be P-type transistors.

[0070] Exemplarily, any two adjacent ones of the plurality of first storage units 400a and the first dummy unit 311 each include a first P-type transistor E1 and a second P-type transistor E2, which are the two closest transistors arranged in the N-well for the any two adjacent ones of the plurality of first storage units 400a and the first dummy unit 311, that is, the first P-type transistor E1 is arranged in one of the any two adjacent ones of the plurality of first storage units 400a and the first dummy unit 311, the second P-type transistor E2 is arranged in the other of the any two adjacent ones of the plurality of first storage units 400a and the first dummy unit 311, and the first electrode of one of the first P-type transistor E1 and the second P-type transistor E2 and the second electrode of the other one can share one electrode. Understandably, in this case, the first P-type transistor and the second P-type transistor are arranged along the first direction X. In this way, the first P-type transistor E1 and the second P-type transistor E2 arranged in the N-well can achieve a design rule of close arrangement.

[0071] Similarly, any two adjacent ones of the second dummy unit 312 and the plurality of second storage units 400b each include a third P-type transistor E3 and a fourth P-type transistor E4, which are the two closest transistors arranged in the N-well for the any two adjacent ones of the second dummy unit 312 and the plurality of second storage units 400b. The first electrode of one of the third P-type transistor E3 and the fourth P-type transistor E4 and the second electrode of the other one share one electrode. In this way, the third P-type transistor E3 and the fourth P-type transistor E4 arranged in the N-well can achieve a design rule of close arrangement.

[0072] In some embodiments, in the case that the gating unit 500 includes the first gating sub-unit 510 and the second gating sub-unit 520, the first gating sub-unit 510 can further include a plurality of first dummy transistors, which are arranged in the first region A1 and the second region A2. For example, the first dummy transistor T7 and the first dummy transistor T8 are arranged in the second region A2, and the first dummy transistor T9 is arranged in the first region A1. The first gating transistor T10 can be arranged in the first region A1, so that the sum of the number of the first dummy transistors arranged in the first region A1 and the number of the first gating transistor T10 arranged in the first region A1 is equal to the number of the first dummy transistors arranged in the second region A2. In this way, the number of the transistors arranged in the first region A1 and the second region A2 of the first gating sub-unit 510 is the same, so that these transistors can be symmetrically arranged with respect to the N-well NW, facilitating the implementation of a design rule of close arrangement.

[0073] Similarly, the second gating subunit 520 also includes a plurality of second dummy transistors, which are arranged in the first region A1 and the second region A2. For example, the second dummy transistor T11 and the second dummy transistor T12 are arranged in the first region A1, and the second dummy transistor T13 is arranged in the second region A2. The second gating transistor T14 can be arranged in the second region A2, so that the sum of the number of the second dummy transistors arranged in the second region A2 and the number of the second gating transistor T14 arranged in the second region A2 is equal to the number of the second dummy transistors arranged in the first region A1.

[0074] In the case that the number of the first dummy transistors is equal to the number of the second dummy transistors, and the number of the first gating transistors is equal to the number of the second gating transistors, the connection of the first dummy transistors and the first gating transistors can be the same as the connection of the second dummy transistors and the second gating transistors.

[0075] For example, referring to FIG. 6, the number of the first dummy transistors is 3, which are the first dummy transistors T7-T9; the number of the second dummy transistors is 3, which are the second dummy transistors T11-T13; the number of the first gating transistors is equal to the number of the second gating transistors, which are the first gating transistor T10 and the second gating transistor T14, respectively.

[0076] The source, the drain and the gate of the first dummy transistor T9 are connected to each other and connected to the source or the drain of the first gate transistor T10, and the first dummy transistor T7 and the first dummy transistor T8 are not directly connected to the first gate transistor T10. The source, the drain and the gate of the first dummy transistor T7 are connected to each other and connected to the gate of the first dummy transistor T8, and the gate of the first dummy transistor T8 is connected to the source or the drain of the first dummy transistor T8 and then connected to the low potential line VSS. Similarly, the source, the drain and the gate of the second dummy transistor T13 are connected to each other and connected to the source or the drain of the second gate transistor T14, and the second dummy transistor T11 and the second dummy transistor T12 are not directly connected to the second gate transistor T14. The source, the drain and the gate of the second dummy transistor T11 are connected to each other and connected to the gate of the second dummy transistor T12, and the gate of the second dummy transistor T12 is connected to the source or the drain of the second dummy transistor T12 and then connected to the low potential line VSS. In this way, the layout design of the first gate subunit 510 and the second gate subunit 520 can be the same, which is conducive to simplifying the layout design. It can be understood that, in order to clearly describe the arrangement of the transistors, only the connection of part of the transistors is shown in the layout design in FIG. 7, for example, only the connection of the first gate transistor T10 and the second gate transistor T14 is shown. At the same time, FIG. 7 only shows the local bit line LB connected with the first storage unit 400a in the first storage area 310, and does not show the local bit line LB connected with the second storage unit 400b in the second storage area 320.

[0077] For example, the sum of the number of the first dummy transistors T7-T9 and the first gate transistor T10 is less than the number of the transistors of the first storage unit 400a. That is, in the case where the first gate subunit 510 only includes the first dummy transistors T7-T9 and the first gate transistor T10, the number of the transistors of the first gate subunit 510 is less than the number of the transistors of the first storage unit 400a.

[0078] Similarly, the sum of the number of the second dummy transistors T11-T13 and the second gate transistor T14 is less than the number of the transistors of the second storage unit 400b. That is, in the case where the second gate subunit 520 only includes the second dummy transistors T11-T13 and the second gate transistor T14, the number of the transistors of the second gate subunit 520 is less than the number of the transistors of the second storage unit 400b. In this way, the conflicting transistors in the first gate subunit 510 can be removed during the layout design, improving the flexibility of the layout design.

[0079] Exemplarily, the number of the first dummy transistors disposed in the second region A2 can be equal to the number of the transistors of the first storage unit 400a disposed in the second region A2. In this way, in the case that the number of the transistors of any one of the first storage unit 400a and the first dummy unit 311 disposed in the first region A1 and the second region A2 is equal, the number of the transistors (the first dummy transistors or the first gate transistors) of the first gate subunit 510 disposed in the first region A1 is equal to the number of the transistors of the first storage unit 400a or the first dummy unit 311 disposed in the second region A2. In this way, the transistors of the first gate subunit 510 can be disposed in the first region A1 and the second region A2 by using the same design rule as the first storage unit 400a.

[0080] Similarly, the number of the second dummy transistors disposed in the first region A1 can also be equal to the number of the transistors of the second storage unit 400b disposed in the first region A1.

[0081] Exemplarily, in the first region A1, the transistor adjacent to the first gate transistor T10 in the first direction X shares a pole with the first gate transistor T10, which can be one transistor of the first dummy unit 311 or the first dummy transistor. For example, the first pole of the first gate transistor T10 and the second pole of one transistor of the first dummy unit 311 adjacent to the first gate transistor T10 share a pole, and the second pole of the first gate transistor T10 and the first pole of the first dummy transistor adjacent to the first gate transistor T10 share a pole.

[0082] Similarly, in the second region A2, the transistor adjacent to the second gate transistor T14 in the first direction X shares a pole with the second gate transistor T14, which can be one transistor of the second dummy unit 312 or the second dummy transistor. For example, the first pole of the second gate transistor T14 and the second pole of the second dummy transistor adjacent to the second gate transistor T14 share a pole, and the second pole of the second gate transistor T14 and the second pole of the second dummy transistor adjacent to the second gate transistor T14 share a pole.

[0083] Exemplarily, in the first region A1 or the second region A2, one first dummy transistor of the first gate subunit 510 is disposed adjacent to one transistor T of the first dummy unit 311, and the first pole of the one transistor T of the first dummy unit and the second pole of the one first dummy transistor can share a pole.

[0084] Similarly, in the first region A1 or the second region A2, one second dummy transistor of the second gating subunit 520 is arranged adjacent to one transistor of the second dummy unit 312, and the first pole of the one transistor of the second dummy unit 312 shares one pole with the second pole of the one second dummy transistor. In this way, the transistors of the first gating subunit 510 can be facilitated to adopt the same design rule as the transistors T of the first dummy unit 311, and the transistors of the second gating subunit 520 can be facilitated to adopt the same design rule as the transistors T of the second dummy unit 312.

[0085] Exemplarily, the first gating subunit 510 can further include a third gating transistor, and the second gating subunit 520 can further include a fourth gating transistor. The gate of the third gating transistor is connected with the area selection line SWL, the first pole of the third gating transistor is connected with the first local bit line LBL1, and the second pole of the third gating transistor is connected with the first global bit line GBL; the gate of the fourth gating transistor is connected with the area selection line SWL, the first pole of the fourth gating transistor is connected with the second local bit line LBLB1, and the second pole of the fourth gating transistor is connected with the second global bit line GBLB. In this way, the impedance between the first global bit line GBL and the first local bit line LBL1 can be reduced, so that the power consumption can be further reduced, and the read / write speed of the static random access memory device 300 can also be improved.

[0086] As described above, the first storage unit 400a, the first dummy unit 311, the gating unit 500, the second dummy unit 312 and the second storage unit 400b can each include transistors arranged in the first region A1 and the second region A2. Please refer to FIG. 7, in the structural arrangement of the static random access memory device 300, the first local bit line LBL1 and the second local bit line LBLB1 can be respectively arranged above the transistors of the first storage unit 400a, the first dummy unit 311 and the gating unit 500 located in the first region A1 and the second region A2, at this time, the first local bit line LBL1 and the second local bit line LBLB1 are respectively arranged to extend in the first direction X. In addition, the size of the first local bit line LBL1 and the second local bit line LBLB1 in the second direction Y can be greater than the size of the source or the drain of the transistors in the second direction Y, and in the orthogonal projection on the plane perpendicular to the first direction X and the second direction Y, the orthogonal projection of at least part of the transistors of the first storage unit 400a, the first dummy unit 311 and the gating unit 500 located in the first region A1 and the second region A2 can be respectively located in the orthogonal projection of the local bit line LBL1 and the local bit line LBLB1.

[0087] In addition, in the case that the first region A1 and the second region A2 are respectively provided in the first pass transistor T10 and the second pass transistor T14, the portion of the zone selection line SWL connecting the gate of the first pass transistor T10 and the gate of the second pass transistor T14 is arranged to extend along the second direction Y. In this way, the first pass transistor T10 and the second pass transistor T14 can be conveniently connected with the zone selection line SWL.

[0088] It can be understood that the transistors forming the first storage unit 400a, the first dummy unit 311, the pass unit 500, the second dummy unit 312 and the second storage unit 400b need to be connected with various signal lines, and the transistors can be connected with the various signal lines through the contact plug CT. For example, still referring to FIG. 7, the first pass transistor T10 can be connected with the first local bit line LBL1 through the contact plug CT, and the second pass transistor T14 can also be connected with the second local bit line LBLB1 through the contact plug CT.

[0089] It can be understood that FIG. 6 and FIG. 7 only show one row or one column of the static random access memory device 300, and for the purpose of more clearly illustrating the present application, please refer to FIG. 8 in combination with FIG. 6 and FIG. 7, which is a possible architecture diagram of the static random access memory device 300 provided by the embodiments of the present application.

[0090] In some embodiments, the static random access memory device 300 includes a row decoder, a plurality of local decoders and a control circuit. The row decoder is connected with the plurality of local decoders and controls the plurality of local decoders. Each storage zone can be connected with one local decoder, and the storage zone here can be the first storage zone 310 or the second storage zone 320. Each local decoder not only controls the word line WL of the storage unit 400 in each storage zone, but also controls the zone selection line SWL of each storage zone. The control circuit can select a column of storage units 400 through the global bit line GB. At the same time, the control circuit can control the zone selection line SWL to turn on the first pass transistor T10 and the second pass transistor T14 in the storage zone through the row decoder, that is, to connect the global bit line GB with the local bit line LB of the storage zone. It can be understood that at this time, the zone selection lines SWL of other storage zones do not control the first pass transistor T10 and the second pass transistor T14 corresponding to the storage zone to be turned on. Thus, the read and write operations of the storage unit 400 in the storage zone can be controlled through the word line WL in the storage zone corresponding to the turned-on first pass transistor T10 and the second pass transistor T14. In addition, a sense amplifier SA can be arranged between the first global bit line GBL and the second global bit line GBLB, and the sense amplifier SA can be used to obtain the read data.

[0091] For example, the static random access memory device 300 can further include an auxiliary unit connected to both the first global bit line GBL and the second global bit line GBLB. The auxiliary unit can increase the potential of the first global bit line GBL and decrease the potential of the second global bit line GBLB when data is written into the memory cell 400. In this way, the influence of the first pass transistor T10 or the second pass transistor T14 on the writing of data can be avoided.

[0092] As can be easily understood, in the process of writing data, for example, writing "0", the first global bit line GBL is at low potential and the second global bit line GBLB is at high potential. Since the first pass transistor T10 is arranged between the first global bit line GBL and the first local bit line LBL1 and the second pass transistor T14 is arranged between the second global bit line GBLB and the second local bit line LBLB1, the potential of the first global bit line GBL can be slightly lower than that of the first local bit line LBL1 and the potential of the second global bit line GBLB can be slightly higher than that of the second local bit line LBLB1, thereby reducing the voltage difference between the two ends of the memory cell 400 connected to the first local bit line LBL1 and the second local bit line LBLB1. At this time, since the auxiliary unit can increase the potential of the first global bit line GBL and decrease the potential of the second global bit line GBLB, the influence of the first pass transistor T10 or the second pass transistor T14 can be avoided.

[0093] In addition, in the process of reading data, for example, reading data "0", although the first pass transistor T10 increases the resistance between the first global bit line GBL and the first local bit line LBL1 and the second pass transistor T14 increases the resistance between the second global bit line GBLB and the second local bit line LBLB1, the speed of discharging is not greatly affected. In addition, when the voltage difference between the first local bit line LBL1 and the second local bit line LBLB1 reaches the read threshold, the sense amplifier SA is turned on, which can further discharge the charges on the first local bit line LBL1 and the first global bit line GBL, thereby reading the data. Thus, the first pass transistor T10 or the second pass transistor T14 has little effect on the reading performance of the memory cell 400.

[0094] Referring to Table 1, Table 1 is a comparison table of power consumption and area of the static random access memory device 300 shown in FIGS. 6 and 7 and the memory device in FIGS. 3 and 5.

[0095] Table 1

[0096] As shown in Table 1, the static random access memory device 300 provided by the present application can reduce read power consumption by 20% to 30%, reduce write power consumption by 0% to 5%, and only increase area by 5% compared with the memory device in FIG. 3. The static random access memory device 300 provided by the present application can reduce area by 20% to 30% compared with the memory device in FIG. 5, while the read and write power consumption is basically the same.

[0097] The above merely provides specific implementation manners of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A static random access memory device, comprising: The static random access memory device comprises: a first storage area and a second storage area, the first storage area comprising a plurality of first storage units and a first dummy unit arranged along a first direction, and the second storage area comprising a second dummy unit and a plurality of second storage units arranged along the first direction, the first direction being the direction in which the first storage area and the second storage area are arranged; a gating unit arranged between the first dummy unit and the second dummy unit; a local bit line connected to the plurality of first storage units or the plurality of second storage units; a global bit line connected to the local bit line through the gating unit; wherein the first dummy unit and the first storage unit each comprise a plurality of transistors, and the number of transistors included is equal, and the arrangement of the plurality of transistors of each of the first dummy unit and the first storage unit changes periodically according to the arrangement order of the first dummy unit and the first storage unit; the second dummy unit and the second storage unit each comprise a plurality of transistors, and the number of transistors included is equal, and the arrangement of the plurality of transistors of each of the second dummy unit and the second storage unit changes periodically according to the arrangement order of the second dummy unit and the plurality of second storage units.

2. The static random access memory device of claim 1, wherein, The connection between the plurality of transistors of the first dummy unit is the same as the connection between the plurality of transistors of the second dummy unit.

3. The static random access memory device of claim 1 or 2, wherein, The gate of the plurality of transistors of the first dummy unit and the gate of the plurality of transistors of the second dummy unit are connected to the same potential.

4. The static random access memory device according to any one of claims 1 to 3, wherein, N wells arranged in the first direction, and a first region and a second region on both sides of the N wells along a second direction, the second direction being perpendicular to the first direction; The number of transistors of the first storage unit arranged in the N wells, the first region and the second region is equal to the number of transistors of the first dummy unit arranged in the N wells, the first region and the second region respectively; The number of transistors of the second storage unit arranged in the N wells, the first region and the second region is equal to the number of transistors of the second dummy unit arranged in the N wells, the first region and the second region respectively.

5. The static random access memory device of claim 4, wherein the number of transistors of any one of the plurality of first storage units and the first dummy unit arranged in the first region and the second region is equal; the transistors of the plurality of first storage units and the first dummy unit arranged in the first region are arranged in sequence along the first direction, and the first electrode of one of any two adjacent transistors and the second electrode of the other share one electrode; the transistors of the plurality of first storage units and the first dummy unit arranged in the second region are arranged in sequence along the first direction, and the first electrode of one of any two adjacent transistors and the second electrode of the other share one electrode; The number of transistors in which the second dummy unit and any one of the plurality of second storage units are arranged in the first region and the second region is equal; the transistors in which the plurality of second storage units and the second dummy unit are arranged in the first region are arranged in sequence, and a first electrode of one of any two adjacent transistors and a second electrode of the other transistor share an electrode; the transistors in which the plurality of second storage units and the second dummy unit are arranged in the second region are arranged in sequence, and a first electrode of one of any two adjacent transistors and a second electrode of the other transistor share an electrode.

6. The static random access memory device of claim 5, wherein, any two adjacent ones of the plurality of first storage units and the first dummy unit include a first P-type transistor and a second P-type transistor, a first electrode of one of the first P-type transistor and the second P-type transistor and a second electrode of the other transistor share an electrode, and the first P-type transistor and the second P-type transistor are the two closest transistors of any two adjacent ones of the plurality of first storage units and the first dummy unit arranged in the N-well; any two adjacent ones of the second dummy unit and the plurality of second storage units include a third P-type transistor and a fourth P-type transistor, a first electrode of one of the third P-type transistor and the fourth P-type transistor and a second electrode of the other transistor share an electrode, and the third P-type transistor and the fourth P-type transistor are the two closest transistors of any two adjacent ones of the plurality of first storage units and the first dummy unit arranged in the N-well.

7. The static random access memory device of any one of claims 4 to 6, wherein, The static random access memory device further comprises a region selection line, the gating unit comprises a first gating sub-unit and a second gating sub-unit arranged along the first direction, the first gating sub-unit comprises a first gating transistor, the second gating sub-unit comprises a second gating transistor, the local bit line comprises a first local bit line and a second local bit line, and the global bit line comprises a first global bit line and a second global bit line; a gate of the first gating transistor is connected to the region selection line, a first electrode of the first gating transistor is connected to the first local bit line, and a second electrode of the first gating transistor is connected to the first global bit line; a gate of the second gating transistor is connected to the region selection line, a first electrode of the second gating transistor is connected to the second global bit line, and a second electrode of the second gating transistor is connected to the second local bit line.

8. The static random access memory device of claim 7, wherein, the first gating sub-unit further comprises a plurality of first dummy transistors, the plurality of first dummy transistors are arranged in the first region and the second region, the first gating transistor is arranged in the first region, and the number of the first dummy transistors arranged in the first region and the number of the first gating transistor arranged in the first region are equal to the number of the first dummy transistors arranged in the second region. The second gating subunit further comprises a plurality of second dummy transistors, the plurality of second dummy transistors are arranged in the first region and the second region, the second gating transistor is arranged in the second region, and the number of the second dummy transistors arranged in the second region and the number of the second gating transistor arranged in the second region are equal to the number of the second dummy transistors arranged in the first region.

9. The static random access memory device of claim 8, wherein, The number of the first dummy transistors arranged in the second region is equal to the number of the transistors of the first storage unit arranged in the second region. The number of the second dummy transistors arranged in the first region is equal to the number of the transistors of the second storage unit arranged in the first region.

10. The static random access memory device of claim 8 or 9, wherein, In the first region or the second region, one first dummy transistor of the first gating subunit is arranged adjacent to one transistor of the first dummy unit, and a first electrode of the one transistor of the first dummy unit and a second electrode of the one first dummy transistor share one electrode. In the first region or the second region, one second dummy transistor of the second gating subunit is arranged adjacent to one transistor of the second dummy unit, and a first electrode of the one transistor of the second dummy unit and a second electrode of the one second dummy transistor share one electrode.

11. The static random access memory device of any one of claims 8-10, wherein, In the first region, a first electrode of the first gating transistor and a second electrode of the transistor of the first dummy unit adjacent to the first gating transistor share one electrode, and a second electrode of the first gating transistor and a first electrode of the first dummy transistor adjacent to the first gating transistor; In the second region, a first electrode of the second gating transistor and a second electrode of the first dummy transistor adjacent to the second gating transistor share one electrode, and a second electrode of the second gating transistor and a second electrode of the second dummy transistor adjacent to the second gating transistor share one electrode.

12. The static random access memory device of claim 7, wherein, The first gating subunit further comprises a third gating transistor, and the second gating subunit further comprises a fourth gating transistor; A gate electrode of the third gating transistor is connected to the region selection line, a first electrode of the third gating transistor is connected to the first local bit line, and a second electrode of the third gating transistor is connected to the first global bit line; A gate electrode of the fourth gating transistor is connected to the region selection line, a first electrode of the fourth gating transistor is connected to the second local bit line, and a second electrode of the fourth gating transistor is connected to the second global bit line.

13. The static random access memory device of any one of claims 7 to 12, wherein, The region selection line is arranged in the second direction to extend part of the gate electrodes of the first gating transistor and the gate electrodes of the second gating transistor.

14. An electronic device, comprising: The static random access memory device of any one of claims 1-13 is arranged on a circuit board.

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