Static random access memory and electronic device

Abstract

A static random access memory (SRAM) (300) and an electronic device, which solve the problem of how to balance the power consumption and area of a SRAM. The SRAM (300) comprises a global bit line, a local bit line, a gating unit (500), and a first memory region (310) and a second memory region (320) which are arranged in a first direction, wherein the gating unit (500) is arranged between the first memory region (310) and the second memory region (320); the first memory region (310) comprises a plurality of first memory cells (400a) and a first dummy cell (311) which is arranged adjacent to the gating unit (500), the second memory region (320) comprises a plurality of second memory cells (400b) and a second dummy cell (312) which is arranged adjacent to the gating unit (500), and the local bit line is connected to the plurality of first memory cells (400a) or the plurality of second memory cells (400b); and the gating unit (500) is connected to the global bit line and the local bit line. The SRAM (300) can be used as a cache in a circuit system.

Description

Static random access memory devices and electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202411292944.0, filed on September 13, 2024, entitled "Static Random Access Memory Device and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and in particular to a static random access memory device and electronic device. Background Technology

[0003] With the rapid development of information technology, people have increasingly higher requirements for low-power chips. Low-power chips not only meet the requirements of green development, but also extend the battery life of portable products. As an important component of most chips, the power consumption of static random access memory (SRAM) directly determines the overall power consumption of the chip.

[0004] Especially with the rapid development of artificial intelligence technology today, in scenarios where artificial intelligence is applied, a large amount of weight data stored in SRAM needs to be read frequently for calculation, making it particularly important to reduce the power consumption of SRAM reads.

[0005] Meanwhile, chip area is also a crucial indicator affecting product competitiveness. SRAM occupies a significant portion of the chip's area. Therefore, to reduce SRAM area, the fixed structural characteristics of SRAM's memory cells can be utilized. By cleverly designing the circuitry and layout of these cells and employing unique design rules different from conventional logic circuits, a dense arrangement can be achieved, thereby reducing the SRAM area.

[0006] However, in some designs, there is a conflict between reducing SRAM power consumption and reducing SRAM area. Therefore, how to balance SRAM power consumption and area is a technical problem that urgently needs to be solved. Summary of the Invention

[0007] This application provides a static random access memory device and electronic device to solve the problem of balancing the power consumption and area of ​​SRAM.

[0008] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0009] In a first aspect, embodiments of this application provide a static random access memory (SRAM) device, which includes a first memory region, a second memory region, a gating unit, a local bit line, and a global bit line. The first memory region includes a plurality of first memory cells and a first virtual cell arranged along a first direction; the second memory region includes a second virtual cell and a plurality of second memory cells arranged along the first direction, where the first direction is the direction in which the first and second memory regions are arranged; the gating unit is disposed between the first virtual cells and the second virtual cells; the local bit line is connected to the plurality of first memory cells or the plurality of second memory cells; the global bit line is connected to the local bit line through the gating unit; wherein, the first virtual cell and the first memory cell each include a plurality of transistors, and the number of transistors included is equal, and the arrangement of the plurality of transistors in each of the plurality of first memory cells and the first virtual cells changes periodically according to the arrangement order of the plurality of first memory cells and the first virtual cells; the second virtual cell and the second memory cell each include a plurality of transistors, and the number of transistors included is equal, and the arrangement of the plurality of transistors in each of the second virtual cell and the plurality of second memory cells changes periodically according to the arrangement order of the second virtual cell and the plurality of second memory cells.

[0010] Since the selection transistor of the selection unit can selectively turn on the connection between the global bit line and the local bit line, when reading or writing the first memory cell in the first memory area or the second memory cell in the second memory area, only the local bit line corresponding to one of the multiple memory areas is turned on, reducing the number of memory cells connected by the local bit line and reducing the load on the bit line. Therefore, the power consumption of the static random access memory device can be reduced.

[0011] Furthermore, since the arrangement of transistors in each of the multiple first memory cells and first virtual cells changes periodically according to their arrangement order, the first virtual cells can adopt the same design rules as the first memory cells, i.e., the same design rules used by the memory cells; similarly, the second virtual cells can also adopt the same design rules as the second memory cells. Since the gating unit is arranged adjacent to the first and second virtual cells, and the first and second virtual cells do not perform storage functions, there are no restrictions on the connection relationships between the transistors in the first and second virtual cells. Therefore, the first and second virtual cells, which adopt a tight arrangement design rule, can be used to ensure that the gating unit meets this tight arrangement design rule, and simultaneously connect the gating unit to local bit lines and global bit lines. Thus, the first memory area, the second memory area, and the gating unit can all adopt a tight arrangement rule. In other words, the bit line load of the static random access memory device can be reduced while avoiding the use of logic circuit design rules, thus avoiding the introduction of buffer modules between devices and memory cells designed according to logic circuit design rules, which would increase the area. Therefore, it is possible to reduce the power consumption of static random access memory devices while avoiding a significant increase in their area.

[0012] In one possible implementation of the first aspect, the connections between the multiple transistors of the first virtual unit are the same as those between the multiple transistors of the second virtual unit. This simplifies the arrangement of the multiple transistors in both the first and second virtual units when using the same design rules.

[0013] In one possible implementation of the first aspect, the gates of the plurality of transistors in the first virtual cell and the gates of the plurality of transistors in the second virtual cell are connected to the same potential, for example, both connected to a low potential, which is a potential lower than the power supply voltage of the static random access memory (SRAM). In this way, the plurality of transistors in the first and second virtual cells can be used only to satisfy design rules and do not function during the operation of the SRAM, thereby reducing design complexity while ensuring the production yield of normal memory cells adjacent to the virtual cells.

[0014] In one possible implementation of the first aspect, the static random access memory (SRAM) device includes an N-well extending in a first direction and a first region and a second region on both sides of the N-well along a second direction perpendicular to the first direction. The number of transistors in the N-well, the first region, and the second region of the first memory cell is equal to the number of transistors in the N-well, the first region, and the second region of the first virtual cell, respectively. The number of transistors in the N-well, the first region, and the second region of the second memory cell is equal to the number of transistors in the N-well, the first region, and the second region of the second virtual cell, respectively. Thus, the transistors in the N-well, the first region, and the second region of the first virtual cell can all adopt the same design rules as the transistors in the corresponding regions of the first memory cell, and the transistors in the N-well, the first region, and the second region of the second virtual cell can all adopt the same design rules as the transistors in the corresponding regions of the second memory cell. Furthermore, a gating unit is disposed between the first virtual cell and the second virtual cell. Since the first virtual cell and the second virtual cell are not used to implement the storage function, the first virtual cell and the second virtual cell can be flexibly configured so that the gating unit also meets the design rules.

[0015] In one possible implementation of the first aspect, the number of transistors in the first and second regions is equal for each of the plurality of first memory cells and first virtual cells; the transistors in the first region are arranged sequentially along a first direction, and the first electrode of any two adjacent transistors shares a common electrode with the second electrode of the other; the number of transistors in the second region is equal for each of the second virtual cells and the plurality of second memory cells; the transistors in the first region are arranged sequentially along a first direction, and the first electrode of any two adjacent transistors shares a common electrode with the second electrode of the other. Similarly, the number of transistors in the first and second regions is equal for each of the second virtual cells and the plurality of second memory cells; the transistors in the first region are arranged sequentially, and the first electrode of any two adjacent transistors shares a common electrode with the second electrode of the other; the transistors in the second region are arranged sequentially, and the first electrode of any two adjacent transistors shares a common electrode with the second electrode of the other. Thus, adjacent transistors in the first and second regions of the first and first memory cells and the first virtual cells can improve storage density by sharing a common electrode, and adjacent transistors in the first and second regions of the second memory cells and the second virtual cells can also improve storage density by sharing a common electrode.

[0016] In one possible implementation of the first aspect, one of any two adjacent first memory cells and first virtual cells includes a first P-type transistor, and the other includes a second P-type transistor. The first electrode of one of the first P-type transistors and the second P-type transistor shares a common electrode with the second electrode of the other. The first P-type transistor and the second P-type transistor are the two closest transistors disposed in the N-well among any two adjacent first memory cells and first virtual cells. Similarly, one of any two adjacent second virtual cells and multiple second memory cells includes a third P-type transistor, and the other includes a fourth P-type transistor. The first electrode of one of the third P-type transistors and the second P-type transistor shares a common electrode with the second electrode of the other. The third P-type transistor and the fourth P-type transistor are the two closest transistors disposed in the N-well among any two adjacent first memory cells and first virtual cells. Thus, transistors disposed in the N-well can also improve storage density by sharing a common electrode.

[0017] In one possible implementation of the first aspect, the static random access memory (SRAM) device further includes a region selection line. The gating unit includes a first gating sub-unit and a second gating sub-unit arranged along a first direction. The first gating sub-unit includes a first gating transistor, and the second gating sub-unit includes a second gating transistor. Local bit lines include a first local bit line and a second local bit line, and global bit lines include a first global bit line and a second global bit line. The gate of the first gating transistor is connected to the region selection line, the first electrode of the first gating transistor is connected to the first local bit line, and the second electrode of the first gating transistor is connected to the first global bit line. The gate of the second gating transistor is connected to the region selection line, the first electrode of the second gating transistor is connected to the second global bit line, and the second electrode of the second gating transistor is connected to the second local bit line. Thus, the first gating transistor and the second gating transistor are respectively disposed in the first gating sub-unit and the second gating sub-unit arranged along the first direction, which reduces mutual interference generated when the first gating transistor and the second gating transistor are disposed, and facilitates the first gating transistor and the second gating transistor conforming to design rules. Furthermore, the first gating transistor and the second gating transistor are simultaneously controlled by the region selection line, thus allowing selection of a specific memory region via the region selection line.

[0018] In one possible implementation of the first aspect, the first gating subunit further includes a plurality of first virtual transistors, which are distributed in a first region and a second region. A first gating transistor is disposed in the first region, and the sum of the number of first virtual transistors in the first region and the number of first gating transistors disposed in the first region is equal to the number of first virtual transistors disposed in the second region. The second gating subunit further includes a plurality of second virtual transistors, which are distributed in the first region and the second region. A second gating transistor is disposed in the second region, and the sum of the number of second virtual transistors in the second region and the number of second gating transistors disposed in the second region is equal to the number of second virtual transistors disposed in the first region. Thus, the number of transistors in the first gating subunit and the number of transistors in the second gating subunit are the same, allowing these transistors to be symmetrically arranged about the N-well, facilitating a compact arrangement design.

[0019] In one possible implementation of the first aspect, the number of first virtual transistors disposed in the second region is equal to the number of transistors disposed in the second region of the first memory cell; the number of second virtual transistors disposed in the first region is equal to the number of transistors disposed in the first region of the second memory cell. Since the number of transistors disposed in the second region of the first virtual cell is equal to the number of transistors disposed in the second region of the first memory cell, the number of first virtual transistors in the second region is also equal to the number of transistors disposed in the second region of the first memory cell. Therefore, the number of transistors disposed in the second region of the first gating sub-unit is equal to the number of transistors disposed in the second region of the first memory cell. Furthermore, the sum of the number of first virtual transistors disposed in the first region and the number of first gating transistors disposed in the first region is equal to the number of first virtual transistors disposed in the second region. Therefore, the number of transistors disposed in the first region of the first gating sub-unit is equal to the number of transistors disposed in the second region of the first memory cell. Similarly, the number of transistors disposed in the first and second regions of the second gating sub-unit is equal to the number of transistors disposed in the first and second regions of the second memory cell, respectively. Thus, the transistors in the first gating sub-unit located in the first and second regions can be arranged in the same way as the transistors in the first and second regions of the first storage unit, and the transistors in the second gating sub-unit located in the first and second regions can be arranged in the same way as the transistors in the second storage unit located in the first and second regions, thereby facilitating the use of a compact arrangement design rule for the first and second gating sub-units.

[0020] In one possible implementation of the first aspect, in the first or second region, a first virtual transistor of the first gating sub-unit is disposed adjacent to a transistor of the first virtual unit, and the first electrode of the transistor of the first virtual unit shares a common electrode with the second electrode of the first virtual transistor; in the first or second region, a second virtual transistor of the second gating sub-unit is disposed adjacent to a transistor of the second virtual unit, and the first electrode of the transistor of the second virtual unit shares a common electrode with the second electrode of the second virtual transistor. Thus, by sharing a common electrode with adjacent transistors, the first virtual transistor facilitates a compact arrangement design between the first gating sub-unit and the first virtual unit, and similarly, by sharing a common electrode with adjacent transistors, the second virtual transistor facilitates a compact arrangement design between the second gating sub-unit and the second virtual unit.

[0021] In one possible implementation of the first aspect, in the first region, the first terminal of the first gate transistor and the second terminal of the transistor of the first virtual cell adjacent to the first gate transistor share a common terminal, and the second terminal of the first gate transistor and the first terminal of the first virtual transistor adjacent to the first gate transistor also share a common terminal; in the second region, the first terminal of the second gate transistor and the second terminal of the first virtual transistor adjacent to the second gate transistor share a common terminal, and the second terminal of the second gate transistor and the second virtual transistor adjacent to the second gate transistor also share a common terminal. Thus, by sharing a common terminal with adjacent transistors, the first gate transistor facilitates a design rule for a close arrangement between the first gate sub-unit and the first virtual cell, and similarly, by sharing a common terminal with adjacent transistors, the second gate transistor facilitates a design rule for a close arrangement between the second gate sub-unit and the second virtual cell.

[0022] In one possible implementation of the first aspect, the first gating subunit further includes a third gating transistor, and the second gating subunit further includes a fourth gating transistor; the gate connection region selection line of the third gating subunit has a first terminal of the third gating transistor connected to a first local bit line, and a second terminal of the third gating transistor connected to a first global bit line; the gate connection region selection line of the fourth gating transistor has a first terminal connected to a second local bit line, and a second terminal of the fourth gating transistor connected to a second global bit line. This reduces the impedance between the first global bit line and the first local bit line, further reducing the power consumption of the static random access memory device, and also helps to improve read / write speed.

[0023] In one possible implementation of the first aspect, the portion of the zone select line connecting the gate of the first gate transistor and the gate of the second gate transistor extends along a second direction. This facilitates the arrangement of the zone select line, allowing simultaneous control of the first and second gate transistors to be turned off or on via the zone select line.

[0024] Secondly, this application provides an electronic device including a circuit board and a static random access memory (SRAM) device as described in any one of the first aspects, wherein the SRAM device is disposed on the circuit board. Since the SRAM device used in the electronic device can reduce power consumption while avoiding a significant increase in area, the electronic device can also reduce the power consumption of the SRAM device while minimizing the impact of arranging the SRAM device. Attached Figure Description

[0025] Figure 1 is a framework diagram of an electronic device provided in an embodiment of this application;

[0026] Figure 2 is a schematic diagram of a static random access memory device in the related art;

[0027] Figure 3 is a circuit schematic diagram of a memory cell in the related technology;

[0028] Figure 4 is a schematic diagram of another static random access memory device in the related technology;

[0029] Figure 5 is a schematic diagram of another static random access memory device in the related technology;

[0030] Figure 6 is a circuit diagram of a static random access memory device provided in an embodiment of this application;

[0031] Figure 7 is a layout design diagram of a static random access memory device provided in an embodiment of this application;

[0032] Figure 8 is an architectural diagram of a possible static random access memory device provided in an embodiment of this application. Detailed Implementation

[0033] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by those skilled in the art. The terms "first," "second," "third," and similar words used in this application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of embodiments in this application, unless otherwise stated, "a plurality of" means two or more.

[0034] The directional terms such as “left,” “right,” “up,” and “down” are defined relative to the orientation of the device shown in the accompanying drawings. It should be understood that these directional terms are relative concepts and are used for relative description and clarification. They can change accordingly depending on the orientation of the chip or semiconductor package structure.

[0035] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0036] Please refer to Figure 1, which is a framework diagram of an electronic device 20 provided in an embodiment of this application. The electronic device 20 can be various types of user equipment or terminal devices, such as mobile phones, computers (e.g., tablets, laptops), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners), drones, radar, aerospace equipment, and vehicle-mounted equipment. The electronic device can also be a network device such as a base station. The embodiments of this application do not impose special limitations on the specific form of the electronic device.

[0037] Electronic device 20 may include circuit board 200, bus 205, and system-on-chip (SoC) 210 connected to bus 205. Bus 205 and SoC 210 may be disposed on circuit board 200. SoC 210 may be used to process data, such as processing application data, image data, and caching temporary data. In one embodiment, SoC 210 may include one or more processors 211, such as an application processor (AP) for processing application data and a graphics processing unit (GPU) for processing image data. Processor 211 may include a computing module and a first-level cache (Cache L1) for caching high-speed data, and the computing module and the first-level cache may be disposed on the same die. SoC 210 may also include more caches, such as a second-level cache (Cache L2), a third-level cache (Cache L3), a fourth-level cache (Cache L4), etc. Understandably, one or more of the Level 2 cache (Cache L2), Level 3 cache (Cache L3), and Level 4 cache (Cache L4) can be configured independently of the processor 211. That is, the Level 2 cache (Cache L2), Level 3 cache (Cache L3), and Level 4 cache (Cache L4) can be located outside the processor 211 and interact with the Level 1 cache (Cache L1) via the data bus in the system-on-chip 210. In this case, the bus 205 can be connected to the data bus in the system-on-chip 210 via a data interface (not shown in Figure 1).

[0038] Electronic device 200 may also include a storage device 220 connected to system-on-a-chip 210 via bus 205. Storage device 220 may also be mounted on a circuit board. Storage device 220 may also be a cache; it can be mounted on circuit board 200 via a slot and interact with various levels of cache in system-on-a-chip 210 via bus 205. The storage capacity of storage device 220 is typically larger than that of various levels of cache in system-on-a-chip 210, but its data transfer speed with processor 211 is slower than that of the cache in system-on-a-chip 210.

[0039] This application also provides a static random access storage device, which can be a cache at various levels as shown in FIG1, or a storage device 220.

[0040] Please refer to Figure 2, which is a schematic diagram of a static random access memory (SRAM) device 300 in the related art. The SRAM device 300 includes multiple memory cells 400 and peripheral circuitry. The peripheral circuitry is connected to the memory cells 400 to control the read and write operations of the memory cells 400. For example, please refer to Figure 3, which is a circuit schematic diagram of a memory cell 400 in the related art. A memory cell 400 may include a pair of access transistors TA0 and TA1, a pair of driving transistors TD0 and TD1, and a pair of load transistors TL0 and TL1. The gates of the pair of access transistors TA0 and TA1 are connected to the same word line WL, and the read and write operations of the memory cell 400 can be controlled through the word line WL. The pair of access transistors TA0 and TA1 and the pair of driving transistors TD0 and TD1 may be N-type metal-oxide-semiconductor (NMOS) transistors, and the pair of load transistors TL0 and TL1 may be P-type metal-oxide-semiconductor (PMOS) transistors.

[0041] In the static random access memory (SRAM) device 300, multiple memory cells 400 can be arranged in an array. Each row of memory cells 400 is connected to a word line, for example, the first row of memory cells 400 is connected to word line WL1, and the 256th row of memory cells 400 is connected to word line WL256. Each column of memory cells 400 is connected to the same pair of bit lines BL and BLB. Understandably, when performing read and write operations on memory cells 400, a memory cell 400 can be selected via the word line and the pair of bit lines BL and BLB, thereby performing read and write operations on that memory cell 400. To increase the storage density of the SRAM device 300, a large number of memory cells 400 are connected to the pair of bit lines BL and BLB. For example, in Figure 2, the pair of bit lines BL and BLB connects 256 memory cells 400. The more memory cells 400 connected to a bit line, the greater the load on the bit line. During the reading and writing process of the static random access memory (SRAM) 300, the pair of bit lines BL and BLB connected to the selected memory cell 400 need to be charged and discharged. During the read and write process, the greater the load on the bit lines, the greater the dynamic power consumption caused by charging and discharging the bit lines. Furthermore, the power consumed by charging and discharging the bit lines can account for more than half of the total power consumption of the SRAM 300; therefore, the greater the load on the bit lines, the greater the total power consumption of the SRAM 300.

[0042] Please refer to Figure 4 and Figure 3. Figure 4 is a schematic diagram of another static random access memory (SRAM) device 300 in the related art. The difference between the SRAM device 300 in Figure 4 and the SRAM device 300 in Figure 2 is that local peripheral circuits are inserted in the column direction of the SRAM device 300. In Figure 4, the SRAM device 300 includes local peripheral circuits and global peripheral circuits. The local peripheral circuits are externally connected to the SRAM device 300 through the global peripheral circuits. The local peripheral circuits divide the SRAM device 300 into multiple storage areas in the column direction. For example, in Figure 4, the SRAM device 300 is divided into storage areas 1 to 4 by two local peripheral circuits. Thus, the bit lines of each column of storage cells 400 are also divided into bit lines BL1 to BL4. When reading data, the local peripheral circuits can be used to select the bit lines corresponding to the storage areas on both sides for read and write operations. As a result, the number of memory cells 400 connected to any of the bit lines BL1 to BL4 is reduced by a factor of two, thereby reducing the load on the bit lines and thus reducing the power consumption of the static random access memory device 300.

[0043] However, inserting local peripheral circuitry along the column direction of the static random access memory (SRAM) 300 increases its area. Furthermore, the local peripheral circuitry requires conventional logic circuit design rules, while the memory cells of the SRAM 300 are arranged in a dense configuration. Circuits constructed using these two design rules cannot be directly adjacent; otherwise, problems may occur during fabrication and in the final product. Therefore, a buffer module needs to be designed between the local peripheral circuitry and the memory cells. The introduction of the buffer module and the local peripheral circuitry increases the area of ​​the SRAM 300 by more than 45%, which is detrimental to improving its storage density.

[0044] Please refer to Figure 5 in conjunction with Figures 3 and 4. Figure 5 is a schematic diagram of another static random access memory (SRAM) device 300 in the related art. The SRAM device 300 in Figure 5 differs from the SRAM device 300 in Figure 3 in that its bit lines BL and BLB are divided into multiple local bit lines LBL and LBLB (only one segment is shown in Figure 5). Each local bit line LBL is connected to the global bit line GBL via a gating transistor TS, and each local bit line LBLB is connected to the global bit line GBLB via a gating transistor TS. The gating transistor TS is controlled by the global word line GWL to be turned on or off. Thus, the memory area can be divided into multiple memory areas, each of which can be smaller. During read / write operations, the global word line GWL controls the gating transistor TS corresponding to the memory area to be read / written to be turned on. Simultaneously, one of the multiple local word lines LWL in that memory area is selected to select a memory cell, thereby enabling read / write operations on the memory cell. Therefore, since the bit line is divided into multiple local bit lines LBL and LBLB, while the number of memory cells 400 on the bit line remains unchanged, the number of memory cells 400 connected by the local bit lines LBL and LBLB can be reduced, that is, the load of the local bit lines LBL and LBLB is reduced, so the power consumption of the static random access memory device 300 can be reduced.

[0045] Similarly, the gate transistor TS also needs to be constructed using conventional logic circuit design rules, while the memory cells of the static random access memory (SRAM) device 300 adopt a densely arranged design rule. Circuits constructed using these two design rules cannot be directly adjacent. Therefore, a buffer module needs to be designed between the gate transistor TS and the memory cells. Introducing a buffer module will also result in a significant area overhead. For example, when the SRAM device 300 in Figure 2 is divided into four memory areas, the area of ​​the SRAM device 300 will increase by more than 25%.

[0046] Please refer to Figures 6 and 7. Figure 6 is a circuit schematic diagram of a static random access memory (SRAM) device 300 provided in an embodiment of this application, and Figure 7 is a layout design diagram of a SRAM device 300 provided in an embodiment of this application. The SRAM device 300 may include a first memory area 310, a second memory area 320, a gating unit 500, a global bit line (GB), and a local bit line (LB). The first memory area 310 and the second memory area 320 may include arrayed memory cells 400. For ease of explanation, the direction in which the first memory area 310 and the second memory area 320 are arranged is defined as the first direction X, and the second direction Y intersects the first direction X; for example, the second direction Y is perpendicular to the first direction X.

[0047] The first storage region 310 includes a first dummy cell 311 and a plurality of first storage cells 400a, which are arranged sequentially along a first direction X. The first dummy cell 311 is disposed on the side of the plurality of first storage cells 400a near the second storage region 320. The first dummy cell 311 may include a plurality of transistors T1 to T6, and the first storage cells 400a may also include a plurality of transistors T. Furthermore, the number of transistors included in the first dummy cell 311 and the first storage cells 400a is equal; for example, both the first dummy cell 311 and the first storage cells 400a include 6 transistors. The first storage cell 400a may be the storage cell shown in FIG3, but this application is not limited to this.

[0048] Furthermore, according to the arrangement order of the plurality of first storage cells 400a and first virtual cells 311, the arrangement of the plurality of transistors in each of the plurality of first storage cells 400a and first virtual cells 311 changes periodically. The period of this arrangement change is not limited; for example, it can be one cell, two cells, three cells, etc., where a cell refers to one first storage cell 400a or one first virtual cell 311. Since the plurality of first storage cells 400a and first virtual cells 311 are arranged sequentially along the first direction X, the first virtual cell 311 is arranged after the plurality of first storage cells 400a along the first direction X. It can be understood that since each of the first storage cells 400a and first virtual cells 311 includes a plurality of transistors, there is a certain positional relationship between the plurality of transistors in the completed static random access memory device 300; this positional relationship is the arrangement of the plurality of transistors. For example, referring to Figure 7, for a first virtual unit 311 including six transistors T1 to T6, the six transistors T1 to T6 can be arranged in four rows in the second direction Y, with each row arranged along the first direction X. The first and fourth rows each include two transistors, and the second and third rows each include one transistor. The transistors in the second row and the transistors in the third row are staggered in the second direction Y. For example, transistors T2 and T1 are arranged sequentially along the first direction X in the first row, transistors T3 and T4 are arranged sequentially along the first direction X in the fourth row, transistor T5 is arranged in the second row, and transistor T6 is arranged in the third row. Furthermore, transistors T5 and T6 are staggered in the second direction Y, transistors T2, T5, and T3 are aligned in the second direction Y, and transistors T1, T6, and T4 are aligned in the second direction Y.

[0049] The second storage area 320 includes a second virtual unit 312 and a plurality of second storage units 400b, which are also arranged sequentially along the first direction X. Understandably, the second virtual unit 312 is disposed on the side of the plurality of second storage units 400b closest to the first storage area 310. Thus, the first virtual unit 311 is disposed between the plurality of first storage units 400a and the plurality of second storage units 400b, and the second virtual unit 312 is also disposed between the plurality of first storage units 400a and the plurality of second storage units 400b. The second virtual unit 312 may include a plurality of transistors T15 to T20, and the second storage unit 400b may also include a plurality of transistors T. Furthermore, the number of transistors included in the second virtual unit 312 and the second storage unit 400b may be equal; for example, both the second virtual unit 312 and the second storage unit 400b may include 6 transistors. The second storage unit 400b may also be a storage unit as shown in FIG3, but this application does not limit it to this.

[0050] Similarly, according to the arrangement order of the second virtual unit 312 and the plurality of second storage units 400b, the arrangement of the multiple transistors in each of the second virtual unit 312 and the plurality of second storage units 400b changes periodically. The period of this arrangement change is not limited; for example, it can be 1 unit, 2 units, 3 units, etc. Since the second virtual unit 312 and the plurality of second storage units 400b are arranged sequentially along the first direction X, the second virtual unit 312 is arranged before the plurality of second storage units 400b along the first direction X. Understandably, since both the second virtual unit 312 and the second storage unit 400b include multiple transistors, there is a certain positional relationship between the multiple transistors in the completed static random access memory device 300; this positional relationship is the arrangement of the multiple transistors. For example, referring to Figure 7, for a second virtual unit 312 including six transistors T15 to T20, the six transistors T15 to T20 can be arranged in four rows along the second direction Y, with each row arranged along the first direction X. The first and fourth rows each include two transistors, and the second and third rows each include one transistor. The transistors in the second row and the third row are staggered in the second direction Y. For example, transistors T15 and T16 are arranged sequentially along the first direction X in the first row, transistors T18 and T17 are arranged sequentially along the first direction X in the fourth row, transistor T19 is arranged in the second row, and transistor T20 is arranged in the third row. Furthermore, transistors T19, T20, and T15 are staggered in the second direction Y, transistors T15, T20, and T18 are aligned in the second direction Y, and transistors T16, T19, and T17 are aligned in the second direction Y.

[0051] A gating unit 500 is disposed between the first storage area 310 and the second storage area 320, and is adjacent to the first virtual unit 311 and the second virtual unit 312. Thus, the first virtual unit 311, the gating unit 500, and the second virtual unit 312 are arranged sequentially along the first direction X; that is, the first virtual unit 311, the gating unit 500, and the second virtual unit 312 are arranged along a straight line, and the extension direction of this straight line is the first direction X. The gating unit 500 can be used to connect the local bit line LB and the global bit line GB. In other words, the local bit line LB is connected to the global bit line GB through the gating unit 500.

[0052] A local bit line LB can be connected to either a first memory cell 400a or a second memory cell 400b. That is, the first memory region 310 and the second memory region 320 correspond to different local bit lines LB. For example, a local bit line LB can be connected to multiple first memory cells 400a in the first memory region 310 (only one first memory cell 400a is shown in FIG. 6), and a local bit line LB can also be connected to multiple second memory cells 400b in the second memory region 320 (only one second memory cell 400b is shown in FIG. 6). Thus, a memory cell 400 in its corresponding memory region can be selected for read / write operations via the local bit line LB. For example, after selecting both the local bit line LB connected to the first memory cell 400a and the word line WL connected to the first memory cell 400a, read / write operations can be performed on the first memory cell 400a in the first memory region 310.

[0053] The global bit line GB can be connected to the local bit line LB via the gating unit 500. Understandably, the end of the global bit line GB not connected to the gating unit 500 can be connected to external circuitry (not shown in Figure 6). The gating unit 500 can selectively enable the connection between the global bit line GB and the local bit line LB. Thus, when reading from or writing to the memory cell 400, only the local bit line corresponding to one of the multiple memory areas is enabled, thereby reducing the number of memory cells 400 connected to the local bit line, reducing the load on the bit line, and thus reducing the power consumption of the static random access memory device 300.

[0054] Furthermore, since the arrangement of multiple transistors in each of the multiple first memory cells 400a and the first virtual cells 311 changes periodically according to their arrangement order, the first virtual cell 311 can adopt the same design rules as the first memory cell 400a, i.e., the close arrangement design rules adopted by the memory cell 400. Similarly, the second virtual cell 312 can also adopt the same design rules as the second memory cell 400b. Since the gating unit 500 is arranged adjacent to the first virtual cell 311 and the second virtual cell 312, and the first virtual cell 311 and the second virtual cell 312 do not perform storage functions, there are no restrictions on the connection relationships between the multiple transistors in the first virtual cell 311 and the multiple transistors in the second virtual cell 312. Therefore, the first virtual cell 311 and the second virtual cell 312 can be used to ensure that the gating unit 500 meets the close arrangement design rules while simultaneously connecting the local bit line LB and the global bit line GB. Therefore, the first storage area 310, the second storage area 320, and the gating unit 500 can all adopt the design rule of a compact arrangement of storage cells 400. In other words, the bit line load of the static random access memory device 300 can be reduced while avoiding the introduction of different design rules due to the use of logic circuits, and avoiding the introduction of buffer modules between the logic circuits and the storage cells 400. Thus, the static random access memory device 300 can reduce power consumption while avoiding a significant increase in area.

[0055] Understandably, the first storage cell 400a in the first storage region 310 and the second storage cell 400b in the second storage region 320 can be the same. That is, the number of transistors in the first storage cell 400a is the same as the number of transistors in the second storage cell 400b, and the arrangement of the transistors in each of the multiple first storage cells 400a can be the same as the arrangement of the transistors in each of the multiple second storage cells 400b. For example, the transistors in the first storage cell 400a can have two arrangements, and the transistors in the second storage cell 400b can also have two arrangements. The two arrangements of the transistors in the first storage cell 400a are the same as the two arrangements of the transistors in the second storage cell 400b, and the periodic variation pattern of the two arrangements of the transistors in the first storage cell 400a is also the same as the periodic variation pattern of the two arrangements of the transistors in the second storage cell 400b.

[0056] In some embodiments, since the arrangement of the transistors in each of the plurality of first memory cells 400a and the first virtual cell 311 changes periodically, the arrangement of the transistors in the first virtual cell 311 is one of the possible arrangements of the transistors in the first memory cell 400a; similarly, the arrangement of the transistors in the second virtual cell 312 is also one of the possible arrangements of the transistors in the second memory cell 400b. Furthermore, since the first memory cell 400a and the second memory cell 400b can be the same, the arrangement of the transistors in the second virtual cell 312 can be the same as or different from the arrangement of the transistors in the first virtual cell 311; when different, both the arrangement of the transistors in the second virtual cell 312 and the arrangement of the transistors in the first virtual cell 311 are one of the periodically changing arrangements. Understandably, in either case, the connection between the multiple transistors of the first virtual unit 311 can be the same as the connection between the multiple transistors of the second virtual unit 312. Thus, when the first virtual unit 311 and the second virtual unit 312 are set up using the same design rules, it is beneficial to simplify the arrangement of the multiple transistors of the first virtual unit 311 and the second virtual unit 312.

[0057] For example, the gates of the plurality of transistors in the first virtual unit 311 and the gates of the plurality of transistors in the second virtual unit 312 can all be connected to the same potential. Therefore, the plurality of transistors in the first virtual unit 311 and the second virtual unit 312 can be used only to satisfy design rules, thereby reducing design complexity and making it easier for the gating unit 500 to satisfy design rules.

[0058] For example, in the first virtual unit 311, the gates of transistors T1 to T6 can all be connected to a low potential. For instance, the gates of transistors T5 and T6 are connected to the same low potential line VSS, while the gates of transistors T1 to T4 are connected to another low potential line VSS. Furthermore, the first terminal of transistor T1 is connected to the first terminal of transistor T2 and then to the gate of transistor T2; the second terminal of transistor T1 is connected to the second terminal of transistor T2 and also to the gate of transistor T2. The first terminal of transistor T5 can be connected to the power supply line VDD, and the second terminal of transistor T5 can be left floating. The first terminals of transistors T3, T4, and T6 can be connected to the local bit line LBLB1, and the second terminals of transistors T3, T4, and T6 are interconnected. Understandably, the first terminal refers to either the source or drain of the transistor, and the second terminal refers to the other of the source or drain. Similarly, the second virtual unit 312 can also have the same connection method, which will not be described further in this application.

[0059] In some embodiments, the static random access memory device 300 may further include a zone selection line SWL, which can be used to control the selection unit 500 to be turned on or off.

[0060] For example, the gating unit 500 may include a first gating sub-unit 510 and a second gating sub-unit 520 arranged along the first direction X. The first gating sub-unit 510 may include a first gating transistor T10, and the second gating sub-unit 520 may include a second gating transistor T14. The local bit line LB may include a first local bit line LBL1 and a second local bit line LBLB1, and the global bit line GB may include a first global bit line GBL and a second global bit line GBLB. The first local bit line LBL1 and the second local bit line LBLB1 are connected to the first memory cell 400a in the first memory region 310.

[0061] The gate of the first select transistor T10 can be connected to the region select line SWL. The first terminal of the first select transistor T10 can be connected to the first local bit line LBL1, and the second terminal of the first select transistor T10 can be connected to the first global bit line GBL. The gate of the second select transistor T14 can be connected to the region select line SWL. The first terminal of the second select transistor T14 can be connected to the second local bit line LBLB1, and the second terminal of the second select transistor T14 can be connected to the second global bit line GBLB (as shown in Figures 6 and 7).

[0062] Understandably, the local bit line LB may also include a third local bit line LBL2 and a fourth local bit line LBLB2. The third local bit line LBL2 and the fourth local bit line LBLB2 can be connected to the first global bit line GBL and the second global bit line GBLB through additional gating units 500. The additional gating units 500 refer to gating units 500 other than those connected to the first local bit line LBL1 and the second local bit line LBLB1.

[0063] Referring to Figure 7 and in conjunction with Figure 6, the static random access memory (SRAM) device 300 further includes an N-well NW extending in the first direction X, and a first region A1 and a second region A2 on both sides of the N-well NW along the second direction Y. It is understood that the transistors in the memory cell 400 may include P-type transistors, which may be disposed in the N-well NW. Therefore, the first virtual cell 311 and the second virtual cell 312 may also include transistors disposed in the N-well NW. Furthermore, the first memory cell 400a, the first virtual cell 311, the gating unit 500, the second virtual cell 312, and the second memory cell 400b are arranged in the first direction X, meaning that each of these components may include transistors disposed in the first region A1 and the second region A2.

[0064] In some embodiments, the number of transistors in the first memory cell 400a located in the N-well NW, the first region A1, and the second region A2 is equal to the number of transistors in the first virtual cell 311 located in the N-well NW, the first region A1, and the second region A2. That is, the number of transistors in the first memory cell 400a located in the N-well NW is equal to the number of transistors in the first virtual cell 311 located in the N-well NW; the number of transistors in the first memory cell 400a located in the first region A1 is equal to the number of transistors in the first virtual cell 311 located in the first region A1; and the number of transistors in the first memory cell 400a located in the second region A2 is equal to the number of transistors in the first virtual cell 311 located in the N-well NW, the first region A1, and the second region A2 can have the same arrangement pattern as the transistors in the first memory cell 400a located in the N-well NW, the first region A1, and the second region A2, making it easier for the first virtual cell 311 to meet the design rules of the first memory cell 400a.

[0065] The number of transistors in the second memory cell 400b located in the N-well NW, the first region A1, and the second region A2 is equal to the number of transistors in the second virtual cell 312 located in the N-well NW, the first region A1, and the second region A2, respectively. This makes it easier for the second virtual cell 312 to meet the design rules of the second memory cell 400b.

[0066] For example, the number of transistors disposed in the first region A1 and the second region A2 is equal for any of the plurality of first memory cells 400a and first virtual cells 311. That is, the number of transistors disposed in the first memory cells 400a in the first region A1 and the second region A2 is equal, and the number of transistors disposed in the first virtual cells 311 in the first region A1 and the second region A2 is equal. For example, the number of transistors disposed in the first virtual cells 311 in the first region A1 and the second region A2 is two, and the transistors disposed in the first region A1 or the second region A2 can be arranged along the first direction X. In this way, the transistors in the first region A1 and the second region A2 can be symmetrically arranged about the N-well NW, thereby facilitating the implementation of a compact arrangement design rule.

[0067] Multiple first memory cells 400a and first virtual cells 311 are disposed in the transistors of the first region A1, arranged sequentially along the first direction X, and the first electrode of any two adjacent transistors shares a common electrode with the second electrode of the other. Similarly, multiple first memory cells 400a and first virtual cells 311 are disposed in the transistors of the second region A2, arranged sequentially along the first direction, and the first electrode of any two adjacent transistors shares a common electrode with the second electrode of the other. Thus, the transistors of the multiple first memory cells 400a and first virtual cells 311 disposed in the first region A1 and the second region A2 can be densely arranged, thereby allowing for a compact design of the first virtual cells 311.

[0068] Similarly, the number of transistors in the second virtual cell 312 and any of the plurality of second memory cells 400b located in the first region A1 and the second region A2 are equal. The transistors in the plurality of second memory cells 400b and the second virtual cell 312 located in the first region A1 are arranged sequentially, and the first electrode of any two adjacent transistors shares a common electrode with the second electrode of the other; similarly, the transistors in the plurality of second memory cells 400b and the second virtual cell 312 located in the second region A2 are arranged sequentially, and the first electrode of any two adjacent transistors shares a common electrode with the second electrode of the other. Thus, the transistors in the plurality of second memory cells 400b and the second virtual cell 312 located in the first region A1 and the second region A2 can be densely arranged, thereby allowing for a compact design of the second virtual cell 312.

[0069] As previously mentioned, the plurality of first memory cells 400a and first virtual cells 311 may include transistors disposed in the N-well NW. Understandably, the transistors disposed in the N-well NW may be P-type transistors.

[0070] For example, any two adjacent first memory cells 400a and first virtual cells 311 respectively include a first P-type transistor E1 and a second P-type transistor E2. The first P-type transistor E1 and the second P-type transistor E2 are the two closest transistors disposed in the N-well among any two adjacent first memory cells 400a and first virtual cells 311. That is, the first P-type transistor E1 is disposed in one of the two adjacent first memory cells 400a and first virtual cells 311, and the second P-type transistor E2 is disposed in the other. Furthermore, the first electrode of one of the first P-type transistors E1 and the second P-type transistor E2 can share a common electrode with the second electrode of the other. Understandably, in this case, the first P-type transistor and the second P-type transistor are arranged along the first direction X. Thus, the first P-type transistors E1 and E2 disposed in the N-well can achieve a closely spaced design.

[0071] Similarly, any two adjacent units in the second virtual cell 312 and the plurality of second memory cells 400b respectively include a third P-type transistor E3 and a fourth P-type transistor E4. The third P-type transistor E3 and the fourth P-type transistor E4 are the two closest transistors disposed in the N-well among any two adjacent units in the second virtual cell 312 and the plurality of second memory cells 400b. The first electrode of one of the third P-type transistors E3 and the second electrode of the other share a common electrode. Thus, the third P-type transistor E3 and the fourth P-type transistor E4 disposed in the N-well can achieve a closely spaced design.

[0072] In some embodiments, when the gating unit 500 includes a first gating subunit 510 and a second gating subunit 520, the first gating subunit 510 may further include a plurality of first virtual transistors, which are respectively disposed in a first region A1 and a second region A2. For example, first virtual transistors T7 and T8 are disposed in the second region A2, and first virtual transistor T9 is disposed in the first region A1. First gating transistor T10 may be disposed in the first region A1, so that the sum of the number of first virtual transistors disposed in the first region A1 and the number of first gating transistors T10 disposed in the first region A1 is equal to the number of first virtual transistors disposed in the second region A2. In this way, the number of transistors disposed in the first gating subunit 510 in the first region A1 and the second region A2 is the same, so that these transistors can be symmetrically arranged about the N-well NW, which facilitates the implementation of a compact arrangement design rule.

[0073] Similarly, the second gating subunit 520 also includes a plurality of second virtual transistors, which are disposed in the first region A1 and the second region A2. For example, second virtual transistors T11 and T12 are disposed in the first region A1, and second virtual transistor T13 is disposed in the second region A2. Second gating transistor T14 can be disposed in the second region A2, so that the sum of the number of second virtual transistors disposed in the second region A2 and the number of second gating transistors T14 disposed in the second region A2 is equal to the number of second virtual transistors disposed in the first region A1.

[0074] When the number of first virtual transistors is equal to the number of second virtual transistors, and the number of first gating transistors is equal to the number of second gating transistors, the connection between the first virtual transistor and the first gating transistor can be the same as the connection between the second virtual transistor and the second gating transistor.

[0075] For example, please refer to Figure 6. The number of first virtual transistors is 3, which are first virtual transistors T7 to T9; the number of second virtual transistors is 3, which are second virtual transistors T11 to T13; the number of first gating transistors and the number of second gating transistors are both 1, which are the number of first gating transistors T10 and the number of second gating transistors T14, respectively.

[0076] The source, drain, and gate of the first virtual transistor T9 are interconnected and then connected to the source or drain of the first gating transistor T10. The first virtual transistors T7 and T8 are not directly connected to the first gating transistor T10. The source, drain, and gate of the first virtual transistor T7 are interconnected and then connected to the gate of the first virtual transistor T8. The gate of the first virtual transistor T8 is simultaneously connected to either its source or drain and then connected to the low-potential line VSS. Similarly, the source, drain, and gate of the second virtual transistor T13 are interconnected and then connected to the source or drain of the second gating transistor T14. The second virtual transistors T11 and T12 are not directly connected to the second gating transistor T14. The source, drain, and gate of the second virtual transistor T11 are interconnected and then connected to the gate of the second virtual transistor T12. The gate of the second virtual transistor T12 is connected to either its source or drain and then connected to the low-potential line VSS. Thus, the layout designs of the first gating subunit 510 and the second gating subunit 520 can be identical, which simplifies the layout design. Understandably, to clearly describe the arrangement of each transistor, only the connections of some transistors are shown in the layout design of Figure 7; for example, only the connection between the first gating transistor T10 and the second gating transistor T14 is shown. Similarly, Figure 7 only shows the partial bit line LB connected to the first memory cell 400a in the first memory region 310, and does not show the partial bit line LB connected to the second memory cell 400b in the second memory region 320.

[0077] For example, the sum of the number of the first virtual transistors T7 to T9 and the first gating transistor T10 is less than the number of transistors in the first memory cell 400a. That is, when the first gating sub-unit 510 includes only the first virtual transistors T7 to T9 and the first gating transistor T10, the number of transistors in the first gating sub-unit 510 is less than the number of transistors in the first memory cell 400a.

[0078] Similarly, the sum of the number of the second virtual transistors T11-T13 and the second gating transistor T14 is less than the number of transistors in the second memory cell 400b. That is, when the second gating sub-unit 520 only includes the second virtual transistors T11-T13 and the second gating transistor T14, the number of transistors in the second gating sub-unit 520 is less than the number of transistors in the second memory cell 400b. Thus, during layout design, conflicting transistors in the first gating sub-unit 510 can be removed, improving layout design flexibility.

[0079] For example, the number of first virtual transistors disposed in the second region A2 can be equal to the number of transistors disposed in the first memory cell 400a in the second region A2. Thus, when the number of transistors disposed in either the multiple first memory cells 400a and the first virtual cell 311 in the first region A1 and the second region A2 is equal, the number of transistors (first virtual transistors or first gating transistors) disposed in the first gating sub-unit 510 in the first region A1 is equal to the number of transistors disposed in either the first memory cell 400a or the first virtual cell 311 in the second region A2. Therefore, the same design rules as for the first memory cell 400a can be used to dispose of the transistors of the first gating sub-unit 510 in the first region A1 and the second region A2.

[0080] Similarly, the number of second virtual transistors disposed in the first region A1 can also be equal to the number of transistors disposed in the second memory cell 400b in the first region A1.

[0081] For example, in the first region A1, the transistor adjacent to the first gate transistor T10 in the first direction X shares a common electrode with the first gate transistor T10. This transistor can be a transistor of the first virtual unit 311 or a first virtual transistor. For example, the first electrode of the first gate transistor T10 and the second electrode of a transistor of the first virtual unit 311 adjacent to the first gate transistor T10 share a common electrode, and the second electrode of the first gate transistor T10 and the first electrode of the first virtual transistor adjacent to the first gate transistor T10 share a common electrode.

[0082] Similarly, in the second region A2, the transistor adjacent to the second gate transistor T14 in the first direction X shares a terminal with the second gate transistor T14. This transistor can be a transistor of the second virtual unit 312 or a second virtual transistor. For example, the first terminal of the second gate transistor T14 and the second terminal of the second virtual transistor adjacent to the second gate transistor T14 share a terminal, and the second terminal of the second gate transistor T14 and the second terminal of the second virtual transistor adjacent to the second gate transistor T14 share a terminal.

[0083] For example, in the first region A1 or the second region A2, a first virtual transistor of the first gating subunit 510 is arranged adjacent to a transistor T of the first virtual unit 311, and the first pole of the transistor T of the first virtual unit and the second pole of the first virtual transistor can share a pole.

[0084] Similarly, in either the first region A1 or the second region A2, a second virtual transistor of the second gating subunit 520 is disposed adjacent to a transistor of the second virtual unit 312, and the first terminal of the transistor of the second virtual unit 312 shares a common terminal with the second terminal of the second virtual transistor. Thus, the transistor of the first gating subunit 510 can easily adopt the same design rules as the transistor T of the first virtual unit 311, and the transistor of the second gating subunit 520 can easily adopt the same design rules as the transistor T of the second virtual unit 312.

[0085] For example, the first gating subunit 510 may further include a third gating transistor, and the second gating subunit 520 may further include a fourth gating transistor. The gate connection region selection line SWL of the third gating subunit is connected to a first local bit line LBL1, and the second terminal of the third gating transistor is connected to a first global bit line GBL. The gate connection region selection line SWL of the fourth gating transistor is connected to a second local bit line LBLB1, and the second terminal of the fourth gating transistor is connected to a second global bit line GBLB. This reduces the impedance between the first global bit line GBL1 and the first local bit line LBL1, thereby further reducing power consumption and also contributing to improving the read / write speed of the static random access memory device 300.

[0086] As previously described, the first storage cell 400a, the first virtual cell 311, the gating cell 500, the second virtual cell 312, and the second storage cell 400b may each include transistors disposed in the first region A1 and the second region A2. Referring to Figure 7, in the structural arrangement of the static random access memory device 300, the first local bit line LBL1 and the second local bit line LBLB1 may be respectively disposed above the transistors in the first storage cell 400a, the first virtual cell 311, and the gating cell 500 located in the first region A1 and the second region A2. In this case, the first local bit line LBL1 and the second local bit line LBLB1 extend in the first direction X. Furthermore, the dimensions of the first local bit line LBL1 and the second local bit line LBLB1 in the second direction Y can be larger than the dimensions of the source or drain of the transistor in the second direction Y, and the orthogonal projections of the first memory cell 400a, the first virtual cell 311, and the gating cell 500 located in the first region A1 and the second region A2 of at least some of the transistors can be located in the orthogonal projections of the local bit line LBL1 and the local bit line LBLB1, respectively.

[0087] Furthermore, when the first selection transistor T10 and the second selection transistor T14 are respectively located in the first region A1 and the second region A2, the portion of the area selection line SWL connecting the gate of the first selection transistor T10 and the gate of the second selection transistor T14 extends along the second direction Y. This facilitates the connection of the first selection transistor T10 and the second selection transistor T14 to the area selection line SWL.

[0088] Understandably, some transistors forming the first memory cell 400a, the first virtual cell 311, the gating cell 500, the second virtual cell 312, and the second memory cell 400b need to be connected to various signal lines. These transistors can be connected to various signal lines via contact plugs CT. For example, referring to Figure 7, the first gating transistor T10 can be connected to the first local bit line LBL1 via contact plug CT, and the second gating transistor T14 can also be connected to the second local bit line LBLB1 via contact plug CT.

[0089] Understandably, Figures 6 and 7 only show one row or one column of the static random access memory device 300. For a clearer explanation of this application, please refer to Figure 8 in conjunction with Figures 6 and 7. Figure 8 is an architectural diagram of a possible static random access memory device 300 provided by an embodiment of this application.

[0090] In some embodiments, the static random access memory (SRAM) device 300 includes a row decoder, a plurality of local decoders, and control circuitry. The row decoder is connected to and controls the plurality of local decoders. Each memory region can be connected to one local decoder; the memory region can be a first memory region 310 or a second memory region 320. Each local decoder controls not only the word line WL of the memory cells 400 in each memory region but also the region select line SWL of each memory region. The control circuitry can select a column of memory cells 400 via the global bit line GB. Simultaneously, the control circuitry can control the region select line SWL of the row decoder to turn on the first gating transistor T10 and the second gating transistor T14 in that memory region, i.e., connect the global bit line GB to the local bit line LB of that memory region. Understandably, at this time, the region select line SWL of other memory regions does not control the first gating transistor T10 and the second gating transistor T14 corresponding to that memory region to turn on. Therefore, the read and write operations of the memory cell 400 in the memory area can be controlled by the word line WL in the memory area corresponding to the first select transistor T10 and the second select transistor T14. In addition, a sensitive amplifier SA can be set between the first global bit line GBL and the second global bit line GBLB, and the sensitive amplifier SA can be used to acquire the read data.

[0091] For example, the static random access memory device 300 may further include an auxiliary unit connected to both the first global bit line GBL and the second global bit line GBLB. When writing data to the memory cell 400, the auxiliary unit can increase the potential of the first global bit line GBL and decrease the potential of the second global bit line GBLB. This avoids the impact on data writing caused by placing the first gating transistor T10 or the second gating transistor T14 between the global bit line GB and the local bit line LB.

[0092] To easily understand, during the data writing process, taking writing "0" as an example, the first global bit line GBL is at a low potential, and the second global bit line GBLB is at a high potential. Because a first gating transistor T10 is set between the first global bit line GBL and the first local bit line LBL1, and a second gating transistor T14 is set between the second global bit line GBLB and the second local bit line LBLB1, the potential of the first global bit line GBL may be slightly lower than that of the first local bit line LBL1, and the potential of the second global bit line GBLB may be slightly higher than that of the second local bit line LBLB1. This would reduce the voltage difference between the memory cell 400 and the two ends connected to the first local bit line LBL1 and the second local bit line LBLB1. At this time, since the auxiliary unit can increase the potential of the first global bit line GBL and decrease the potential of the second global bit line GBLB, the influence of setting the first gating transistor T10 or the second gating transistor T14 can be avoided.

[0093] Furthermore, taking the reading of data "0" as an example, although the first gating transistor T10 increases the resistance between the first global bit line GBL and the first local bit line LBL1, and the second gating transistor T14 increases the resistance between the second global bit line GBLB and the second local bit line LBLB1, the impact on the discharge speed is minimal. Additionally, when the voltage difference between the first local bit line LBL1 and the second local bit line LBLB1 reaches the read threshold, the sensitive amplifier SA turns on, further releasing the charge on the first local bit line LBL1 and the first global bit line GBL, thereby reading the data. Therefore, setting the first gating transistor T10 or the second gating transistor T14 has almost no impact on the read performance of the memory cell 400.

[0094] Please refer to Table 1, which is a comparison table of power consumption and area between the static random access memory device 300 shown in Figures 6 and 7 and the memory devices in Figures 3 and 5.

[0095] Table 1

[0096] As shown in Table 1, the static random access memory (SRAM) device 300 provided in this application can reduce read power consumption by 20% to 30% and write power consumption by 0% to 5% compared to the memory device in Figure 3, but the area only increases by 5%. Compared with the memory device in Figure 5, the SRAM device 300 provided in this application has basically the same read and write power consumption, but the area is reduced by 20% to 30%.

[0097] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A static random access memory device, characterized in that, include: A first storage area and a second storage area, wherein the first storage area includes a plurality of first storage cells and a first virtual cell arranged along a first direction, and the second storage area includes a second virtual cell and a plurality of second storage cells arranged along the first direction, wherein the first direction is the direction in which the first storage area and the second storage area are arranged; A gating unit is disposed between the first virtual unit and the second virtual unit; Local bit lines are connected to the plurality of first memory cells or the plurality of second memory cells; The global bit line is connected to the local bit line through the gating unit; The first virtual unit and the first memory unit each include a plurality of transistors, and the number of transistors included is equal. According to the arrangement order of the plurality of first memory units and the first virtual unit, the arrangement of the plurality of transistors in each of the plurality of first memory units and the first virtual unit changes periodically. The second virtual unit and the second memory unit each include a plurality of transistors, and the number of transistors included is equal. According to the arrangement order of the second virtual unit and the plurality of second memory units, the arrangement of the plurality of transistors in each of the second virtual unit and the plurality of second memory units changes periodically.

2. The static random access memory device as described in claim 1, characterized in that, The connection configuration between the plurality of transistors in the first virtual unit is the same as that between the plurality of transistors in the second virtual unit.

3. The static random access memory device as described in claim 1 or 2, characterized in that, The gates of the plurality of transistors in the first virtual unit and the gates of the plurality of transistors in the second virtual unit are connected to the same potential.

4. The static random access memory device as described in any one of claims 1 to 3, characterized in that, It includes an N-well extending in the first direction and a first region and a second region on both sides of the N-well along a second direction, wherein the second direction is perpendicular to the first direction; The number of transistors in the first memory cell disposed in the N-well, the first region, and the second region is equal to the number of transistors in the first virtual cell disposed in the N-well, the first region, and the second region, respectively. The number of transistors in the second memory cell disposed in the N-well, the first region, and the second region is equal to the number of transistors in the second virtual cell disposed in the N-well, the first region, and the second region, respectively.

5. The static random access memory device as described in claim 4, characterized in that, The number of transistors disposed in the first region and the second region is equal for any of the plurality of first storage cells and the first virtual cells; the transistors disposed in the first region of the plurality of first storage cells and the first virtual cells are arranged sequentially along the first direction, and the first electrode of any two adjacent transistors shares a common electrode with the second electrode of the other; the transistors disposed in the second region of the plurality of first storage cells and the first virtual cells are arranged sequentially along the first direction, and the first electrode of any two adjacent transistors shares a common electrode with the second electrode of the other. The number of transistors in the first region and the second region is equal for each of the second virtual units and the plurality of second memory units; the transistors in the first region are arranged sequentially for the plurality of second memory units and the second virtual units, and the first electrode of any two adjacent transistors shares a common electrode with the second electrode of the other; the transistors in the second region are arranged sequentially for the plurality of second memory units and the second virtual units, and the first electrode of any two adjacent transistors shares a common electrode with the second electrode of the other.

6. The static random access memory device as described in claim 5, characterized in that, One of any two adjacent first memory cells and the first virtual cell includes a first P-type transistor, and the other includes a second P-type transistor. The first electrode of the first P-type transistor and the second P-type transistor share a common electrode with the second electrode of the other. The first P-type transistor and the second P-type transistor are the two transistors that are closest to each other in the N-well among any two adjacent first memory cells and the first virtual cell. One of any two adjacent second virtual cells and the plurality of second memory cells includes a third P-type transistor, and the other includes a fourth P-type transistor. The first electrode of one of the third P-type transistor and the second electrode of the other share a common electrode. The third P-type transistor and the fourth P-type transistor are the two transistors that are closest to each other in the N-well among any two adjacent first memory cells and the first virtual cells.

7. The static random access memory device as described in any one of claims 4 to 6, characterized in that, The static random access memory device further includes a region selection line, the gating unit includes a first gating sub-unit and a second gating sub-unit arranged along the first direction, the first gating sub-unit includes a first gating transistor, the second gating unit includes a second gating transistor, the local bit line includes a first local bit line and a second local bit line, and the global bit line includes a first global bit line and a second global bit line. The gate of the first gate transistor is connected to the region selection line, the first terminal of the first gate transistor is connected to the first local bit line, and the second terminal of the first gate transistor is connected to the first global bit line. The gate of the second gating transistor is connected to the region selection line, the first terminal of the second gating transistor is connected to the second global bit line, and the second terminal of the second gating transistor is connected to the second local bit line.

8. The static random access memory device as described in claim 7, characterized in that, The first gating subunit further includes a plurality of first virtual transistors, which are disposed in the first region and the second region respectively. The first gating transistors are disposed in the first region, and the sum of the number of first virtual transistors in the first region and the number of first gating transistors disposed in the first region is equal to the number of first virtual transistors disposed in the second region. The second gating subunit further includes a plurality of second virtual transistors, which are disposed in the first region and the second region respectively. The second gating transistors are disposed in the second region, and the sum of the number of second virtual transistors in the second region and the number of second gating transistors disposed in the second region is equal to the number of second virtual transistors in the first region.

9. The static random access memory device as described in claim 8, characterized in that, The number of the first virtual transistors disposed in the second region is equal to the number of transistors disposed in the first memory cell in the second region; The number of the second virtual transistors disposed in the first region is equal to the number of transistors disposed in the second memory cell in the first region.

10. The static random access memory device as described in claim 8 or 9, characterized in that, In the first region or the second region, a first virtual transistor of the first gating subunit is disposed adjacent to a transistor of the first virtual unit, and the first electrode of the transistor of the first virtual unit and the second electrode of the first virtual transistor share a common electrode; In the first region or the second region, a second virtual transistor of the second gating subunit is disposed adjacent to a transistor of the second virtual unit, and the first electrode of the transistor of the second virtual unit shares a electrode with the second electrode of the second virtual transistor.

11. The static random access memory device as claimed in any one of claims 8 to 10, characterized in that, In the first region, the first terminal of the first gate transistor and the second terminal of the transistor of the first virtual cell adjacent to the first gate transistor share a common terminal, and the second terminal of the first gate transistor and the first terminal of the first virtual transistor adjacent to the first gate transistor; In the second region, the first terminal of the second gate transistor and the second terminal of the first virtual transistor adjacent to the second gate transistor share a common terminal, and the second terminal of the second gate transistor and the second terminal of the second virtual transistor adjacent to the second gate transistor share a common terminal.

12. The static random access memory device as claimed in claim 7, characterized in that, The first gating subunit further includes a third gating transistor, and the second gating subunit further includes a fourth gating transistor; The gate of the third gating sub-unit is connected to the region selection line, the first terminal of the third gating transistor is connected to the first local bit line, and the second terminal of the third gating transistor is connected to the first global bit line. The gate of the fourth gate transistor is connected to the region selection line, the first terminal of the fourth gate transistor is connected to the second local bit line, and the second terminal of the fourth gate transistor is connected to the second global bit line.

13. The static random access memory device as described in any one of claims 7 to 12, characterized in that, The portion of the zone selection line connecting the gate of the first gate transistor and the gate of the second gate transistor extends along a second direction.

14. An electronic device, characterized in that, It includes a circuit board and a static random access memory device as described in any one of claims 1 to 13, wherein the static random access memory device is disposed on the circuit board.

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