Cache management method and apparatus

Abstract

The present disclosure provides a cache management method. The cache management method combines both the SW allocation cache and HW cache locking to improve a success rate of data storage while ensuring that the data is stored in the cache without being moved out. The method includes: obtaining data having a size of N bytes to be stored; invoking a memory allocator to determine a first region having a size equal to N bytes; invoking a locked region manager to determine a second region based on the first size and restrictions of hardware (HW); storing the data into the second region; and invoking a lock driver to lock the second region.

Description

CACHE MANAGEMENT METHOD AND APPARATUSTECHNICAL FIELD

[0001] The present disclosure generally relates to the field of computer technologies, and in particular to a cache management method and a cache management apparatus.BACKGROUND

[0002] In the computer technology field, most cache management apparatuses may use a hardware (HW) cache technology to store the most frequently accessed data. Typically, a cache management apparatus may use a HW cache technology to automatically decide what to put to the cache and when to replace the data in the cache with the new one. Generally, the HW cache technology may decide to put the most frequently used data into the cache. In a case where the data is subsequently not the most frequently used data, the data may be moved out of the cache. Therefore, the HW cache technology may not guarantee that specific data is stored in the cache and not be removed out, which may affect the throughput and latency of important processes in a case where the specific data may be important data related to an important process.

[0003] One common approach is to organize codes which may enhance a possibility that specific data may be stored in the cache. However, in this way, the HW may have restrictions for the data to be stored in the cache, and a success rate of data storage may be low. Therefore, how to develop a suitable method for cache management to improve the success rate of data storage is a pressing issue.SUMMARY

[0004] In view of this, implementations of the present disclosure provide a cache management method and an apparatus, which may improve a success rate of data storage while ensuring that the data is stored in the cache without being moved out.

[0005] In a first aspect, a cache management method is described. The method may be applied to a cache management apparatus, or a component in the cache management apparatus (e.g., a module, a circuit, or a chip in the storage device). The method includes: obtaining data having a size of N bytes to be stored; invoking a memory allocator to determine a first region having a first size equal to N bytes; invoking a locked region manager to determine a second region based on the first size and restrictions of hardware (HW); storing the data into the second region; and invoking a lock driver to lock the second region.

[0006] In this case, the cache management method combines both the software (SW) cache allocation and HW cache locking to ensure that specific data is stored in the cache and a region where the data is stored may be locked. In addition, HW lockdown mechanism may also be combined with flexibility of the SW, and restrictions of the HW mentioned above may be satisfied iby the second region which is determined based on the first size and restrictions of the HW. In this case, there may be no restrictions for a size of the data to be stored in the cache. And this may improve the success rate of storing data in the cache.

[0007] In addition, the cache management apparatus may control the memory allocator to finish a process of cache allocation, by using one or a few lines of codes, and the lock driver controlling the HW to lock a region may be a fixed process and the corresponding codes may not need to be changed each time. As a result, in a case where a SW may need to put some data to the cache, it may take one or a few lines of codes to call a cache allocation related function instead of rewriting a plurality of codes based on specific application scenarios, which may improve the maintainability of the codes.

[0008] In some embodiments, determining the second region includes: determining the first region as the second region in a case where the first size satisfies the restrictions of the HW.

[0009] In this case, based on the restrictions of the HW, there may be no need to search for a new region as the second region, which may simplify steps of a data storage process and reduce computational complexity.

[0010] In some embodiments, determining the second region includes: searching for a region of a size satisfying the restrictions of the HW in a case where the first size does not satisfy the restrictions of the HW; and determining the region of the size satisfying the restrictions of the HW as the second region.

[0011] In some embodiments, searching for the region of the size satisfying the restrictions of the HW includes: obtaining a second size, based on the first size and a lock granularity required when locking the data in the HW.

[0012] In a possible implementation, the lock granularity required may refer to a fact that the hardware locks a region storing the data in a case where the region has a size that is an integer multiple of the lock granularity. The cache management apparatus may determine a region with the second size as the second region by invoking the locked region manager. In this case, even data of size of 1 byte may be stored in the cache and not removed, which may improve a success rate of storing data in the cache.

[0013] In some embodiments, searching for the region of the size satisfying the restrictions of the HW includes: searching for a region of a size and an address both satisfying the restrictions of the HW.

[0014] In some embodiments, searching for the region of the size and the address both satisfying the restrictions of the HW includes: obtaining a second address, based on an alignment required when storing the data in the HW and a first address of the first region; and obtaining a second size,based on the first size and a lock granularity required when locking the data in the HW.

[0015] In some embodiments, a value corresponding to the second address is obtained by subtracting a remainder of the first address to the alignment from a sum of the first address and the alignment.

[0016] In this case, the first address may be pointed by a pointer p, which may point to a start of the first region. It is understood that in a case where the first address (which may be pointed by a pointer p) does not satisfy restrictions of the HW, the cache management apparatus may determine a second address based on the first address.

[0017] In some embodiments, the second size is obtained by subtracting a remainder of the first size to the lock granularity from a sum of the first size and the lock granularity.

[0018] In this case, the cache management method may have no restrictions for a size of the data to be stored in the cache, and may make the second size as small as possible while satisfying the restrictions of the HW. This may be a significant breakthrough in the restrictions of the HW and may make the cache management method more flexible.

[0019] In some embodiments, the cache management method further includes: passing a second address of the second region and a second size of the second region to the memory allocator; and invoking the memory allocator to update a first list based on the second address of the second region and the size of the second region, where the first list includes addresses and sizes of one or more regions of allocated cache.

[0020] It is noted that the first list described above may also be referred to as a busy list. The first list is used to manage information (addresses and sizes) of regions of allocated cache. The regions of allocated cache may refer to regions of the cache that may be already in use, such as regions that may have data stored therein or regions that may be locked.

[0021] In the case where the second region is determined, the second address of the second region and the second size of the second region may be passed to the memory allocator, which may ensure an accuracy of the first list used to maintain information about allocated cache regions for subsequent management.

[0022] In some embodiments, updating the first list includes: removing the first address and the first size from the first list; and inserting the second address and the second size to the first list.

[0023] The region ultimately used to store data may be the second region rather than the first region. In other words, the first region may not be a region of allocated cache anymore whereas the second region may be a region of allocated cache in this case. Therefore, updating the first list through the process above may enhance the effectiveness of decision-making, ensure rational allocation of resources and reduce errors and redundant information.

[0024] In some embodiments, invoking the memory allocator to determine the first region includes: invoking the memory allocator to perform: searching for a third region of a size greater than or equal to N bytes in a second list, where the second list includes addresses and sizes of one or more free regions, and the one or more free regions include the third region; splitting the third region into the first region and a fourth region in a case where the size of the third region is greater than N bytes; removing an address of the third region and the size of the third region from the second list; inserting a first address of the first region and the first size to a first list, where the first list includes addresses and sizes of one or more regions of allocated cache; and inserting an address of the fourth region and a size of the fourth region to the first list.

[0025] The second list which may also be called a free list includes addresses and sizes of one or more free regions in the cache. In this way, information (addresses and sizes) of regions in different states (free or already allocated cache) is stored in different lists by the cache management apparatus via the memory allocator, which may facilitate subsequent management and maintenance. In addition, the fourth region serves as a backup region, which may further improve system reliability and ensure data security.

[0026] In some embodiments, the cache management method further includes: determining the third region as the first region in a case where the size of the third region is equal to N bytes.

[0027] In this case, there may not be the fourth region, which may make less information about regions stored in the first list, and reduce a complexity of managing the first list.

[0028] In some embodiments, invoking the lock driver to lock the second region includes: determining whether there exists a fifth region adjacent to the second region, where the fifth region is a locked region; invoking the lock driver to unlock the fifth region if the fifth region exists; obtaining an address of a sixth region, based on a second address of the second region and the address of the fifth region, and a size of the sixth region, based on a second size of the second region and the size of the fifth region, where the sixth region is a merged region of the second region and the fifth region; and invoking the lock driver to lock the sixth region.

[0029] In this case, the number of locked regions may be reduced and an amount of information to be maintained in the third list which is used to maintain information of the locked regions may also be reduced. As a result, system performance may be improved and cache management may be simplified.

[0030] In some embodiments, determining whether there exists the fifth region adjacent to the second region includes: searching for the fifth region based on the second address of the second region and the second size in a third list, where the third list includes addresses and sizes of one or more locked regions, and the one or more locked regions include the fifth region. The cachemanagement method further includes: updating the third list based on the address of the sixth region and the size of the sixth region.

[0031] In some embodiments, updating the third list based on the address of the sixth region and the size of the sixth region includes: removing the address of the fifth region and the size of the fifth region from the third list; and inserting the address of the sixth region and the size of the sixth region to the third list.

[0032] In this case, the update of the third list may improve an accuracy of the third list to facilitate subsequent management of locked regions, which may also enhance the effectiveness of decision-making, ensure rational allocation of resources and reduce errors and redundant information.

[0033] In some embodiments, the cache management apparatus may obtain an address of a seventh region to be deallocated and invoke the memory allocator to determine a size of the seventh region from one or more regions of allocated cache. The cache management apparatus may then invoke the locked region manager to determine an eighth region to be unlocked based on an address of the seventh region, where a size of the eighth region is greater than or equal to the size of the seventh region; and the cache management apparatus may invoke the lock driver to unlock the eighth region.

[0034] In this case, the cache management apparatus may be allowed to edit specific data in the cache as needed, which may improve data flexibility and access efficiency. It is noted that the seventh region may be the second region, or may be another region that was previously allocated in the cache, and it is not limited thereto.

[0035] In some embodiments, the cache management method further includes: in a case where the size of the eighth region is greater than the size of the seventh region, invoking the lock driver to lock remaining regions of the eighth region other than the seventh region.

[0036] In the case where the size of the eighth region is greater than the size of the seventh region, the remaining regions of the eighth region other than the seventh region may be locked. The locking of the remaining regions may allow the cache management apparatus to achieve a precise deallocation of a region where the data to be deallocated is located without interference from adjacent regions, which may ensure data consistency and reliability.

[0037] In a second aspect, an apparatus is described. The apparatus has a function of implementing the first aspect. For example, the apparatus includes a corresponding module, unit, or means for performing operations in the first aspect. The module, unit, or means may be specifically implemented by using software, may be implemented by using hardware, or may be implemented by using software in combination with hardware.

[0038] In a third aspect, an apparatus is described, which includes: one or more processors; and a memory storing instructions which, when executed by the one or more processors, cause the apparatus to perform any implementation of the first aspect.

[0039] In a fourth aspect, a computer-readable storage medium is described, which has instructions stored thereon which, when executed by one or more processors, cause the one or more processors to perform the method in any possible implementation of the first aspect.

[0040] In a fifth aspect, a computer program product is described, which stores instructions which, when executed, cause an apparatus to perform the method in any possible implementation of the first aspect.

[0041] This disclosure encompasses various embodiments, including not only method embodiments, but also other embodiments such as apparatus embodiments and embodiments related to non-transitory computer readable storage media. Embodiments may incorporate, individually or in combinations, the features disclosed herein.BRIEF DESCRIPTION OF THE DRAWINGS

[0042] For a better understanding of the various described embodiments, reference should be made to the Detailed Description below, in conjunction with the following drawings in which like reference numerals refer to corresponding parts throughout the figures.

[0043] FIG. 1 is a schematic diagram of a software architecture of a cache management apparatus that some embodiments of the present disclosure can use;

[0044] FIG. 2 is a flow chart of a cache management method, in accordance with some embodiments of the present disclosure;

[0045] FIG. 3 is a schematic diagram of a process for cache allocation in accordance with some embodiments of the present disclosure;

[0046] FIG. 4 is a schematic diagram of a process for cache deallocation in accordance with some embodiments of the present disclosure; and

[0047] FIG. 5 is a schematic diagram of different situations of overlap between the common region and the region to be deallocated in accordance with some embodiments of the present disclosure;

[0048] FIG. 6 is a block diagram of an apparatus in accordance with some embodiments; and

[0049] FIG. 7 is a block diagram of another apparatus in accordance with some embodiments. DETAILED DESCRIPTION

[0050] Embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0051] In the computer technology field, caching is a technique used to increase the speed of dataaccess, primarily by storing frequently used data to reduce the time it takes to access main memory. Typically, hardware (HW) may automatically decide what to put to the HW cache and when to replace the data in the HW cache with the new one. The HW cache may be a type of high-speed memory in a computer system that may be used to temporarily store data and instructions to increase the access speed of the HW, and the HW cache may can be abbreviated as cache. The HW may be a reduced instruction set computer (RISC) machine (ARM) central processing unit (CPU), and the HW may also be a graphics processing unit (GPU), an accelerator, etc. In this case, the HW may behave suboptimal because the HW bases its decisions on the frequency of accesses to the data, and most frequently used data is not necessarily the most performance critical one. This may lead to some problems in some application scenarios, which include but is not limited to:

[0052] 1. In a case where low-importance process runs concurrently with a performance critical one and pollutes shared cache, overall performance may not be that important, and what is important may be performance of a particular process.

[0053] 2. At data level, a portion of code may operate with important (e.g., latency-sensitive) data and non-important data (e.g., stream of non-repeating input data). Generally, computers perform a large number of operations per second, and latency-sensitive data may require the shortest possible latency. However, the hardware may not be able to correctly recognize the importance of the data, thus leading to long latency times, which may affect the computational performance.

[0054] 3. To satisfy some quality of service (QoS) metrics, codes may need ensure some data has predictable and good latency access, which may not be guaranteed in this case.

[0055] To solve the problem that the HW may base its decisions on the frequency of accesses to the data, an approach is to organize codes such that the data may be accessed in a cache-friendly manner, which may enhance a possibility that the specific data may be stored in the cache. A classic example is blocked matrix multiplication.

[0056] In a common matrix multiplication algorithm, for multiplying two two-dimensional matrices, it is common to iterate over rows and columns of the two matrices separately and then multiply the rows and columns separately. In this case, four loops may be used. However, in a blocked matrix multiplication algorithm, matrices may be blocked and multiplied, and more loops may be used, in which extra loops may be used to divide the matrices into smaller blocks. Elements in a matrix block may usually be stored in order in the cache. In a case where a processor performs sequential accesses to data in a matrix block, adjacent data may already be stored in the cache. Thus, the cache time may be reduced and further the cache may be utilized efficiently.

[0057] The way of organizing codes may enhance a possibility of storing data which may bePCI7RU2024 / 000350 deemed important by a user in the cache. However, in order to store data in the cache and ensure that the data is not moved out, the data may satisfy restrictions of the HW. These restrictions of the HW may include, but are not limited to the following:

[0058] 1. Data may be physically continuous. In this case, data to be stored in the cache may be continuous in the physical sense and of a certain size.

[0059] 2. Data may be aligned to some boundary. In this case, a location of data stored in the cache may conform to specific boundary requirements. For example, some hardware requires data to be aligned on boundaries such as 4-byte, 8-byte, etc., to optimize access speed and reduce errors. For example, 4-byte alignment on 32-bit systems means that data may be stored at addresses that are multiples of 4-byte, such as 4-byte, 8-byte, or 12-byte.

[0060] 3. Data to be locked may be at a low granularity. Generally, data to be locked in the cache may be at a minimum granularity of kilobytes, and therefore smaller sized data (e.g., smaller than kilobytes) may not be locked.

[0061] In this case, data that meets the restrictions of the HW may be stored in the cache and not moved out. These restrictions may greatly reduce a success rate of storing data in the cache.

[0062] Therefore, how to develop a suitable method for cache management to improve the success rate of storing data in the cache is an urgent problem to be solved.

[0063] In view of this, embodiments of the present disclosure provide a cache management method. The cache management method may combine a memory allocator and HW lock functionality. This may both manage the memory and ensure the data is locked through HW lock mechanism.

[0064] In this way, in a case where a software (SW) puts some data to the cache, the HW may search for a region in the cache for storing the data. In a case where the region satisfies the restrictions of the HW, there may not be restrictions for a size of the data. In this case, even data of size of 1 byte may be stored in the cache and not moved out, which may improve a success rate of storing data in the cache.

[0065] For ease of understanding, embodiments of the present disclosure are described by taking an example in which the cache management method is performed at a cache management apparatus. The cache management apparatus may be a computer, a processor, a microprocessor, a multiprocessor, or other devices, and a type of the device is not limited thereto.

[0066] For ease of understanding, functions of various parts of a software architecture of the cache management apparatus are described in detail in conjunction with FIG. 1 as below. FIG. 1 is a schematic diagram of a software architecture of a cache management apparatus that some embodiments of the present disclosure can use. The cache management apparatus may have thesoftware architecture including the following components.

[0067] 1. User application

[0068] The user application refers to a software application that users use directly via computing devices. The user application may provide a graphical user interface (GUI) that may allow the user to interact with the SW in an intuitive manner. The user application may run on a variety of platforms, including desktop computers, mobile devices and web browsers.

[0069] 2. Public application programming interface (API)

[0070] Public API refers to an open application programming interface that may allow a developer to access functionality and data of a particular SW or service. Unlike private API, the public API may be open to all developers, and allow developers to access, send, or modify data in a particular system, which may facilitate development and integration of third-party applications.

[0071] 3. Memory allocator

[0072] The memory allocator may be a component of an operating system that may be responsible for dynamically allocating and managing computer memory, e.g., allocating and reclaiming blocks of memory for a program at runtime. The memory allocator may manage a relationship between free and allocated memory to ensure efficient use of memory resources. It is noted that the memory allocator may also be used for cache management, and may therefore also be referred to as a cache allocator and a name of this component is not limited here.

[0073] 4. Locked region manager

[0074] Locked region manager is a management mechanism to manage locked cache regions (or memory regions) and prevent data in the locked cache regions (or memory regions) from being swapped out or otherwise modified.

[0075] 5. Lock driver

[0076] The lock diver may refer to a component or module used to implement a locking mechanism. The lock driver is responsible for programming the HW to handle the locking mechanisms, which may ensure that cache regions are properly locked and managed.

[0077] 6. Hardware (HW)

[0078] The HW may refer to a hardware component related to a cache management system, which may be driven by software drivers for cache management related functions. The HW may be a reduced instruction set computer (RISC) machine (ARM) central processing unit (CPU), and the HW may also be a graphics processing unit (GPU), an accelerator, etc.

[0079] It is noted that the components described above may be used to implement the cache management method proposed in embodiments of the present disclosure. In addition, other components may also be used for the cache management method.

[0080] FIG. 2 is a flow chart of a cache management method 200, in accordance with some embodiments of the present disclosure. The cache management method shown in FIG. 2 may be performed by a cache management apparatus, and a possible software architecture of the cache management apparatus is shown in FIG. 1. The cache management method 200 may include steps 210 to 250.

[0081] In step 210, the cache management apparatus may obtain data having a size of N bytes to be stored.

[0082] For example, the cache management apparatus may obtain data with a number of N bytes to be stored in the cache via the user application.

[0083] In step 220, the cache management apparatus may invoke a memory allocator to determine a first region having a first size equal to N bytes.

[0084] For example, the cache management apparatus may invoke the public API to call an interface that may include functions to implement cache allocation. The public API may enable different SW components to communicate and interact with each other (such as the user application and the memory allocator). In this case, the cache management apparatus may further invoke the memory allocator to determine a first region having a first size equal to A to ensure that there may be a suitable space in the cache to store the data with the number of N bytes.

[0085] In step 230, the cache management apparatus may invoke a locked region manager to determine a second region based on the first size and restrictions of hardware (HW).

[0086] Although the first size of the first region may meet a requirement for storing data, the first size may also need to meet restrictions of the HW. For example, in a case where the HW locks the first region, the first size may need to satisfy a locking granularity specified by the HW. In a case where the first size does not satisfy the restrictions, the cache management apparatus may need to determine a second region based on the first region. In a case where the first region satisfies the restrictions, the second region may be the first region.

[0087] In step 240, the cache management apparatus may store the data into the second region.

[0088] In this case, the data to be stored may be moved in the cache and stored.

[0089] In step 250, the cache management apparatus may invoke a lock driver to lock the second region.

[0090] In this case, the lock driver has a capability to control the HW through programming to lock the second region. As a result, the data stored in the second region (which is also stored in the cache) may not be replaced or removed. The locked second region may prevent the data from being accidentally changed or deleted and ensure the accuracy and reliability of the data. Especially in a multi-user environment, locked regions may prevent different users from performing conflictingoperations on a same region, thus maintaining data consistency and further reducing the risk of data errors caused by misuse.

[0091] As mentioned above, the cache management method combines both the SW cache allocation and HW cache locking to ensure that data specified by a cache management apparatus is stored in the cache and a region where the data is stored may be locked. In addition, HW lockdown mechanism may also be combined with flexibility of the S W, and the restrictions of the HW mentioned above may be satisfied by the second region which is determined based on the first size and the restrictions of the HW. In this case, there may not be restrictions for a size of the data. And this may improve flexibility of the data to be stored in the cache.

[0092] In addition, the cache management apparatus may control the memory allocator to finish a process of cache allocation, by using one or a few lines of codes, and the lock driver controlling the HW to lock a region may be a fixed process and the corresponding codes may not need to be changed each time. As a result, in a case where a SW may need to put some data to the cache, it may take one or a few lines of codes to call a cache allocation related function instead of rewriting a plurality of codes based on specific application scenarios, which may improve the maintainability of the codes.

[0093] In the step 230, according to whether the first size meets the restrictions of the HW, there may be two cases as follows:

[0094] (1) Case 1, the first size satisfies the restrictions of the HW, and the cache management apparatus may determine the first region as the second region.

[0095] In this case, based on the restrictions of the HW, there may be no need to search for a new region as the second region, which may simplify steps of a data storage process and reduce computational complexity.

[0096] (2) Case 2, the first size may not satisfy the restrictions of the HW. The cache management apparatus may search for a region of a size satisfying the restrictions of the HW and determine the region of the size satisfying the restrictions of the HW as the second region.

[0097] For example, the cache management apparatus may obtain a second size, based on the first size and a lock granularity required when locking the data in the HW.

[0098] In a possible implementation, the lock granularity may mean that a region storing the data has a size that may be an integer multiple of the lock granularity when the HW locks the region storing the data. The cache management apparatus may determine the region of the second size satisfying the restrictions of the HW as the second region by invoking the locked region manager. In this case, even data of 1 byte may be stored in the cache and not moved out.

[0099] Further, the restrictions of the HW may also include requirements for an address of a iiregion in which the data is stored. For example, a first address refers to an address of the first region described above. According to whether the first address satisfies the restrictions of the HW, based on the method 200 described above, there may be two cases as follows:

[0100] (1) Case 1, the first address satisfies the restrictions of the HW. The cache management apparatus may determine a region with the second size as the second region.

[0101] (2) Case 2, the first address does not satisfy the restrictions of the HW. The cache management apparatus may search for a region of a size and an address both satisfying the restrictions of the HW and determine the region as the second region.

[0102] In some embodiments, the cache management apparatus may obtain a second address, based on an alignment required when storing the data in the HW and a first address of the first region. The cache management apparatus may also obtain a second size, based on the first size and a lock granularity required when locking the data in the HW.

[0103] The alignment requirement means that when the HW allocates a region for data storage, an address of the region where the data is stored corresponds to a value that may be an integer multiple of the alignment requirement. In this case, a pointer may point to an address of a region, and the value of the pointer is the value corresponding to the address of the region. After determining the second address and the second size, the cache management apparatus may invoke the locked region manager to determine a region with the second size and the second address as the second region.

[0104] In some embodiments, a value corresponding to the second address is obtained by subtracting a remainder of the first address to the alignment from a sum of the first address and the alignment requirement.

[0105] In this case, the first address may be pointed by a pointer p, which may point to a start of the first region. It is understood that in a case where the first address (which may be pointed by a pointer p) does not satisfy restrictions of the HW, the cache management apparatus may obtain the second address based on the first address.

[0106] For example, the first address (which may be pointed by a pointer p) may not satisfy the restrictions of the HW. There may be a calculation based on the pointer p to obtain a pointer p ’ (which may point to the second address). In an implementation, the restrictions of the HW include an alignment requirement^, and the pointer p ’ may be obtained by the following equation: p' = p + A - p%A. (1)Where p and A are both positive integers, the pointer p' may point to the second address (the address of the second region), and p% A refers to taking a remainder of p divided by A. The alignment requirement A refers to an alignment requirement that may need to be satisfied by anaddress of a region to be allocated in the cache which may store the data. For example, assuming that p is 13 and the alignment requirement A is 8 (which means that an address of a region to be allocated which may store the data may need to be aligned with a boundary of 8 bytes). Then p%A = 5 and p' = 16 may be obtained by the calculation. And the pointer p' may satisfy the alignment requirement A.

[0107] In some embodiments, the second size is obtained by subtracting a remainder of the first size to the lock granularity from a sum of the first size and the lock granularity.

[0108] Likewise, for example, the restrictions of the HW may include a lock size granularity G. The first size (which may be N bytes) may not satisfy the restrictions of the HW. And the second size N' (a size of the second region) may be obtained by the following equation:N' = N + G - N%G. (2)Where N and G are both positive integers, N' may refer to the second size of the second region, and N% G refers to taking a remainder of N divided by G. The lock size granularity G refers to the lock size granularity that may need to be satisfied by a size of a region to be locked in the cache which may store the data. For example, assuming that A is 13 and the lock size granularity G is 8 (which means that a size of a region to be locked which may store the data may need to be an integer multiple of the lock size granularity of 8 bytes). Then N%G = 5 and N' = 16 may be obtained by the calculation. And the A’ may satisfy the lock size granularity G.

[0109] Because the cache management method may combine a memory allocator and HW lock functionality, with the solution mentioned above (by searching for a second region whose size and address may satisfy the restrictions of the HW), even data with a byte of 1 may be stored in the cache and locked by the cache management apparatus.

[0110] In this case, the cache management method may have no restrictions for a size of the data to be stored in the cache; in addition, the method may make the second size as small as possible while satisfying the restrictions of the HW. This may be a significant breakthrough in the restrictions of the HW and may make the cache management method more flexible.

[0111] In some embodiments, the cache management method further includes: passing a second address of the second region and a second size of the second region to the memory allocator; and invoking the memory allocator to update a first list based on the second address of the second region and the size of the second region, where the first list includes addresses and sizes of one or more regions of allocated cache.

[0112] It is noted that the first list described above may also be referred to as a busy list. The first list is used to manage information (addresses and sizes) of regions of allocated cache. The regions of allocated cache may refer to regions of the cache that may be already in use, such as regionsPCI7RU2024 / 000350 that may have data stored therein or regions that may be locked.

[0113] In the case where the second region is determined, the second address of the second region and the second size of the second region may be passed to the memory allocator, which may ensure an accuracy of the first list used to maintain information about allocated cache regions for subsequent management.

[0114] In some embodiments, updating the first list includes: removing the first address and the first size from the first list; and inserting the second address and the second size to the first list.

[0115] The region ultimately used to store data may be the second region rather than the first region. In other words, the first region may not be a region of allocated cache anymore whereas the second region may be a region of allocated cache in this case. So updating the first list through the process above may enhance the effectiveness of decision-making, ensure rational allocation of resources and reduce errors and redundant information.

[0116] In some embodiments, the step 220 may include that: the cache management apparatus may invoke the memory allocator to perform: searching for a third region of a size greater than or equal to N bytes in a second list, where the second list includes addresses and sizes of one or more free regions, where the one or more free regions include the third region; and performing step (1) or (2) according to the size of the third region.

[0117] It is noted that the second list may also be referred to a free list. The second list is used to manage information (addresses and sizes) of free regions. The free regions may refer to unused regions in the cache.

[0118] In step (1), in a case where the size of the third region is greater than N, the cache management apparatus may invoke the memory allocator to perform: splitting the third region into the first region and a fourth region; removing an address of the third region and the size of the third region from the second list; inserting a first address of the first region and the first size to a first list, where the first list includes addresses and sizes of one or more regions of allocated cache; and inserting an address of the fourth region and a size of the fourth region to the first list.

[0119] The second list which may also be called a free list includes addresses and sizes of one or more free regions in the cache. In this case, the cache management apparatus may invoke the public API to call an interface that may include functions to implement cache allocation. The public API may enable different SW components to communicate and interact with each other (such as the user application and the memory allocator). For example, the cache management apparatus may call cache_alloc () API, which may be a function to implement cache allocation according to the number of A bytes (equal to the size of the object that the cache management apparatus may want to be in the cache). And the cache management apparatus may invoke the memory allocator tosearch for a region which is called the third region with an appropriate size used for storing the data in the first list. As a result, the first region in the third region is used for storing the cache management apparatus-specific data, whereas the fourth region in the third region is used as- a backup region to facilitate a storage of subsequent data.

[0120] Because the third region may have stored data and may not be a free region now, the address of the third region and the size of the third region may be removed from the second list by the cache management apparatus via the memory allocator. Then, the first address and the first size may be inserted to the second list by the cache management apparatus via the memory allocator. And the address of the fourth region and the size of the fourth region may also be inserted to the first list by the cache management apparatus via the memory allocator.

[0121] In this way, information (addresses and sizes) of regions in different states (free or already allocated cache) is stored in different lists by the cache management apparatus via the memory allocator, which may facilitate subsequent management and maintenance. In addition, the fourth region serves as a backup region, which may further improve system reliability and ensure data security.

[0122] In step (2), in a case where the size of the third region is equal to N, the cache management apparatus may determine the third region as the first region.

[0123] In this case, there may not be the fourth region, which may make less information about regions stored in the first list, and reduce a complexity of managing the first list.

[0124] In some embodiments, invoking the lock driver to lock the second region in step 250 includes: determining whether there exists a fifth region adjacent to the second region, where the fifth region is a locked region. The cache management apparatus may perform step (1) or (2) depending on whether the fifth region exists.

[0125] In step (1), in a case where there is no fifth region adjacent to the second region, the cache management apparatus may invoke the lock driver to lock a sixth region, which may be the second region. In this case, the cache management apparatus may insert information of the sixth region (an address and a size of the second region) to a third list. The third list includes addresses and sizes of one or more locked regions. The locked regions may refer to regions in the cache that are locked, and data stored in the locked regions may not be changed or removed.

[0126] In step (2), in a case where there is a fifth region adjacent to the second region, the cache management apparatus may invoke the lock driver to unlock the fifth region. In addition, the cache management apparatus may obtain an address of a sixth region based on the second address and the address of the fifth region. The cache apparatus may also obtain a size of a sixth region based on the second size and the size of the fifth region, where the sixth region is a merged region of thesecond region and the fifth region. The cache management apparatus may invoke the lock driver to lock the sixth region.

[0127] It is noted that the fifth region may include one or more regions which are adjacent to the second region, and a merged region called the sixth region may be obtained. For example, the cache management apparatus may invoke the lock driver to program the HW to unlock the fifth region and lock the sixth region. In this case, a number of locked regions may be reduced and an amount of information to be maintained in the third list which is used to maintain information of the locked regions, may also be reduced. As a result, system performance may be improved and cache management may be simplified.

[0128] In some embodiments, determining whether there exists the fifth region adjacent to the second region includes: searching for the fifth region based on the second address of the second region and the second size in a third list, where the third list includes addresses and sizes of one or more locked regions, and the one or more locked regions includes the fifth region. The cache management method further includes: updating the third list based on the address of the sixth region and the size of the sixth region.

[0129] In some embodiments, updating the third list based on the address of the sixth region and the size of the sixth region includes: removing the address of the fifth region and the size of the fifth region from the third list; and inserting the address of the sixth region and the size of the sixth region to the third list.

[0130] The update of the third list may improve an accuracy of the third list to facilitate subsequent management of locked regions, which may also enhance the effectiveness of decisionmaking, ensure rational allocation of resources and reduce errors and redundant information.

[0131] A possible process of cache allocation is described in detail below.

[0132] It is noted that the cache management apparatus may need to pre-allocate physically continuous empty cache space before the cache allocation. And the three lists may be created by the cache management apparatus, which may be called a busy list (the first list), a free list (the second list), and a locked region list (the third list).

[0133] In the busy list, each item consists of a pair of a pointer (an address of a busy region, which may be called busy. item, pointer) and a size (a size of a busy region, which may be called busy. item. size). In the free list, each item may include a pair of a pointer (an address of a free region, which may be called free. item, pointer) and a size (a size of a free region, which may be called free. item. size). In the locked region list, each item consists of a pair of a pointer (an address of a locked region, which may be called locked, item, pointer) and a size (a size of a locked region, which may be called locked, item. size).

[0134] FIG. 3 is a schematic diagram of a process for cache allocation in accordance with some embodiments of the present disclosure. A data allocation process 300 includes steps 301 to 312.

[0135] In step 301, the user application may invoke the public API and pass a pointer p, and accordingly, the public API may receive the pointer p. The pointer p may be allocated by the user application as a null pointer to indicate an address of the first region to be allocated.

[0136] For example, the user application may respond to a line of codes p = cache alloc (J 024 * sizeof (int)) which means that a region in the cache of a sufficient size to hold a size of 1024 integers (a size of data, which may also refer to a size of N bytes) may need to be allocated. The user application may then use the pointer p to indicate the address of the first region to be allocated and pass the pointer p to the public API. It is noted that the address of the first region may not be determined in this step, p is passed as a null pointer, and the cache management apparatus may need to determine the address of the first region based on the size of the data in subsequent steps.

[0137] In step 302, the public API may invoke the memory allocator and pass the pointer p, and accordingly, the memory allocator may receive the pointer p.

[0138] For example, after receiving the pointer p, the public API may respond to a line of codes p = cache allocate {1024* sizeof int)) which means that the cache management apparatus may need to search for a free region to store data of size of 1024 integers, and the public API may invoke the memory allocator and pass the pointer p to the memory allocator.

[0139] In step 303, the memory allocator may determine a first region based on a size of the data to be allocated.

[0140] The size of the data to be stored may also refer to a size of N bytes. The memory allocator may search for the third region having a size which is greater than or equal to N in the free list. Alternatively, the memory allocator may let a variable called freePtr equal to pointers from the free list. The memory allocator may iterate over the free list, and then let p =free. item, pointer and freeSize =free. item, size for each item in the free list. The memory allocator may perform one of steps (1), (2), and (3) depending on the size of N in relation to reeSize.

[0141] In step (1), in a case where N > freeSize, there may be no good region to store the data of byte, and the memory allocator may end the allocation process with failure.

[0142] In step (2), in a case where the freeSize = N, the region \p,p + N) may be determined as the first region by the memory allocator, and the first region with an address of p and a size of N may be used to store the data. Because the first region may be used for cache allocation, the region \p,free. item, pointer +free. item, size) may not be free anymore. Therefore, an address and a size of the region [p, p + N) may be removed from the free list and inserted to the busy list by the memory allocator.

[0143] In step (3), in a case where the freeSize > N, the found region with an address of p may be split into two new regions p, p + N) and [p + N, free. item, pointer +free. item, size) by the memory allocator. The region \p, p + N) may be determined as the first region whereas the region [p + N,free. item, pointer +free. item, size) may be determined as the fourth region by the memory allocator. Because these two regions may be used for cache allocation, the region [p,free. item. pointer +free. item, size) may not be free anymore. Therefore, an item (i.e., an address and a size of the region [p, free. item, pointer +free. item, size)) may be removed from the free list by the memory allocator. Likewise, the region \p + N,free. item, pointer +free. item, size) may be updated to [p + N, busy. item, pointer +busy. item, size), addresses and sizes of the two new regions [p, p + N) and [p + N, busy. item, pointer +busy. item, size) may be inserted to the busy list by the memory allocator.

[0144] In step 304, the memory allocator may invoke the locked region manager and pass p and N to the locked region manager. Accordingly, the locked region may receive p and the N, where the pointer p may point to the first address of the first region and N may represent the first size of N bytes of the first region.

[0145] In the three steps (1), (2) and (3) mentioned above, in a case where N < freeSize, the memory allocator may pass p and N to the locked region manager and the locked region manager may receive p and N.

[0146] In step 305, the locked region manager may search for a second region based on the restrictions of the HW.

[0147] As mentioned above, the size N may need to satisfy the restrictions of the HW. In a case where the size N satisfies the restrictions of the HW, the allocation process may continue. In a case where the size N does not satisfy the restrictions of the HW, the second size of A’ may be obtained. Further, in a case where neither p nor N satisfies the restrictions of the HW, the second address (which may be pointed by a pointer p ’) and the second size of A ’may both be obtained.

[0148] The process of calculation (as shown in Eq. (1) and Eq. (2)) is described above, and it will not be repeated here.

[0149] In step 306, the locked region manager may invoke the memory allocator and pass p ’and A’ to the memory allocator. Accordingly, the memory allocator may receive p ’ and A’, where the pointer p ’ may point to the second address of the second region and A’ may represent the second size of the second region.

[0150] In case where p and A both do not satisfy the restrictions of the HW, p ’ and N’ may be obtained based on p and A. As a result, the locked region manager may invoke the memory allocator and pass the pointer p ’ and the size A’ to the memory allocator, where p ’ may point tothe second address and A ’may represent the second size. Addresses and sizes of the two regions \p, p + N) and \p + N, busy. item, pointer +busy. item, size) may be removed from the busy list, and addresses and sizes of the two regions [p ’, p’ + N’) and [p ’ + N’, busy. item, pointer +busy. item, size) may be inserted to the busy list by the memory allocator.

[0151] In step 307, the locked region manager may search for a fifth region adj acent to the second region.

[0152] The locked region manager may iterate over the third list (or the locked region list) and search for a fifth region adjacent to the second region based on the second address and the second size of the second region. In this case, the locked region list may be iterated over and the smallest region that the region [p ’,p ’ + N’) (the second region) has any intersection with may be found by the locked region manager, and represented as minRegion. Also, the largest region that [p ’, p ’ + N’) has any intersection with may be found by the locked region manager, and represented as maxRegion.

[0153] In step 308, the locked region manager may merge the second region and the fifth region to obtain a sixth region.

[0154] Based on the fifth region (e.g., minRegion or maxRegion) adjacent to the second region found in S307, the locked region manager may merge the second region with the fifth region to obtain a common region, which is referred to as the sixth region. The sixth region may be represented as [min minRegion. pointer, p ’), max (maxRegion. pointer + maxRegion. size, p ’ + A’)).

[0155] In step 309, the locked region manager may invoke the lock driver and pass a message indicating to unlock the fifth region. Accordingly, the lock driver may receive the message.

[0156] In step 310, the lock driver may unlock the fifth region.

[0157] In an implementation, regions starting from minRegion and up to and including maxRegion may be iterated over by the lock driver, and the lock driver may program the HW to unlock all of the regions. In this case, the lock region manager may also update the third list to remove information of the fifth region from the third list. For example, the locked region manager may remove information (addresses and sizes) of the regions [minRegion, maxRegion] from the third list.

[0158] In step 311, the locked region manager may invoke the lock driver and pass another message indicating to lock the sixth region. Accordingly, the lock driver may receive the message.

[0159] In step 312, the lock driver may lock the sixth region.

[0160] In this case, the locked region manager may also update the third list by adding information of the sixth region to the third list. For example, the locked region manager may insertinformation (an address and a size) of the sixth region [min (minRegion. pointer, p ’), max (maxRegion. pointer + maxRegion. size, p ’ + N’)) to the third list.

[0161] It is noted that after success of the above allocation process, the cache manager apparatus may invoke the user application and pass the pointer p ’ to the user application. Accordingly, the user application may receive the pointer p

[0162] The process of cache allocation and region locking is described above in conjunction with FIG. 3. In practice, the cache management apparatus may also unlock locked regions and deallocate cache, which is described in more detail below.

[0163] In some embodiments, the cache management apparatus may obtain an address of a seventh region to be deallocated and invoke the memory allocator to determine a size of the seventh region from one or more regions of allocated cache. The cache management apparatus may then invoke the locked region manager to determine an eighth region to be unlocked based on an address of the seventh region, where a size of the eighth region is greater than or equal to the size of the seventh region; and the cache management apparatus may invoke the lock driver to program the HW to unlock the eighth region.

[0164] The cache management apparatus may obtain the address (which may be pointed by a pointer q) of the seventh region to be deallocated. The memory allocator may be invoked to iterate over the first list (also called the busy list) to find a size (which may be a size AT) of the seventh region. Because the eighth region may include the seventh region, and information of the eighth region may be in the third list, based on the address of the seventh region, the eighth region to be unlocked may be found and unlocked. In this case, the cache management apparatus may be allowed to edit specific data in the cache as needed, which may improve data flexibility and access efficiency. It is noted that the seventh region may be the second region, or may be another region where was previously allocated in the cache, and it is not limited thereto.

[0165] In some embodiments, the cache management method further includes: in a case where the size of the eighth region is greater than the size of the seventh region, invoking the lock driver to lock remaining regions of the eighth region other than the seventh region.

[0166] In the case where the size of the eighth region is greater than the size of the seventh region, the remaining regions of the eighth region other than the seventh region may be locked. The locking of the remaining regions may allow the cache management apparatus to achieve a precise deallocation of a region where the data to be deallocated is located without interference from adjacent regions, which may ensure data consistency and reliability.

[0167] FIG. 4 is a schematic diagram of a process for cache deallocation in accordance with some embodiments of the present disclosure. A data deallocation process includes steps 401 to 410.

[0168] In step 401, the user application may invoke the public API and pass a pointer q. Accordingly, the public API may receive the pointer q. The pointer q may point to an address of a region to be deallocated from the cache.

[0169] For example, the user application may respond to a line of codes cache Jree (<?), which means that a region in the cache corresponding to the pointer q may need to be deallocated, and the user application may use the pointer q as an address of the region and pass the pointer q to the public API.

[0170] It is noted that the pointer q may refer to the pointer ^ ’mentioned above; the pointer q may also refer to another pointer, and this is not limited thereto.

[0171] In step 402, the public API may invoke the memory allocator and pass the pointer q. Accordingly, the memory allocator may receive the pointer q.

[0172] For example, after receiving the pointer q, the public API may respond to a line of codes q = cache Jree J) which means that the cache management apparatus may need to search for a locked region corresponding to the pointer q, and the public API may invoke the memory allocator and pass the pointer q to the memory allocator.

[0173] In step 403 , the memory allocator may determine a seventh region based on the pointer q.

[0174] The cache management apparatus may invoke the memory allocator to iterate over the first list (i.e., the busy list) to find the seventh region with an address corresponding to the pointer q. There may be two cases as below.

[0175] In a case where the region with an address corresponding to the pointer q is not found, it indicates that the q may be incorrect and the memory allocator may end the process with failure.

[0176] In a case where the region with an address corresponding to the pointer q is found, a size of the region may also be determined as M and the region may be determined as the seventh region to be deallocated.

[0177] In step 404, the memory allocator may remove information of the seventh region from the first list.

[0178] In a case where the seventh region is determined, the memory allocator may remove information of the seventh region from the first list (the busy list). The information may include the address of the seventh region (which may be pointed by the pointer q) and the size of the seventh region (which may be a size M).

[0179] In step 405, the memory allocator may invoke the locked region manager and pass q and M. Accordingly, the locked region manager may receive q and M.

[0180] In step 406, the locked region manager may determine an eighth region based on q.

[0181] For example, the locked region manager may iterate over the third list to search for aregion in the third list that contains pointer q, and identify the region as the eighth region.

[0182] In step 407, the locked region manager may invoke the lock driver and pass a message indicating to unlock the eighth region. Accordingly, the lock driver may receive the message.

[0183] In step 408, the lock driver may unlock the eighth region.

[0184] The lock driver may program the HW to unlock the eighth region. In this case, the locked region manager may also update the third list to remove information of the eighth region from the third list.

[0185] In step 409, the locked region manager may invoke the lock driver and pass a message indicating to lock remaining regions. Accordingly, the lock driver may receive the message.

[0186] The remaining regions refer to regions of the eighth region other than the seventh region. In a case where the size of the eighth region is greater than the size of the seventh region, the remaining regions may be locked.

[0187] In step 410, the lock diver may lock the remaining regions.

[0188] In this case, the locked region manager may also update the third list by adding information of the remaining areas (address of the remaining regions and sizes of the remaining regions) to the third list.

[0189] For steps 408 to 410, according to different situations of overlap between the eighth region (which may also be called a common region) and the seventh region to be deallocated, there may be four cases.

[0190] FIG. 5 is a schematic diagram illustrating different situations of overlap between the common region and the region to be deallocated, in accordance with some embodiments of the present disclosure. An address of the common region (i.e., the eighth region) may be represented as region, pointer, and a size of the common region (i.e., the eighth region) may be represented as region, size. The deallocation algorithm will be described below in conjunction with FIG. 5 according to the different situations of overlap between the eighth region and the seventh region.

[0191] Case A: In a case where q = region, pointer and q + M < region, size, the region [q, q + M) may be unlocked and a region [region. pointer + M, region, pointer + region, size) may be locked.

[0192] Case B: In a case where q > region, pointer and q + M < region, size, the region [q, q + M) may be unlocked, and regions [region. pointer, q) and [q + M, region, pointer + region, size) may be locked.

[0193] Case C: In a casethe region [q, q + M) may be unlocked, and a region [region, pointer, q) may be locked.

[0194] Case D: In a case where q = region, pointer and M= region, size, the region [q, q + M)may be unlocked and there may be no region which needs to be locked.

[0195] The cache management method provided in the embodiments of the present disclosure are described in detail above with reference to FIGS. 1 to 5. Next, the cache management apparatus in the embodiments of the present disclosure will be described in detail below with reference to FIGS. 6 and 7.

[0196] In some embodiments of the present disclosure, an apparatus 600 is provided as shown in FIG. 6.

[0197] The apparatus 600 may have an obtaining module 601 and a processing module 602. In some embodiments, these module may be units. The obtaining module 601 is configured to obtain data having a size of N bytes to be stored; the processing module 602 is configured to invoke a memory allocator to determine a first region having a size equal to N bytes, invoke a locked region manager to determine a second region based on the first size and restrictions of hardware (HW), store the data into the second region, and invoke a lock driver to lock the second region.

[0198] In a possible implementation, the processing module 602 is configured to determine the first region as the second region in a case where the first size satisfies the restrictions of the HW.

[0199] In a possible implementation, the processing module 602 is configured to search for a region of a size satisfying the restrictions of the HW in a case where the first size does not satisfy the restrictions of the HW, and determine the region of the size satisfying the restrictions of the HW as the second region.

[0200] In a possible implementation, the processing module 602 is configured to obtain a second size, based on the first size and a lock granularity required when locking the data in the HW.

[0201] In a possible implementation, the processing module 602 is configured to search for a region of a size and an address both satisfying the restrictions of the HW.

[0202] In a possible implementation, the processing module 602 is configured to obtain a second address, based on an alignment required when storing the data in the HW and a first address of the first region and obtain a second size, based on the first size and a lock granularity required when locking the data in the HW.

[0203] In a possible implementation, the second size is obtained by subtracting a remainder of the first size to the lock granularity from a sum of the first size and the lock granularity.

[0204] In a possible implementation, the processing module 602 is configured to pass a second address of the second region and a second size of the second region to the memory allocator, and invoke the memory allocator to update a first list based on the second address and the second size, where the first list includes addresses and sizes of one or more regions of allocated cache.

[0205] In a possible implementation, the processing module 602 is configured to remove the firstaddress and the first size from the first list, and insert the second address and the second size to the first list.

[0206] In a possible implementation, the processing module 602 is configured to invoke the memory allocator to perform: searching for a third region of a size greater than or equal to ?V bytes in a second list, where the second list includes addresses and sizes of one or more free regions, and the one or more free regions include the third region; splitting the third region into the first region and a fourth region in a case where the size of the third region is greater than N bytes; removing an address of the third region and the size of the third region from the second list; inserting a first address of the first region and the first size to a first list, where the first list includes addresses and sizes of one or more regions of allocated cache; and inserting an address of the fourth region and a size of the fourth region to the first list.

[0207] In a possible implementation, the processing module 602 is configured to determine the third region as the first region in a case where the size of the third region is equal to N bytes.

[0208] In a possible implementation, the processing module 602 is configured to determine whether there exists a fifth region adjacent to the second region, where the fifth region is a locked region and invoke the lock driver to unlock the fifth region if the fifth region exists; and obtain an address of a sixth region, based on a second address of the second region and the address of the fifth region, and a size of the sixth region, based on a second size of the second region and the size of the fifth region, wherein the sixth region is a merged region of the second region and the fifth region; and the processing module 602 is also configured to invoke the lock driver to program the HW to lock the sixth region.

[0209] In a possible implementation, the processing module 602 is configured to search for the fifth region based on the second address of the second region and the second size in a third list, where the third list comprises addresses and sizes of one or more locked regions, and the one or more locked regions comprises the fifth region, and update the third list based on the address of the sixth region and the size of the sixth region.

[0210] In a possible implementation, the processing module 602 is configured to remove the address of the fifth region and the size of the fifth region from the third list; and insert the address of the sixth region and the size of the sixth region to the third list.

[0211] In a possible implementation, the obtaining module 601 is configured to obtain an address of a seventh region to be deallocated; the processing module 602 is configured to invoke the memory allocator to determine a size of the seventh region from one or more regions of allocated cache, invoke the locked region manager to determine an eighth region to be unlocked based on an address of the seventh region, where a size of the eighth region is greater than or equal to thesize of the seventh region; and invoke the lock driver to unlock the eighth region.

[0212] In a possible implementation, in a case where the size of the eighth region is greater than the size of the seventh region, the processing module 602 is configured to invoke the lock driver to lock remaining regions of the eighth region other than the seventh region.

[0213] The apparatus 600 may be equivalent to the cache management apparatus (e.g., a module, a circuit, or a chip in the storage device) mentioned above, and be used to perform the cache management method performed by cache management apparatus. A more detailed description of the apparatus 600 may be referred to the relevant description in the foregoing method embodiment shown in FIG. 2.

[0214] In some embodiments of the present disclosure, another apparatus 700 is provided as shown in FIG. 7.

[0215] The apparatus 700 includes a processor 701 and an interface circuit 702. The processor701 and the interface circuit 702 are coupled to each other. It is understood that the interface circuit702 can be a transceiver or an input / output interface. In some embodiments, the apparatus 700 may also include a memory 703, and the memory 703 is configured to store instructions executed by the processor 701, the input data required by the processor 701 to run the instructions or the data produced after the processor 701 has run the instructions. The interface circuit 702 may also be understood as part of the processor 701, where the apparatus 700 includes the processor 701.

[0216] The apparatus 700 may be equivalent to the cache management apparatus (e.g., a module, a circuit, or a chip in the storage device) mentioned above, and be used to perform the cache management method performed by the cache management apparatus. A more detailed description of the apparatus 700 may be referred to the relevant description in the foregoing method embodiment shown in FIG. 2.

[0217] Some embodiments of the present disclosure provide a computer-readable storage medium (e.g., a non-transitory computer-readable storage medium). The computer-readable storage medium has stored thereon program instructions that, when run on a cache management apparatus, cause the cache management apparatus to execute one or more steps of the method as described in any one of the above embodiments.

[0218] Some embodiments of the present disclosure further provide a computer program product. The computer program product includes program instructions carried on a non-transitory computer-readable storage medium. When executed on a cache management apparatus, the computer program instructions cause the cache management apparatus to perform one or more steps of the method as described in the above embodiments.

[0219] In the present disclosure, the terms "a", "an" and "one" are defined to mean" at least one",that is, these terms do not exclude a plural number of items, unless stated otherwise.

[0220] In the present disclosure, terms such as "substantially", "generally" and "about", which modify a value, condition or characteristic of a feature of an exemplary embodiment, should be understood to mean that the value, condition or characteristic is defined within tolerances that are acceptable for the proper operation of this exemplary embodiment for its intended application.

[0221] In the present disclosure, unless stated otherwise, the terms "connected" and "coupled", and derivatives and variants thereof, refer herein to any structural or functional connection or coupling, either direct or indirect, between two or more elements. For example, the connection or coupling between the elements can be acoustical, mechanical, optical, electrical, thermal, logical, or any combinations thereof.

[0222] In the present disclosure, expressions such as "match", "matching" and "matched", including variants and derivatives thereof, are intended to refer herein to a condition in which two or more elements are either the same or within some predetermined tolerance of each other. That is, these terms are meant to encompass not only "exactly" or "identically" matching the two elements but also "substantially", "approximately or" subjectively "matching the two or more elements, as well as providing a higher or best match among a plurality of matching possibilities.

[0223] In the present disclosure, the expression "based on" is intended to mean "based at least partly on", that is, this expression can mean "based solely on or" based partially on ", and so should not be interpreted in a limited manner. More particularly, the expression "based on" could also be understood as meaning "depending on", "representative of', "indicative of, "associated with" or similar expressions.

[0224] In the present disclosure, the terms "system" and "network" may be used interchangeably in embodiments of this application. "At least one" means one or more, and "a plurality of means two or more. The term "and / or" describes an association relationship of associated objects, and indicates that three relationships may exist. For example, A and / or B may indicate the following three cases: only A exists, both A and B exist, and only B exists, where A and B may be singular or plural. The character " / " usually indicates an "or" relationship between associated objects. "At least one of the following items (pieces)" or a similar expression thereof indicates any combination of these items, including a single item (piece) or any combination of a plurality of items (pieces). For example, "at least one of A, B, or C" includes A, B, C, A and B, A and C, B and C, or A, B, and C, and "at least one of A, B, and C" may also be understood as including A, B, C, A and B, A and C, B and C, or A, B, and C. In addition, unless otherwise specified, ordinal numbers such as "first" and "second" in embodiments of this application are used to distinguish between a plurality of objects, and are not used to limit a sequence A time sequence, priorities, or importance of theplurality of objects.

[0225] A person skilled in the art should understand that embodiments of this application may be provided as a method, an apparatus (or system), computer-readable storage medium, or a computer program product. Therefore, this application may use a form of a hardware-only embodiment, a software-only embodiment, or an embodiment with a combination of software and hardware. Moreover, this application may use a form of a computer program product that is implemented on one or more computer-usable storage media (including but not limited to a disk memory, an optical memory, and the like) that include computer-usable program code.

[0226] This application is described with reference to the flowcharts and / or block diagrams of the method, the device (system), and the computer program product according to this application. It should be understood that computer program instructions may be used to implement each process and / or each block in the flowcharts and / or the block diagrams and a combination of a process and / or a block in the flowcharts and / or the block diagrams. The computer program instructions may be provided for a general-purpose computer, a dedicated computer, an embedded processor, or a processor of another programmable data processing device to generate a machine, so that the instructions executed by the computer or the processor of the another programmable data processing device generate an apparatus for implementing a specific function in one or more procedures in the flowcharts and / or in one or more blocks in the block diagrams.

[0227] The computer program instructions may alternatively be stored in a computer-readable memory that can indicate a computer or another programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate an artifact that includes an instruction apparatus. The instruction apparatus implements a specific function in one or more procedures in the flowcharts and / or in one or more blocks in the block diagrams.

[0228] The computer program instructions may alternatively be loaded onto a computer or another programmable data processing device, so that a series of operations and steps are performed on the computer or the another programmable device, so that computer-implemented processing is generated. Therefore, the instructions executed on the computer or the another programmable device provide steps for implementing a specific function in one or more procedures in the flowcharts and / or in one or more blocks in the block diagrams.

[0229] It is clearly that a person skilled in the art can make various modifications and variations to this application without departing from the scope of this application. This application is intended to cover these modifications and variations of this application provided that they fall within the scope of protection defined by the following claims and their equivalent technologies.

Claims

PCI7RU2024 / 000350CLAIMS1. A cache management method comprising: obtaining data having a size of A bytes to be stored; invoking a memory allocator to determine a first region having a first size equal to A bytes; invoking a locked region manager to determine a second region based on the first size and restrictions of hardware (HW); storing the data into the second region; and invoking a lock driver to lock the second region.

2. The method of any of claim 1, wherein determining the second region comprises: determining the first region as the second region in a case where the first size satisfies the restrictions of the HW.

3. The method of claim 1, wherein determining the second region comprises: searching for a region of a size satisfying the restrictions of the HW in a case where the first size does not satisfy the restrictions of the HW; and determining the region of the size satisfying the restrictions of the HW as the second region.

4. The method of claim 3, wherein searching for the region of the size satisfying the restrictions of the HW comprises: obtaining a second size, based on the first size and a lock granularity required when locking the data in the HW.

5. The method of claim 3, wherein searching for the region of the size satisfying the restrictions of the HW comprises: searching for a region of a size and an address both satisfying the restrictions of the HW.

6. The method of claim 5, wherein searching for the region of the size and the address both satisfying the restrictions of the HW comprises: obtaining a second address, based on an alignment required when storing the data in the HW and a first address of the first region; obtaining a second size, based on the first size and a lock granularity required when locking the data in the HW.

7. The method of claim 6, wherein a value corresponding to the second address is obtained by subtracting a remainder of the first address to the alignment from a sum of the first address and the alignment.

8. The method of any of claims 4, 6 and 7, wherein the second size is obtained by subtracting a remainder of the first size to the lock granularity from a sum of the first size and the lock granularity.

9. The method of any of claims 3 to 8, further comprising: passing a second address of the second region and a second size of the second region to the memory allocator; and invoking the memory allocator to update a first list based on the second address and the second size, wherein the first list comprises addresses and sizes of one or more regions of allocated cache.

10. The method of claim 9, wherein updating the first list comprises: removing the first address and the first size from the first list; and inserting the second address and the second size to the first list.

11. The method of any of claims 1 to 10, wherein invoking the memory allocator to determine the first region comprises: invoking the memory allocator to perform: searching for a third region of a size greater than or equal to N bytes in a second list, wherein the second list comprises addresses and sizes of one or more free regions, and the one or more free regions comprise the third region; splitting the third region into the first region and a fourth region in a case where the size of the third region is greater than N bytes; removing an address of the third region and the size of the third region from the second list; inserting a first address of the first region and the first size to a first list, wherein the first list comprises addresses and sizes of one or more regions of allocated cache; and inserting an address of the fourth region and a size of the fourth region to the first list.

12. The method of claim 11, further comprising: determining the third region as the first region in a case where the size of the third region is equal to JV bytes.

13. The method of any of claims 1 to 12, wherein invoking the lock driver to lock the second region comprises: determining whether there exists a fifth region adjacent to the second region, wherein the fifth region is a locked region; invoking the lock driver to unlock the fifth region if the fifth region exists; obtaining an address of a sixth region, based on a second address of the second region and the address of the fifth region, and a size of the sixth region, based on a second size of the second region and the size of the fifth region, wherein the sixth region is a merged region of the second region and the fifth region; andinvoking the lock driver to lock the sixth region.

14. The method of claim 13, wherein determining whether there exists the fifth region adjacent to the second region comprises: searching for the fifth region based on the second address of the second region and the second size in a third list, wherein the third list comprises addresses and sizes of one or more locked regions, and the one or more locked regions comprises the fifth region; and the method further comprising: updating the third list based on the address of the sixth region and the size of the sixth region.

15. The method of claim 14, wherein updating the third list based on the address of the sixth region and the size of the sixth region comprises: removing the address of the fifth region and the size of the fifth region from the third list; and inserting the address of the sixth region and the size of the sixth region to the third list.

16. The method of any of claims 1 to 15, further comprising: obtaining an address of a seventh region to be deallocated; invoking the memory allocator to determine a size of the seventh region from one or more regions of allocated cache; invoking the locked region manager to determine an eighth region to be unlocked based on an address of the seventh region, wherein a size of the eighth region is greater than or equal to the size of the seventh region; and invoking the lock driver to unlock the eighth region.

17. The method of claim 16, further comprising: in a case where the size of the eighth region is greater than the size of the seventh region, invoking the lock driver to lock remaining regions of the eighth region other than the seventh region.

18. An apparatus, comprising: one or more processors; a memory storing instructions which, when executed by the one or more processors, cause the apparatus to perform the method of any one of claims 1 to 17.

19. A computer-readable storage medium having instructions stored thereon which, when executed by one or more processors, cause the one or more processors to perform the method of any one of claims 1 to 17.

20. A computer program product storing instructions which, when executed, cause an apparatus to perform the method of any one of claims 1 to 17.

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