Surface-mounted inductor and wafer-level manufacturing method thereof
A surface-mount, wafer-level technology, applied in the field of surface-mount inductance devices and their wafer-level manufacturing, can solve the problems of difficult ultra-thin packaging, reduced assembly yield, and low inductance accuracy, and achieve high density The effect of mounting, improving inductance accuracy, and improving dimensional accuracy
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Publication Date
- 2013-11-20
Smart Images
Figure 1 Figure 2 Figure 3
Abstract
Description
technical field
[0001] The invention relates to a surface-mounted inductance device and a wafer-level manufacturing method thereof, belonging to the field of passive device manufacturing. Background technique
[0002] Inductors are essential components in electronic devices. With the miniaturization trend of electronic devices, especially handheld electronic devices such as mobile phones, the size of inductors is getting smaller and smaller. At present, the RF inductor models for wireless communication mainly have 0201 size and 0402 size (imperial system). Among them, the package length of the 0201 size model is between 500 microns and 700 microns, the width is between 250 microns and 350 microns, and the height is 250 microns. Microns to 350 microns; 0402 size models have packages with lengths between 900 microns and 1100 microns, widths between 400 microns and 600 microns, and heights between 450 microns and 550 microns. Traditional inductors are mainly made by multi-lay...
Examples
Embodiment 1
[0057] see Figure 4 and Figure 5 , a surface mount inductance device of the present invention, the metal wiring layer 200 is disposed on the surface of the substrate 110, Figure 5 In the metal wiring layer 200, only the metal wiring layer I 210 and the metal wiring layer II 220 are shown as an example. The metal wiring layer II 220 is arranged above the metal wiring layer I 210, and the two are connected through the dielectric layer via hole 401 to realize electrical communication. . The metal wiring layer I 210 and the metal wiring layer II 220 respectively extend to the electrode regions on both sides, and are respectively connected to the electrodes 300 of equal height on both sides. A metal protection layer 600 is provided inside the surface protection layer opening pattern 501. The metal protection layer 600 extends downwards to wrap the sidewall of the electrode 300. The material of the metal protection layer 600 is an inert metal such as nickel or gold. The metal p...
Embodiment 2
[0059] see Figure 4 and Figure 6 , a surface mount inductance device of the present invention differs from the first embodiment as follows, a passivation layer 700 may also be provided between the substrate 110 and the metal wiring layer 200 to improve the reliability of the inductance device. Figure 6 In the metal wiring layer 200, only the metal wiring layer I 210 and the metal wiring layer II 220 are shown as an example. The metal wiring layer II 220 is arranged above the metal wiring layer I 210, and the two are connected through the dielectric layer via hole 401 to realize electrical communication. . The metal wiring layer I 210 and the metal wiring layer II 220 respectively extend to the electrode areas on both sides, and are respectively connected to the electrodes 300 of equal height on both sides. If necessary, the metal wiring layer I 210 and the metal wiring layer II 220 can be bent. The cross-section of the surface protection layer opening pattern 501 is recta...