Storage devices

Abstract

A memory device includes: multiple gate electrode layers stacked on a substrate; multiple channel layers passing through the multiple gate electrode layers; a gate insulating layer between the multiple gate electrode layers and the multiple channel layers; and a common source line adjacent to the gate electrode layers on the substrate. The common source line includes a first portion and a second portion arranged alternately in a first direction and having different heights in a direction perpendicular to the top surface of the substrate. The gate insulating layer includes a plurality of vertical portions and a horizontal portion. The plurality of vertical portions surround corresponding channel layers among the plurality of channel layers. The horizontal portion extends parallel to the top surface of the substrate.

Description

Technical Field

[0001] Example embodiments of the inventive concepts relate to memory devices. Background Art

[0002] A three-dimensional memory device includes multiple memory cells arranged vertically relative to a substrate to form a vertical NAND string structure. In some three-dimensional flash memories, a NAND string can be constructed vertically, stacking the individual FETs of the string on top of each other so that the string extends out from the substrate. Summary of the Invention

[0003] Example embodiments of the inventive concepts provide memory devices having increased integration density.

[0004] According to some example embodiments of the inventive concept, a memory device may include: a substrate; a plurality of gate electrode layers stacked on the substrate; a plurality of channel layers passing through the plurality of gate electrode layers; a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers; and a common source line adjacent to the plurality of gate electrode layers on the substrate. The common source line includes a first portion and a second portion alternately arranged in a first direction and having different heights in a direction perpendicular to a top surface of the substrate. The gate insulating layer may include a plurality of vertical portions and a horizontal portion. The plurality of vertical portions may surround corresponding channel layers among the plurality of channel layers. The horizontal portion may be below the plurality of gate electrode layers and may extend parallel to the top surface of the substrate.

[0005] According to some example embodiments of the inventive concept, a memory device may include: a substrate; a plurality of gate structures on the substrate, each of the plurality of gate structures including a plurality of gate electrode layers and a plurality of insulating layers alternately stacked on the substrate; a plurality of channel layers extending in a direction perpendicular to a top surface of the substrate; a charge storage layer; and a horizontal channel layer. The plurality of channel layers may pass through the plurality of gate structures. The charge storage layer may include a vertical portion and a horizontal portion. The vertical portion may be outside a corresponding channel layer in the plurality of channel layers of each of the plurality of gate structures. The horizontal portion may extend from the vertical portion to underlie each gate structure. The horizontal channel layer may be under the horizontal portion of the charge storage layer. The horizontal channel layer may connect the plurality of channel layers to each other and contact the substrate.

[0006] According to some example embodiments of the inventive concept, a memory device may include: a substrate; a plurality of gate structures on the substrate, each of the plurality of gate structures including a plurality of gate electrode layers stacked on the substrate; a plurality of channel layers extending perpendicular to a top surface of the substrate through the plurality of gate electrode layers of corresponding gate structures; a horizontal channel layer connecting the plurality of channel layers to the substrate below the plurality of gate structures; a charge storage layer between the plurality of gate electrode layers and the plurality of channel layers and on a top surface of the horizontal channel layer; and a common source line on the substrate between the plurality of gate structures and extending in a first direction parallel to the top surface of the substrate. The substrate may include a first impurity region below the horizontal channel layer and a second impurity region between the common source line and the horizontal channel layer, the first impurity region and the second impurity region may include carbon.

[0007] According to some example embodiments of the inventive concept, a memory device may include a stacked structure on a substrate. The stacked structure may include: a gate insulating layer including a horizontal portion extending parallel to the top surface of the substrate and a plurality of vertical portions spaced apart from each other and extending vertically above the top surface of the substrate; a plurality of channel layers surrounded by the plurality of vertical portions of the gate insulating layer and extending perpendicularly to the top surface of the substrate; a plurality of gate electrode layers and insulating layers alternately stacked on top of each other on the horizontal portion of the gate insulating layer; a plurality of strings; and a horizontal channel layer. The plurality of strings may be defined by the gate insulating layer, the plurality of channel layers, and the plurality of gate electrode layers, each string may include a plurality of memory cells stacked on top of each other between a ground select transistor and a string select transistor. The horizontal channel layer may connect at least some of the plurality of channel layers to each other and may extend between a lower surface of the horizontal portion of the gate insulating layer and the top surface of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic block diagram illustrating a memory device according to some example embodiments of the inventive concept.

[0009] Figure 2 is a circuit diagram illustrating a memory cell array of a memory device according to some example embodiments of the inventive concept.

[0010] Figure 3 are schematic plan views illustrating memory devices according to some example embodiments of the inventive concept.

[0011] Figure 4 and 5 Some example embodiments according to the inventive concept are shown. Figure 3 A perspective view of a portion of a storage device.

[0012] Figure 6 According to some exemplary embodiments of the inventive concept Figure 4An enlarged cross-sectional view of portion A of FIG.

[0013] Figure 7 According to some exemplary embodiments of the inventive concept Figure 3 A cross-sectional view taken along line II'.

[0014] Figure 8 According to some exemplary embodiments of the inventive concept Figure 3 A cross-sectional view taken along line II-II'.

[0015] Figure 9 According to some exemplary embodiments of the inventive concept Figure 3 A cross-sectional view taken along line II'.

[0016] Figure 10 According to some exemplary embodiments of the inventive concept Figure 3 A cross-sectional view taken along line II'.

[0017] Figure 11 are perspective views illustrating memory devices according to some example embodiments of the inventive concepts.

[0018] Figures 12 to 59 are cross-sectional views illustrating a method of manufacturing a memory device according to some example embodiments of the inventive concept.

[0019] Figure 60 is a schematic block diagram illustrating an electronic apparatus including a memory device according to some example embodiments of the inventive concept. DETAILED DESCRIPTION

[0020] Example embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which some example embodiments are shown. Example embodiments of the inventive concept may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

[0021] Figure 1 is a schematic block diagram illustrating a memory device according to some example embodiments of the inventive concept.

[0022] Reference Figure 1 , a memory device 1 according to some example embodiments of the inventive concept may include a memory cell array 2 , a row decoder 3 , and a core logic circuit 6 . The core logic circuit 6 may include a read / write circuit 4 and a control circuit 5 .

[0023] The memory cell array 2 may include a plurality of memory cells arranged in rows and columns. The plurality of memory cells may be connected to a row decoder 3 via word lines WL, a common source line CSL, a string select line SSL, and a ground select line GSL, and may be connected to a read / write circuit 4 via bit lines BL. In some example embodiments, a plurality of memory cells arranged along the same row may be connected to the same word line WL, and a plurality of memory cells arranged along the same column may be connected to the same bit line BL.

[0024] The plurality of memory cells included in the memory cell array 2 may be divided into a plurality of memory blocks. Each block may include a plurality of word lines WL, a plurality of string selection lines SSL, a plurality of ground selection lines GSL, a plurality of bit lines BL, and at least one common source line CSL.

[0025] The row decoder 3 may receive address information ADDR from the outside and may decode the received address information ADDR to determine voltages supplied to at least some of the word lines WL, common source lines CSL, string selection lines SSL, and ground selection lines GSL connected to the memory cell array 2 .

[0026] The read / write circuit 4 can select at least some of the bit lines BL connected to the memory cell array 2 according to a command received from the control circuit 5. The read / write circuit 4 can read data stored in the memory cells connected to the selected at least some of the bit lines BL and can write data to the memory cells connected to the selected at least some of the bit lines BL. The read / write circuit 4 may include circuits such as a page buffer, an input / output buffer, or a data latch to perform at least the above operations.

[0027] The control circuit 5 can control the operation of the row decoder 3 and the read / write circuit 4 in response to a control signal CTRL transmitted from the outside. When reading data stored in the memory cell array 2, the control circuit 5 can control the operation of the row decoder 3 to supply a read voltage to the word line WL connected to the memory cell in which the data to be read is stored. When the read voltage is supplied to a certain word line WL, the control circuit 5 can control the read / write circuit 4 to read the data stored in the memory cell connected to the certain word line WL.

[0028] When writing data into the memory cell array 2, the control circuit 5 can control the operation of the row decoder 3 to supply a write voltage to the word line WL connected to the memory cell into which the data is to be written. When the write voltage is supplied to a certain word line WL, the control circuit 5 can control the read / write circuit 4 to write data into the memory cell connected to the certain word line WL.

[0029] Figure 2is a circuit diagram illustrating a memory cell array of a memory device according to some example embodiments of the inventive concept. In some example embodiments, the memory device may be a vertical NAND flash memory device (or a three-dimensional NAND flash memory device).

[0030] Reference Figure 2 The memory cell array may include: a plurality of memory cell strings S, each including n memory cells MC1-MCn (n is a natural number); and a ground selection transistor GST and a string selection transistor SST connected in series to both ends of the memory cells MC1-MCn. The n memory cells MC1-MCn connected in series to each other may be connected to n word lines WL1-WLn for selecting the memory cells MC1-MCn. According to some example embodiments, a dummy cell may be further provided between the first memory cell MC1 and the ground selection transistor GST, and between the nth memory cell MCn and the string selection transistor SST.

[0031] The gate terminal of the ground selection transistor GST may be connected to the ground selection line GSL, and the source terminal thereof may be connected to the common source line CSL. The gate terminal of the string selection transistor SST may be connected to the string selection line SSL, and the source terminal of the string selection transistor SST may be connected to the drain terminal of the n-th memory cell MCn. In some example embodiments, a single ground transistor GST and a single string selection transistor SST may be connected to a common source line CSL. Figure 2 In other example embodiments, a plurality of grounding transistors GST and a plurality of string selection transistors SST may be connected to the n memory cells MC1 -MCn connected in series with each other.

[0032] The drain terminal of the string select transistor SST can be connected to a plurality of bit lines BL1-BLm. When a signal is applied to the gate terminal of the string select transistor SST via the string select line SSL, the signal applied via the bit lines BL1-BLm can be transmitted to the n memory cells MC1-MCn connected in series, thereby performing data read operations and data write operations. By applying a certain erase voltage to a well formed in the substrate, an erase operation can be performed to erase the data written in the memory cells MC1-MCn.

[0033] In some example embodiments, a memory device may include at least one dummy string DS. The dummy string DS may be a string including a dummy channel electrically separated from the bit lines BL1-BLm.

[0034] Figure 3 are schematic plan views illustrating memory devices according to some example embodiments of the inventive concept.

[0035] Reference Figure 3, the memory device 100 according to some example embodiments of the inventive concept may include a plurality of channel structures CH and a plurality of dummy channel structures DCH separated from each other in a plan view. The dummy channel structures DCH may not be electrically connected to the bit lines, unlike the channel structures CH. The channel structures CH and the dummy channel structures DCH may extend in a direction (Z direction) perpendicular to the top surface (XY plane) of the substrate to pass through the plurality of gate electrode layers and the insulating interlayer 170.

[0036] The plurality of gate electrode layers may be divided into a plurality of unit structures by a common source line 150. Spacers 109 may be provided on the sidewalls of the common source line 150 to separate the common source line 150 from the plurality of gate electrode layers. A separation insulating layer 155 may be provided between adjacent common source lines 150. In some example embodiments, the separation insulating layer 155 may divide at least one of the plurality of gate electrode layers. A dummy channel structure DCH may pass through the separation insulating layer 155.

[0037] The common source line 150 may extend in the Z direction and in a first direction (X direction) parallel to the top surface (XY plane) of the substrate. The common source line 150 may be connected to the source region in the substrate. In some example embodiments of the inventive concept, multiple support regions 105 may be provided in a portion of the substrate, so that the common source line 150 may include multiple portions having different heights.

[0038] Figure 4 and 5 Some example embodiments according to the inventive concept are shown. Figure 3 1 is a perspective view of a portion of a memory device 100.

[0039] Reference Figure 4 and 5 The memory device 100 may include: a substrate 101; a plurality of gate electrode layers 131-138 (130) and a plurality of insulating layers 141-149 (140) stacked on the substrate 101, for example, stacked on the top surface of the substrate 101; and a plurality of channel layers 110 passing through the plurality of gate electrode layers 130 and the plurality of insulating layers 140. A gate insulating layer 160 may be provided between the plurality of gate electrode layers 130 and the plurality of channel layers 110.

[0040] The gate insulating layer 160 may include a blocking layer 162, a charge storage layer 164, and a tunnel layer 166 sequentially arranged in a direction extending from the gate electrode layer 130 to the channel layer 110. The gate insulating layer 160 may further include an additional blocking layer 168 between the blocking layer 162 and the gate electrode layer 130. In some example embodiments, the additional blocking layer 168 may be omitted.

[0041] The plurality of gate electrode layers 130, each of the plurality of channel layers 110, and the gate insulating layer 160 may constitute a ground selection transistor GST, memory cells MC1-MCn, and a string selection transistor SST. The number of the ground selection transistor GST and the string selection transistor SST may be determined from Figure 4 and 5 As shown in the variation, the ground select transistor GST and the string select transistor SST may have a different structure from the memory cells MC1 -MCn.

[0042] The multiple channel layers 110 may form multiple channel structures CH or multiple dummy channel structures DCH, respectively. The multiple channel structures CH and the multiple dummy channel structures DCH may have similar structures. As an example, the channel structure CH and the dummy channel structure DCH may include a channel layer 110, a buried insulating layer 115 inside the channel layer 110, a gate insulating layer 160 on the outer sidewalls of the channel layer 110, and a drain region 113 on the top of the channel layer 110.

[0043] The channel layer 110 may have a hollow cylindrical shape. In some example embodiments, the channel layer 110 may not have a space therein. In some example embodiments, the buried insulating layer 115 may be omitted. Figure 4 and Figure 5 As shown, the blocking layer 162, the charge storage layer 164, and the tunnel layer 166 may surround the outer sidewalls of the channel layer 110, and the additional blocking layer 168 may surround the plurality of gate electrode layers 130. In some example embodiments, the gate insulating layer 160 without the additional blocking layer 168 may surround the outer sidewalls of the channel layer 110. The buried insulating layer 115 may extend a greater distance into the substrate 101 than the gate insulating layer 160 and the plurality of channel layers 110.

[0044] The common source line 150 may extend in the Z direction and the first direction (X direction). The common source line 150 may be connected to the source region 108 thereunder. The source region 108 may be an impurity region formed by implanting impurities (eg, n-type impurities) into the substrate 101 .

[0045] Reference Figure 4, the common source line 150 may include a first portion 151 and a second portion 152 having different heights in the Z direction. The height of the second portion 152 may be greater than the height of the first portion 151. The substrate 101 may include a plurality of support regions 105 protruding vertically toward the common source line 150. The plurality of support regions 105, each below the first portion 151, may be arranged in the first direction (X direction). In the manufacturing process of the memory device 100, the plurality of support regions 105 may be formed before forming the common source line 150, and the first portion 151 may be defined as a portion of the common source line 150 located on the plurality of support regions 105. The bottom surface of the first portion 151 may contact the top surfaces of the plurality of support regions 105. Due to the plurality of support regions 105, the thickness of the substrate 101 below the first portion 151 may be greater than the thickness of the substrate 101 below the second portion 152.

[0046] At least a portion of the gate insulating layer 160 may be disposed on the top surface of the substrate 101. That is, at least a portion of the gate insulating layer 160 may be located between the top surface of the substrate 101 and the lowermost insulating layer 141 in the Z direction. Figure 5 (which shows a structure in which a portion of the gate electrode layer 130 and a portion of the insulating layer 140 are removed), a portion of the blocking layer 162 , a portion of the tunnel layer 166 , and a portion of the charge storage layer 164 may be located on the top surface of the substrate 101 .

[0047] In some example embodiments of the inventive concept, in each unit structure defined as a region between adjacent common source lines 150, at least one layer (e.g., charge storage layer 164) included in the gate insulating layer 160 may include a horizontal portion disposed on the top surface of the substrate 101 and a vertical portion surrounding the outer sidewall of the corresponding channel layer 110 and perpendicular to the top surface of the substrate 101. The horizontal portion may be defined as a layer extending parallel to the top surface of the substrate 101. For example, the horizontal portion may have a plate shape. Referring to Figure 4 and Figure 5 , blocking layer 162, charge storage layer 164, and tunnel layer 166 may each include a horizontal portion extending parallel to the top surface of substrate 101 and a vertical portion surrounding channel layer 110. The vertical portions surrounding the corresponding channel layer 110 of each of blocking layer 162, charge storage layer 164, and tunnel layer 166 may be connected to each other through their corresponding horizontal portions. Multiple vertical portions of each of blocking layer 162, charge storage layer 164, and tunnel layer 166 may be connected through a single horizontal portion of each of blocking layer 162, charge storage layer 164, and tunnel layer 166.

[0048] The plurality of channel layers 110, each disposed inside the gate insulating layer 160, may be directly connected to the substrate 101. As an example, the plurality of channel layers 110 may be connected to each other through a horizontal channel layer in the substrate 101.

[0049] Figure 6 According to some exemplary embodiments of the inventive concept Figure 4 An enlarged cross-sectional view of portion A of FIG.

[0050] Reference Figure 6 According to some example embodiments of the inventive concept, a substrate 101 may include a first region 102, a second region 103, and a third region 104. The first to third regions 102, 103, and 104 may have the same or different crystal structures. As an example, the first to third regions 102, 103, and 104 may include polycrystalline silicon.

[0051] In some example embodiments, at least one layer included in the gate insulating layer 160 may be connected to each other on the top surface of the substrate 101. As an example, the blocking layer 162, the charge storage layer 164, and the tunnel layer 166 may each include a horizontal portion extending parallel to the top surface of the substrate 101 and a vertical portion surrounding the channel layer 110. The vertical portions of the blocking layer 162, the charge storage layer 164, and the tunnel layer 166 may each be connected to each other through their corresponding horizontal portions.

[0052] A portion of the gate insulating layer 160 may be provided as a retained portion 162a, 164a, and 166a. The number of layers included in the retained portions 162a, 164a, and 166a may be equal to or less than the number of layers included in the horizontal portion. The retained portions 162a, 164a, and 166a may be formed from portions of the blocking layer 162, the charge storage layer 164, and the tunnel layer 166 that remain below the buried insulating layer 115 during the manufacturing process of the memory device 100.

[0053] The memory device 100 may include a horizontal channel layer 110h. The horizontal channel layer 110h connects the plurality of channel layers 110 extending in the Z direction below the plurality of gate electrode layers 130 and the plurality of insulating layers 140. In some example embodiments, the horizontal channel layer 110h may directly contact the second region 103 of the substrate 101 and may include polysilicon. Thus, the plurality of channel layers 110 may be connected to the substrate 101 through the horizontal channel layer 110h. The horizontal channel layer 110h may be disposed below a horizontal portion of at least one layer of the gate insulating layer 160 (e.g., a horizontal portion of the charge storage layer 164). The horizontal portion of at least one layer of the gate insulating layer 160 may not extend above the bottom surface of the horizontal channel layer 110h.

[0054] Figure 7According to some exemplary embodiments of the inventive concept Figure 3 A cross-sectional view taken along line II'. Figure 8 According to some exemplary embodiments of the inventive concept Figure 3 A cross-sectional view taken along line II-II'.

[0055] Reference Figure 7 and 8 The memory device 100 may include a plurality of gate structures GS, each gate structure GS including a plurality of gate electrode layers 131-138 and a plurality of insulating layers 141-149. The plurality of gate structures GS may be arranged on the substrate 101 to be separated from each other by a common source line 150, and the plurality of gate electrode layers 131-138 and the plurality of insulating layers 141-149 may be alternately and repeatedly stacked on top of each other.

[0056] An insulating interlayer 170 may be disposed on the plurality of gate structures GS. The insulating interlayer 170 may be formed of an insulating material such as silicon nitride or silicon oxide and may be disposed on a peripheral circuit device 180 in the peripheral circuit region. The peripheral circuit device 180 may be covered by a lower insulating interlayer 171, and the insulating interlayer 170 may be disposed on the lower insulating interlayer 171.

[0057] Peripheral circuit device 180 may include a planar transistor including peripheral source / drain regions 181 , peripheral gate electrode 182 , peripheral gate insulating layer 183 , and peripheral spacer 184 . Peripheral gate electrode 182 and peripheral source / drain regions 181 may be connected to contacts 185 .

[0058] The plurality of channel layers 110 may pass through each of the plurality of gate structures GS and may be connected to each other through the horizontal channel layer 110h under each of the plurality of gate structures GS. The plurality of channel layers 110 may be directly connected to the substrate 101 under the gate structures GS.

[0059] The horizontal portions of the blocking layer 162, the charge storage layer 164, and the tunnel layer 166 may be located between the horizontal channel layer 110h and the gate structure GS. The horizontal portions may not extend under the horizontal channel layer 110h. In some example embodiments, the horizontal portions may not be formed under the horizontal channel layer 110h.

[0060] The substrate 101 may include first to third regions 102, 103, and 104. In some example embodiments, the first to third regions 102, 103, and 104 of the substrate 101 may be regions formed in separate processing steps and include the same material or different materials. The first to third regions 102, 103, and 104 may include polycrystalline silicon.

[0061] In the memory device 100, a plurality of support regions 105 under the common source line 150 between the plurality of gate structures GS may protrude upward from the first region 102. The plurality of support regions 105 may be used to restrict and / or prevent the collapse of the gate structure DS during the manufacturing process of the memory device 100. The plurality of support regions 105 may have a width greater than that of the common source line 150 in a second direction (Y direction) perpendicular to the first direction (X direction) and may be arranged in the first direction (X direction), as shown in FIG. Figures 3 to 5 A plurality of support regions 105 may be disposed between the first region 102 and the third region 104 of the substrate 101 .

[0062] The substrate 101 may include an impurity region containing carbon. In some example embodiments, a portion of the upper portion of the first region 102 adjacent to the interface between the second region 103 and the first region 102 may contain carbon (or a portion of the upper portion of the first region 102 may be a carbon-doped region). The third region 104 may also contain carbon (or the third region 104 may be a carbon-doped region). The third region 104 may have a smaller width in the second direction (Y direction) than the carbon-doped region in the first region 102. Since the substrate 101 contains carbon, it is possible to limit and / or prevent the substrate 101 from being undesirably etched during the manufacturing process of the memory device 100.

[0063] In such Figure 7 and 8 In the cross-section along line II' and the cross-section along line II-II' shown, the common source line 150 may have different heights due to the support area 105. The bottom surface of the common source line 150 in the cross-section along line II-II' may be located at a higher level than in the cross-section along line II'. Therefore, the common source line 150 may include multiple portions having different heights in the Z direction. The multiple portions may be alternately arranged in the first direction (X direction). The portion with a relatively small height among the multiple portions may be arranged on multiple support areas 105. The source region 108 may be arranged below the common source line 150 and may be connected to the common source line 150. The source region 108 may have an uneven or curved top surface along the first direction (X direction) due to the multiple support areas 105.

[0064] Figure 9 According to some example embodiments, Figure 3 A cross-sectional view taken along line II'. Figure 10 According to some example embodiments, Figure 3 A cross-sectional view taken along line II-II'.

[0065] according to Figure 9 and 10In some example embodiments of the inventive concept shown, the substrate 101' may include at least one void Vo therein. The void Vo may be formed in the second region 103'. In some example embodiments, the void Vo may be an air gap. Figures 6 to 8 The remaining portions 162a, 164a, and 166a shown between the buried insulating layer 115 and the first region 102 may not be formed by structural differences occurring in the process for forming the second region 103'. In addition to the second region 103', a void Vo may also be formed in the horizontal channel layer 110h.

[0066] Figure 11 are perspective views illustrating memory devices according to some example embodiments of the inventive concepts.

[0067] Reference Figure 11 , the memory device 200 may include a cell-on-periphery (COP) structure, in which a peripheral circuit region including a peripheral circuit device 280 is disposed below a cell region including a plurality of memory cells MC1-MCn. The peripheral circuit device 280 may be disposed on the second substrate 207 and may be covered by a second insulating interlayer 271. The peripheral source / drain regions 281 and the peripheral gate electrode 282 included in the peripheral circuit device 280 may be connected to an interconnection pattern 285. The second insulating interlayer 271 may be formed of silicon oxide or silicon nitride.

[0068] The cell region may include a first substrate 201. The first substrate 101 may be disposed on a second insulating interlayer 271. In the cell region, a plurality of gate electrode layers 231-238 (230) and a plurality of channel layers 210 may be disposed to provide a plurality of memory cells MC1-MCn. The plurality of gate electrode layers 230 may be divided into a plurality of unit structures by a common source line 250. The common source line 250 may include a first portion 251 and a second portion 252.

[0069] The first portion 251 may be smaller in height than the second portion 252. The first portion 251 and the second portion 252 may be alternately arranged along the first direction (X direction). The first portion 251 may be provided on the plurality of support regions 205 and may have a smaller height than the second portion 252 due to the thickness of the support regions 205. The common source line 250 may be connected to the source region 208 in the substrate 201. The source region 208 may have an uneven or curved top surface along the first direction due to the plurality of support regions 205.

[0070] Figures 12 to 59 are cross-sectional views illustrating a method of manufacturing a memory device according to some example embodiments of the inventive concept. Figure 12 、 14, 16, 18, 20, 22, 24, 27, 30, 33, 36, 39, 42, 45, 48, 51, 54, and 57 are plan views illustrating methods of forming memory devices according to some example embodiments of the inventive concept. Figure 13 、 15 , 17, 19, 21 and 25 are respectively along Figure 12 、 14 , 16 , 18 , 20 and 22 are cross-sectional views taken along line IV-IV′. Figure 26 It is along Figure 24 A cross-sectional view taken along line V-V'. Figure 28 、 31 , 34, 37, 40, 43, 46, 49, 52, 55 and 58 are respectively along Figure 7 、 30 , 33 , 36 , 39 , 42 , 45 , 48 , 51 , 54 and 57 are cross-sectional views taken along line IV-IV′. Figure 29 、 32 , 35, 38, 41, 44, 47, 50, 53, 56 and 59 are respectively along Figure 7 、 30 , 33 , 36 , 39 , 42 , 45 , 48 , 51 , 54 and 57 are cross-sectional views taken along line VI-VI′.

[0071] Reference Figure 12 and 13 , a peripheral circuit device 380 may be formed on the first region 302 in the peripheral region P. The peripheral circuit device 380 may include a peripheral source / drain region 381, a peripheral gate electrode 182, a peripheral gate insulating layer 383, and a peripheral spacer 384. The peripheral circuit device 380 may be covered by a lower insulating interlayer 371. The lower insulating interlayer 371 may include a material having excellent gap-filling properties such as a high-density plasma (HDP) oxide.

[0072] The first region 302 may be a portion of a substrate used to manufacture a memory device and may include a semiconductor material. As an example, the first region 302 may include polycrystalline silicon. Carbon may be implanted into a portion of an upper portion of the first region 302 to form a first impurity region C1 in the cell region C. The first impurity region C1 containing carbon may have a lower etching rate during a wet etching process compared to other regions of the first region 302.

[0073] Reference Figure 14 and 15, a first sacrificial layer 303A and a second sacrificial layer 303B may be formed on the first region 302. The first sacrificial layer 303A and the second sacrificial layer 303B may be formed of an insulating material. As an example, the first sacrificial layer 303A may include silicon oxide, and the second sacrificial layer 303B may include silicon nitride. The second sacrificial layer 303B may have a greater thickness than the first sacrificial layer 303A, but is not limited thereto.

[0074] Reference Figure 16 and 17 , a first mask layer M1 including a plurality of first openings OP1 may be formed on the second sacrificial layer 303B. The plurality of first openings OP1 may be separated from each other, as shown in FIG. Figure 16 After forming the first mask layer M1 , the first sacrificial layer 303A and the second sacrificial layer 303B exposed to the plurality of first openings M1 may be removed to expose the first region 302 through the plurality of first openings M1 .

[0075] Reference Figure 18 and 19 After removing the first mask layer OP1, polysilicon may be deposited on the first region 302 to form a first polysilicon layer 305A. The first polysilicon layer 305A may fill the region where the first sacrificial layer 303A and the second sacrificial layer 303B are removed. The first polysilicon layer 305A may be subjected to a chemical mechanical polishing process to form a plurality of support regions 305, such as Figure 20 and 21 The plurality of support regions 305 may be separated from each other in the XY plane, as shown. Figure 20 The positions of the plurality of support areas 305 may correspond to those shown in FIG. Figures 16 to 19 The top surfaces of the plurality of support regions 305 may be coplanar with the top surface of the second sacrificial layer 303B.

[0076] Reference Figure 22 and 23 , the second polysilicon layer 304A may be formed on the plurality of support regions 305 and the second sacrificial layer 303B. As an example, the second polysilicon layer 304A may have a thickness of several hundred thickness.

[0077] Reference Figures 24 to 26 A second mask layer M2 including a plurality of second openings OP2 may be formed on the second polysilicon layer 304A. Carbon may be implanted into the second polysilicon layer 304A through the plurality of second openings OP2 to form second impurity regions C2 including carbon.

[0078] The second impurity region C2 may be Figure 25 As shown, it is located on multiple support areas 305 and can be as Figure 26 As shown, the second impurity region C2 extends in the first direction (X direction). Compared with the plurality of support regions 305 arranged to be separated from each other along the first direction, the second impurity region C2 may be a region extending continuously along the first direction.

[0079] Reference Figures 27 to 29 , a plurality of sacrificial layers 321-328 (320) and a plurality of insulating layers 341-347 (340) may be alternately and repeatedly stacked on the second polysilicon layer 304A. In some example embodiments, before forming the plurality of sacrificial layers 320 and the plurality of insulating layers 340, the first sacrificial layer 303A and the second sacrificial layer 303B and the second polysilicon layer 304A may be removed in the peripheral circuit region P. The number and thickness of the sacrificial layers 320 and the insulating layer 340 may be modified differently according to some example embodiments. In some example embodiments, the number of sacrificial layers 320 may be equal to the sum of the number of ground selection transistors, string selection transistors, memory cells, and dummy transistors included in the memory device.

[0080] The plurality of sacrificial layers 320 and the plurality of insulating layers 340 may extend to different lengths in directions parallel to the top surface of the second polysilicon layer 304A (X and Y directions), thereby forming a step structure. The step structure may be formed adjacent to the peripheral circuit region P. After the step structure is formed, an insulating interlayer 370 may be formed on the plurality of sacrificial layers 320 and the plurality of insulating layers 340. The insulating interlayer 370 may be formed on the lower insulating interlayer 371 in the peripheral region P. The insulating interlayer 370 may include silicon oxide such as HDP oxide or tetraethyl orthosilicate (TEOS) oxide, or silicon nitride.

[0081] A separation insulating layer 355 may be formed in the cell region C. The separation insulating layer 355 may extend in a first direction (X direction) and downward from the top surface of the insulating interlayer 370 to divide the uppermost sacrificial layer 328 into a plurality of patterns. The uppermost sacrificial layer 328 may be replaced with a gate electrode layer of a string selection transistor.

[0082] Reference Figures 30 to 32 , a plurality of channel holes CHH and a plurality of dummy channel holes DCHH may be formed in a region for forming a channel structure and a dummy channel structure. Figure 30As shown, a plurality of channel holes CHH may be arranged to be separated from each other on the first region 302 on which the plurality of support regions 305 are not formed. A plurality of dummy channel holes DCHH may be formed to be arranged in the first direction (X direction) at the arrangement position of the separation insulating layer 355. The plurality of channel holes CHH may be formed to pass through the insulating interlayer 370, the plurality of sacrificial layers 320, and the plurality of insulating layers 340. In addition to the plurality of sacrificial layers 320 and the plurality of insulating layers 340, the plurality of dummy channel holes DCHH may be formed to also pass through the separation insulating layer 355. The plurality of channel holes CHH and the plurality of dummy channel holes DCHH may extend to pass through the second polysilicon layer 304A and the first and second sacrificial layers 303A and 303B. Therefore, the first region 302 may be exposed through the plurality of channel holes CHH and the plurality of dummy channel holes DCHH. As the number of sacrificial layers 320 and insulating layers 340 increases, the plurality of channel holes CHH and the plurality of dummy channel holes DCHH may have a tapered shape having a width that becomes narrower toward the second polysilicon layer 304A in the depth direction (Z direction).

[0083] Reference Figures 33 to 35 , wet etching can be performed through the plurality of channel holes CHH and the plurality of dummy channel holes DCHH, so that the portion of the second polysilicon layer 304A exposed by the plurality of channel holes CHH and the plurality of dummy channel holes DCHH can be removed. The portion of the second polysilicon layer 304A that remains without being removed can be provided as the third region 304. A plurality of supporting regions 305 or the first sacrificial layer 303A and the second sacrificial layer 303B can be provided between the third region 304 and the first region 302.

[0084] The third region 304 that remains without being removed by the wet etching may correspond to the second impurity region C2 containing carbon. That is, the width (or length in the Y direction) of the third region 304 may be substantially equal to the width of the second region C2 in the Y direction. In some example embodiments, since a polysilicon layer into which carbon is implanted may have a lower etching rate than a polysilicon layer into which carbon is not implanted, the second impurity region C2 containing carbon may not be removed during the wet etching process, so that a portion of the second polysilicon layer 304A may remain to form the third region 304.

[0085] The second polysilicon 304A may be removed except for the third region 304, thereby forming a third opening OP3. Through the third opening OP3 between the plurality of sacrificial layers 320 and the second sacrificial layer 303B, the plurality of channel holes CHH may be connected to each other.

[0086] Reference Figure 37 and 38The gate insulating layer 360, the channel layer 310, and the drain region 313 may be formed in corresponding channel holes among the plurality of channel holes CHH to form a channel structure CH. A dummy channel structure DCH may be formed in corresponding dummy channel holes among the plurality of dummy channel holes DCHH to have a structure similar to the channel structure CH. The plurality of channel structures CH and the plurality of dummy channel structures DCH may be formed on the first region 302.

[0087] The process of forming the channel structure CH and the dummy channel structure DCH includes forming a gate insulating layer 360 in the plurality of channel holes CHH and the plurality of dummy channel holes DCHH.

[0088] The gate insulating layer 360 may include a blocking layer 362, a charge storage layer 364, and a tunnel layer 366 and may be formed by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process to fill a portion of each of the plurality of channel holes CHH and a portion of each dummy channel hole DCHH. The gate insulating layer 360 may also be formed in the third opening OP3. Thus, the gate insulating layer 360 may contact the first region 302 below the plurality of channel holes CHH.

[0089] As an example, blocking layer 362 may include a high-k dielectric material having a higher dielectric constant than silicon oxide. Tunneling layer 366 may be configured to allow charges to tunnel through FN tunneling and move into charge storage layer 364. Tunneling layer 366 may include, for example, silicon oxide.

[0090] In some example embodiments, the barrier layer 362 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or a high-k dielectric material. The high-k dielectric material may include aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSi x Oy), hafnium oxide (HfO2), hafnium silicon oxide (HfSi x O y ), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y) and at least one of praseodymium oxide (Pr2O3). The blocking layer 362 may be formed of a single layer, but is not limited thereto. For example, the blocking layer 362 may be formed of a multilayer including a high-k dielectric layer and a low-k dielectric layer having different dielectric constants from each other. In this case, the low-k dielectric layer may be close to the charge storage layer 364, and the high-k dielectric layer may have a dielectric constant higher than that of the tunnel layer 366. The low-k dielectric layer may be provided on one side of the high-k dielectric layer to adjust the energy band such as the barrier height so that the characteristics of the non-volatile memory device (e.g., erase characteristics) can be improved.

[0091] The charge storage layer 364 may be a charge trapping layer or a floating gate conductive layer. When the charge storage layer 364 is a floating gate conductive layer, the charge storage layer 364 may be formed of polysilicon deposited by a low pressure chemical vapor deposition (LPCVD) process. When the charge storage layer 364 is a charge trapping layer, the charge storage layer 364 may include a dielectric material such as silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), hafnium oxide (HfO2), zirconium oxide (ZrO2), tantalum oxide (Ta2O3), titanium oxide (TiO2), hafnium aluminum oxide (HfAlxOy), hafnium tantalum oxide (HfTa x O y ), Hafnium Silicon Oxide (HfSi x O y ), aluminum nitride (Al x N y ) and aluminum gallium nitride (AlGa x N y In some example embodiments, the charge storage layer 364 may include quantum dots or nanocrystals. Here, the quantum dots or nanocrystals may be formed of metal nanoparticles or semiconductor nanoparticles.

[0092] The tunnel layer 366 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), hafnium oxide (HfO2), hafnium silicon oxide (HfSi x O y ), at least one of aluminum oxide (Al2O3) and zirconium oxide (ZrO2).

[0093] The channel layer 310 may be formed on the inside of the gate dielectric layer 360 and may include polysilicon. As an example, the channel layer 310 may be formed on the inside of the tunnel layer 366, which is formed last among the layers included in the gate insulating layer 360. The channel layer 310 may have a thickness in the range of approximately 1 / 50 to 1 / 5 of the diameter of the channel hole CHH. The channel layer 310 may be formed by an ALD process or a CVD process.

[0094] The channel layer 310 may have a hollow cylindrical shape. A buried insulating layer 315 may be formed within the channel layer 310. In some example embodiments, before forming the buried insulating layer 315, the structure including the channel layer 310 may be further subjected to a hydrogen annealing process in an atmosphere containing hydrogen or deuterium. Numerous crystal defects present in the channel layer 310 may be repaired through the hydrogen annealing process. A drain region 313 formed of a conductive material such as polysilicon may be formed on the channel layer 310.

[0095] The horizontal channel layer 310h may be formed to fill a portion of the third opening OP3 that is not filled by the gate insulating layer 360. The horizontal channel layer 310h may extend from the channel layer 310 and may include polysilicon. Therefore, a plurality of channel layers separated from each other in the XY plane may be integrally connected to each other through the horizontal channel layer 310h, thereby forming an integral layer.

[0096] Reference Figures 39 to 41 , a word line cutout WC may be formed. The word line cutout WC may be formed in a region where a common source line will be formed in the following process. The third region 304 may be exposed at the bottom of the word line cutout WC, and the plurality of sacrificial layers 320 and the plurality of insulating layers 340 may be exposed at the inner sidewalls of the word line cutout WC.

[0097] Reference Figures 42 to 44 After polysilicon spacers 306 are formed on the inner sidewalls of the wordline cutout WC, additional etching may be performed through the wordline cutout WC by a dry etching process to further form a trench RCS below the wordline cutout WC. The trench RCS may extend from the wordline cutout WC and may be formed to a sufficient depth to expose the plurality of support regions 30 and the second sacrificial layer 303B. In some example embodiments, the trench RCS may be formed without forming the polysilicon spacers 306.

[0098] Reference Figures 45 to 47 , the first sacrificial layer 303A and the second sacrificial layer 303B can be removed through the wordline cutout WC and the trench RCS to form a substrate opening OPS. The second sacrificial layer 303B exposed by the wordline cutout WC and the trench RCS can be removed first, and then the first sacrificial layer 303A can be removed. By removing the first sacrificial layer 303A and the second sacrificial layer 303B, a portion of the first region 302, a portion of the third region 304, and a portion of each of the plurality of support regions 305 can be exposed through the substrate opening OPS. When the substrate opening OPS is formed, the plurality of sacrificial layers 320 and the plurality of insulating layers 320 can be supported by the plurality of support regions 305 without collapsing.

[0099] When the first sacrificial layer 303A and the second sacrificial layer 303B are removed, or when an additional etching process is performed after removing the second sacrificial layer 303B, the gate insulating layer 360 below the horizontal channel layer 310h and on the sidewalls of the horizontal channel layer 310h may be removed. In some example embodiments, when the second sacrificial layer 303B is first removed by performing a first etching process through the word line cutout WC and the trench RCS, the gate insulating layer 360 may be exposed through the area where the second sacrificial layer 303B was removed. By performing a second etching process after the first etching process, the first sacrificial layer 303A and a portion of the gate insulating layer 360 (e.g., the barrier layer 362) may be removed together. That is, the barrier layer 362 below the horizontal channel layer 310h may be removed by the second etching process. In this case, the barrier layer 362 on the sidewalls of the horizontal channel layer 310h may also be removed.

[0100] After the second etching process, a third etching process may be performed to remove the charge storage layer 364 and tunnel layer 366 below the horizontal channel layer 310h. In this case, the charge storage layer 364 and tunnel layer 366 on the sidewalls of the horizontal channel layer 310h may also be removed. Since at least one of the blocking layer 362, the charge storage layer 364, and the tunnel layer 366 may comprise a different material than the others, multiple etching processes as described above may be performed to remove the gate insulating layer 360 below the horizontal channel layer 310h. When the gate insulating layer 360 below the horizontal channel layer 310h is removed, a portion of the gate insulating layer 360 may remain between the first region 302 and the horizontal channel layer 310h. That is, a portion of the gate insulating layer 360 (i.e., a portion of the blocking layer 362, a portion of the charge storage layer 364, and a portion of the tunnel layer 366) remains between the first region 302 and the horizontal channel layer 310h below the bottom surface of the buried insulating layer 315. The gate insulating layer 360 may remain on the top surface of the horizontal channel layer 310h to constitute a horizontal portion of the gate insulating layer 360. Through the horizontal portion, vertical portions of the gate insulating layer 360, each surrounding an outer portion of the channel layer 310, may be connected to each other.

[0101] Reference Figures 48 to 50 , the substrate opening OPS may be filled with polysilicon through the word line cutout WC. The polysilicon layer 303C may fill the substrate opening OPS. The polysilicon layer 303C may fill the trench RCA and may also be formed in the word line cutout WC. Figure 9 and 10When the substrate opening OPS is filled with polysilicon, at least one void Vo may be formed in the polysilicon layer 303C. The first region 302, the third region 304, the channel layer 310, and the horizontal channel layer 310h may be connected to each other through the polysilicon layer 303C. In some example embodiments, the polysilicon layer 303C may be undoped.

[0102] Reference Figures 51 to 53 , an etching process can be performed through the wordline cutout WC. The etching process can be performed to selectively remove polysilicon. Through this etching process, the polysilicon layer 303C and polysilicon spacers 306 in the wordline cutout WC can be removed. In this case, the polysilicon layer 303C below the wordline cutout WC can be removed. However, because the first region 302 and the third region 304 contain carbon, the first region 302 and the third region 304 may not be removed during the etching process. By removing the polysilicon layer 303C below and in the wordline cutout WC, as well as the polysilicon spacers 306 in the wordline cutout WC, multiple sacrificial layers 320 and multiple insulating layers 340 can be exposed through the wordline cutout WC, and multiple support regions 305 and / or the first region 302 can also be exposed through the trench RCS. In addition, the polysilicon layer 303C can remain in the substrate opening OPS to form the second region 303. For example, the second region 303 may be a region in which the substrate opening OPS formed by removing the first sacrificial layer 303A and the second sacrificial layer 303B is filled with polysilicon.

[0103] Thus, a substrate 301 including first to third regions 302, 303, and 304 and a plurality of support regions 305 may be formed. The first region 302 and the third region 304 may be connected to the channel layer 310 and the horizontal channel layer 310h through the second region 303.

[0104] In general, when the channel layer is formed, a channel hole can be formed, and then the epitaxial layer can be formed in the channel hole. Next, a gate insulating layer can be formed in the channel hole with the epitaxial layer. In this case, since the top surface of the epitaxial layer can be covered by the gate insulating layer, an etching process can be performed to expose the top surface of the epitaxial layer, and then the channel layer can be formed. However, when the top surface of the epitaxial layer may be fully exposed, a fault may occur in which the epitaxial layer and the channel layer are not connected to each other. Therefore, it is required to increase the diameter of the channel hole. However, such a method will impose restrictions on the integration density of the memory device.

[0105] According to some example embodiments of the inventive concept, the channel layer 310 may be directly connected to the substrate 301 without growing an epitaxial layer. In addition, when forming the channel layer 310, the process of forming the channel layer 310 after removing a portion of the gate insulating layer 360 may be omitted. Figures 36 to 38As described above, the gate insulating layer 360 may be formed in the channel hole CHH, and then the channel layer 310 may be formed on the gate insulating layer 360 in the channel hole CHH. In a subsequent process, a portion of the gate insulating layer 360 surrounding the channel layer 310 may be removed, and the removed region of the gate insulating layer 360 may be filled with polysilicon so that the horizontal channel layer 310h below the horizontal portion of the gate insulating layer may directly contact the substrate 301. Therefore, the diameter of the channel hole CHH may be reduced to increase the integration density of the memory device, thereby improving the reliability of the memory device.

[0106] Reference Figures 54 to 56 , the multiple sacrificial layers 320 exposed by the word line cuts WC can be selectively removed, and then a conductive material can be filled in the region where the multiple sacrificial layers 320 are removed so that multiple gate electrode layers 331-338 (330) can be formed. The gate electrode layer 330 may include metal, polysilicon or metal silicide. The metal silicide may include cobalt silicide (CoSi), nickel silicide (NiSi), hafnium silicide (HfSi), platinum silicide (PtSi), tungsten silicide (WSi), titanium silicide (TiSi) or a combination thereof. When the gate electrode layer 330 can be formed of metal silicide, after silicon is filled in the region where the multiple sacrificial layers 320 are removed, a metal layer can be formed, and then a silicidation process can be performed to form the gate electrode layer 330. In some example embodiments, the gate electrode layer 330 may include multiple metallic layers, such as a titanium nitride (TiN) layer and a tungsten (W) layer. In some example embodiments, before forming the multiple gate electrode layers 330, similar to Figure 6 The additional barrier layer 168 shown may be formed in the region where the plurality of sacrificial layers 320 are removed. Thus, the additional barrier layer may surround the plurality of gate electrode layers 330.

[0107] Reference Figures 57 to 59 After forming the plurality of gate electrode layers 330, spacers 309 may be formed on the sidewalls of the word line cutouts WC and impurity ions may be implanted into the substrate 301 (e.g., the first region 302 and the plurality of support layers 305) to form source regions 308. The source regions 308 may include n-type impurities. After forming the source regions 308, a common source line 350 may be formed in the word line cutouts WS having the spacers 309 by filling them with a conductive material.

[0108] In a memory device according to some example embodiments of the inventive concept, a plurality of channel layers and a substrate may be directly connected to each other without an epitaxial layer therebetween, and a plurality of channel layers may be connected to each other through a horizontal channel layer in the substrate, thereby reducing the diameter of a channel hole in which each channel layer is formed. Thus, disconnection failure (or non-contact) between the channel layer and the substrate may be limited and / or prevented, and the integration density of the memory device may also be improved.

[0109] Figure 60 is a schematic block diagram illustrating an example of an electronic apparatus including at least one semiconductor memory device according to some example embodiments of the inventive concept.

[0110] Reference Figure 60 , the electronic device 1000 may include a communication unit 1010 , an input unit 1020 , an output unit 1030 , a memory 1040 , and a processor 1050 .

[0111] The communication unit 1010 may include a wired / wireless communication module. The communication unit 1010 may include a wireless Internet module, a local area communication module, a global positioning system (GPS) module, a mobile communication module, etc. The wired / wireless communication module may be connected to an external communication network through various communication standards and may transmit and receive data.

[0112] The input unit 1020 may be provided as a module configured to allow the user to control the operation of the electronic device 1000 and may include a mechanical switch, a touch screen, a voice recognition module, etc. In addition, the input unit 1020 may include a trackball type or a laser pointer type mouse or a finger mouse device. The input unit 1020 may include various sensor modules in which the user can input data.

[0113] The output unit 1030 may be configured to output information processed in the electronic device 1000 in an audio or video format. The memory 1040 may store data, programs for controlling and processing the processor 1050, and the like. The memory 1040 may include at least one of the memory devices 100, 200, and 300 according to some example embodiments described above. The processor 1050 may send instructions to the memory 1040 depending on the required operation, so that data can be stored or output.

[0114] The memory 1040 may communicate with the processor 1050 through an interface in the electronic device 1000 or a separate interface. The processor 1050 may communicate with the memory 1040 through various interface standards such as SD, SDHC, SDXC, micro SD, or USB to store data in or retrieve data from the memory 1040.

[0115] The processor 1050 may control the operation of each unit in the electronic device 1000. The processor 1050 may perform control and processing related to audio calls, video calls, data communications, multimedia playback and management, etc. In addition, the processor 1050 may process input sent from a user through the input unit 1020 and may output a corresponding result through the output unit 1030. The processor 1050 may store data required for controlling the operation of the electronic device 1000 in the memory 1040 or may retrieve such data from the memory 1040.

[0116] It should be understood that the example embodiments described herein should be understood in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each device or method according to some example embodiments should generally be considered applicable to other similar features or aspects in other devices or methods according to some example embodiments. Although some example embodiments of the inventive concept have been shown and described in detail, those skilled in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the claims.

[0117] This application claims the benefit of Korean Patent Application No. 10-2016-0077840 filed on June 22, 2016, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2016-0097148 filed on July 29, 2016, in the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety.

Claims

1. A storage device comprising: substrate; a plurality of gate electrode layers stacked on the substrate; a plurality of channel layers passing through the plurality of gate electrode layers; a horizontal channel layer extending parallel to the top surface of the substrate, below the plurality of gate electrode layers, and connecting at least some of the plurality of channel layers to each other; a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, the gate insulating layer comprising a horizontal portion and a plurality of vertical portions, the plurality of vertical portions surrounding corresponding channel layers among the plurality of channel layers, the horizontal portion extending below the plurality of gate electrode layers and parallel to a top surface of the substrate; as well as a common source line adjacent to the plurality of gate electrode layers on the substrate, the common source line including first and second portions alternately arranged in a first direction and having different heights in a direction perpendicular to a top surface of the substrate, wherein a top surface of at least a portion of the horizontal channel layer contacts the horizontal portion, and a bottom surface of at least a portion of the horizontal channel layer contacts the substrate, wherein the horizontal channel layer includes a plurality of portions respectively corresponding to the at least some of the plurality of channel layers and protruding downward into the substrate, and The substrate includes a plurality of support areas, which protrude toward the common source line below the common source line and are separated from each other in the first direction to prevent the collapse of the gate structure, and in a second direction perpendicular to the first direction, the width of the plurality of support areas is greater than the width of the common source line.

2. The memory device according to claim 1, wherein The substrate includes a source region below the common source line, and The source region includes an uneven surface in the first direction. 3 . The memory device according to claim 1 , wherein the first portion of the common source line is on the plurality of support regions, and a height of the first portion is smaller than a height of the second portion. 4 . The memory device of claim 1 , wherein top surfaces of the plurality of support regions contact a bottom surface of the first portion of the common source line. 5 . The memory device of claim 1 , wherein the horizontal portion of the gate insulating layer extends from the plurality of vertical portions of the gate insulating layer and connects at least some of the plurality of vertical portions to each other. The memory device of claim 1 , wherein the plurality of channel layers are connected to the substrate through the horizontal channel layer.

7. The memory device according to claim 1, further comprising: a buried insulating layer on the substrate, wherein The plurality of channel layers surround the buried insulating layer, and The buried insulating layer extends vertically a greater distance into the substrate than the plurality of channel layers.

8. A storage device comprising: substrate; a plurality of gate structures on the substrate, each of the plurality of gate structures comprising a plurality of gate electrode layers and a plurality of insulating layers alternately stacked on the substrate; a plurality of channel layers extending in a direction perpendicular to a top surface of the substrate, the plurality of channel layers passing through the plurality of gate structures; a common source line on the substrate between the plurality of gate structures, the common source line extending along a first direction parallel to the top surface of the substrate; The charge storage layer includes a vertical portion and a horizontal portion, The vertical portion is outside a corresponding channel layer among the plurality of channel layers of each of the plurality of gate structures, and The horizontal portion extends from the vertical portion to under each of the plurality of gate structures; as well as a horizontal channel layer below the horizontal portion of the charge storage layer, the horizontal channel layer connecting the plurality of channel layers to each other and contacting the substrate, wherein the horizontal portion of the charge storage layer is only on a top surface of the horizontal channel layer, wherein the horizontal channel layer includes a plurality of portions respectively corresponding to the plurality of channel layers and protruding downward into the substrate, and The substrate includes a plurality of support areas, which protrude toward the common source line below the common source line and are separated from each other in the first direction to prevent the collapse of the plurality of gate structures, and in a second direction perpendicular to the first direction, the width of the plurality of support areas is greater than the width of the common source line. 9 . The memory device of claim 8 , wherein the vertical portions of the charge storage layer are connected to each other through the horizontal portion of the charge storage layer. 10 . The memory device of claim 8 , wherein the common source line includes first and second portions having different heights and alternately arranged in the first direction.

11. The memory device according to claim 8, wherein The substrate includes an impurity region below the horizontal channel layer, and The impurity region includes carbon.

12. A memory device comprising: substrate; a plurality of gate structures on the substrate, each of the plurality of gate structures comprising a plurality of gate electrode layers stacked on the substrate; a plurality of channel layers passing through the plurality of gate electrode layers of corresponding gate structures among the plurality of gate structures and extending in a direction perpendicular to a top surface of the substrate; a horizontal channel layer connecting the plurality of channel layers to the substrate, the horizontal channel layer being below the plurality of gate structures; a charge storage layer including a vertical portion between the plurality of gate electrode layers and the plurality of channel layers and a horizontal portion contacting a top surface of the horizontal channel layer; as well as a common source line on the substrate between the plurality of gate structures and extending in a first direction parallel to the top surface of the substrate, The substrate includes a first impurity region below the horizontal channel layer and a second impurity region between the common source line and the horizontal channel layer, the first impurity region and the second impurity region include carbon, wherein the horizontal channel layer includes a plurality of portions respectively corresponding to the plurality of channel layers and protruding downward into the substrate, and The substrate includes a plurality of support areas, which protrude toward the common source line below the common source line and are separated from each other in the first direction to prevent the collapse of the plurality of gate structures, and in a second direction perpendicular to the first direction, the width of the plurality of support areas is greater than the width of the common source line.

13. The memory device of claim 12, further comprising: a buried insulating layer on the substrate, wherein The plurality of channel layers surround the buried insulating layer, The buried insulating layer extends a greater distance into the substrate than the plurality of channel layers. 14 . The memory device of claim 12 , wherein the common source line includes first and second portions alternately arranged in the first direction and having different heights.

15. The memory device according to claim 14, wherein The first portion of the common source line is on the plurality of support regions, and The height of the first portion is smaller than the height of the second portion. 16 . The memory device of claim 15 , wherein a thickness of the substrate under the first portion is greater than a thickness of the substrate under the second portion.

17. A memory device comprising: substrate; A stacking structure, on the substrate, comprising: a gate insulating layer including a horizontal portion extending parallel to a top surface of the substrate and a plurality of vertical portions spaced apart from each other and extending vertically above the top surface of the substrate, a plurality of channel layers surrounded by the plurality of vertical portions of the gate insulating layer and extending perpendicularly to the top surface of the substrate, a plurality of gate electrode layers and insulating layers alternately stacked on top of each other on the horizontal portion of the gate insulating layer, a plurality of strings defined by the gate insulating layer, the plurality of channel layers, and the plurality of gate electrode layers, each string including a plurality of memory cells stacked on top of each other between a ground selection transistor and a string selection transistor, and a horizontal channel layer connecting at least some of the plurality of channel layers to each other and extending between a lower surface of the horizontal portion of the gate insulating layer and the top surface of the substrate; as well as a common source line adjacent to the stack structure on the substrate and extending in a first direction parallel to the top surface of the substrate, wherein a top surface of at least a portion of the horizontal channel layer contacts the lower surface of the horizontal portion, and a bottom surface of at least a portion of the horizontal channel layer contacts the top surface of the substrate, wherein the horizontal channel layer includes a plurality of portions respectively corresponding to the at least some of the plurality of channel layers and protruding downward into the substrate, and The substrate includes a plurality of support areas, which protrude toward the common source line below the common source line and are separated from each other in the first direction to prevent the collapse of the gate structure, and in a second direction perpendicular to the first direction, the width of the plurality of support areas is greater than the width of the common source line.

18. The memory device according to claim 17, wherein The substrate includes a source region below the common source line, and The source region includes an uneven top surface. 19 . The memory device of claim 17 , wherein the substrate comprises at least one void below the horizontal channel layer.

20. The memory device according to claim 17, wherein The substrate includes an impurity region adjacent to the horizontal channel layer, And the impurity region includes carbon.

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