Method and apparatus for scoring a sealing structure

Abstract

The present invention relates to a method and apparatus for scribe-sealing structures. An exemplary integrated circuit die (FIG. 8, 801) comprises: a plurality of lower-level conductor layers, a plurality of lower-level insulator layers located between the plurality of lower-level conductor layers, a plurality of lower-level vias extending vertically through the lower-level insulator layers, a plurality of upper-level conductor layers overlying the lower-level conductor layers, a plurality of upper-level insulator layers located between and surrounding the upper-level conductor layers, a plurality of upper-level vias; at least two scribe-sealings (805, 807) arranged to form a vertical barrier layer extending vertically from a semiconductor substrate to a passivation layer at an upper surface of the integrated circuit die; and at least one opening (809) extending vertically through one of the at least two scribe-sealings and extending through: the upper-level conductor layer, the upper-level via layer, the lower-level conductor layer, and the lower-level via layer.

Description

[0001] Related Applications Cross Reference

[0002] This application claims the benefit of priority under 35 U.S.C. §119(a) to a commonly owned provisional patent application filed in India on September 7, 2016 (Indian Patent Application No. 201641030533 designating Texas Instruments Incorporated as the applicant) entitled “METHODS AND APPARATUS FOR SCRIBE SEAL STRUCTURES,” which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present invention relates generally to the use of scribe seals in semiconductor device and integrated circuit fabrication, and more particularly to scribe seals used to enhance inter-die RF coupling and inter-die coupling using magnetic and capacitive coupling. Background Art

[0004] Integrated circuits are formed as multiple bare chips on a semiconductor wafer. Various process steps are performed on the semiconductor wafer, including: forming active areas within the semiconductor material by using impurity doping and ion implantation; depositing and patterning insulator layers; and forming conductor layers such as metal layers. Insulator layers are formed above the semiconductor substrate and between and around the conductor layers to provide electrical insulation between the conductor layers. The conductor layers include materials such as doped polysilicon, aluminum, gold, and copper conductor layers. Another insulator layer is formed over the entire device and is called a "passivation layer" or sometimes a "protective overcoat" or "PO" layer. The passivation layer provides electrical insulation and protection from moisture and other impurities that may corrode or adversely affect the conductors and the semiconductor substrate. The insulator layer is a thin, brittle layer of dielectric material that may sometimes be considered a ceramic material such as silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, and polyimide. A bonding pad layer, typically aluminum or another conductor, may be formed on top of the uppermost insulator layer and covered by the PO layer. The bonding pad is then exposed by the opening portion of the PO layer. Bond wires may be mechanically and electrically coupled to bond pads to form terminals of a packaged integrated circuit when the integrated circuit die is completed as an integrated circuit. Solder balls, solder pillars, solder bumps, or other connectors may be used in place of or in addition to bond wires to provide electrical terminals. Packaging materials such as mold compounds may be applied to individual dies or in a "wafer level" process prior to forming individual dies; the final package protects the integrated circuit die and the bond wires or solder balls from moisture and mechanical stress.

[0005] After the integrated circuits are completely fabricated but while the integrated circuits still reside on a single semiconductor wafer, the devices are separated from each other. This operation is called "singulation" or "dicing" of the semiconductor wafer. Singulation of the integrated circuit devices from the semiconductor wafer includes physically separating the devices by sawing or scribing operations. Mechanical sawing or laser sawing cuts through the semiconductor wafer. Cutting is done in kerf lanes or scribing streets defined between the integrated circuit dies. Sometimes singulation includes laser scribing along the scribed areas followed by a mechanical breaking operation.

[0006] When sawing semiconductor wafers, cutting of the semiconductor wafer may occur. In a mechanical cutting operation, the rotating saw blade must cut through the insulating layer, the conductor layer, and through the semiconductor wafer. The saw blade has significant vibrations and generates heat as the saw blade rotates and cuts through these mechanically fragile layers. The use of thick metal layers to form joints or probe pads in the saw lanes has led to increased cutting and unwanted cracking in the semiconductor wafer during sawing. Cracked wafers result in the loss of finished integrated circuit devices, thereby reducing yield and increasing unit cost.

[0007] A scribe seal is used in order to protect sensitive metal conductors and doped diffusion regions within the integrated circuit die during singulation and then to protect the completed integrated circuit die. A scribe seal is a structure that is typically formed at the periphery of the integrated circuit die and extends from the uppermost layer of conductor material, through the insulating layer, and to the surface of the semiconductor device. The scribe seal may include: conductor material from each conductor metal layer; conductive vias between layers; and contact material to the semiconductor substrate to form a vertical structure that extends from the passivation layer to the semiconductor substrate and forms a metal seal that extends from the passivation layer, through the insulating layer, to the semiconductor substrate.

[0008] The scribe seal forms a barrier to ions and process contaminants that might otherwise migrate into sensitive structures within the integrated circuit die, and forms a barrier to moisture and contaminants that might otherwise affect the finished integrated circuit die. The scribe seal structure may include multiple scribe seals formed at the periphery of the integrated circuit die. The scribe seal may be formed in multiple concentric scribe seals that are spaced a distance apart to further increase the effectiveness of the barrier to ion migration and moisture. Summary of the invention

[0009] In the described examples, an integrated circuit die includes: a plurality of lower-level conductor layers overlying a semiconductor substrate, a plurality of lower-level insulator layers between and surrounding the plurality of lower-level conductor layers, a plurality of lower-level vias extending vertically through the lower-level insulator layers and electrically coupling some of the lower-level conductors, a plurality of upper-level conductor layers overlying the lower-level conductor layers, a plurality of upper-level insulator layers between and surrounding the upper-level conductor layers, a plurality of lower-level vias extending vertically through the lower-level insulator layers and electrically coupling some of the lower-level conductors, A plurality of upper level vias; at least two scribed seals located at the periphery of the integrated circuit die and spaced apart from each other, the at least two scribed seals comprising the upper level conductor layer, the upper level vias, the lower level conductor layer and the lower level vias to form a vertical barrier layer extending vertically from the semiconductor substrate to the passivation layer at the upper surface of the integrated circuit die; and at least one opening extending vertically through a respective one of the at least two scribed seals and extending through: the upper level conductor layer, the upper level via layer, the lower level conductor layer and the lower level via layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 Illustration of semiconductor wafers and integrated circuit dies.

[0011] Figure 2 Illustration of a semiconductor wafer and a wafer dicing saw.

[0012] Figure 3 A portion of a semiconductor wafer and integrated circuit die with scribe streets and scribe seals is illustrated in plan view.

[0013] Figure 4 A portion of a semiconductor wafer is illustrated in cross-sectional view.

[0014] Figure 5A illustrating in projection an integrated circuit die including a scribed seal area, and Figure 5B The integrated circuit die and scribed seal area are illustrated in plan view.

[0015] Figure 6 An integrated circuit die having a first scribe seal and a second scribe seal and additional circuitry is depicted in plan view.

[0016] Figure 7 Depicted is a pair of integrated circuit dies with scribed seals.

[0017] Figure 8 An integrated circuit die including a scribed seal of an embodiment is depicted in plan view.

[0018] Fig. 9 An integrated circuit die having a scribe seal of another embodiment is depicted in plan view.

[0019] Fig.10 An integrated circuit die having a scribe seal of additional embodiments is depicted in plan view.

[0020] Fig.11 A portion of an integrated circuit die including a scribe seal embodiment is depicted in a cross-sectional view.

[0021] Fig.12 A scribed and sealed integrated circuit die incorporating an embodiment is depicted in plan view.

[0022] Fig.13 A portion of an integrated circuit die incorporating an alternative scribe seal embodiment is depicted in a cross-sectional view.

[0023] Fig.14 A portion of an integrated circuit die incorporating another alternative scribe seal embodiment is depicted in a cross-sectional view.

[0024] Fig.15 A portion of a scored seal of an embodiment is depicted in plan view.

[0025] Fig.16 Method embodiments are illustrated in flow charts. DETAILED DESCRIPTION

[0026] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are not necessarily drawn to scale.

[0027] The term "coupled" may include connections with intervening elements, and additional elements and various connections may exist between any elements that are "coupled."

[0028] The term "scribe street" includes similar terms such as "scribe lane" and "scribe line" and refers to an area on a semiconductor wafer between adjacent integrated circuit dies that is set aside for physically separating the integrated circuit dies. In a mechanical sawing operation, a kerf lane is centrally located in the scribe street. A laser or saw blade traverses the kerf lane during singulation. Material in the kerf lane is damaged and then lost during the mechanical sawing operation.

[0029] There is an increasing need to isolate communications between circuits. The ground voltage difference between isolated circuits can exceed 1000 volts. To provide isolated communications, optical coupling has been used. However, recent approaches eliminate the need for optical coupling and associated optical transmitters and receivers. In one approach, capacitive coupling is used. In another approach, inductive coupling is used.

[0030] Recent inter-die communication techniques include magnetic coupling using coils formed in integrated circuit dies. The coils use electromagnetic radiation to transmit and receive signals. In multi-chip module packaging, the physical spacing between the dies forms the necessary isolation. Materials such as molding compounds formed between the dies may also form part of the isolation. By modulating the signals transmitted between the devices, inter-die communication can be achieved without the need for signal traces, pins, and bonding wires between the devices, and isolation can be maintained. In other applications, coils on integrated circuits are used for devices where electrical isolation between devices is required. These applications include power circuits, transformers, oscillators, and magnetic or inductive interfaces between independent voltage forms on integrated circuits, where large voltage differences may exist. Coils can be used to transfer power or signals from one device to another while also galvanically isolating integrated circuit devices from each other.

[0031] A coil formed on an integrated circuit may be part of an inductor-capacitor tank ("LC" tank) of a voltage controlled oscillator on the integrated circuit, and current flowing in the coil may induce eddy currents in the score seal. It has been found that the use of the score seal substantially interferes with inter-die coupling and reduces the efficiency of magnetic and inductive coupling. The interference occurs due to unwanted induced currents or eddy currents flowing in the score seal.

[0032] Figure 1 A plurality of integrated circuit dies 110 formed on a semiconductor wafer 105 are depicted in plan view 100. The semiconductor wafer 105 is shown arranged on a wafer support or frame 107. A support backing material called "dicing tape" located below and adhered to the semiconductor wafer 105 is not visible in this view. The dicing tape supports and stabilizes the integrated circuit dies 110 during the cutting or singulation operation. When cutting or sawing through the semiconductor wafer, the integrated circuit dies remain in place, physically supported by the wafer dicing tape, and do not fall from the support 107. Pick-and-place or other die handling equipment may then be used to remove the integrated circuit dies from the wafer dicing tape after the integrated circuit dies have been sawn apart. The integrated circuit dies 110 are then further processed and ultimately packaged to form a completed integrated circuit device.

[0033] Each of the integrated circuit dies 110 may include active devices (not shown), such as transistors, diodes, and similar devices formed on the semiconductor substrate 105. The active devices are formed in active regions of the semiconductor wafer. Active regions are regions formed using ion implantation and impurity doping techniques to become p-type and n-type doped regions. These p-type and n-type doped regions can be used to form transistors, such as: bipolar transistors; metal oxide semiconductor (MOS) field effect transistors (MOSFETs); diodes; silicon controlled rectifiers; and other devices that conduct current in response to voltage or current. Passive devices may be formed on the semiconductor wafer, including: capacitors; resistors; and inductors. The passive devices may be formed using substrate materials or formed in layers formed above the substrate. Sensors such as fluxgate sensors, current sensors, light sensors, temperature sensors, and other sensors may be formed using active regions and layers formed above the substrate. In an example, a fluxgate sensor is formed on an integrated circuit die. The fluxgate sensor includes a magnetic core material that includes iron wound in a conductive coil. Coils and inductors can be formed on an integrated circuit die, including antennas.

[0034] When completed, the integrated circuit dies 110 each form a complete circuit that performs a desired function. The integrated circuit die 110 may form a functional circuit, such as: a transistor; a digital circuit, such as a logic gate; an analog circuit, such as a rectifier; a controller, such as a microcontroller; a processor, such as a digital signal processor or a central processing unit (CPU); a non-volatile storage device, such as a FLASH device; a memory device, such as a static random access memory (SRAM) device or a dynamic random access memory (DRAM) device; an integrated sensor device, or other integrated circuit devices. Each of the integrated circuit dies 110 on the semiconductor wafer 105 may be the same integrated circuit. An integrated circuit may include a few, thousands, or even millions of devices.

[0035] Figure 2 A semiconductor wafer 205 shown in a mechanical sawing operation is illustrated in another plan view 200. Figure 2 Similar numbers are used for Figure 1 The components of the same Figure 2 Except for those that begin with the number "2". Figure 2 2, a semiconductor wafer 205 includes a number of integrated circuit dies 210. A support 207 provides mechanical support for the semiconductor wafer 205. A saw blade 212 is shown applied to the top surface of the semiconductor wafer 205. The saw blade 212 will saw through the semiconductor wafer 205 in defined kerf lanes in the scribe streets positioned between the integrated circuit dies 210. The kerf lanes of the scribe streets are areas that will be removed during the sawing operation and thus any circuits positioned there will be destroyed.

[0036] Figure 3 A portion of a conventional semiconductor wafer 300 with several integrated circuit dies 310 formed thereon is depicted in a plan view. Regions 326 and 328 are scribe lanes that include saw kerf lanes 329, which are used to saw the integrated circuit dies 310 apart in a cutting operation. Scribe lanes 326, 328 have a width that can vary from about forty microns to more than one hundred microns. In an example, the scribe lanes are about eighty microns wide. It is desirable to use less area of ​​the semiconductor wafer for the scribe lane area because using a lower area for the scribe lane area allows more semiconductor wafer area to be used to form additional integrated circuit dies, thereby reducing the cost per integrated circuit. The slit lanes 329 in the central portion of the scribe lanes 326 and 328 identify where the saw will cut through the insulator layer and conductors overlying the semiconductor wafer. The saw blade can also completely cut through the semiconductor wafer to physically separate the integrated circuit dies from each other. In an alternative, the scribe operation can be followed by a fracture operation to separate the integrated circuit dies along the scribe lines.

[0037] exist Figure 3 In the embodiment of the present invention, each integrated circuit die 310 is surrounded by at least one conventional scribe seal 322 and may include a second scribe seal 323. The scribe seals 322, 323 include insulator layers and conductor layers that are also used in the process of forming the insulators and conductors within the integrated circuit die 310. The conductor layers of the scribe seal are formed simultaneously with the integrated circuit conductor layers. The insulator layers located between and surrounding the conductor layers within the integrated circuit die 310 are also formed in the scribe seal 322.

[0038] Still refer to Figure 3 , a scribe seal is disposed between scribe streets 326 and integrated circuit die 310, and the scribe seal surrounds integrated die 310. The scribe seal is intended to reduce or prevent cracks formed in the insulator layer during cutting in scribe streets 326, 328 during sawing or scribing from propagating into integrated circuit die 310, and provides protection for the completed integrated circuit die as described above.

[0039] Semiconductor wafer 300 may be any of several known semiconductor materials including silicon, gallium, gallium arsenide, silicon germanium, and other III-V compounds. These materials may be brittle. The insulator layer may be any of the insulator materials used in semiconductor processing including: silicon dioxide; silicon nitride; silicon oxynitride; silicon carbide; doped glass such as borosilicate glass; phosphosilicate glass; undoped silicate glass; fluorosilicate glass; tetraethyl orthosilicate oxide (TEOS); and silyl-containing hydrogen silsesquioxanes. Gels and organics such as polyimides, organic polymers, and foams may be used.

[0040] Figure 4 A portion of a semiconductor wafer 405 including an upper level conductor layer and a lower level conductor layer such as used in current semiconductor processes is depicted in a cross-sectional view. Scribe seal 422 is a closed loop metal barrier or wall that includes each conductive layer and is connected to the semiconductor substrate. Figure 4 , an exemplary scribed seal 422 is shown. In this scribed seal structure 422, three lower level metal layers 446 are coupled to a substrate 448 and to each other through conductive vias 440 and 444 extending through the lower level insulator layers. Figure 4 In the structure, two upper level conductor layers 432, 438 are formed in an upper level insulator layer 454. The two upper level conductor layers are perpendicular and electrically coupled to each other through an upper level via layer including vias 435, 436. A passivation layer 456 overlies the structure.

[0041] exist Figure 4 In the structure 422 in FIG. 4 , a semiconductor wafer 448 has an active region 439 formed in an upper portion. The active region may be, for example, an n-doped or p-doped region for forming a transistor.

[0042] exist Figure 4 In the example, the structure 422 is shown as Figure 3 A portion of the scored seal 322, 323 is shown in plan view. Figure 4 4, a scribe seal 422 is shown to illustrate the various insulator layers, conductor layers, and vias used in fabricating semiconductor wafers.

[0043] The scribe seal 422 includes lower level vias 440 formed between three lower level conductor layers 446. For example, the lower level vias 440 may be formed using tungsten plugs. Other conductive materials used for vias in semiconductor processes may be used. The vias 440 in the scribe seal 422 are trench vias. The trench vias form a continuous interruption of the insulator layers on one side of the integrated circuit die. The scribe seal 422 is formed simultaneously with and using the same insulator layers and conductor layers used in forming devices within the integrated circuit die 410. Figure 4 , the lower level conductor 446 may be aluminum. Other metals and alloys may also be used. The contact material forming the lowermost level of metal in the scribed seal may be aluminum or other material contacting the semiconductor substrate 448. Aluminum has good adhesion to oxides (such as silicon oxide) commonly used for insulator layers, and has good conductivity / resistance, and is relatively low cost.

[0044] Insulator layer 450 is sometimes referred to by different terms depending on the application and position above the semiconductor substrate. For example, an insulator material formed above the active area and before any metallization step may be referred to as a "pre-metal dielectric" or "PMD". An insulator layer formed around a metal layer may be referred to as an "interlayer dielectric" or "ILD". An insulator layer formed between conductor layers may be referred to as an "intermetal dielectric" layer or "IMD". Sometimes, different materials are used for different applications. Sometimes, the label indicates the position of the insulator relative to the vertical structure of the conductor and insulator layers. Trench via 440 is shown as being vertically stacked above and in contact with active area 439. For the purpose of this application, the term "via" includes both an opening formed in an insulator layer and a conductive material that fills the opening to form a vertical physical and electrical connection. In the scribe seal 422, the trench via 440 is used in the portion of the scribe seal closest to the integrated circuit die. The trench via 440 and the conductor layer are coupled together, thus forming a continuous wall of conductive material interrupting each of the insulating layers.

[0045] exist Figure 4 In the embodiment of the present invention, the lower level conductor layer 446 can be formed in a "front end of line" process from a metal used to form conductors in semiconductor processes. For example, the metal layer 446 can be formed from aluminum and aluminum alloys. Aluminum conductors in semiconductor devices can be formed using optical lithography (including photoresist deposition, photoresist exposure, photoresist patterning and etching methods). The trench via 440 can be formed using conductive via materials commonly used in semiconductor processes, such as tungsten and its alloys. Other conductive materials can be used.

[0046] Insulating layers 450, 452, and 454 are formed using conventional semiconductor processes for dielectrics. These layers can be formed using chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), and can be thermally grown. Tetraethyl orthosilicate (TEOS) can be used. Typically, insulator layers 450, 454, 452 will include oxide and nitride layers in different portions so that a selective etching process can be used. Figure 4 An etch stop layer (ESL) may also be formed in addition to and between the layers visible in the insulator layer. Additional films and layers may be included to: assist in the etch process; assist in adhesion; provide a barrier layer; provide an anti-reflective coating; and provide a backside anti-reflective coating to improve optical lithography processes. Materials for the insulator layer may include, without limitation: silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiOC, and other film and gel dielectrics. High-k and low-k dielectrics may be included in the insulator layer.

[0047] exist Figure 4, the scribed seal 422 also includes upper level layer conductors 432, 438. These conductors may be formed in a "back end of line" or "BEOL" process. Copper conductors are used in many semiconductor processes to form upper level metal conductor layers. Copper has a lower electrical resistance than aluminum and may be less susceptible to electromigration issues. A diffusion barrier material (not shown for clarity) surrounds the copper on all sides to prevent copper ions from diffusing into surrounding layers or materials. Figure 4 , the scribed seal 422 includes a first copper conductor 438 and a second copper conductor 432, which is the uppermost upper level conductor in this example. In various example semiconductor processes, more or fewer conductor layers may be used, including more or fewer lower level conductor layers and more or fewer upper level conductor layers.

[0048] exist Figure 4 , the copper conductor layers 432, 438 may be formed using a damascene process in BEOL processing. In the damascene process, the copper is not patterned and etched (as with the aluminum lower level conductors). Instead, a metal embedding process known as a "damascene" process is used. The insulator layers 452, 454 are patterned to form trenches. A copper seed layer material is sputtered or otherwise deposited. An electroplating process is performed to fill the trenches and ensure complete filling of the trenches, with the electroplating continuing over the surface of the trenches.

[0049] After plating is completed with respect to the "capping" layer formed above the surface of the trench, a chemical mechanical process or "CMP" is performed to complete the copper conductor layer and planarize the upper surface of the layer. In CMP, a chemically active slurry is applied to a polishing pad. The slurry contains abrasive particles. The surface of the semiconductor wafer with excess electroplated material is applied to the pad in a circular or other motion, and the excess copper material is wiped off, leaving the planar trenches filled with planarized copper conductors. Additional insulator layers are formed and vias such as 435 and 436 can be formed between the conductor layers using etching and etch stop layers of dielectric material. The upper level vias and overlying trenches can be filled using an electroplating process. In this way, several layers of upper level conductors can be formed.

[0050] In the scribe seal 422, the uppermost conductor layer 432 is vertically connected to layer 438 by a trench via 436. This trench via is formed on the side of the scribe seal 422 closest to the integrated circuit die and continues the vertical walls formed to interrupt the insulating layers 450, 452, 454. Figure 4 , an etch stop layer 452 is shown. However, this is merely one example arrangement and insulator layers 454, 450, and 452 may be formed of similar materials or of different materials as described above.

[0051] Figure 4The scribed seal 422 also includes a passivation layer 456, which overlies the upper surface of the uppermost conductor layer 432 and can be formed of silicon oxide, silicon nitride, silicon oxynitride, and other dielectric materials. Figure 4 , the uppermost layer 457 of the passivation layer 456 is silicon nitride. The remainder of the passivation layer 459 may be silicon dioxide. The passivation layer 456 forms a protective layer that electrically insulates the conductors and also provides a physical coating to protect the metal conductors and the semiconductor substrate from corrosive elements and moisture. To form bond pads that contact upper level conductor layers in the integrated circuit die, openings are formed in the passivation layer 456 by patterning and etching processes.

[0052] In an exemplary semiconductor process, the lower level conductor layer 446 is quite thin, such as about 1 micron thick or less. However, the upper level copper conductor layer and the upper level copper via layer are each quite thick, about 3 microns each, to achieve a total vertical thickness of 9 microns. In a conventional scribed seal area, each of the conductor layers including the upper level conductor layers 432, 438 and the vias 436 would be present to form a complete vertical barrier layer.

[0053] Figure 5A and 5B A portion of an integrated circuit die 501 incorporating a scribe seal embodiment is illustrated in projection and plan views, respectively.

[0054] exist Figure 5A 5 , a silicon die 501 is shown with a scribe seal region 503. In a typical example, multiple scribe seals forming a ring around the periphery of the integrated circuit may be used in region 503. Silicon is just one example material for the substrate and other semiconductor substrate materials may be used, including gallium arsenide, germanium, silicon germanium, indium phosphide, sapphire and other III-V semiconductor substrates. The epitaxial layer may form a semiconductor substrate or a portion of a substrate.

[0055] Figure 5B A plan or top view of semiconductor die 501 is shown. Two scribe seals 505, 507 are shown, with scribe seal 505 at the outer periphery and scribe seal 507 adjacent to and formed inside scribe seal 505. Each scribe seal forms a continuous loop around the periphery of die 501. The scribe seal width will vary with the specific semiconductor process, but may be approximately 20 ums, for example. The spacing between scribe seals may also vary, but may be a similar spacing distance. The scribe seal forms a wall or barrier layer extending from the passivation layer at the upper portion of the integrated circuit structure to the semiconductor substrate, and includes each conductor layer and each via layer extending through each of the insulator layers.

[0056] Also shown on the integrated circuit die 501 is a circuit having an inductive coil or loop antenna 509. This circuit includes an excitation source or voltage supply 511 that puts current into the coil 509. The desired inductor current i L It appears to flow in the coil 509. Since the scored seals 505, 507 also form a coil around the coil 509, they are marked as i E The corresponding eddy current is also L This eddy current or induced current occurs due to magnetic coupling between the coils and is not desired in the circuit, but occurs because the scored seals 505, 507 form a coil around the coil 509 and are magnetically coupled to the coil 509. For example, when two dies use a pair of coils to communicate, the current i E Reduce the inter-die coupling efficiency. Current i E It is an induced current that flows in the scribe seal and has no function in the circuit and therefore represents an energy loss with respect to source 511. Induced current flowing in the scribe seal 505, 507 reduces the efficiency of the circuits within die 501 and reduces the efficiency of inter-die coupling or inter-die communication.

[0057] Figure 6 Integrated circuit die 601 is shown in plan view and includes a first scribed seal 605 at the outer periphery and a second scribed seal 607 formed spaced apart from scribed seal 605 and forming a loop within scribed seal 605. A first coil 609 is coupled to a supply or excitation source 611 and a current i L Flows in coil 609. A second coil 613 is shown in another portion of the integrated circuit die 601.

[0058] When the current i L When flowing in the coil 609, the induced current or eddy current i E flows in the scored seal, which forms a coil coupled to coil 609. Coil 609 can be considered an "aggressor" circuit because it actively causes the current i L Coil 613 is the “victim” current and has an induced current i flowing therein. V This current i V By coupling to the scored seal and through the eddy current i E The scored seal forms a coil around the aggressor coil 609, and the current i E In response to the current i L Flows, and thus the victim coil 613 also has the unwanted current flowing therein.

[0059] Figure 7Illustrate an application where coils are used as transmitter and receiver antennas to perform inter-die communication. Figure 7 For clarity, the reference numerals used for the components are similar to Figure 6 701. For example, integrated circuit die 601 corresponds to integrated circuit die 701. Integrated circuit die 701 is formed with coil 709 and scribed seal area 703 (which may include multiple scribed seals). Similarly, integrated circuit die 731 is formed and physically separated from integrated circuit 701 to provide electrical isolation. Integrated circuit die 731 includes coil 739 that may act as an antenna or magnetic coupling element. Integrated circuit die 731 includes scribed seal area 733, which may include multiple scribed seals, or may be a single scribed seal.

[0060] In communication applications, coils 739 and 709 are used to transmit and receive signals. In experiments, it was observed that Figure 7 The inter-die communication is not efficient when the scribed seals 703, 733 are arranged as shown in FIG. Eddy currents or induced currents flowing in the scribed seals in the device interfere with the communication efficiency.

[0061] Figure 8 An integrated circuit die 801 incorporating an embodiment is illustrated in plan view. For clarity, Figure 8 The notation used in Figure 6 For example, integrated circuit die 801 corresponds to Figure 6 The integrated circuit die 601 in the Figure 8 8, scored seal 805 and scored seal 807 are arranged at the periphery of integrated circuit die 801 and are spaced apart. Score seal 805 is a nearly continuous loop of conductive layers at the periphery and forms a coil, and has openings 811. Openings 811 cut through all of the conductive layers in scored seal 805. Similarly, scored seal 807, which is located within scored seal 805, forms a loop and has openings 809. Openings 809 extend through each of the conductor layers in scored seal 807.

[0062] The openings 809, 811 in the scored seals reduce or prevent eddy currents or induced currents from flowing in the scored seals 805, 807. By reducing the induced currents, the efficiency of the coils used in the integrated circuit die is increased. In experiments where the coils are antennas, as in Figure 8The use of a scored seal together with the opening shown in the multi-chip module results in a substantial increase in coupling efficiency between two integrated circuit dies in a multi-chip module. In an example, the opening is approximately 10 microns wide. The opening width should be large enough to prevent or reduce induced current from flowing in the scored seal, while being small enough that ions or contaminants will be less likely to cross the opening. In an example, the opening is approximately 10 microns. In additional examples, an opening between 10 microns and 20 microns may be used. Other opening widths may also be used depending on the semiconductor process.

[0063] Figure 8 The openings in the scribe seal in the die 801 are arranged at opposite sides so that any migrating ions or contaminants will not be able to cross the two scribe seal openings and move into the interior of the integrated circuit die. Various other embodiment arrangements can be formed to interrupt the flow of the inductive current in the scribe seal while preventing ions or contaminants from reaching the interior of the integrated circuit die.

[0064] Fig. 9 An alternative embodiment comprising a scored seal with an opening is illustrated in plan view. For clarity, Fig. 9 The notation used in Figure 8 For example, integrated circuit die 601 corresponds to integrated circuit die 801. Fig. 9 In the embodiment shown in , the openings are formed in the corner regions of the scored seal.

[0065] exist Fig. 9 In FIG. 9 , the integrated circuit die 901 includes an outer scribe seal 905 having an opening in one corner 915. A second scribe seal 907 spaced apart from and formed within the scribe seal 905 has a second opening 913.

[0066] exist Fig. 9 In the embodiment of the present invention, the openings 915, 913 extend through each conductor layer and through the conductive via layer of the corresponding scribe seal 905, 907 and prevent or reduce the flow of induced current in the scribe seal. Fig. 9 The openings in are arranged away from each other and at opposite corners of the integrated circuit die 901. The positions of the openings are arranged to prevent ions from migrating into the interior of the integrated circuit die 901 by placing the openings away from each other.

[0067] Fig.10 An integrated circuit die 1001 incorporating another alternative embodiment is illustrated in plan view. For clarity, like reference numerals are shown in FIG. Fig.10 Used in similar Figure 8 For example, the integrated circuit die 1001 corresponds to Figure 8 The integrated circuit die 801 in the Fig.10In FIG. 1 , an integrated circuit die 1001 has a scribe seal 1005 and a scribe seal 1007, wherein scribe seal 1005 is formed at or near the outer periphery of the integrated circuit die 1001 and scribe seal 1007 is formed spaced apart from scribe seal 1005 and is located within scribe seal 1005. Fig.10 1, each of the scribe seals 1005, 1007 has two openings. For example, the scribe seal 1005 has openings 1021, 1023 formed on opposite sides of the integrated circuit die 1001 and positioned away from each other. The scribe seal 1007 has openings 1027, 1031 formed on opposite sides and away from each other and positioned away from the opening in the scribe seal 1005.

[0068] Fig.11 In cross-sectional views, diagrams are shown e.g. Figures 8 to 10 For clarity, similar reference numerals are shown in Fig.11 Used in similar Figure 8 For example, the integrated circuit die 1101 corresponds to Figure 8 The integrated circuit die 801 in the Fig.11 , an integrated circuit die 1101 is shown with scribe seals 1105 and 1107 positioned spaced apart and in close proximity to one another at or near the periphery of the integrated circuit 1101. Contact level metal forms the bottom portion of the scribe seal structure above the substrate, shown as metal 1133 for scribe seal 1105 and metal 1137 for scribe seal 1107. The scribe seals each include an active area in the substrate 1101, in this example a p-diffusion region is formed for each scribe seal, shown as 1135 for scribe seal 1105 and 1139 for scribe seal 1107.

[0069] In operation, the diffusion regions 1135, 1139 are separated from each other by the substrate material of the integrated circuit die 1101, and this material has an intrinsic resistance 1141. Current can flow through the substrate between the diffusion regions, and the current will flow through the intrinsic resistance 1141.

[0070] Although Figures 8 to 11 The use of the scribe seal in the embodiment shown in greatly reduces the induced current flowing in the scribe seal, but in experiments, some induced current flows through the substrate, such as 1101, and continues to flow in the scribe seal even when the opening is formed.

[0071] Fig.12 Diagram illustrating an example of induced current flow. For clarity, Fig.12 The elements in Fig. 9Similar reference numerals are used for similar elements in FIG. 1 . For example, integrated circuit die 1201 corresponds to integrated circuit die 901. Fig.12 , the plan view of the integrated circuit die 1201 includes a plan view similar to Fig. 9 The scored seals 1205, 1207 are arranged in a manner similar to those in the scored seals, wherein the openings 1215 and 1213 are located in the corners. Fig.12 In the flow, there is an induced current or eddy current i E The induced current i E Flows through substrate 1201 near the opening at 1213 and back to scribed seal 1207, spanning the opening. Substrate 1201 has an intrinsic resistance so that the induced current is substantially reduced over previously known continuous scribed seals, yet the induced current can still flow. In additional alternative embodiments, the scribed seal includes structure in the substrate in the area where the scribed seal metal contacts contact the substrate to further reduce or eliminate the induced current flow.

[0072] Fig.13 An alternative embodiment having additional structures in the semiconductor substrate is illustrated in cross-sectional view. For clarity, Fig.13 The reference numerals for the elements in FIG. 1 are similar to those used for similar elements in the previous figures. For example, integrated circuit die 1301 corresponds to Figure 6 The integrated circuit bare die 601 in FIG.

[0073] exist Fig.13 In the example, the active area below the seal is scribed relative to Fig.11 The scored seal shown in the Fig.13 , scribe seals 1305, 1307 are shown in close proximity and spaced apart. A metal layer in contact with the substrate forms metal contacts 1333 of scribe seal 1305 and metal contacts 1343 of scribe seal 1307. Substrate 1301 is shown as a p-type silicon substrate, although other substrate types may also be used. Fig.13 1305, an N+ region is formed within an N-type diffusion in the scribed seal area, and metal contact 1333 of scribed seal 1305 contacts N+ region 1335, which is located within N diffusion 1337. Similarly, N+ region 1345 is formed within N-type diffusion 1347 in the scribed seal area of ​​scribed seal 1307. Metal contact 1343 contacts N+ region 1345 and N-type region 1347.

[0074] In operation, the p-silicon substrate has a boundary with an N-region that forms intrinsic and reverse biased diodes at the pn junction for both the N-region 1337 corresponding to the scribed seal 1305 and the N-region 1347 corresponding to the scribed seal 1307. The intrinsic diode of the scribed seal 1305 is labeled 1351, and the intrinsic diode of the scribed seal 1307 is labeled 1353. These diodes are formed due to the pn junction between the N-diffusion and the P-type silicon substrate.

[0075] Intrinsic diodes 1351 and 1353 are reverse biased with respect to the scored seal. Therefore, when using Fig.13 In the embodiments described herein, induced currents or eddy currents are prevented or greatly reduced from flowing in the substrate and between the scribed seals.

[0076] However, when using Fig.13 In the embodiment of FIG. 5 , some current may still flow in the substrate from the scribed seal. Fig.14 Another embodiment is illustrated that provides additional structure to prevent or reduce induced current from flowing in the substrate.

[0077] exist Fig.14 For clarity, the components have similar Fig.13 For example, Fig.14 The scored seal 1405 corresponds to Fig.13 The scored seal 1305 in.

[0078] Fig.14 An alternative embodiment of a scribe seal is illustrated in a cross-sectional view. Scribe seals 1405 and 1407 are spaced apart from one another at a peripheral region of integrated circuit die 1401. Metal contacts 1433 of scribe seal 1405 and metal contacts 1443 of scribe seal 1407 overlie the semiconductor substrate. Fig.14 In the embodiment, an N+ region 1435 is formed for the scribe seal 1405, and another N+ region 1445 is formed for the scribe seal 1407. The integrated circuit die 1401 is formed of a p-type silicon substrate material. The scribe seals 1405 and 1407 include N-type trenches 1437 and 1447 of the P-type region surrounding the N+ diffusion regions 1435 and 1445.

[0079] Intrinsic diodes are formed at the pn junctions formed in the scribed seals 1405, 1407. For example, diode 1461 is formed between the p-type material surrounding the N+ diffusion region 1435 and the N+ diffusion region. A second intrinsic diode 1463 is formed between the P-type material surrounding the N+ diffusion region and the N- trench 1437. A third intrinsic diode 1451 of the scribed seal 1405 is formed between the P-type silicon substrate 1401 and the N- trench 1437.

[0080] Similarly, the scribed seal 1407 has an intrinsic diode 1471 between the N-type region 1445 and the surrounding P-type silicon material, a diode 1473 between the N-trench 1447 and the P-type silicon material surrounding the N+ region 1445 , and a diode 1453 between the P-type silicon substrate 1401 and the N-trench 1447 .

[0081] In operation, induced current or eddy current is blocked or reduced by six intrinsic diodes formed in the scribed seals 1405 and 1407. Diode 1461 is reverse biased from the N+ diffusion region 1435 and the P silicon material surrounding the N+ diffusion 1435. Similarly intrinsic diode 1451 is reverse biased from the N- trench 1437 and the P-type silicon 1401. Current flowing from the scribed seal 1407 toward the scribed seal 1405 is blocked by the reverse biased diode 1463 between the N- trench 1437 and the P silicon material surrounding the N+ diffusion 1435.

[0082] exist Fig.14 Embodiments of the invention prevent or greatly reduce induced current in the scribe seal because the reverse biased diode blocks induced current from flowing from the scribe seal into the substrate material in either direction, and also blocks induced current from flowing from the substrate material into the scribe seal.

[0083] Fig.15 Additional aspects of the embodiments are illustrated in plan view. Fig.15 For clarity, the components have similar Fig.14 For example, Fig.15 The scored seal 1505 corresponds to Fig.14 The scored seal 1405 in.

[0084] exist Fig.15 , a portion of the scribed seal 1505 is shown in plan view. The contact metal portion 1533 is shown overlying the N-region 1537. A grounding strip 1539 is shown. By periodically grounding the metal 1533, the induced current can be further reduced or eliminated. Alternatively, 1539 can be tied to different bias levels. The use of bias strips can be used with Fig.14 The structures in (for example) are incorporated together to form additional embodiments and further improve performance.

[0085] Fig.16 The method embodiment is illustrated in a flow chart. The method starts at step 1601 (start). The method then proceeds to step 1603 where integrated circuit die areas are arranged into rows and columns on a semiconductor wafer and separated by scribe streets for sawing or singulation.

[0086] Fig.16The method then proceeds to step 1605. In step 1605, a plurality of scribe seals are defined around each integrated circuit die at a periphery of the integrated circuit die.

[0087] In step 1607, a scribe seal is formed along with other structures in the integrated circuit die, the scribe seal comprising a plurality of conductor layers stacked vertically and extending to the surface of the semiconductor substrate, each of the conductor layers being surrounded by an insulator material and comprising conductive vias in the insulator layers between the conductive layers. The scribe seal forms a vertical barrier layer comprising each conductor layer and each via layer used in the integrated circuit die.

[0088] At step 1609, openings are formed in the scribe seal for each of the conductor layers and for each of the via layers. The openings in the scribe seal will be formed simultaneously with the formation of each of the conductive layers, and each opening will be filled with insulator material when the insulator and conductor layers are completed.

[0089] At step 1611, after the integrated circuit dies are completed, the semiconductor wafer is singulated, thereby forming individual integrated circuit dies. Each individual integrated circuit die has the plurality of scribe seals at or near the periphery of the integrated circuit die and including openings.

[0090] Although the examples described above illustrate two scribe seals at the periphery of the integrated circuit die, in additional alternative embodiments, three or more scribe seals may be used. The openings in each of the scribe seals may reduce or eliminate the induced current. The additional scribe seals may also include Fig.13 and 14 The intrinsic diode is used to further reduce the induced current flowing in the substrate.

[0091] Exemplary embodiments and arrangements include an integrated circuit die comprising: a plurality of lower-level conductor layers overlying a semiconductor substrate; a plurality of lower-level insulator layers located between and surrounding the plurality of lower-level conductor layers; a plurality of lower-level vias extending vertically through the lower-level insulator layers and electrically coupling some of the lower-level conductors; a plurality of upper-level conductor layers overlying the lower-level conductor layers; a plurality of upper-level insulator layers located between and surrounding the upper-level conductor layers; and a plurality of upper-level vias extending vertically through the upper-level insulator layers and coupling the upper-level conductor layers. The integrated circuit die includes: at least two scribed seals, which are positioned at the periphery of the integrated circuit die and spaced apart from each other, the at least two scribed seals including the upper level conductor layer, the upper level via, the lower level conductor layer and the lower level via to form a vertical barrier layer extending vertically from the semiconductor substrate to the passivation layer at the upper surface of the integrated circuit die; and at least one opening, which vertically extends through a corresponding one of the at least two scribed seals and extends through: the upper level conductor layer, the upper level via layer, the lower level conductor layer and the lower level via layer.

[0092] In yet another example, the integrated circuit die includes the at least two scribe seals, the at least two scribe seals further including a second opening spaced apart from the at least one opening. In yet another example, in the integrated circuit die, the at least one opening of the at least two scribe seals is in a corner of the integrated circuit die.

[0093] In yet another example, in the integrated circuit die described above, the at least two scribed seals have openings positioned in a central portion of one side of the integrated circuit die, and the at least one opening of a first scribed seal of the at least two scribed seals is on a side opposite to the at least one opening of a second scribed seal of the at least two scribed seals. In an alternative example, in the integrated circuit die described above, the at least two scribed seals further include: a first doped diffusion region having a first concentration of a first conductivity type in the semiconductor substrate; and a second doped diffusion region having a second concentration of the first conductivity type in the semiconductor substrate and surrounding the first doped diffusion region; and the semiconductor substrate has a second conductivity type different from the first conductivity type. In yet another example, in the integrated circuit die described above, the at least two scribed seals further include at least one lower level conductor having a stripe portion coupled to receive a bias voltage.

[0094] In an additional example, an apparatus includes a plurality of integrated circuit dies on a semiconductor substrate and spaced apart from one another, and the plurality of integrated circuit dies have a plurality of scribe seals formed at peripheries of respective ones of the plurality of integrated circuit dies, the plurality of scribe seals further including: a plurality of lower-level conductor layers overlying the semiconductor substrate; a plurality of lower-level insulator layers between and surrounding the lower-level conductor layers; a plurality of lower-level vias extending vertically through the lower-level insulator layers and electrically coupling the lower-level conductor; a plurality of upper-level conductor layers overlying the lower-level conductor layer; a plurality of upper-level insulator layers located between and surrounding the plurality of upper-level conductor layers; a plurality of upper-level vias extending vertically through the upper-level insulator layers and coupling the upper-level conductor layers; and at least one opening extending vertically through each of the scribed seals and cutting through each of: the upper-level conductor layer, the upper-level via layer, the lower-level conductor layer, and the lower-level via layer.

[0095] In another exemplary arrangement, in the apparatus described above, the plurality of scribed seals form a vertical metal barrier layer around the periphery of the integrated circuit die and extend from the surface of the semiconductor substrate to a passivation layer. In yet another example, in the apparatus described above, at least one opening in the scribed seal is located in a corner portion of the integrated circuit die. In yet another additional example, in the apparatus described above, the plurality of scribed seals include at least a first scribed seal and a second concentric scribed seal. In yet another exemplary arrangement, in the apparatus described above, the plurality of scribed seals include at least a first scribed seal having a first opening and a second scribed seal having a second opening positioned at a point opposite to the first opening. In an additional arrangement, in the apparatus described above, at least one opening in the scribed seal is located in a central portion of one side of the integrated circuit die. In yet another arrangement, in the apparatus described above, the at least one opening in the scribed seal is located in a corner portion of the integrated circuit die. In yet another arrangement, in the apparatus described above, the plurality of scribe seals each include at least two openings, the two openings being positioned on opposite sides of the integrated circuit die.

[0096] In an additional exemplary arrangement, in the apparatus described above, the plurality of scored seals include a first scored seal and a second scored seal positioned spaced apart from and surrounded by the first scored seal, and the at least two openings in the first scored seal are spaced apart from the at least two openings in the second scored seal.

[0097] In yet another exemplary arrangement, the plurality of scribed seals further include: a first doped diffusion region having a first concentration of a first conductivity type in the semiconductor substrate; and a second doped diffusion region having a second concentration of the first conductivity type in the semiconductor substrate and surrounding the first doped diffusion region; wherein the semiconductor substrate has a second conductivity type different from the first conductivity type.

[0098] In yet another arrangement, in the apparatus described above, the scribed seals in the plurality of scribed seals further include: a first doped diffusion region having a first concentration of a first conductivity type in the semiconductor substrate; and a first region of the semiconductor substrate surrounding the first doped diffusion region in the semiconductor substrate and having a second conductivity type different from the first conductivity type; and a second doped diffusion region in the semiconductor substrate surrounding the first region of the semiconductor substrate and having a second concentration of the first conductivity type; and the semiconductor substrate has the second conductivity type. In yet another exemplary arrangement, in the apparatus described above, the first conductivity type is N-type, and the second conductivity type is P-type.

[0099] An exemplary method arrangement includes: defining an integrated circuit region on a semiconductor substrate; defining a scribed seal region at a periphery of the integrated circuit region; forming at least two scribed seals spaced apart from each other and surrounding the periphery of the integrated circuit region, including: forming a lower level conductor layer spaced apart by a lower level insulator layer, forming lower level vias extending through the lower level insulator layer between the lower level conductors, forming an upper level conductor layer overlying the lower level conductor layer, the upper level conductor layer spaced apart by the upper level insulator layer, forming lower level vias extending through the upper level insulator layer between the upper level conductors, layer and electrically connects the upper-level conductor layers to each other and to the upper-level conductive holes of the lower-level conductor; the scribed seal forms a vertical barrier layer, which extends from a passivation layer overlying the scribed seal area and passes through the upper-level conductor layer, the upper-level conductive hole layer, the lower-level conductor layer and the lower-level conductive hole layer, and contacts the semiconductor substrate; and at least one vertical opening is formed in the scribed seal, which extends through each of the upper-level conductor layer, the upper-level conductive hole layer, the lower-level conductor layer and the lower-level conductive hole layer.

[0100] In yet another example, in the method described above, forming at least one vertical opening in the scored seal further includes positioning the at least one vertical opening in the at least two scored seals that are separated from each other.

[0101] Modifications are possible in the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. An integrated circuit die having a first side and a second side having different sides, the integrated circuit die comprising: a semiconductor substrate having a first conductivity type; a first scribe seal and a second scribe seal adjacent to a periphery of the integrated circuit die, the first scribe seal and the second scribe seal comprising respective lower level conductor layers, lower level vias, upper level conductor layers, and upper level vias, the lower level conductor layers overlying the semiconductor substrate, and the upper level conductor layers overlying the lower level conductor layers, wherein the first scribe seal and the second scribe seal are concentric; a lower-level insulator layer located between and surrounding the lower-level conductor layers, the lower-level via extending through and electrically coupling some of the lower-level insulator layers; an upper-level insulator layer located between and surrounding the upper-level conductor layers, the upper-level via extending through and electrically coupling some of the upper-level insulator layers; and The first scribe seal has a first opening adjacent to the first side of the integrated circuit die, the first opening extending through an upper level conductor layer, an upper level via layer, a lower level conductor layer, and a lower level via layer of the first scribe seal; and the second scribe seal having a second opening adjacent the second side of the integrated circuit die, the second opening extending through an upper level conductor layer, an upper level via layer, a lower level conductor layer, and a lower level via layer of the second scribe seal; The first scratch seal includes: a first doped diffusion region in the semiconductor substrate, and a second doped diffusion region in the semiconductor substrate, the first doped diffusion region having a first concentration of a second conductivity type different from the first conductivity type; a portion of the semiconductor substrate surrounding the first doped diffusion region and having the first conductivity type; and the second doped diffusion region surrounding the portion and having a second concentration of the second conductivity type.

2. The integrated circuit die of claim 1 , wherein the integrated circuit die has a first surface and a second surface relative to each other, the integrated circuit die further comprising a passivation layer located on the first surface, the semiconductor substrate is located on the second surface, and the first scribe seal and the second scribe seal form respective barrier layers extending from the semiconductor substrate to the passivation layer.

3. The integrated circuit die of claim 1, wherein the first opening is located in a first corner portion of the integrated circuit die and the second opening is located in a second corner portion of the integrated circuit die.

4. The integrated circuit die of claim 1, wherein the second opening is opposite to the first opening.

5. The integrated circuit die of claim 1, wherein the first opening is adjacent to a central portion of the first side.

6. The integrated circuit die of claim 1, wherein The first scribe seal has a third opening, the third opening is opposite to the first opening, the third opening extends through the upper level conductor layer, the upper level via layer, the lower level conductor layer and the lower level via layer of the first scribe seal; and The second scribe seal has a fourth opening opposite to the second opening, the fourth opening extending through the upper level conductor layer, the upper level via layer, the lower level conductor layer, and the lower level via layer of the second scribe seal.

7. The integrated circuit die of claim 1 wherein the second scribe seal is spaced apart from the first scribe seal.

8. The integrated circuit die of claim 1, wherein The semiconductor substrate and the second doped diffusion region form a reverse biased intrinsic diode to prevent eddy current from flowing from the second doped diffusion region into the semiconductor substrate.

9. The integrated circuit die of claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type.

Images