An AlGaN / GaN heterojunction HEMT device compatible with Si-CMOS process and a manufacturing method thereof

Abstract

The present invention discloses an AlGaN / GaN heterojunction HEMT device compatible with Si-CMOS process and a manufacturing method. The device comprises: an AlGaN / GaN heterojunction epitaxial layer, a passivation layer, a gate dielectric layer, a gold-free gate electrode, and a gold-free source and drain electrode. The AlGaN / GaN heterojunction epitaxial layer comprises, from bottom to top, a substrate, a nitride nucleation layer, a nitride buffer layer, a GaN channel layer, an AlGaN intrinsic barrier layer, and an AlGaN heavily doped layer. The AlGaN heavily doped layer generates charges by ionizing donors to compensate for the surface acceptor energy level of the semiconductor, thereby suppressing current collapse. At the same time, it forms an ohmic contact with the electrode through low-temperature annealing. The gold-free electrode avoids Au contamination of the Si-CMOS process line. The present invention adopts a double-layer AlGaN layer in the AlGaN / GaN heterojunction, combines the gold-free electrode process and the low-temperature ohmic process, can effectively suppress the current collapse of the HEMT device, improve the device performance, and reduce the process temperature and simplify the process flow, thereby solving the technical bottleneck of the compatibility of the AlGaN / GaN heterojunction HEMT with the Si-CMOS process, and helping to reduce the manufacturing cost of the AlGaN / GaN heterojunction HEMT.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a method for manufacturing an AlGaN / GaN heterojunction HEMT device compatible with Si-CMOS technology, which can be used in the fields of power electronics and microwave communications. Background Art

[0002] With the development of modern weapons and equipment, aerospace, nuclear energy, communication technology, automotive electronics, and switching power supplies, higher requirements are placed on the performance of semiconductor devices. As a typical representative of wide bandgap semiconductor materials, GaN-based materials have the characteristics of large bandgap width, high electron saturation drift velocity, high critical breakdown field strength, high thermal conductivity, good stability, corrosion resistance, and radiation resistance. They can be used to make high-temperature, high-frequency, and high-power electronic devices. In addition, GaN also has excellent electronic properties and can form a modulation-doped AlGaN / GaN heterostructure with AlGaN. This structure can obtain a temperature higher than 1500cm at room temperature. 2 / Vs, and an electron mobility as high as 3×10 7 cm / s and a peak electron velocity of 2×10 7 cm / s saturated electron velocity, and obtain a higher two-dimensional electron gas density than the second-generation compound semiconductor heterostructure, and is hailed as an ideal material for the development of microwave power devices. Therefore, microwave power devices based on AlGaN / GaN heterojunctions have very good application prospects in high-frequency, high-power wireless communications, radars and other fields.

[0003] However, HEMT devices still face many challenges, such as current collapse, threshold stability and device reliability. Current collapse refers to the phenomenon that the on-resistance of the device increases after the device is stressed by high-voltage off-state. One of the main reasons for this phenomenon is the more serious interface state or surface state in the HEMT device, and the electron concentration in the device channel is reduced due to the capture of defects. At the same time, the high cost limits the widespread application of HEMT devices. One way to reduce the manufacturing cost of HEMT is to achieve large-scale production of HEMT in Si-CMOS process lines. However, several factors limit the processing of HEMT devices in CMOS process lines: 1. The gold contact metal used in the ohmic and Schottky contact processes of conventional HEMT devices causes Au to contaminate the CMOS process line; 2. The ohmic process temperature of conventional HEMT devices is relatively high, causing Ga to contaminate the CMOS process line. At the same time, the high temperature causes the AlGaN / GaN epitaxial layer on the large-size silicon substrate to break, reducing the product yield. Summary of the invention

[0004] The purpose of the present invention is to overcome the defects of the above-mentioned prior art. By adopting a double-layer AlGaN layer in the AlGaN / GaN heterojunction, combined with a gold-free electrode process and a low-temperature ohmic process, the current collapse of the HEMT device can be effectively suppressed, the device performance can be improved, and the process temperature can be reduced and the process flow can be simplified. The technical bottleneck of the compatibility of the AlGaN / GaN heterojunction HEMT with the Si-CMOS process is solved, which helps to reduce the manufacturing cost of the AlGaN / GaN heterojunction HEMT.

[0005] The purpose of the present invention is achieved by at least one of the following technical solutions.

[0006] An AlGaN / GaN heterojunction HEMT device compatible with Si-CMOS process, the device comprises: an AlGaN / GaN heterojunction epitaxial layer, a passivation layer, a gate dielectric layer, a gold-free gate electrode, and a gold-free source and drain electrode. The AlGaN / GaN heterojunction epitaxial layer comprises, from bottom to top, a substrate, a nitride nucleation layer, a nitride buffer layer, a GaN channel layer, an AlGaN intrinsic barrier layer, and an AlGaN heavily doped layer. The AlGaN heavily doped layer generates charges by ionizing donors to compensate for the surface acceptor energy level of the semiconductor, thereby suppressing current collapse. At the same time, the AlGaN heavily doped layer forms an ohmic contact with the gold-free source and drain electrode through low temperature annealing. The gold-free electrode prevents Au from contaminating the Si-CMOS process line.

[0007] Furthermore, the substrate of the AlGaN / GaN heterojunction epitaxial layer is made of sapphire, silicon, silicon carbide or homoepitaxial GaN, the nitride nucleation layer is GaN or AlN, the nitride buffer layer is GaN, AlGaN, gradient composition AlGaN or a combination thereof, and there is a two-dimensional electron gas with high electron mobility between the GaN channel layer and the AlGaN intrinsic barrier layer.

[0008] Furthermore, the molar content of Al element in the AlGaN intrinsic barrier layer is between 0.2 and 0.3, the thickness is 10 to 15 nm, and no doping is performed during epitaxial growth of the layer.

[0009] Furthermore, the molar content of Al in the heavily doped AlGaN layer is between 0.1 and 0.2, the thickness is 5 to 10 nm, and the doping concentration of the donor impurity (such as Si) is 1x10 18 cm ‐3 Up to 1x10 20 cm ‐3 .

[0010] Furthermore, the passivation layer covers the heavily doped AlGaN layer, and is made of one of SiN, SiO2, and SiON, or a multilayer structure formed by a combination thereof, with a thickness of 100nm to 200nm.

[0011] Furthermore, the gate dielectric layer covers the passivation layer, and its material is one of SiN, SiO2, SiON, Ga2O3, Al2O3, AlN, HfO2, or a multilayer structure formed by a combination thereof, and its thickness is 20nm to 30nm.

[0012] Furthermore, the passivation layer under the gold-free gate electrode is removed, the bottom of the electrode contacts the gate dielectric layer, and the gate dielectric layer is between the gold-free gate electrode and the AlGaN heavily doped layer. At the same time, the corresponding AlGaN heavily doped layer under the gate electrode is completely or partially oxidized into oxide.

[0013] Furthermore, the material of the gold-free gate electrode is a multilayer metal, in which the bottom metal is Ni or other metals with higher work functions, and the surface layer is W, TiW or TiN, etc., which are stable and not easily oxidized in the air, forming a multilayer metal system such as Ni / W, Ni / TiW, or Ni / TiN.

[0014] Furthermore, the gate dielectric layer and the passivation layer below the gold-free source and drain electrode are removed, and the bottom of the gold-free source and drain electrode is in contact with the AlGaN heavily doped layer.

[0015] Furthermore, the material of the gold-free source and drain electrodes is a multilayer metal, wherein the bottom metal is a multilayer metal such as Ti / Al, and the surface layer is a metal such as W, TiW or TiN that is stable in the air and not easily oxidized, forming a multilayer metal system such as Ti / Al / Ti / W, or Ti / Al / TiW, or Ti / Al / Ti / TiN, and forming an ohmic contact with the AlGaN heavily doped layer through a low-temperature annealing process.

[0016] The preparation of the AlGaN / GaN heterojunction HEMT device compatible with Si-CMOS process comprises the following steps:

[0017] 1) Epitaxial growth: A nitride nucleation layer, a nitride buffer layer, a GaN channel layer, an AlGaN intrinsic barrier layer, and an AlGaN heavy doping layer are sequentially epitaxially grown on a substrate by a metal organic vapor deposition (MOCVD) method to form an AlGaN / GaN heterojunction epitaxial layer;

[0018] 2) Device isolation: Define the active area through photolithography, use photoresist to cover and protect the active area, use ICP or RIE etching to remove the AlGaN / GaN heterojunction outside the active area, and the etching depth is greater than the AlGaN intrinsic barrier layer. Remove the AlGaN heavily doped layer, AlGaN intrinsic barrier layer and part of the GaN channel layer to achieve isolation between different devices;

[0019] 3) Passivation layer deposition: depositing a passivation layer of a certain thickness on the AlGaN / GaN heterojunction epitaxial layer;

[0020] 4) Gate opening: Define the gold-free gate electrode pattern on the passivation layer through photolithography, etch the passivation layer through ICP or RIE, and completely remove the passivation layer under the gold-free gate electrode pattern. Oxidize the AlGaN heavily doped layer exposed in the gate electrode pattern through ICP or RIE to generate oxide or oxynitride;

[0021] 5) Gate dielectric layer: depositing a gate dielectric layer on the passivation layer to cover the surface of the entire device;

[0022] 6) Gate electrode: define the gold-free gate electrode pattern by photolithography, deposit the gold-free gate electrode metal film by electron beam evaporation or magnetron sputtering, and then form the gold-free gate electrode by lift-off process;

[0023] 7) Source and drain electrodes: Define the gold-free source and drain electrode pattern on the passivation layer through photolithography, etch the gate dielectric layer and passivation layer through ICP or RIE, and completely remove the gate dielectric layer and passivation layer under the gold-free source and drain electrode pattern. Deposit the gold-free source and drain electrode metal film through electron beam evaporation or magnetron sputtering, and then form the gold-free source and drain electrode through a lift-off process;

[0024] 8) Low temperature annealing: Through the annealing process, the gold-free source and drain electrode metal forms an ohmic contact with the AlGaN / GaN heterojunction epitaxial layer.

[0025] Furthermore, the molar content of Al element in the AlGaN intrinsic barrier layer is between 0.2 and 0.3, the thickness is 10 to 15 nm, and no doping is performed during epitaxial growth of the layer; the molar content of Al element in the AlGaN heavily doped layer is between 0.1 and 0.2, the thickness is 5 to 10 nm, and the doping concentration of donor impurities is between 1E18 cm-3 and 1E20 cm-3.

[0026] Furthermore, the material of the passivation layer is one of SiN, SiO2, SiON, or a combination thereof to form a multilayer structure with a thickness of 100nm to 200nm, and the deposition method can be one of metal organic chemical vapor deposition MOCVD, plasma enhanced chemical vapor deposition PECVD, and low pressure chemical vapor deposition LPCVD.

[0027] Furthermore, the oxidation treatment refers to the oxidation of all or part of the AlGaN heavily doped layer under the gate electrode by using oxygen ions through ICP or RIE, and the generated oxide or oxynitride is Al2O3, Ga2O3, AlSiON, AlON or any combination thereof.

[0028] Furthermore, the material of the gate dielectric layer is one of SiN, SiO2, SiON, Ga2O3, Al2O3, AlN, HfO2, or a combination thereof to form a multilayer structure with a thickness of 20nm to 30nm, and the deposition method can be one of plasma enhanced chemical vapor deposition PECVD and low pressure chemical vapor deposition LPCVD.

[0029] Furthermore, the material of the gold-free gate electrode is a multilayer metal, in which the bottom metal is Ni or other metals with higher work functions, and the surface layer is W, TiW or TiN, etc., which are stable and not easily oxidized in the air, forming a multilayer metal system such as Ni / W, Ni / TiW, or Ni / TiN.

[0030] Furthermore, the material of the gold-free source and drain electrodes is a multilayer metal, wherein the bottom metal is a multilayer metal such as Ti / Al, and the surface layer is a metal such as W, TiW or TiN that is stable in the air and not easily oxidized, forming a multilayer metal system such as Ti / Al / Ti / W, or Ti / Al / TiW, or Ti / Al / Ti / TiN, and forming an ohmic contact with the AlGaN heavily doped layer through a low-temperature annealing process.

[0031] Furthermore, low temperature annealing refers to placing the sample in a pure nitrogen atmosphere, annealing at a temperature not higher than 600 degrees Celsius, and the annealing time is 5 to 10 minutes.

[0032] Compared with the prior art, the present invention has the following advantages and technical effects:

[0033] The device is an AlGaN / GaN heterojunction HEMT device compatible with Si-CMOS process. A double AlGaN layer is used in the AlGaN / GaN heterojunction. The AlGaN heavily doped layer generates charges by ionizing donors to compensate for the surface acceptor energy level of the semiconductor, thereby suppressing current collapse and improving device performance. Combining the gold-free electrode process and low-temperature ohmic process, Au contamination of the Si-CMOS process line is avoided, while the process temperature is reduced and the process flow is simplified, solving the technical bottleneck of AlGaN / GaN heterojunction HEMT compatibility with Si-CMOS process, and helping to reduce the manufacturing cost of AlGaN / GaN heterojunction HEMT. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic structural diagram of an AlGaN / GaN heterojunction HEMT device compatible with Si-CMOS process in the present invention.

[0035] Figure 2a to Figure 2g It is a schematic diagram of the preparation process of an AlGaN / GaN heterojunction HEMT device compatible with Si-CMOS process in an example of the present invention. DETAILED DESCRIPTION

[0036] The specific implementation of the present invention is further described below in conjunction with the drawings and examples, but the implementation and protection of the present invention are not limited thereto. It should be pointed out that if there are any processes or process parameters that are not particularly described in detail below, they can be implemented by those skilled in the art with reference to the prior art.

[0037] Reference Figure 1 , an AlGaN / GaN heterojunction HEMT device compatible with Si-CMOS process and a manufacturing method, the device comprises: an AlGaN / GaN heterojunction epitaxial layer 1, a passivation layer 2, a gate dielectric layer 3, a gold-free gate electrode 4, and a gold-free source and drain electrode 5. The AlGaN / GaN heterojunction epitaxial layer comprises, from bottom to top, a substrate 6, a nitride nucleation layer 7, a nitride buffer layer 8, a GaN channel layer 9, an AlGaN intrinsic barrier layer 10, and an AlGaN heavily doped layer 11.

[0038] The substrate 6 of the AlGaN / GaN heterojunction epitaxial layer 1 is made of silicon, the nitride nucleation layer 7 is AlN, the nitride buffer layer 8 is GaN, and there is a two-dimensional electron gas with high electron mobility between the GaN channel layer 9 and the AlGaN intrinsic barrier layer 10. The molar content of the Al element in the AlGaN intrinsic barrier layer 10 is 0.25, the thickness is 15nm, and no doping is performed when the layer is epitaxially grown. The molar content of the Al element in the AlGaN heavily doped layer 11 is 0.15, the thickness is 5nm, and the doping concentration of the donor impurity is 1E20cm-3.

[0039] The passivation layer 2 covers the AlGaN heavily doped layer 11, and is made of SiN with a thickness of 200nm. The gate dielectric layer 3 covers the passivation layer 2, and is made of SiN with a thickness of 30nm. The passivation layer 2 under the gold-free gate electrode 4 is removed, and the bottom of the electrode is in contact with the gate dielectric layer 3, and the gate dielectric layer 3 is between the gold-free gate electrode 4 and the AlGaN heavily doped layer 11. At the same time, the corresponding AlGaN heavily doped layer 11 under the gate electrode is partially oxidized into Al2O3. The material of the gold-free gate electrode 4 is Ni / TiN=50 / 150nm. The gate dielectric layer 3 and the passivation layer 2 under the gold-free source and drain electrode 5 are removed, and the bottom of the gold-free source and drain electrode 5 is in contact with the AlGaN heavily doped layer 11. The material of the gold-free source and drain electrode 5 is Ti / Al / Ti / TiN=20 / 100 / 20 / 100nm, and an ohmic contact is formed with the AlGaN heavily doped layer 11 through a low-temperature annealing process.

[0040] Just as an example, Figure 2a to Figure 2g , the specific implementation steps are as follows:

[0041] Step 1: epitaxial growth. By using the metal organic vapor deposition (MOCVD) method, a nitride nucleation layer 7, a nitride buffer layer 8, a GaN channel layer 9, an AlGaN intrinsic barrier layer 10, and an AlGaN heavy doping layer 11 are epitaxially grown on a substrate 6 in sequence to form an AlGaN / GaN heterojunction epitaxial layer 1, as shown in FIG. Figure 2a As shown; wherein the molar content of Al element in the AlGaN intrinsic barrier layer 10 is 0.25, the thickness is 15nm, and no doping is performed during epitaxial growth of the layer. The molar content of Al element in the AlGaN heavily doped layer 11 is 0.15, the thickness is 5nm, and the doping concentration of the donor impurity is 1E20cm-3.

[0042] Step 2: Device isolation. Define the active area through photolithography, use photoresist to cover and protect the active area, use ICP etching to remove the AlGaN / GaN heterojunction outside the active area, the etching depth is greater than the AlGaN intrinsic barrier layer 10, which is 200nm, and remove the AlGaN heavily doped layer 11, the AlGaN intrinsic barrier layer 10 and a part of the GaN channel layer 9 to achieve isolation between different devices, such as Figure 2b As shown;

[0043] Step 3: Deposition of passivation layer. A passivation layer 2 is deposited on the AlGaN / GaN heterojunction epitaxial layer, such as Figure 2c As shown. The material of the passivation layer 2 is SiN, with a thickness of 200 nm, and the deposition method is low pressure chemical vapor deposition LPCVD;

[0044] Step 4: Gate opening. Define a gold-free gate electrode pattern on the passivation layer by photolithography, and etch the passivation layer 2 by ICP using fluorine-based ions to completely etch away the passivation layer 2 under the gold-free gate electrode pattern. Figure 2d Then, the AlGaN heavily doped layer 11 exposed in the gate electrode pattern is oxidized by using oxygen ions through ICP to generate oxide Al2O3;

[0045] Step 5: Gate dielectric layer. A gate dielectric layer 3 is deposited on the passivation layer 2 to cover the entire surface of the device. The material is SiN with a thickness of 30 nm. The deposition method is low-pressure chemical vapor deposition LPCVD. Figure 2e shown.

[0046] Step 6: Gate electrode. Define the gold-free gate electrode pattern by photolithography, deposit the gold-free gate electrode metal film Ni / TiN=50 / 150nm by electron beam evaporation, and then form the gold-free gate electrode 5 by lift-off process. Figure 2f As shown;

[0047] Step 7, source and drain electrodes. Define the gold-free source and drain electrode pattern on the passivation layer by photolithography, etch the gate dielectric layer 3 and the passivation layer 2 by ICP, and completely remove the gate dielectric layer 3 and the passivation layer 2 under the gold-free source and drain electrode pattern. Deposit the gold-free source and drain electrode metal film Ti / Al / Ti / TiN=20 / 100 / 20 / 100nm by electron beam evaporation, and then form the gold-free source and drain electrode 5 by stripping process, as shown in FIG. Figure 2g As shown;

[0048] Step 8: low temperature annealing: The sample is placed in a pure nitrogen atmosphere and annealed at 600 degrees Celsius for 5 minutes, so that the gold-free source and drain electrode metal forms an ohmic contact with the AlGaN / GaN heterojunction epitaxial layer.

[0049] The device is an AlGaN / GaN heterojunction HEMT device compatible with Si-CMOS process. A double AlGaN layer is used in the AlGaN / GaN heterojunction. The AlGaN heavily doped layer 11 generates charges by ionizing donors to compensate for the surface acceptor energy level of the semiconductor, thereby suppressing current collapse and improving device performance. Combining the gold-free electrode process and low-temperature ohmic process, Au contamination of the Si-CMOS process line is avoided, while the process temperature is reduced and the process flow is simplified, solving the technical bottleneck of AlGaN / GaN heterojunction HEMT compatibility with Si-CMOS process, and helping to reduce the manufacturing cost of AlGaN / GaN heterojunction HEMT.

[0050] The above embodiments are only preferred examples of the present invention and do not constitute any limitation to the present invention. It is obvious that for professionals in this field, after understanding the content and principles of the present invention, they can make various modifications and changes in form and details according to the method of the present invention without departing from the principles and scope of the present invention. However, these modifications and changes based on the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. An AlGaN / GaN heterojunction HEMT device compatible with Si-CMOS process, characterized in that: The device comprises an AlGaN / GaN heterojunction epitaxial layer, a passivation layer, a gate dielectric layer, a gold-free gate electrode, and a gold-free source and drain electrode; the AlGaN / GaN heterojunction epitaxial layer comprises, from bottom to top, a substrate, a nitride nucleation layer, a nitride buffer layer, a GaN channel layer, an AlGaN intrinsic barrier layer, and an AlGaN heavily doped layer; the AlGaN heavily doped layer generates charges by ionizing donors to compensate for the surface acceptor energy level of the semiconductor, thereby suppressing current collapse, and at the same time forms an ohmic contact with the gold-free source and drain electrode through low temperature annealing; the preparation of the device comprises the following steps: 1) Epitaxial growth: A nitride nucleation layer, a nitride buffer layer, a GaN channel layer, an AlGaN intrinsic barrier layer, and an AlGaN heavy doping layer are sequentially epitaxially grown on a substrate by a metal organic vapor deposition (MOCVD) method to form an AlGaN / GaN heterojunction epitaxial layer; 2) Device isolation: Define the active area through photolithography, use photoresist to cover and protect the active area, use ICP or RIE etching to remove the AlGaN / GaN heterojunction outside the active area, and the etching depth is greater than the AlGaN intrinsic barrier layer. Remove the AlGaN heavily doped layer, AlGaN intrinsic barrier layer and part of the GaN channel layer to achieve isolation between different devices; 3) Passivation layer deposition: depositing a passivation layer of a certain thickness on the AlGaN / GaN heterojunction epitaxial layer; 4) Gate opening: define a gold-free gate electrode pattern on the passivation layer by photolithography, etch the passivation layer by ICP or RIE, and completely remove the passivation layer under the gold-free gate electrode pattern; oxidize the AlGaN heavily doped layer exposed in the gate electrode pattern by ICP or RIE to generate oxide or oxynitride; 5) Gate dielectric layer: depositing a gate dielectric layer on the passivation layer to cover the surface of the entire device; 6) Gate electrode: define the gold-free gate electrode pattern by photolithography, deposit the gold-free gate electrode metal film by electron beam evaporation or magnetron sputtering, and then form the gold-free gate electrode by lift-off process; 7) Source and drain electrodes: define the gold-free source and drain electrode pattern on the passivation layer by photolithography, etch the gate dielectric layer and the passivation layer by ICP or RIE, and completely remove the gate dielectric layer and the passivation layer under the gold-free source and drain electrode pattern; deposit the gold-free source and drain electrode metal film by electron beam evaporation or magnetron sputtering, and then form the gold-free source and drain electrodes by stripping process; 8) Low temperature annealing: Through the annealing process, the gold-free source and drain electrode metal forms an ohmic contact with the AlGaN / GaN heterojunction epitaxial layer; The molar content of Al element in the AlGaN intrinsic barrier layer is between 0.2 and 0.3, the thickness is 10 to 15 nm, and no doping is performed during epitaxial growth of the layer; the molar content of Al element in the AlGaN heavily doped layer is between 0.1 and 0.2, the thickness is 5 to 10 nm, and the doping concentration of donor impurities is between 1E18 cm-3 and 1E20 cm-3; the material of the passivation layer is one of SiN, SiO2, SiON, or a multilayer structure formed by a combination thereof, with a thickness of 100 nm to 200 nm, and the deposition method can be metal organic chemical vapor deposition MOCVD, plasma enhanced chemical vapor deposition PECVD, low pressure chemical gas deposition The gate dielectric layer is a material of SiN, SiO2, SiON, Ga2O3, Al2O3, AlN, HfO2, or a multilayer structure formed by a combination thereof, with a thickness of 20nm to 30nm, and the deposition method can be one of plasma enhanced chemical vapor deposition PECVD and low pressure chemical vapor deposition LPCVD; the bottom metal is Ti / Al multilayer metal, and the surface layer is W, TiW or TiN, forming a Ti / Al / Ti / W, or Ti / Al / TiW, or Ti / Al / Ti / TiN multilayer metal system, and forming an ohmic contact with the AlGaN heavily doped layer through a low temperature annealing process.

2. The AlGaN / GaN heterojunction HEMT device compatible with Si-CMOS process according to claim 1, characterized in that: The substrate of the AlGaN / GaN heterojunction epitaxial layer is made of sapphire, silicon, silicon carbide or homoepitaxial GaN, the nitride nucleation layer is made of GaN or AlN, the nitride buffer layer is one or a combination of two or more of GaN, AlGaN, and gradient composition AlGaN, and there is a two-dimensional electron gas between the GaN channel layer and the AlGaN intrinsic barrier layer.

3. The AlGaN / GaN heterojunction HEMT device compatible with Si-CMOS process according to claim 1, characterized in that: The molar content of Al in the AlGaN intrinsic barrier layer is 0.2-0.3, the thickness is 10-15 nm, and no doping is performed during epitaxial growth of the AlGaN intrinsic barrier layer; the molar content of Al in the AlGaN heavily doped layer is 0.1-0.2, the thickness is 5-10 nm, and the doping concentration of the donor impurity is 1x10 18 cm -3 Up to 1x10 20 cm -3 .

4. The AlGaN / GaN heterojunction HEMT device compatible with Si-CMOS process according to claim 1, characterized in that: The passivation layer covers the AlGaN heavily doped layer, and its material is one of SiN, SiO2, SiON, or a multilayer structure formed by a combination thereof, with a thickness of 100nm to 200nm; the gate dielectric layer covers the passivation layer, and its material is one of SiN, SiO2, SiON, Ga2O3, Al2O3, AlN, HfO2, or a multilayer structure formed by a combination thereof, with a thickness of 20nm to 30nm.

5. The AlGaN / GaN heterojunction HEMT device compatible with Si-CMOS process according to claim 1, characterized in that: The passivation layer under the gold-free gate electrode is removed, the bottom of the gold-free gate electrode contacts the gate dielectric layer, and the gate dielectric layer is between the gold-free gate electrode and the AlGaN heavily doped layer; at the same time, the corresponding AlGaN heavily doped layer under the gate electrode is completely or partially oxidized into oxide; the material of the gold-free gate electrode is a multi-layer metal, in which the bottom metal is Ni, and the surface layer is W, TiW or TiN, which is a metal that is stable and not easily oxidized in the air, forming a Ni / W, or Ni / TiW, or Ni / TiN multi-layer metal system.

6. The AlGaN / GaN heterojunction HEMT device compatible with Si-CMOS process according to claim 1, characterized in that: The gate dielectric layer and the passivation layer under the gold-free source and drain electrodes are removed, and the bottom of the gold-free source and drain electrodes is in contact with the AlGaN heavily doped layer.

7. The AlGaN / GaN heterojunction HEMT device compatible with Si-CMOS process according to claim 1, characterized in that: The material of the gold-free source and drain electrodes is a multilayer metal, wherein the bottom metal is a Ti / Al multilayer metal and the surface layer is W, TiW or TiN, forming a Ti / Al / Ti / W, or Ti / Al / TiW, or Ti / Al / Ti / TiN multilayer metal system, and forming an ohmic contact with the AlGaN heavily doped layer through a low temperature annealing process.

8. The AlGaN / GaN heterojunction HEMT device compatible with Si-CMOS process according to claim 1, characterized in that: Oxidation treatment refers to the use of oxygen ions to completely or partially oxidize the AlGaN heavily doped layer under the gate electrode through ICP or RIE, and the generated oxide or oxynitride is Al2O3, Ga2O3, AlSiON, AlON or any combination thereof; low-temperature annealing refers to placing the sample in a pure nitrogen atmosphere and annealing it at a temperature not higher than 600 degrees Celsius for 5 to 10 minutes.

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