Die on power grid trace bump formation

Abstract

A die-on-chip power grid device is disclosed, comprising solder traces that enhance the current of power traces between adjacent power bumps. Solder traces are also coated on power drain traces between power drain bumps.

Description

Technical Field

[0001] This disclosure relates to mounting substrate technology that allows for high current in the face of miniaturization. Background Technology

[0002] Miniaturization of the package allows for smaller dimensions to meet higher performance requirements. While power and ground wiring also require miniaturization, they still need to carry enough current to satisfy higher performance demands. Attached Figure Description

[0003] The disclosed embodiments are illustrated in the accompanying drawings by way of example and not limitation, wherein similar reference numerals may refer to similar elements, as shown in the drawings:

[0004] Figure 1 This is a top plan view of the substrate of the power mesh-on-die device according to an embodiment;

[0005] Figure 1A This is a top plan view of a portion of the on-die power grid device during processing, according to an embodiment;

[0006] Figure 2A , 3A And 4A is Figure 1A Various cross-sectional elevation views of the power grid device on the die shown;

[0007] Figure 1B This is a further processing according to the embodiment. Figure 1A The top view of the power grid device on the die shown;

[0008] Figure 2B , 3B And 4B is Figure 1B Various cross-sectional elevation views of the power grid device on the die shown;

[0009] Figure 1C This is a further processing according to the embodiment. Figure 1B The top view of the power grid device on the die shown;

[0010] Figure 2C , 3C And 4C is Figure 1C Various cross-sectional elevation views of the power grid device on the die shown;

[0011] Figure 1D This is a further processing according to the embodiment. Figure 1C The top view of the power grid device on the die shown;

[0012] Figure 2D ,3D And 4D is Figure 1D Various cross-sectional elevation views of the power grid device on the die are shown. Furthermore, Figure 4D This is a further processing according to the embodiment. Figure 1D A cross-sectional elevation view of the power grid device on the die shown;

[0013] Figure 5 According to the embodiments, from Figure 1C The section details within section line 5 are captured;

[0014] Figure 6 According to the embodiments, from Figure 1C The section details within section line 5 are captured;

[0015] Figure 7 According to the embodiments, from Figure 1C The section details within section line 5 are captured;

[0016] Figure 8 The illustrations, according to embodiments, depict a process flow diagram of assembling a power grid device on a die; and

[0017] Figure 9 Examples of applications of higher-level devices are included to illustrate the disclosed embodiments. Detailed Implementation

[0018] The disclosed embodiments include power grid bumping on the die, wherein solder traces enhance the capacitance of the power grid and ground grid through channeled solder between the power bumps or ground bumps.

[0019] Figure 1 This is a top plan view 100 of a substrate 10 supporting a power grid on-die device 1A according to an embodiment. The substrate 10 supports a ball array comprising an embodiment of the power grid on-die device. Figure 1A , 1B More detailed embodiments are given in 1C and 1D and the associated accompanying drawings.

[0020] Semiconductor package embodiments include wiring for power distribution and signal distribution. In high-power states, reducing resistance within the power distribution network and improving the associated current-resistance (IR) drop manages switching speed and noise levels to prevent functional failures. The disclosed embodiments achieve lower resistance and thus higher electrical performance by increasing the amount of wiring within the power and ground grid wiring.

[0021] When solder connections are required in semiconductor packaging, openings are made in the solder mask above the trace routing to locally create solder-enhanced traces between adjacent power solder bumps. Similarly, when a solder mask is opened above a ground trace, solder-enhanced ground traces are created between adjacent solder bumps.

[0022] The process is accomplished by applying solder after opening channels in a solder mask (e.g., between two adjacent power bumps). In one embodiment, solder application within the solder mask channels between adjacent bumps is performed using a ball coating technique. In another embodiment, solder application within the solder mask channels between adjacent bumps is performed during a solder bump formation technique. In yet another embodiment, solder application within the solder mask channels between adjacent bumps is performed using bump reflow, where the wetting of the solder bumps allows the solder to flow through a wicking action, thereby forming solder traces between adjacent bumps along traces exposed within the solder mask channels. In another embodiment, conditions are set such that the wicking of the solder is blocked by the solder mask but enhanced by the existing traces.

[0023] Figure 1A This is a top plan view of a portion of the on-die power grid (power MOD) device 1001 during processing, according to an embodiment.

[0024] Although the term "power grid on die" is used, it should be understood that the substrate on which the power grid can be built can be any substrate other than a semiconductor die. In an embodiment, power MOD device 1001 includes a portion of a mounting substrate 10, such as a motherboard, with traces and bonding pads located on the upper surface 11 of the substrate. In an embodiment, power MOD device 1001 includes a portion of the packaging substrate 10 for a processor die. In an embodiment, power MOD device 1001 includes a portion of a semiconductor device substrate located at the top metallization (e.g., for solder-on-die devices). In any case and unless explicitly indicated otherwise, the power MOD can be any of the disclosed substrates.

[0025] According to an embodiment, a first voltage-source (first VSS) trace 102 is accompanied by a subsequent VSS trace 106. Other VSS traces may be used in a given power supply MOD device. A first VSS bonding pad 104 is one of a plurality of VSS bonding pads that are all linearly coupled (along the X direction) to the first VSS trace 102. A subsequent VSS bonding pad 108 is one of a plurality of VSS bonding pads that are all linearly coupled (along the X direction) to the subsequent VSS trace 106. A first voltage-drain (first VDD) trace 110 is also located on the substrate 10. A first VDD bonding pad 112 is one of a plurality of bonding pads that are all linearly coupled (along the X direction) to the first VDD trace 110.

[0026] According to an embodiment, a first signal trace (signal 1 trace) is located between a first VSS trace 102 and a first VDD trace 110. A signal 1 bonding pad 116 is one of a plurality of signal 1 bonding pads that are all linearly (along the X direction) coupled to signal 1 trace 114. According to an embodiment, a second signal trace (signal 2 trace) 118 is located between a subsequent VSS trace 106 and the first VDD trace 110. A signal 2 bonding pad 120 is one of a plurality of signal 2 bonding pads that are all linearly (along the X direction) coupled to signal 2 trace 118.

[0027] In the embodiments, it can be observed that the bonding pads are arranged in a body-centered hexagonal (BCH) configuration, resulting in a total of seven bonding pads, where the hexagons of six bonding pads are centered around the seventh bonding pad. Other bonding pad arrangements can be used, such as simple quadrilateral-filled bonding pads. Other bonding pad arrangements can be used, such as body-centered quadrilateral-filled bonding pads with five bonding pads. Other bonding pad arrangements can also be used, such as simple quadrilateral-filled bonding pads. Other bonding pad arrangements can also be used, such as body-centered quadrilateral-filled bonding pads with five bonding pads.

[0028] Figure 2A According to the embodiments Figure 1A The image shows a cross-sectional elevation view of the power supply MOD device 1001. The cross-section is along section line 2-2 from... Figure 1A The image shows the substrate 10 supporting the subsequent VSS bonding pads 108 on the upper surface 11 along the Y direction from left to right. Figure 1A The signal trace 118 and the first VDD bonding pad 112 shown are shown. Figure 1A The signal 1 trace 114 and the first VSS bonding pad 104 are shown.

[0029] Figure 3AAccording to the embodiments Figure 1A The image shows a cross-sectional elevation view of the power supply MOD device 1001. The cross-section is along section line 3-3 from... Figure 1A The image shows the substrate 10 bearing loads on the upper surface 11 along the Y direction in a left-to-right order. Figure 1A The subsequent VSS trace 106 and signal 2 bonding pad 120 are shown. Figure 1A The first VDD trace 110, signal 1 bonding pad 116, and shown are shown. Figure 1A The first VSS trace 102 is shown. In an embodiment, the upper surface 11 is opposite to the lower surface 19. In an embodiment, the lower surface 19 provides sufficient electrical insulation to act as the housing 19 of the computing device. It is understood that the housing 19 is positioned away from the upper surface 11.

[0030] Figure 4A According to the embodiments Figure 1A The image shows a cross-sectional elevation view of the power supply MOD device 1001. The cross-section is along section line 4-4 from... Figure 1A The image shows the substrate 10 carrying, from left to right, the following regions in the X direction: a coverage area 104' (left), a coverage area 102', a coverage area 102', a coverage area 104' (center), a coverage area 102', a coverage area 102', and a coverage area 104' (right), covering the cross-section of the first VSS bonding pad 104.

[0031] Figure 1B This is a further processing according to the embodiment. Figure 1A The diagram shows a top plan view 1002 of the power supply MOD device 1001. According to an embodiment, the power supply MOD device 1002 has been covered with a film such as a solder mask 12, thereby preparing it for opening the solder mask 12 to receive solder. The solder mask 12 has a solder mask upper surface 13.

[0032] The first VSS trace 102 and subsequent VSS trace 106 are both shown in dashed lines because, according to the embodiment, each of them is covered by the solder mask 12. Similarly, the first VSS bonding pad 104 and subsequent VSS bonding pad 108 are both shown in dashed lines because each of them is covered by the solder mask 12. Similarly, the first VDD trace 110 is also shown in dashed lines because it is covered by the solder mask 12. Similarly, the first VDD bonding pad 112 is shown in dashed lines because it is covered by the solder mask 12. Similarly, the signal 1 trace 114 is shown in dashed lines because it is covered by the solder mask 12. The signal 1 bonding pad 116 is shown in dashed lines because it is covered by the solder mask 12. The signal 2 trace 118 is shown in dashed lines because it is covered by the solder mask 12. And, the signal 2 bonding pad 120 is shown in dashed lines because it is covered by the solder mask 12.

[0033] Figure 2B According to the embodiments Figure 1B The image shows a cross-sectional elevation view of the power supply MOD device 1002. The cross-section is along section line 2-2 from... Figure 1B The image shows a cutaway view. The substrate 10 is seen beneath the upper surface 13 of the solder mask. The substrate 10 is seen carrying, from left to right along the Y direction, subsequent VSS bonding pads 108, signal 2 traces 118, first VDD bonding pads 112, signal 1 traces 114, and first VSS bonding pads 104. The solder mask 12 is seen superimposed on the substrate 10 and the various traces and bonding pads. In this embodiment, the solder mask 12 is spin-coated, cured, and planarized to obtain the upper surface 13 of the solder mask.

[0034] Figure 3B According to the embodiments Figure 1B The diagram shows a cross-sectional elevation view of the voltage MOD device 102. The cross-section is along section line 3-3 from... Figure 1B The image shows the substrate 10 carrying, from left to right, the subsequent VSS trace 106, signal 2 bonding pad 120, first VDD trace 110, signal 1 bonding pad 116, and first VSS trace 102 along the Y direction. The solder mask 12 is seen superimposed on the substrate 10 and the various traces and bonding pads.

[0035] Figure 4B According to the embodiments Figure 1B The diagram shows a cross-sectional elevation view of the voltage MOD device 102. The cross-section is along section line 4-4 from... Figure 1BThe image shows the substrate 10 along the X direction, from left to right, carrying a coverage area 104' (left) covering the cross-section of the first VSS bonding pad 104, a coverage area 102' covering the cross-section of the first VSS trace 102, a coverage area 104' (center) covering the cross-section of the first VSS bonding pad 104, a coverage area 102' covering the cross-section of the first VSS trace 102, and a coverage area 104' (right) covering the cross-section of the first VSS bonding pad 104. The solder mask 12 is seen superimposed on the substrate 10 and the various traces and bonding pads.

[0036] Figure 1C This is a further processing according to the embodiment. Figure 1B The top plan view 1003 of the power supply MOD device 1002 is shown. According to an embodiment, the solder mask 12 (…) has been made accessible by opening an opening in the upper surface 13 of the solder mask. Figure 1B (As shown) Patterning is used to form a patterned mask 14 for further processing of the power supply MOD device 1003.

[0037] According to an embodiment, the first VSS trace 102 is shown as a channel cross-section through the patterned mask 14. Similarly, according to an embodiment, the subsequent VSS trace 106 is also shown as a channel cross-section through the patterned mask 14. The first VSS bonding pad 104 and the subsequent VSS bonding pad 108 are shown as openings through the patterned mask 14. The first VDD trace 110 is shown as a channel cross-section through the patterned mask 14. Similarly, the first VDD bonding pad 112 is shown as an opening through the patterned mask 14. The signal 1 trace 114 is shown in dashed lines because it is covered by the patterned mask 14. The signal 1 bonding pad 116 is shown extending beyond the opening of the patterned mask 14. The signal 2 trace 118 is shown in dashed lines because it is covered by the patterned mask 14. And the signal 2 bonding pad 120 is shown as an opening through the patterned mask 14.

[0038] Figure 2C According to the embodiments Figure 1C The image shows a cross-sectional elevation view of the power supply MOD device 1003. The cross-section is along section line 2-2 from... Figure 1C The image shows the substrate 10 carrying, from left to right along the Y direction, the following pads: VSS bonding pad 108 (exposed through patterned mask 14), signal 2 trace (covered by patterned mask 14), first VDD bonding pad 112 (exposed through patterned mask 14), signal 1 trace 114 (covered by patterned mask 14), and first VSS bonding pad 104 (exposed through patterned mask 14).

[0039] Figure 3C According to the embodiments Figure 1CThe image shows a cross-sectional elevation view of the power supply MOD device 1003. The cross-section is along section line 3-3 from... Figure 1C The image shows a cross-section. The substrate 10, along the Y direction, carries the subsequent VSS trace 106, signal 2 bonding pad 120, first VDD trace 110, signal 1 bonding pad 116, and first VSS trace 102 in a left-to-right order. The patterned mask 14 is superimposed on the substrate 10 and the various traces and bonding pads. It can be seen that the subsequent VSS trace 106 is disposed within a solder mask channel formed in the patterned mask 14. Similarly, it can be seen that the first VDD trace 110 in this cross-section is disposed within a solder mask channel formed in the patterned mask 14. And similarly, it can be seen that the first VSS trace 102 in this cross-section is disposed within a solder mask channel formed in the patterned mask 14.

[0040] Figure 4C According to the embodiments Figure 1C The image shows a cross-sectional elevation view of the power supply MOD device 1003. The cross-section is along section line 4-4 from... Figure 1C The image shows the substrate 10 along the X direction, from left to right, carrying the following areas: a coverage area 104' (left), covering the first VSS bonding pad 104; a coverage area 102', covering the first VSS trace 102; a coverage area 104' (center), covering the first VSS bonding pad 104; a coverage area 102', covering the first VSS trace 102; and a coverage area 104', covering the first VSS bonding pad 104 (right). Due to the placement of section line 4-4, in... Figure 4C The patterned mask 14 is not visible. Therefore, each of the trace coverage sections 102' is located within the solder mask channel formed by the patterned mask 14.

[0041] Figure 1D This is a further processing according to the embodiment. Figure 1C The top view 1004 of the power supply MOD device 1003 is shown. According to the embodiment, the power supply MOD device 1004 has been further processed by positioning the solder bump precursor and solder trace core region through the opening and solder mask channel in the patterned mask 14.

[0042] According to an embodiment, the first VSS solder trace core-holding region 152 is shown as passing through a solder mask channel in the patterned mask 14. The first VSS solder trace core-holding region 152 occupies the exposed portion of the first VSS trace 102, see Figure 1A Similarly, according to an embodiment, the subsequent VSS solder trace wicking region 156 also occupies the exposed portion of the subsequent VSS trace 106 shown as passing through the solder mask channel in the patterned mask 14.

[0043] According to an embodiment, the first VSS solder bump precursor 154 is configured to pass through an opening in the patterned mask 14 and lie on the first VSS bonding pad 104 (which is covered). Furthermore, according to an embodiment, the subsequent VSS solder bump precursor 158 is configured to pass through an opening in the patterned mask 14 and lie on the subsequent VSS bonding pad 108 (which is covered). The first VDD solder trace core-sucking region 160 occupies the exposed portion of the first VDD trace 110 seen in the solder mask channel within the patterned mask 14, see... Figure 1A Similarly, the first VDD solder bump precursor 162 is disposed above and on the first VDD bonding pad 112 (masked) through the opening in the patterned mask 14.

[0044] Signal 1 trace 114 is shown in dashed lines because it is covered by patterned mask 14. Signal 1 solder bump precursor 166 is disposed in an opening in patterned mask 14, and is positioned above and on signal 1 bonding pad 116 (which is covered). Signal 2 trace 118 is shown in dashed lines because it is covered by patterned mask 14. Signal 2 solder bump precursor 170 is disposed in a solder mask channel in patterned mask 14, and is positioned above and on signal 2 bonding pad 120 (which is covered).

[0045] Figure 2D According to the embodiments Figure 1D The image shows a cross-sectional elevation view of the voltage MOD device 1004. The cross-section is along section line 2-2 from... Figure 1D The image shows a substrate 10 carrying, from left to right, a subsequent VSS bonding pad 108 overlaid with a subsequent VSS solder bump precursor 158. Next, signal 2 trace 118 is covered by patterned mask 14. Next, a first VDD bonding pad 112 is overlaid with a first VDD solder bump precursor 162. Next, signal 1 trace 114 is covered by patterned mask 14. Finally, a first VSS bonding pad 104 is overlaid with a first VSS bonding pad precursor 154. It can be seen that, according to the embodiment, each of the solder bump precursors 158, 162, and 154 extends above the upper surface 13 of patterned mask 14.

[0046] Figure 3D According to the embodiments Figure 1D The image shows a cross-sectional elevation view of the power supply MOD device 1004. The cross-section is along section line 3-3 from... Figure 1DThe image shows the substrate 10 carrying subsequent VSS traces 106 in a left-to-right order along the Y direction, exposing the subsequent VSS solder trace core-holding region 156. It can be seen that the subsequent VSS trace 106 is within the solder mask channel and a portion of the subsequent VSS solder trace core-holding region 156 within the solder mask channel. Next, the signal 2 bonding pad 120 is overlaid with a signal 2 solder bump precursor 170, and the solder bump precursor 170 extends above the upper surface 13 of the patterned mask. Next, the first VDD trace 110 exposes the first VDD solder trace core-holding region 160. Next, the signal 1 bonding pad 116 is overlaid with a signal 1 solder bump precursor 166. Finally, the first VSS trace 102 exposes the first VSS solder trace core-holding region 152. The patterned mask 14 is seen superimposed on the substrate 10 and various traces and bonding pads. As can be seen, according to the embodiment, each of the solder bump precursors 166 and 170 extends above the upper surface 13 of the patterned mask 14.

[0047] The process is accomplished, for example, by applying solder after creating a channel in a solder mask between two adjacent power bumps. In one embodiment, the application of the solder precursor within the solder mask channel between adjacent bumps is performed using a ball coating technique. In another embodiment, the application of solder within the solder mask channel between adjacent bumps is performed during the solder bump formation process.

[0048] In this embodiment, solder coating within the solder mask channel between adjacent bumps is accomplished via bump reflow. During bump reflow, the wetting of the solder bumps allows solder to flow, and solder traces are formed between adjacent bumps along the traces exposed in the solder mask channel. Furthermore, in Figure 4D Further examples and discussions of reflow solder bridging within solder mask channels are shown in the figure.

[0049] Figure 4D This is according to the embodiments and after further processing. Figure 1D The diagram shows a cross-sectional elevation view of the power supply MOD device 1004. The cross-section is along section line 4-4 and extends from [the point of view] after further processing. Figure 1DThe image shows a cutaway view. The substrate 10, along the X direction, carries a first VSS bonding pad cover area 104' covered with a first VSS solder bump 174 (left in the image, and reflowing from the first VSS solder bump precursor 154) in a left-to-right sequence. Next, a first VSS trace cover area 102' is covered with a reflowed first VSS solder trace 172 (second from the left in the image, and reflowing from the first VSS solder bump precursor 154). Next, the first VSS bonding pad cover area 104' is covered with a first VSS solder bump 174 (center in the image, and reflowing from the first VSS solder bump precursor 154). Next, the first VSS trace cover area 102' is covered with a reflowed first VSS solder trace 172 (second from the right in the image, and reflowing from the first VSS solder bump precursor 154). Finally, the first VSS bonding pad coverage area 104' is overlaid with the first VSS solder bump 174 (right figure, and reflow from the first VSS solder bump precursor 154).

[0050] As can be understood from the diagram, an opening is made above the trace routing to provide a channel for the solder mask trace, and a solder-containing trace (e.g., trace 102 and the first VSS solder trace 172 for reflow) is applied. The solder mask lithography is modified to include selected solder mask channels at selected power and ground locations where lower resistance is useful.

[0051] As can be understood from the diagram, an integrated solder structure exists within the solder channel of the first VSS solder trace 172 and between the two adjacent first VSS solder bumps 174. Therefore, due to this integrated solder structure and the ability of current to flow into a given trace between adjacent solder bumps, the resistance between the bumps decreases.

[0052] In one embodiment, solder can be deposited by placing a wetted solder ball with sufficient volume and reflow rate on the exposed trace in the solder mask channel, which is sufficient to achieve this. Figure 4D The reinforced trace structure is roughly shown. In this embodiment, solder bumps and reinforced solder traces are accumulated starting from a seed layer, followed by electroplating via a plating resist that promotes the formation of the reinforced solder traces, and then removal of the plating resist.

[0053] In this embodiment, a tin-containing coating of the exposed trace is deposited onto the solder trace wicking region via a separate process. The tin-containing coating resists erosion because the trace's negative charge is lower than that of the solder-enhanced trace. Due to the reduced overall resistance, the high-current operation of the power MOD device protects the original trace while also accommodating more current in the solder trace.

[0054] To reduce overall resistance, linear coupling (along the entire length between the bumps) is achieved between the original trace and the solder-enhanced trace. It can now be understood that "linear contact" or "linear overlap" refers to material contact between the bumps defining the length of a given trace. For example, at any given coverage area 102' of the first VSS trace 102, the return first VSS solder trace 172 makes linear contact along the entire length of the first VSS trace 102. In any case, a reduction in overall resistance is achieved in the useful power and ground portions formed by the grid bumps on the die without increasing the XY wiring size.

[0055] refer to Figure 1D and 2D It should be pointed out that the patterned mask 14 in Figure 1D The X direction and its relationship with Figure 2D The patterned mask 14 is in linear contact with the signal trace 114 in a direction orthogonal to the plane of the image. Similarly, it should be noted that the patterned mask 14 is in... Figure 1D The X direction and its relationship with Figure 2D The plane of the figure is in orthogonal direction and is in linear contact with the trace 118 of signal 2.

[0056] In an embodiment, the nominal volume of a given VSS trace is compared to the nominal volume of a VSS solder trace overlaid on the initial VSS trace. In an embodiment, the nominal volume of the first VSS solder trace 172 is smaller than the nominal volume of the initial first VSS trace coverage area 102'. In an embodiment, the nominal volume of the first VSS solder trace 172 is approximately equal to (within 1%) the nominal volume of the initial first VSS trace coverage area 102'. In an embodiment, the nominal volume of the first VSS solder trace 172 is between approximately 1% and approximately twice the nominal volume of the initial first VSS trace coverage area 102'. In an embodiment, the nominal volume of the first VSS solder trace 172 is approximately five times the nominal volume of the initial first VSS trace coverage area 102'.

[0057] The nominal volume ratio can be controlled by the height of the patterned mask 14 above the thickness in the Z direction of a given trace. For example, with a nominal volume of approximately 5:1 that favors solder traces and with uniform initial trace heights, the patterned mask 14 will have a comparable Z-direction height of approximately 6:1, measured from the upper surface 11 of the substrate.

[0058] In this embodiment, the nominal volume ratio is measured where the solder trace is at its minimum cross-sectional volume. For example... Figure 4D As shown, a neck-like narrowing is seen in the first VSS solder trace 172, roughly where the baseline 172 touches the first VSS solder trace 172.

[0059] Figure 5 According to the embodiments, from Figure 1C The cut-off section detail 500 is within section line 5. In an embodiment, one technique for implementing solder traces is to reflow solder bumps during solder bump reflow by wicking them back onto the trace where solder is stacked. The wicking can continue as some of the solder bump precursors are drawn onto the exposed trace until bridging is completed between, for example, two VSS solder bumps, thereby establishing the first reflowed VSS solder trace 172. The accompanying drawings show the patterned mask upper surface 13 and the first VSS bonding pad 104, as well as the first VSS trace 102, according to an embodiment.

[0060] In one embodiment, the wicking of exposed solder along the trace is controlled by narrowing the first VSS trace 102 to limit wicking action via a first centered trace blockage portion 572. In another embodiment, a second centered trace blockage portion 573 is located opposite the first centered trace blockage portion 572.

[0061] Figure 6 According to the embodiments, from Figure 1C The cut-off section detail 600 within section line 5. The accompanying drawing shows the patterned mask upper surface 13 and the first VSS bonding pad 104 and the first VSS trace 102 according to the embodiment.

[0062] In this embodiment, the wicking of exposed solder along the trace is controlled by narrowing the first VSS trace 102 to limit wicking action via a first unilateral trace blockage 574. In this embodiment, a second unilateral trace blockage 575 is located opposite the first unilateral trace blockage 574. In this embodiment, a given unilateral trace blockage is closer to the bonding pads than to the central region between two bonding pads. For example, the first unilateral trace blockage 574 is closer to the first VSS bonding pad 104 in the left figure than to the first VSS bonding pad 104 in the right figure.

[0063] Figure 7 According to the embodiments, from Figure 1C The cut-off section detail 700 within section line 5. The view shown reveals the patterned mask upper surface 13 and the first VSS bonding pad 104 and the first VSS trace 102 according to the embodiment.

[0064] In an embodiment, solder wicking along the trace is controlled at least by asymmetric deployment of at least one trace occlusion portion. As shown, in addition to trace occlusion portions 572, 573, 574, and 575, trace occlusion portion 576 establishes asymmetry of trace occlusion portions on one side of the first VSS trace 102. In an embodiment, the number of trace occlusion portions is only one. In an embodiment, the number of trace occlusion portions is two, but they can be deployed on the same side of a given trace. In an embodiment, the number of trace occlusion portions is even, but more trace occlusion portions can be deployed on a given first side of the trace than on a given second side. In an embodiment, the number of trace occlusion portions is odd, but more trace occlusion portions can be deployed on a given first side of the trace than on a given second side.

[0065] Figure 8 This is a schematic diagram 800 illustrating the process flow of assembling a power grid device on a die, according to an embodiment.

[0066] In 810, the process includes patterning power traces, ground traces, and signal traces, as well as bonding pads, on the upper surface of the substrate.

[0067] In 812, the process includes forming a trace obstruction in a trace.

[0068] At 820, the process includes forming a patterned mask to create openings in the bonding pads and opening a channel between two power bonding pads to form exposed traces.

[0069] At 830, the process includes depositing solder on the bonding pads and drawing some solder cores into the channels and exposed traces to form a power grid device on the die.

[0070] At 840, the process includes coupling an on-die power grid device to a semiconductor device.

[0071] At 850, the process includes assembling an on-die power grid device into a computing system.

[0072] Figure 9Examples of higher-level device applications included to illustrate the disclosed embodiments are shown. In embodiments, computing system 900 includes, but is not limited to, desktop computers. In embodiments, system 900 includes, but is not limited to, laptop computers. In embodiments, system 900 includes, but is not limited to, netbooks. In embodiments, system 900 includes, but is not limited to, tablet computers. In embodiments, system 900 includes, but is not limited to, notebook computers. In embodiments, system 900 includes, but is not limited to, personal digital assistants (PDAs). In embodiments, system 900 includes, but is not limited to, servers. In embodiments, system 900 includes, but is not limited to, workstations. In embodiments, system 900 includes, but is not limited to, cellular phones. In embodiments, computing system 900 includes, but is not limited to, mobile computing devices. In embodiments, system 900 includes, but is not limited to, smartphones. In embodiments, system 900 includes, but is not limited to, internet applications. Other types of computing devices may also be configured as microelectronic devices including embodiments of power grid-on-die devices.

[0073] In an embodiment, processor 910 has one or more processing cores 912 and 912N, where 912N represents the Nth processor core within processor 910, and N is a positive integer. In an embodiment, the electronic device system 900 using a power grid-on-die embodiment includes multiple processors, including 910 and 905, where processor 905 has logic similar to or equivalent to that of processor 910. In an embodiment, processing core 912 includes, but is not limited to, prefetch logic for fetching instructions, decoding logic for decoding instructions, and execution logic for executing instructions. In an embodiment, processor 910 has a cache memory 916 that caches at least one of the instructions and data for the power grid-on-die device in system 900. The cache memory 916 can be organized into a hierarchical structure including one or more levels of cache memory.

[0074] In one embodiment, the processor 910 includes a memory controller 914, which can be configured to perform functions enabling the processor 910 to access and communicate with at least one of the memory 930, including volatile memory 932 and non-volatile memory 934. In another embodiment, the processor 910 is coupled to the memory 930 and the chipset 920. The processor 910 may also be coupled to a wireless antenna 978 to communicate with any device configured to transmit and / or receive wireless signals. In another embodiment, the wireless antenna interface 978 operates according to, but is not limited to, the IEEE 802.11 standard and its related families, HomePlug AV (HPAV), Ultra Wideband (UWB), Bluetooth, WiMAX, or any form of wireless communication protocol.

[0075] In this embodiment, the volatile memory 932 includes, but is not limited to, synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS dynamic random access memory (RDRAM), and / or any other type of random access memory device. The non-volatile memory 934 includes, but is not limited to, flash memory, phase-change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

[0076] Memory 930 stores information and instructions to be executed by processor 910. In embodiments, memory 930 may also store temporary variables or other intermediate information during processor 910 instruction execution. In the illustrated embodiment, chipset 920 is connected to processor 910 via point-to-point (PtP or PP) interfaces 917 and 922. Any of these PtP embodiments can be implemented using the on-die power grid embodiments described in this disclosure. Chipset 920 enables processor 910 to connect to other components in the on-die power grid device of system 900. In embodiments, interfaces 917 and 922 operate according to the PtP communication protocol, for example, according to... It works using Fast Path Interconnect (QPI) and similar methods. In other embodiments, different interconnects may be used.

[0077] In this embodiment, the chipset 920 can be used to communicate with the processor 910, 905N, the display device 940, and other devices 972, 976, 974, 960, 962, 964, 966, 977, etc. The chipset 920 can also be coupled to a wireless antenna 978 to communicate with any device configured to transmit and / or receive wireless signals.

[0078] Chipset 920 is connected to display device 940 via interface 926. Display 940 may be, for example, a liquid crystal display (LCD), a plasma display, a cathode ray tube (CRT) display, or any other form of visual display device. In an embodiment, processor 910 and chipset 920 are integrated into a single on-die power grid device in the system. Furthermore, chipset 920 is connected to one or more buses 950 and 955 that interconnect various components 974, 960, 962, 964, and 966. Buses 950 and 955 may be interconnected via bus bridge 972, for example, via at least one on-die power grid embodiment. In an embodiment, chipset 920 is coupled to non-volatile memory 960, mass storage device 962, keyboard / mouse 964, network interface 966, and consumer electronics device 977 via at least one of interfaces 924 and 974, smart TV 976, etc.

[0079] In one embodiment, the mass storage device 962 includes, but is not limited to, solid-state drives, hard disk drives, Universal Serial Bus flash memory drives, or any other form of computer data storage medium. In one embodiment, the network interface 966 may be implemented via any type of known network interface standard, including but not limited to Ethernet interfaces, Universal Serial Bus (USB) interfaces, Peripheral Component Interconnect (PCI) Fast interfaces, wireless interfaces, and / or any other suitable type of interface. In one embodiment, the wireless interface operates according to, but is not limited to, the IEEE 802.11 standard and its related series, HomePlug AV (HPAV), Ultra Wideband (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0080] although Figure 9 The modules shown are depicted as separate modules within the on-die power grid device in computing system 900, but some of the functions performed by these blocks may be integrated into a single semiconductor circuit, or may be implemented using two or more separate integrated circuits. For example, although cache memory 916 is depicted as a separate block within processor 910, cache memory 916 (or selected aspects of 916) may be incorporated into processor core 912.

[0081] Where useful, the computing system 900 may have a casing, for example, Figure 3A The housing 19 is shown. In this embodiment, the housing is also an electrically insulating structure that provides physical protection for the power grid devices on the die.

[0082] To illustrate the embodiments and methods of the on-die power grid device disclosed herein, a non-limiting list of examples is provided:

[0083] Example 1 is a die-on power grid device comprising: a substrate including an upper surface; a VSS trace disposed on the upper surface and between two voltage-source (VSS) bonding pads; and a VSS solder trace disposed between the two VSS bonding pads and linearly superimposed on the VSS trace.

[0084] In Example 2, the subject matter according to Example 1 optionally includes a patterned mask disposed on the upper surface of a substrate, wherein VSS solder traces are disposed in channels in the patterned mask.

[0085] In Example 3, the subject matter according to Example 2 may optionally include, wherein each of the two VSS bonding pads supports a VSS solder bump, and wherein the VSS solder trace and the two VSS solder bumps are an integral solder structure.

[0086] In Example 4, the subject matter described according to any one or more of Examples 2-3 may optionally include the obstruction in the VSS trace.

[0087] In Example 5, the subject matter according to any one or more of Examples 1-4 optionally includes, wherein the VSS trace is a first VSS trace, the solder trace is a first VSS solder trace, and further includes: a subsequent VSS trace disposed on the upper surface and between two VSS bonding pads; and a subsequent VSS solder trace disposed on the subsequent VSS trace and linearly superimposed on the first VSS trace.

[0088] In Example 6, the subject matter according to Example 5 optionally includes a patterned mask disposed on the upper surface of a substrate, wherein the VSS solder trace is a first VSS solder trace disposed in a channel in the patterned mask; and wherein subsequent VSS solder traces are disposed in subsequent channels in the patterned mask.

[0089] In Example 7, the subject matter according to any one or more of Examples 1-6 optionally includes, wherein the VSS trace is a first VSS trace, the solder trace is a first VSS solder trace, and further includes: a VDD trace disposed between two voltage-drain-drain (VDD) bonding pads; a VDD solder trace disposed on the VDD trace and linearly superimposed on the VDD trace; a subsequent VSS trace disposed on the upper surface and between two VSS bonding pads, wherein the first VSS trace and the subsequent VSS trace are separated by the VDD trace; and a subsequent VSS solder trace disposed on the subsequent VSS trace and linearly superimposed on the subsequent VSS trace.

[0090] In Example 8, the subject matter according to Example 7 optionally includes a patterned mask disposed on the upper surface of a substrate, wherein the VSS solder trace is a first VSS solder trace disposed in a first channel of the patterned mask; wherein subsequent VSS solder traces are disposed in subsequent channels of the patterned mask; and wherein the VDD solder traces are disposed in channels of the patterned mask.

[0091] In Example 9, the subject matter according to any one or more of Examples 1-8 optionally includes, wherein the VSS trace is a first VSS trace, the solder trace is a first VSS solder trace, and further includes: a VDD trace disposed between two voltage-drain-drain (VDD) bonding pads; a VDD solder trace disposed on the VDD trace and linearly superimposed on the VDD trace; a subsequent VSS trace disposed on the upper surface and between the two VSS bonding pads, wherein the first VSS trace and the subsequent VSS trace are separated by the VDD trace; and a subsequent VSS solder trace disposed on the subsequent VSS trace and linearly superimposed on the subsequent VSS trace; a first signal (signal 1) trace disposed between the first VSS trace and the VDD trace; and a second signal (signal 2) trace disposed between the VDD trace and the subsequent VSS trace.

[0092] In Example 10, the subject matter according to Example 9 optionally includes a patterned mask disposed on the upper surface of the substrate, wherein the patterned mask is in linear contact with each of the signal 1 trace and the signal 2 trace.

[0093] In Example 11, the subject matter described in any one or more of Examples 1-10 may optionally include, wherein the substrate is a semiconductor die.

[0094] In Example 12, the subject matter described in any one or more of Examples 1-11 may optionally include, wherein the substrate is a semiconductor die package.

[0095] In Example 13, the subject matter described in any one or more of Examples 1-12 may optionally include, wherein the substrate is a printed wiring board.

[0096] Example 14 is a method of assembling a power grid device on a die, comprising: patterning power traces having at least two bonding pads on a substrate; patterning ground traces having at least two bonding pads on the substrate; patterning signal traces having bonding pads on the substrate; patterning a mask to expose the bonding pads; patterning the mask to open channels to expose the power traces; and depositing solder traces in the channels and on the exposed power traces.

[0097] In Example 15, the subject matter described in Example 14 may optionally include the deposition of solder traces by drawing solder from adjacent solder bumps disposed on the at least two bonding pads onto the power traces.

[0098] In Example 16, the subject matter described in any one or more of Examples 14-15 may optionally include: depositing a solder bump precursor on a plurality of bonding pads; and reflowing the solder traces in the channel and the solder bump precursor to form an integral structure for the two solder bumps and solder traces.

[0099] In Example 17, the subject matter described in any one or more of 14-16 may optionally include forming a trace blockage on the power trace.

[0100] In Example 18, the subject matter according to any one or more of Examples 14-17 optionally includes: patterning a mask to open a channel thereby exposing the ground trace; depositing solder traces in the channel and on the exposed ground traces; and wherein patterning the mask leaves the signal traces still covered by the mask.

[0101] In Example 19, the subject matter according to any one or more of Examples 14-18 optionally includes: depositing solder bump precursors on a plurality of bonding pads; reflowing solder traces and solder bump precursors in a channel to form an integrated structure for the two solder bumps and solder traces; and reflowing solder traces and two solder bump precursors in a channel exposing the ground trace to form an integrated structure for the two solder bumps and ground solder traces.

[0102] In Example 20, the subject matter according to any one or more of Examples 14-19 optionally includes, wherein the power trace is a first power trace; further includes: patterning a subsequent power trace between two bonding pads; patterning a mask to open a channel to expose the subsequent power trace; and depositing a subsequent solder trace in the channel and on the exposed subsequent power trace.

[0103] In Example 21, the subject matter according to any one or more of Examples 14-20 optionally includes traces, further comprising: patterning the signal 2 traces on a substrate; and wherein the patterning of the mask leaves the signal 2 traces still covered by the mask.

[0104] Example 22 is a computing system including a power grid device on a die, comprising: a substrate including an upper surface; a first VSS trace disposed on the upper surface and between two first voltage-source (VSS) bonding pads; a first VSS solder trace disposed between the two first VSS bonding pads and linearly superimposed on the first VSS trace; a subsequent VSS trace disposed on the upper surface and between two subsequent VSS bonding pads; a subsequent VSS solder trace disposed between the two subsequent VSS bonding pads and linearly superimposed on the subsequent VSS trace; a VDD trace disposed between two voltage-drain (VDD) bonding pads; a VDD solder trace disposed on the VDD trace and linearly superimposed on the VDD trace; a patterned mask disposed on the upper surface of the substrate, wherein each VSS solder trace is disposed in a channel in the patterned mask; and a housing disposed away from the upper surface.

[0105] In Example 23, the subject matter described in Example 22 may optionally include, wherein each of the two VSS bonding pads supports a VSS solder bump, and wherein the first VSS solder trace and the two VSS solder bumps are an integral solder structure.

[0106] The detailed description above includes reference to the accompanying drawings, which form a part of the detailed description. The drawings illustrate specific embodiments in which the invention can be practiced by way of illustration. These embodiments are referred to herein as “examples.” Such examples may include elements other than those shown or described. However, the inventors also contemplate other examples in which only the shown or described elements are provided. Furthermore, the inventors contemplate examples using any combination or substitution of those elements shown or described relative to the specific examples (or one or more aspects thereof) or other examples (or one or more aspects thereof) shown or described herein.

[0107] If there is any inconsistency in usage between this text and any references incorporated by way of citation, then the usage in this text shall prevail.

[0108] In this document, as is common in patent literature, the term “a” is used to include one or more, independent of any other instances or uses of “at least one” or “one or more.” In this document, the term “or” is used to indicate a non-exclusive OR, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated. In this document, the terms “comprising” and “in…” are used as common English synonyms for the corresponding terms “comprising” and “wherein.” Furthermore, in the following claims, the term “comprising” is open-ended, meaning that a system, apparatus, article, composition, formula, or process that includes elements other than those listed after such a term in the claim is still considered to fall within the scope of that claim. Additionally, in the following claims, the terms “first,” “second,” and “third,” etc., are used merely as labels and are not intended to impose numerical requirements on their objects.

[0109] The methods described herein can be implemented, at least in part, by a machine or computer. Some examples may include a computer-readable or machine-readable medium encoded with instructions that can be used to configure an electronic device to perform the methods described in the examples above. Implementations of such methods may include code, such as microcode, assembly language code, or high-level language code. Such code may include computer-readable instructions for performing various methods. The code may form part of a computer program product. Furthermore, in the examples, the code may be tangibly stored, for example, during execution or at other times, on one or more volatile, non-transient, or non-volatile tangible computer-readable media. Examples of such tangible computer-readable media may include, but are not limited to, hard disks, removable disks, removable optical disks (e.g., compressed disks and digital video disks), magnetic tape cassettes, memory cards or memory sticks, random access memory (RAM), and read-only memory (ROM).

[0110] The foregoing description is intended to be illustrative and not limiting. For example, the examples (or one or more aspects thereof) described above may be used in combination with each other. Other embodiments may be used by those skilled in the art upon review of the foregoing description. An abstract is provided to conform to 37C.FR §1.72(b) to allow the reader to quickly determine the essence of the disclosure. The abstract is provided in the understanding that it should not be used to interpret or limit the scope and meaning of the claims. Moreover, in the detailed description above, various features may be grouped together to simplify the disclosure. This should not be construed as indicating that any unclaimed disclosed feature is essential to any claim. Rather, the subject matter of the invention may be found in fewer than all the features of the particular embodiments disclosed. Therefore, the following claims are incorporated herein as examples or embodiments, each claim being an independent embodiment in itself, and it is conceivable that such embodiments may be combined with each other in various combinations or substitutions. The scope of the invention should be determined by reference to the appended claims together with the full scope of equivalents that give power to such claims.

Claims

1. A power grid device on a die, comprising: Including the substrate on the upper surface; A voltage source VSS trace is disposed on the upper surface, between two VSS bonding pads, and electrically coupled to the two VSS bonding pads. as well as VSS solder traces are positioned between the two VSS bonding pads and linearly superimposed on the voltage source traces.

2. The on-die power grid device according to claim 1, further comprising: A patterned mask disposed on the upper surface of the substrate, wherein the VSS solder traces are disposed in channels in the patterned mask.

3. The on-die power grid device according to claim 2, wherein, Each of the two VSS bonding pads supports a VSS solder bump, and wherein the VSS solder trace and the two VSS solder bumps are an integral solder structure.

4. The on-die power grid device according to claim 2 further includes a blockage portion in the voltage source pole trace.

5. The on-die power grid device according to claim 1, wherein, The voltage source trace is a first voltage source trace, the solder trace is a first VSS solder trace, and the on-die power grid device further includes: Subsequent VSS traces are provided on the upper surface and between the two VSS bonding pads; Subsequent VSS solder traces are disposed on the subsequent VSS traces and linearly superimposed on the first voltage source trace.

6. The on-die power grid device according to claim 5, further comprising: A patterned mask disposed on the upper surface of the substrate, wherein the VSS solder trace is a first VSS solder trace disposed in a channel within the patterned mask; and The subsequent VSS solder traces are set in the subsequent channels of the patterned mask.

7. The on-die power grid device according to claim 1, wherein, The voltage source trace is a first voltage source trace, the solder trace is a first VSS solder trace, and the on-die power grid device further includes: Voltage drain trace, which is positioned between two VDD bonding pads; VDD solder traces are disposed on the voltage drain traces and linearly superimposed on the voltage drain traces; Subsequent VSS traces, disposed on the upper surface and between two VSS bonding pads, wherein the first voltage source trace and the subsequent VSS traces are separated by the voltage drain trace; and Subsequent VSS solder traces are provided on the subsequent VSS traces and linearly superimposed on the subsequent VSS traces.

8. The on-die power grid device according to claim 7, further comprising: A patterned mask disposed on the upper surface of the substrate, wherein the VSS solder trace is a first VSS solder trace disposed in a first channel of the patterned mask; The subsequent VSS solder traces are set in the subsequent channels of the patterned mask; and The VDD solder traces are located in channels within the patterned mask.

9. The on-die power grid device according to claim 1, wherein, The voltage source trace is a first voltage source trace, the solder trace is a first VSS solder trace, and the on-die power grid device further includes: Voltage drain trace, which is positioned between two VDD bonding pads; VDD solder traces are disposed on the voltage drain traces and linearly superimposed on the voltage drain traces; Subsequent VSS traces are disposed on the upper surface and between two VSS bonding pads, wherein the first voltage source trace and the subsequent VSS traces are separated by the voltage drain traces. Subsequent VSS solder traces are disposed on the subsequent VSS traces and linearly superimposed on the subsequent VSS traces; A first signal trace is disposed between the first voltage source trace and the first voltage drain trace; and A second signal trace is disposed between the voltage drain trace and the subsequent VSS trace.

10. The on-die power grid device according to claim 9, further comprising: A patterned mask disposed on the upper surface of the substrate, wherein the patterned mask is in linear contact with each of the first signal trace and the second signal trace.

11. The on-die power grid device according to claim 1, wherein, The substrate is a semiconductor die.

12. The on-die power grid device according to claim 1, wherein, The substrate is a semiconductor die package.

13. The on-die power grid device according to claim 1, wherein, The substrate is a printed wiring board.

14. A method for assembling a power grid device on a die, comprising: A power trace having at least two bonding pads is patterned on a substrate, wherein the power trace is disposed between two of the at least two bonding pads and electrically coupled to the two of the at least two bonding pads. Ground traces with at least two bonding pads are patterned on the substrate; Signal traces with bonding pads are patterned on the substrate; The mask is patterned to expose the bonding pads; Patterning the mask to open channels and expose the power traces; and Solder traces are deposited in the channels and on the exposed power traces.

15. The method according to claim 14, wherein, Solder traces are deposited by drawing solder from adjacent solder bumps located on the at least two bonding pads onto the power traces.

16. The method of claim 14, further comprising depositing solder bump precursors on a plurality of bonding pads; and The solder bump precursor and the solder trace in the channel are reflowed to form an integrated structure for the two solder bumps and the solder trace.

17. The method of claim 14, further comprising forming a trace blockage portion on the power trace.

18. The method of claim 14, further comprising: The mask is patterned to open channels, thereby exposing the grounding traces; Solder traces are deposited in the channel and on the exposed ground traces; and In this process, the mask is patterned so that the signal traces are still covered by the mask.

19. The method of claim 14, further comprising: Deposit solder bump precursors on several bonding pads; The solder bump precursor and the solder trace in the channel are reflowed to form an integrated structure for the two solder bumps and the solder trace; as well as The solder trace in the two solder bump precursors and the exposed ground trace is reflowed to form an integrated structure for the two solder bumps and the ground solder trace.

20. The method of claim 14, wherein, The power trace is a first power trace; the method further includes: Pattern the subsequent power traces between the two bonding pads; Patterning the mask to open channels and expose the subsequent power traces; and Subsequent solder traces are deposited in the channel and on the exposed subsequent power traces.

21. The method according to claim 14, wherein, The signal trace is a signal 1 trace, and the method further includes: Signal traces 2 are patterned on the substrate; and In this process, the mask is patterned so that the trace of signal 2 is still covered by the mask.

22. A computing system including an on-die power grid device, comprising: Including the substrate on the upper surface; A first voltage source VSS trace is disposed on the upper surface, between two first VSS bonding pads, and electrically coupled to the two first VSS bonding pads. The first VSS solder trace is disposed between the two first VSS bonding pads and linearly superimposed on the first voltage source trace. Subsequent VSS traces are provided on the upper surface and between two subsequent VSS bonding pads; Subsequent VSS solder traces are positioned between the two subsequent VSS bonding pads and linearly overlapped on the subsequent VSS traces; Voltage drain trace, which is positioned between two VDD bonding pads; VDD solder traces are disposed on the voltage drain traces and linearly superimposed on the voltage drain traces; A patterned mask is disposed on the upper surface of the substrate, wherein each VSS solder trace is disposed in a channel in the patterned mask; as well as The outer casing is positioned away from the upper surface.

23. The computing system according to claim 22, wherein, Each of the two VSS bonding pads supports a VSS solder bump, wherein the first VSS solder trace and the two VSS solder bumps are an integral solder structure.

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