Autonomous Vehicle Advanced Sensing and Response

Abstract

The present application discloses advanced sensing and response for autonomous vehicles. One embodiment provides a computing device within an autonomous vehicle, the computing device comprising: a wireless network device for enabling a wireless data connection to an autonomous vehicle network; a plurality of processors, including general-purpose processors and general-purpose graphics processors, configured to execute a compute manager to manage execution of computational workloads associated with the autonomous vehicle, the computational workloads being associated with autonomous operation of the autonomous vehicle; and offload logic configured to execute on the plurality of processors, the offload logic configured to determine to offload one or more of the computational workloads to one or more autonomous vehicles within range of the wireless network device.

Description

Technical Field

[0001] Embodiments relate generally to data processing, and more particularly to data processing via a general-purpose graphics processing unit. Background Art

[0002] Current parallel graphics data processing includes systems and methods developed for performing specific operations on graphics data, such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors have used fixed-function compute units to process graphics data; however, recently, portions of graphics processors have become programmable, enabling such processors to support a wider variety of operations for processing vertex and fragment data.

[0003] To further improve performance, graphics processors typically implement processing techniques (e.g., pipelining) that attempt to process as much graphics data in parallel as possible across different parts of the graphics pipeline. Parallel graphics processors with a single instruction multiple thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In a SIMT architecture, multiple groups of parallel threads attempt to execute program instructions together synchronously as often as possible to improve processing efficiency. A general overview of software and hardware for a SIMT architecture can be found in Shane Cook's CUDA Programming, Chapter 3, pages 37-51 (2013); and / or Nicholas Wilt's CUDA Handbook (A Comprehensive Guide to GPU Programming), Sections 2.6.2 to 3.1.2 (June 2013). BRIEF DESCRIPTION OF THE DRAWINGS

[0004] In order that the features of the present invention may be understood in detail, a more particular description of the present invention may be had by reference to embodiments, some of which are shown in the accompanying drawings. It should be noted, however, that the drawings show only typical embodiments and are therefore not to be considered as limiting the scope of all embodiments.

[0005] Figure 1 is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein;

[0006] Figures 2A to 2D A parallel processor component according to an embodiment is shown;

[0007] Figures 3A to 3B is a block diagram of a graphics multiprocessor according to an embodiment;

[0008] Figures 4A to 4F An exemplary architecture is presented in which multiple GPUs are communicatively coupled to multiple multi-core processors;

[0009] Figure 5 A graphics processing pipeline according to an embodiment is shown;

[0010] Figure 6 presenting a machine learning software stack according to an embodiment;

[0011] Figure 7 A highly parallel general purpose graphics processing unit according to an embodiment is presented;

[0012] Figure 8 A multi-GPU computing system according to an embodiment is presented;

[0013] Figures 9A to 9B The layers of an exemplary deep neural network are shown;

[0014] Figure 10 An exemplary recurrent neural network is presented;

[0015] Figure 11 Demonstrated the training and deployment of deep neural networks;

[0016] Figure 12 It is a block diagram showing distributed learning;

[0017] Figure 13 An exemplary inference system-on-chip (SOC) suitable for performing inference using a trained model is presented;

[0018] Figure 14 A vehicle communication network that may be used by the embodiments described herein is presented;

[0019] Figure 15 A distributed computing management system according to an embodiment is presented;

[0020] Figure 16 The relationship between computational power and communication latency in a local autonomous vehicle as described in this paper is demonstrated;

[0021] Figure 17 is a flow chart illustrating autonomous vehicle computation offloading logic according to an embodiment;

[0022] Figure 18 demonstrated the use of autonomous vehicle sensors to assist in distributed search;

[0023] Figure 19 Distributed autonomous vehicle search logic according to an embodiment is presented;

[0024] Figure 20 Demonstrates sharing of inferred data between autonomous vehicles according to an embodiment;

[0025] Figure 21 is a flow chart illustrating inference sharing logic according to an embodiment;

[0026] Figure 22 An autonomous vehicle configured to minimize damage from an autonomous vehicle accident via internal sensors according to an embodiment is presented;

[0027] Figure 23 is a flow chart illustrating collision avoidance and mitigation logic according to an embodiment;

[0028] Figure 24 An autonomous post-crash system according to an embodiment is presented;

[0029] Figure 25 Details of autonomous post-crash logic according to an embodiment are presented;

[0030] Figure 26 is a block diagram of a processing system according to an embodiment;

[0031] Figure 27 is a block diagram of an embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor;

[0032] Figure 28 is a block diagram of a graphics processor, which may be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores;

[0033] Figure 29 is a block diagram of a graphics processing engine of a graphics processor according to some embodiments;

[0034] Figure 30 is a block diagram of a graphics processor provided by an additional embodiment;

[0035] Figure 31 Thread execution logic is shown, including an array of processing elements employed in some embodiments;

[0036] Figure 32 is a block diagram illustrating a graphics processor instruction format according to some embodiments;

[0037] Figure 33 is a block diagram of a graphics processor according to another embodiment;

[0038] Figures 34A to 34B A graphics processor command format and command sequence according to some embodiments is presented;

[0039] Figure 35An exemplary graphics software architecture for a data processing system according to some embodiments is presented;

[0040] Figure 36 is a block diagram illustrating an IP core development system according to an embodiment;

[0041] Figure 37 is a block diagram illustrating an exemplary system-on-chip integrated circuit according to an embodiment;

[0042] Figure 38 is a block diagram illustrating an additional graphics processor according to an embodiment; and

[0043] Figure 39 is a block diagram illustrating an additional exemplary graphics processor of a system-on-chip integrated circuit according to an embodiment. DETAILED DESCRIPTION

[0044] In some embodiments, a graphics processing unit (GPU) is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of how the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0045] In the following description, numerous specific details are set forth to provide a more comprehensive understanding. However, it will be apparent to those skilled in the art that the embodiments described herein may be practiced without one or more of these specific details. In other instances, well-known features are not described to avoid obscuring the details of the present embodiments.

[0046] System Overview

[0047] Figure 11 is a block diagram illustrating a computer system 100 configured to implement one or more aspects of the embodiments described herein. Computing system 100 includes a processing subsystem 101 having one or more processors 102 and system memory 104, which communicate via an interconnect path that may include a memory hub 105. Memory hub 105 may be a separate component within a chipset assembly or integrated within one or more processors 102. Memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. I / O subsystem 111 includes an I / O hub 107, which enables computing system 100 to receive input from one or more input devices 108. Additionally, I / O hub 107 enables a display controller (which may be included in one or more processors 102) to provide output to one or more display devices 110A. In one embodiment, the one or more display devices 110A coupled to I / O hub 107 may include a local display device, an internal display device, or an embedded display device.

[0048] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112, which are coupled to the memory hub 105 via a bus or other communication link 113. The communication link 113 can be one of any number of standard-based communication link technologies or protocols (such as, but not limited to, PCI Express), or a vendor-specific communication interface or communication structure. In one embodiment, the one or more parallel processors 112 form a compute-centric parallel or vector processing system that includes a large number of processing cores and / or processing clusters such as integrated many-core (MIC) processors. In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one of one or more display devices 110A coupled via the I / O hub 107. The one or more parallel processors 112 can also include a display controller and display interface (not shown) to enable direct connection to one or more display devices 110B.

[0049] Within the I / O subsystem 111, a system storage unit 114 can be connected to the I / O hub 107 to provide a storage mechanism for the computing system 100. An I / O switch 116 can be used to provide an interface mechanism to enable connections between the I / O hub 107 and other components that can be integrated into the platform, such as a network adapter 118 and / or a wireless network adapter 119, as well as various other devices that can be added via one or more plug-in devices 120. The network adapter 118 can be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices that include one or more radio devices.

[0050] Computing system 100 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 107 . Figure 1 The communication paths interconnecting the various components may be implemented using any suitable protocol such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express), or (multiple) any other bus or point-to-point communication interface and / or protocol such as the NV-Link high-speed interconnect or interconnect protocols known in the art.

[0051] In one embodiment, one or more parallel processors 112 incorporate circuits optimized for graphics and video processing, including, for example, video output circuitry, and the circuits constitute a graphics processing unit (GPU). In another embodiment, one or more parallel processors 112 incorporate circuits optimized for general-purpose processing while retaining the basic computing architecture described in more detail herein. In yet another embodiment, the components of the computing system 100 can be integrated with one or more other system elements on a single integrated circuit. For example, one or more parallel processors 112, memory hub 105, (multiple) processors 102, and I / O hub 107 can be integrated into a system-on-chip (SoC) integrated circuit. Alternatively, the components of the computing system 100 can be integrated into a single package to form a system-in-package (SIP) configuration. In other embodiments, at least a portion of the components of the computing system 100 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules to form a modular computing system.

[0052] It should be understood that the computing system 100 shown herein is illustrative and that variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of processor(s) 102, and the number of parallel processor(s) 112, can be modified as needed. For example, in some embodiments, the system memory 104 is connected to the processor(s) 102 directly rather than through a bridge, while other devices communicate with the system memory 104 via the memory hub 105 and the processor(s) 102. In other alternative topologies, the parallel processor(s) 112 are connected to the I / O hub 107 or directly to one of the one or more processors 102 rather than to the memory hub 105. In other embodiments, the I / O hub 107 and the memory hub 105 can be integrated into a single chip. Some embodiments may include two or more groups of processor(s) 102 attached via multiple sockets, which may be coupled to two or more instances of the parallel processor(s) 112.

[0053] Some specific components shown herein are optional and may not be included in all implementations of computing system 100. For example, any number of plug-in cards or peripheral devices may be supported, or some components may be omitted. In addition, some architectures may use different terminology to describe the components associated with the computing system 100. Figure 1 For example, in some architectures, memory hub 105 may be referred to as a north bridge, while I / O hub 107 may be referred to as a south bridge.

[0054] Figure 2A A parallel processor 200 according to an embodiment is shown. The various components of the parallel processor 200 may be implemented using one or more integrated circuit devices such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). According to an embodiment, the parallel processor 200 shown is Figure 1 A variation of one or more parallel processors 112 is shown.

[0055] In one embodiment, parallel processor 200 includes a parallel processing unit (PPU) 202. The PPU includes an I / O unit 204 that enables communication with other devices, including other instances of PPU 202. I / O unit 204 can be directly connected to other devices. In one embodiment, I / O unit 204 connects to other devices via the use of a hub or switch interface, such as memory hub 105. The connection between memory hub 105 and I / O unit 204 forms communication link 113. Within PPU 202, I / O unit 204 is connected to a host interface 206 that receives commands related to performing processing operations and a memory crossbar switch 216 that receives commands related to performing memory operations.

[0056] When host interface 206 receives command buffers via I / O unit 204, it can direct the work operations required to execute those commands to front-end 208. In one embodiment, front-end 208 is coupled to scheduler 210, which is configured to distribute commands or other work items to processing cluster array 212. In one embodiment, scheduler 210 ensures that processing cluster array 212 is properly configured and in a valid state before distributing tasks to processing clusters within processing cluster array 212. In one embodiment, scheduler 210 is implemented via firmware logic executed on a microcontroller. Scheduler 210 implemented via a microcontroller can be configured to perform complex scheduling and work distribution operations at both coarse and fine granularity, enabling rapid preemption and context switching of threads executing on processing array 212. In one embodiment, host software can identify workloads for scheduling on processing array 212 via one of multiple graphics processing doorbell mechanisms. These workloads can then be automatically distributed across processing array 212 by scheduler 210 logic within the scheduler microcontroller.

[0057] Processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B, and so on, up to cluster 214N). Each cluster 214A through 214N of processing cluster array 212 may execute a large number of concurrent threads. Scheduler 210 may use various scheduling and / or work distribution algorithms to distribute work to clusters 214A through 214N of processing cluster array 212, which may vary depending on the workload induced by each type of program or computation. Scheduling may be handled dynamically by scheduler 210, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by processing cluster array 212. In one embodiment, different clusters 214A through 214N of processing cluster array 212 may be assigned to process different types of programs or to perform different types of computations.

[0058] Processing cluster array 212 can be configured to perform various types of parallel processing operations. In one embodiment, processing cluster array 212 is configured to perform general-purpose parallel computing operations. For example, processing cluster array 212 may include logic for performing processing tasks including filtering of video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0059] In one embodiment, processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where parallel processors 200 are configured to perform graphics processing operations, processing cluster array 212 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In addition, processing cluster array 212 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. Parallel processing units 202 may transfer data from system memory via I / O units 204 for processing. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 222) during processing and then written back to system memory.

[0060] In one embodiment, when parallel processing unit 202 is used to perform graphics processing, scheduler 210 can be configured to divide the processing workload into tasks of approximately equal size to better enable the distribution of graphics processing operations to multiple clusters 214A to 214N of processing cluster array 212. In some embodiments, portions of processing cluster array 212 can be configured to perform different types of processing. For example, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to produce a rendered image for display. Intermediate data generated by one or more of clusters 214A to 214N can be stored in a buffer to allow the intermediate data to be transferred between clusters 214A to 214N for further processing.

[0061] During operation, the processing cluster array 212 may receive processing tasks to be executed via the scheduler 210, which receives commands defining the processing tasks from the front end 208. For graphics processing operations, a processing task may include data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters defining how to process the data and an index of a command (e.g., which program to execute). The scheduler 210 may be configured to obtain an index corresponding to a task or may receive an index from the front end 208. The front end 208 may be configured to ensure that the processing cluster array 212 is configured to be in a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0062] Each of the one or more instances of parallel processing unit 202 can be coupled to parallel processor memory 222. Parallel processor memory 222 can be accessed via memory crossbar switch 216, which can receive memory requests from processing cluster array 212 and I / O unit 204. Memory crossbar switch 216 can access parallel processor memory 222 via memory interface 218. Memory interface 218 can include multiple partition units (e.g., partition unit 220A, partition unit 220B, through partition unit 220N), each of which can be coupled to a portion of parallel processor memory 222 (e.g., memory cells). In one implementation, the number of partition units 220A through 220N is configured to be equal to the number of memory cells, such that the first partition unit 220A has a corresponding first memory cell 224A, the second partition unit 220B has a corresponding memory cell 224B, and the Nth partition unit 220N has a corresponding Nth memory cell 224N. In other embodiments, the number of partition units 220A through 220N may not be equal to the number of memory devices.

[0063] In various embodiments, memory units 224A through 224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, memory units 224A through 224N may also include 3D stacked memory, including, but not limited to, high bandwidth memory (HBM). Those skilled in the art will appreciate that the specific implementation of memory units 224A through 224N may vary and may be selected from a variety of conventional designs. Render targets, such as frame buffers or texture maps, may be stored on memory units 224A through 224N, allowing partition units 220A through 220N to write to portions of each render target in parallel, efficiently utilizing the available bandwidth of parallel processor memory 222. In some embodiments, to support a unified memory design that utilizes system memory along with local cache memory, the local instance of parallel processor memory 222 may be excluded.

[0064] In one embodiment, any of the clusters 214A to 214N in the processing cluster array 212 can process data to be written to any of the memory units 224A to 224N within the parallel processor memory 222. Memory crossbar 216 can be configured to pass the output of each cluster 214A to 214N to any partition unit 220A to 220N or another cluster 214A to 214N, which can perform additional processing operations on the output. Each cluster 214A to 214N can communicate with a memory interface 218 via the memory crossbar 216 to perform read or write operations on various external memory devices. In one embodiment, memory crossbar 216 can be connected to memory interface 218 to communicate with I / O unit 204 and to a local instance of parallel processor memory 222, thereby enabling processing units within different processing clusters 214A to 214N to communicate with system memory or other memory that is not local to the parallel processing unit 202. In one embodiment, the memory crossbar 216 may use virtual channels to separate traffic flows between the clusters 214A through 214N and the partition units 220A through 220N.

[0065] Although a single instance of parallel processing unit 202 is shown within parallel processor 200, any number of instances of parallel processing unit 202 may be included. For example, multiple instances of parallel processing unit 202 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. Different instances of parallel processing unit 202 may be configured to interoperate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, and in one embodiment, some instances of parallel processing unit 202 may include higher precision floating point units relative to other instances. Systems incorporating one or more instances of parallel processing unit 202 or parallel processor 200 may be implemented in a variety of configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0066] Figure 2B is a block diagram of the partition unit 220 according to an embodiment. In one embodiment, the partition unit 220 is Figure 2A2. As shown, partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and a ROP 226 (raster operation unit). L2 cache 221 is a read / write cache that is configured to execute load and store operations received from memory crossbar 216 and ROP 226. Read misses and urgent write-back requests are output by L2 cache 221 to frame buffer interface 225 for processing. Updates can also be sent to the frame buffer via frame buffer interface 225 for processing. In one embodiment, frame buffer interface 225 interfaces with one of the memory units in parallel processor memory, such as memory units 224A to 224N of FIG. 2 (e.g., within parallel processor memory 222).

[0067] In graphics applications, ROP 226 is a processing unit that performs raster operations (e.g., stenciling, z-testing, color blending, etc.). ROP 226 then outputs processed graphics data that is stored in graphics memory. In some embodiments, ROP 226 includes compression logic that compresses depth or color data written to memory and decompresses depth or color data read from memory. The compression logic can be lossless compression logic that uses one or more of a variety of compression algorithms. The type of compression performed by ROP 226 can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta color compression is performed on depth and color data on a tile-by-tile basis.

[0068] In some embodiments, ROP 226 is included within each processing cluster (e.g., clusters 214A through 214N of FIG. 2 ) rather than within partition unit 220. In this embodiment, read and write requests for pixel data are transmitted through memory crossbar 216 rather than pixel fragment data. The processed graphics data may be displayed on a display device such as a Figure 1 to one of the one or more display devices 110, routed by the processor(s) 102 for further processing, or by Figure 2A One of the processing entities within parallel processor 200 is routed for further processing.

[0069] Figure 2C2 is a block diagram of a processing cluster 214 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 214A to 214N of Figure 2. The processing cluster 214 can be configured to execute multiple threads in parallel, where the term "thread" refers to an instance of a specific program executed on a specific input data set. In some embodiments, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, single instruction multiple thread (SIMT) technology is used to use a public instruction unit configured to issue instructions to a group of processing engines within each of the processing clusters to support the parallel execution of a large number of roughly synchronized threads. Unlike the SIMD execution mechanism in which all processing engines typically execute the same instruction, SIMT execution allows different threads to more easily follow the divergent execution path that passes through a given thread program. Those skilled in the art will understand that the SIMD processing mechanism represents a functional subset of the SIMT processing mechanism.

[0070] The operation of the processing cluster 214 can be controlled via a pipeline manager 232 that distributes processing tasks to the SIMT parallel processors. The pipeline manager 232 receives instructions from the scheduler 210 of FIG. 2 and manages the execution of those instructions via the graphics multiprocessor 234 and / or the texture unit 236. The illustrated graphics multiprocessor 234 is an illustrative example of a SIMT parallel processor. However, various types of SIMT parallel processors with different architectures can be included in the processing cluster 214. One or more instances of the graphics multiprocessor 234 can be included in the processing cluster 214. The graphics multiprocessor 234 can process data, and the data crossbar 240 can be used to distribute the processed data to one of multiple possible destinations, including other shading units. The pipeline manager 232 can facilitate the distribution of the processed data by specifying a destination for the data to be distributed via the data crossbar 240.

[0071] Each graphics multiprocessor 234 within a processing cluster 214 may include the same set of function execution logic (e.g., arithmetic logic unit, load-store unit, etc.). The function execution logic may be configured in a pipelined manner, where a new instruction may be issued before the previous instruction has completed. The function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and calculations of various algebraic functions. In one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0072] Instructions transmitted to the processing cluster 214 constitute threads. A group of threads executing on a set of parallel processing engines is a thread group. A thread group executes the same program on different input data. Each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 234. A thread group can include fewer threads than the number of processing engines within the graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle in which the thread group is being processed. A thread group can also include more threads than the number of processing engines within the graphics multiprocessor 234. When a thread group includes more threads than the number of processing engines within the graphics multiprocessor 234, processing can be performed on consecutive clock cycles. In one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 234.

[0073] In one embodiment, the graphics multiprocessor 234 includes internal cache memory for performing load and store operations. In one embodiment, the graphics multiprocessor 234 may forgo the internal cache and instead use cache memory within the processing cluster 214 (e.g., L1 cache 308). Each graphics multiprocessor 234 also has access to an L2 cache within a partition unit (e.g., partition units 220A through 220N in FIG. 2 ) that is shared across all processing clusters 214 and can be used to transfer data between threads. The graphics multiprocessor 234 also has access to off-chip global memory, which may include one or more of the local parallel processor memory and / or system memory. Any memory external to the parallel processing unit 202 may be used as global memory. Embodiments in which a processing cluster 214 includes multiple instances of the graphics multiprocessor 234 may share common instructions and data that may be stored in the L1 cache 308.

[0074] Each processing cluster 214 may include an MMU 245 (memory management unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of the MMU 245 may reside within the memory interface 218 of FIG. 2 . The MMU 245 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles and, optionally, cache line indexes. The MMU 245 may include an address translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 234 or L1 cache or processing cluster 214. Physical addresses are processed to distribute surface data access locality to achieve efficient request interleaving between partition units. The cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0075] In graphics and compute applications, the processing clusters 214 can be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown) or, in some embodiments, from an L1 cache within the graphics multiprocessor 234 and retrieved from an L2 cache, local parallel processor memory, or system memory as needed. Each graphics multiprocessor 234 outputs processed tasks to a data crossbar 240 to provide the processed tasks to another processing cluster 214 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 216. A preROP 242 (pre-raster operations unit) is configured to receive data from the graphics multiprocessor 234 and direct the data to ROP units, which can be located using partition units (e.g., partition units 220A through 220N of FIG. 2 ) as described herein. The preROP 242 unit optimizes color blending, organizes pixel color data, and performs address translation.

[0076] It should be understood that the core architecture described herein is illustrative and that variations and modifications are possible. Any number of processing units, such as graphics multiprocessor 234, texture unit 236, preROP 242, etc., may be included within processing cluster 214. Furthermore, while only one processing cluster 214 is shown, the parallel processing unit described herein may include any number of instances of processing cluster 214. In one embodiment, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 cache, etc.

[0077] Figure 2D A graphics multiprocessor 234 is shown according to one embodiment. In such an embodiment, the graphics multiprocessor 234 is coupled to the pipeline manager 232 of the processing cluster 214. The graphics multiprocessor 234 has an execution pipeline that includes, but is not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268.

[0078] In one embodiment, the instruction cache 252 receives a stream of instructions to be executed from the pipeline manager 232. These instructions are cached in the instruction cache 252 and dispatched for execution by the instruction unit 254. The instruction unit 254 can dispatch instructions as thread groups (e.g., warps), with each thread of the thread group being assigned to a different execution unit within the GPGPU core 262. Instructions can access any of the local, shared, or global address spaces by specifying an address within the unified address space. The address mapping unit 256 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 266.

[0079] The register file 258 provides a set of registers for the functional units of the graphics multiprocessor 324. The register file 258 provides temporary storage for operands for the data paths of the functional units (e.g., the GPGPU core 262, the load / store unit 266) connected to the graphics multiprocessor 324. In one embodiment, the register file 258 is divided between each of the functional units so that each functional unit is allocated a dedicated portion of the register file 258. In one embodiment, the register file 258 is divided between the different warps being executed by the graphics multiprocessor 324.

[0080] The GPGPU cores 262 may each include a floating point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 324. Depending on the embodiment, the architecture of the GPGPU cores 262 may be similar or different. For example, and in one embodiment, the first portion of the GPGPU core 262 includes a single-precision FPU and an integer ALU, while the second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 floating-point arithmetic standard or enable variable-precision floating-point arithmetic. In addition, the graphics multiprocessor 324 may also include one or more fixed-function or special-function units for performing specific functions such as copying rectangles or pixel blending operations. In one embodiment, one or more of the GPGPU cores may also include fixed-function or special-function logic.

[0081] In one embodiment, the GPGPU core 262 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 262 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. The SIMD instructions of the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. Multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example, and in one embodiment, eight SIMT threads can be executed in parallel via a single SIMD8 logic unit, and these eight SIMT threads perform the same or similar operations.

[0082] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 324 to the register file 258 and the shared memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to perform load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, so data transfers between the GPGPU core 262 and the register file 258 have very low latency. The shared memory 270 can be used to facilitate communication between threads executing on the functional units within the graphics multiprocessor 234. For example, the cache memory 272 can be used as a data cache to cache texture data communicated between the functional units and the texture unit 236. The shared memory 270 can also be used as a cached managed program. In addition to automatically cached data stored in the cache memory 272, threads executing on the GPGPU core 262 can also programmatically store data in the shared memory.

[0083] Figures 3A to 3B Additional graphics multiprocessors are shown according to an embodiment. The graphics multiprocessors 325, 350 shown are Figure 2C The illustrated graphics multiprocessors 325, 350 may be configured as streaming multiprocessors (SMs) capable of executing a large number of execution threads simultaneously.

[0084] Figure 3A A graphics multiprocessor 325 is shown according to an additional embodiment. The graphics multiprocessor 325 includes Figure 2DThe graphics multiprocessor 325 may include multiple additional instances of execution resource units of the graphics multiprocessor 234. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A-332B, register files 334A-334B, and texture unit(s) 344A-344B. The graphics multiprocessor 325 may also include multiple sets of graphics or compute execution units (e.g., GPGPU cores 336A-336B, GPGPU cores 337A-337B, GPGPU cores 338A-338B) and multiple sets of load / store units 340A-340B. In one embodiment, the execution resource units have a common instruction cache 330, texture and / or data cache memory 342, and shared memory 346.

[0085] Various components can communicate via interconnect fabric 327. In one embodiment, interconnect fabric 327 includes one or more crossbar switches to facilitate communication between the various components of graphics multiprocessor 325. In one embodiment, interconnect fabric 327 is a separate, high-speed network fabric layer upon which each component of graphics multiprocessor 325 is stacked. Components of graphics multiprocessor 325 communicate with remote components via interconnect fabric 327. For example, GPGPU cores 336A-336B, 337A-337B, and 3378A-338B can each communicate with shared memory 346 via interconnect fabric 327. Interconnect fabric 327 can arbitrate communications within graphics multiprocessor 325 to ensure fair bandwidth distribution between components.

[0086] Figure 3B A graphics multiprocessor 350 is shown according to an additional embodiment. Figure 2D As shown in FIG3A , the graphics processor includes multiple sets of execution resources 356A to 356D, each of which includes multiple instruction units, register files, GPGPU cores, and load-store units. The execution resources 356A to 356D can work with (multiple) texture units 360A to 360D to perform texture operations while sharing an instruction cache 354 and a shared memory 362. In one embodiment, the execution resources 356A to 356D can share multiple instances of the instruction cache 354 and the shared memory 362 as well as texture and / or data cache memories 358A to 358B. The various components can be connected to the graphics processor via the CPU. Figure 3A The interconnect structure 327 communicates with a similar interconnect structure 352 .

[0087] Those skilled in the art will understand that Figure 1 、 Figures 2A to 2D and Figures 3A to 3BThe architecture described in the accompanying drawings is illustrative and does not limit the scope of the embodiments of the present invention. Therefore, the techniques described herein can be implemented on any appropriately configured processing unit, including but not limited to: one or more mobile application processors; one or more desktop or server central processing units (CPUs), including multi-core CPUs; one or more parallel processing units such as parallel processing unit 202 of FIG. 2; and one or more graphics processors or special-purpose processing units, without departing from the scope of the embodiments described herein.

[0088] In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of the manner in which the GPU is connected, the processor core can allocate work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then processes these commands / instructions efficiently using dedicated circuits / logic.

[0089] Technologies for GPU to host processor interconnect

[0090] Figure 4A An exemplary architecture is shown in which multiple GPUs 410 to 413 are communicatively coupled to multiple multi-core processors 405 to 406 via high-speed links 440 to 443 (e.g., a bus, a point-to-point interconnect, etc.). In one embodiment, the high-speed links 440 to 443 support a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or higher, depending on the implementation. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the underlying principles of the present invention are not limited to any particular communication protocol or throughput.

[0091] Furthermore, in one embodiment, two or more of the GPUs 410 to 413 are interconnected via high-speed links 444 to 445, which may be implemented using the same or different protocols / links as used for high-speed links 440 to 443. Similarly, two or more of the multi-core processors 405 to 406 may be connected via high-speed link 433, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, Figure 4AAll communications between the various system components shown in can be accomplished using the same protocol / links (eg, through a common interconnect structure). However, as mentioned, the underlying principles of the invention are not limited to any particular type of interconnect technology.

[0092] In one embodiment, each multi-core processor 405-406 is communicatively coupled to processor memory 401-402 via memory interconnects 430-431, respectively, and each GPU 410-413 is communicatively coupled to GPU memory 420-423 via GPU memory interconnects 450-453, respectively. Memory interconnects 430-431 and 450-453 can utilize the same or different memory access technologies. By way of example and not limitation, processor memory 401-402 and GPU memory 420-423 can be volatile memory such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memory such as 3D XPoint or Nano-Ram. In one embodiment, a portion of the memory can be volatile memory, while another portion can be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0093] As described below, although the various processors 405-406 and GPUs 410-413 may each be physically coupled to a specific memory 401-402, 420-423, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed across all of the various physical memories. For example, the processor memories 401-402 may each include 64GB of system memory address space, and the GPU memories 420-423 may each include 32GB of system memory address space (resulting in a total of 256GB of addressable memory space in the described example).

[0094] Figure 4B 4 shows additional details of the interconnection between the multi-core processor 407 and the graphics acceleration module 446 according to one embodiment. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card coupled to the processor 407 via the high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

[0095] The processor 407 shown includes multiple cores 460A to 460D, each of which has a translation lookaside buffer 461A to 461D and one or more caches 462A to 462D. These cores may include various other components (e.g., instruction fetch units, branch prediction units, decoders, execution units, reorder buffers, etc.) for executing instructions and processing data not shown to avoid obscuring the basic principles of the present invention. Caches 462A to 462D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 426 may be included in the cache hierarchy and shared by each group of cores 460A to 460D. For example, one embodiment of the processor 407 includes 24 cores, each of which has its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 cache and the L3 cache is shared by two adjacent cores. The processor 407 and the graphics accelerator integrated module 446 are connected to the system memory 441 , which may include the processor memories 401 to 402 .

[0096] Coherence is maintained for data and instructions stored in the various caches 462A to 462D, 456, and system memory 441 via inter-core communication via a coherence bus 464. For example, each cache may have associated cache coherence logic / circuitry to communicate via the coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented via the coherence bus 464 to snoop cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art, and to avoid obscuring the underlying principles of the present invention, they are not described in detail herein.

[0097] In one embodiment, the proxy circuit 425 communicatively couples the graphics acceleration module 446 to the coherence bus 464, thereby allowing the graphics acceleration module 446 to participate in the cache coherence protocol as a peer of the core. Specifically, the interface 435 provides connectivity to the proxy circuit 425 via a high-speed link 440 (e.g., a PCIe bus, NVLink, etc.), and the interface 437 connects the graphics acceleration module 446 to the link 440.

[0098] In one implementation, the accelerator integrated circuit 436 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 431, 432, 43N of the graphics acceleration module 446. The graphics processing engines 431, 432, 43N can each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, 43N can include different types of graphics processing engines such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a block image transfer engine within the GPU. In other words, the graphics acceleration module can be a GPU having multiple graphics processing engines 431, 432, 43N, or the graphics processing engines 431 to 432, 43N can be separate GPUs integrated on a common package, line card, or chip.

[0099] In one embodiment, the accelerator integrated circuit 436 includes a memory management unit (MMU) 439 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and a memory access protocol for accessing system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, cache 438 stores commands and data for efficient access by graphics processing engines 431-432, 43N. In one embodiment, data stored in cache 438 and graphics memory 433-434, 43N is kept consistent with core caches 462A-462D, 456, and system memory 411. As mentioned, this may be accomplished via proxy circuitry 425, which participates in cache coherence mechanisms on behalf of cache 438 and memories 433 to 434, 43N (e.g., sending updates to cache 438 related to modifications / accesses of cache lines on processor caches 462A to 462D, 456 and receiving updates from cache 438).

[0100] A set of registers 445 stores context data for threads executed by graphics processing engines 431 to 432, 43N, and context management circuitry 448 manages thread contexts. For example, context management circuitry 448 can perform save and restore operations to save and restore the contexts of various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, upon context switching, context management circuitry 448 can store current register values ​​to a designated area in memory (e.g., identified by a context pointer). The context management circuitry can restore register values ​​upon returning to context. In one embodiment, interrupt management circuitry 447 receives and processes interrupts received from system devices.

[0101] In one implementation, the virtual / effective addresses from the graphics processing engine 431 are translated into real / physical addresses in the system memory 411 by the MMU 439. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator module 446 can be dedicated to a single application executing on the processor 407, or can be shared among multiple applications. In one embodiment, a virtual graphics execution environment is presented in which the resources of the graphics processing engines 431 to 432, 43N are shared with multiple applications or virtual machines (VMs). The resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0102] Thus, the accelerator integrated circuit acts as a bridge to the system for the graphics acceleration module 446 and provides address translation and system memory cache services. Additionally, the accelerator integrated circuit 436 can provide virtualization facilities for the host processor to manage virtualization of the graphics processing engine, interrupts, and memory management.

[0103] Because the hardware resources of the graphics processing engines 431-432, 43N are explicitly mapped into the real address space seen by the host processor 407, any host processor can directly address these resources using effective address values. In one embodiment, one function of the accelerator integrated circuit 436 is the physical separation of the graphics processing engines 431-432, 43N so that they appear to the system as independent units.

[0104] As mentioned, in the illustrated embodiment, one or more graphics memories 433-434, 43M are coupled to each of the graphics processing engines 431-432, 43N, respectively. Graphics memories 433-434, 43M store instructions and data being processed by each of the graphics processing engines 431-432, 43N. Graphics memories 433-434, 43M can be volatile memory such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memory such as 3D XPoint or Nano-Ram.

[0105] In one embodiment, to reduce data traffic on link 440, a biasing technique is used to ensure that the data stored in graphics memories 433-434, 43M is the data most frequently used by graphics processing engines 431-432, 43N and preferably not used (at least not frequently) by cores 460A-460D. Similarly, the biasing mechanism attempts to keep data needed by the cores (and preferably not graphics processing engines 431-432, 43N) within caches 462A-462D, 456 of the core and system memory 411.

[0106] Figure 4C Another embodiment is shown in which the accelerator integrated circuit 436 is integrated into the processor 407. In this embodiment, the graphics processing engines 431 to 432, 43N communicate directly with the accelerator integrated circuit 436 via the interface 437 and the interface 435 via the high-speed link 440 (which may also utilize any form of bus or interface protocol). The accelerator integrated circuit 436 can perform operations related to Figure 4B The same operations are described, but given their close proximity to the coherency bus 462 and caches 462A to 462D, 426, may operate at a higher throughput.

[0107] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The shared programming model can include a programming model controlled by the accelerator integrated circuit 436 and a programming model controlled by the graphics acceleration module 446.

[0108] In one embodiment of a dedicated process model, graphics processing engines 431 to 432, 43N are dedicated to a single application or process under a single operating system. A single application can funnel other application requests to graphics engines 431 to 432, 43N, thereby providing virtualization within a VM / partition.

[0109] In a dedicated process programming model, graphics processing engines 431 to 432, 43N can be shared by multiple VM / application partitions. This shared model requires a hypervisor, which virtualizes graphics processing engines 431 to 432, 43N to allow access by each operating system. In a single-partition system without a hypervisor, graphics processing engines 431 to 432, 43N are owned by the operating system. In both cases, the operating system can virtualize graphics processing engines 431 to 432, 43N to provide access to each process or application.

[0110] For the shared programming model, the graphics acceleration module 446 or the individual graphics processing engines 431 to 432, 43N use a process handle to select a process element. In one embodiment, process elements are stored in system memory 411 and can be addressed using the effective address to real address translation techniques described herein. The process handle can be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 431 to 432, 43N (i.e., calling system software to add a process element to the process element linked list). The lower 16 bits of the process handle can be the offset of the process element within the process element linked list.

[0111] Figure 4D An exemplary accelerator integrated slice 490 is shown. As used herein, a "slice" comprises a designated portion of the processing resources of an accelerator integrated circuit 436. An application effective address space 482 within system memory 411 stores process elements 483. In one embodiment, process elements 483 are stored in response to GPU calls 481 from applications 480 executing on processor 407. Process elements 483 contain the processing state of the corresponding application 480. A work descriptor (WD) 484 contained in a process element 483 can be a single job requested by the application, or can contain a pointer to a job queue. In the latter case, WD 484 is a pointer to a job request queue in the application address space 482.

[0112] Graphics acceleration module 446 and / or individual graphics processing engines 431-432, 43N may be shared by all or some processes in the system. Embodiments of the present invention include an infrastructure for establishing a processing state and sending a WD 484 to graphics acceleration module 446 to start a job in a virtual environment.

[0113] In one implementation, a dedicated process programming model is specific to a particular implementation. In this model, a single process owns either the graphics acceleration module 446 or a separate graphics processing engine 431. Because the graphics acceleration module 446 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 436 to obtain the owned partition, and the operating system initializes the accelerator integrated circuit 436 to obtain the owned process when the graphics acceleration module 446 is allocated.

[0114] In operation, the WD fetch unit 491 in the accelerator integrated slice 490 fetches the next WD 484, which includes an indication of work to be performed by one of the graphics processing engines of the graphics acceleration module 446. As shown, data from the WD 484 can be stored in registers 445 and used by the MMU 439, the interrupt management circuit 447, and / or the context management circuit 446. For example, one embodiment of the MMU 439 includes a segment / page walk circuit for accessing the segment / page table 486 within the OS virtual address space 485. The interrupt management circuit 447 can process interrupt events 492 received from the graphics acceleration module 446. When executing graphics operations, the effective addresses 493 generated by the graphics processing engines 431 to 432, 43N are converted into real addresses by the MMU 439.

[0115] In one embodiment, the same set of registers 445 is replicated for each graphics processing engine 431 to 432, 43N, and / or graphics acceleration module 446, and can be initialized by a hypervisor or operating system. Each of these replicated registers can be included in an accelerator integration slice 490. Table 1 shows exemplary registers that can be initialized by a hypervisor.

[0116] 1 Slice Control Register 2 Real Address (RA) Dispatch Process Area Pointer 3 Authorization mask override register 4 Interrupt vector table entry offset 5 Interrupt vector table entry limit 6 Status Register 7 Logical partition ID 8 Real Address (RA) Manager Accelerator Utilizes Record Pointers 9 Storage Description Register

[0117] Example registers that may be initialized by the operating system are shown in Table 2.

[0118] 1 Process and thread identifiers 2 Effective Address (EA) context save / restore pointer 3 Virtual Address (RA) Accelerator Utilizes Record Pointers 4 Virtual Address (RA) storage segment table pointer 5 Authorization Mask 6 Job Descriptor

[0119] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engine 431 to 432, 43N. The WD contains all the information needed by the graphics processing engine 431 to 432, 43N to complete its work, or the WD may be a pointer to a memory location where the application has set up a command queue for work to be completed.

[0120] Figure 4E4. The embodiment of the sharing model includes a hypervisor real address space 498 in which a process element list 499 is stored. The hypervisor real address space 498 is accessible via a hypervisor 496 that virtualizes the graphics acceleration module engine of the operating system 495.

[0121] The shared programming model allows all or some processes from all or some partitions in the system to use the graphics acceleration module 446. There are two programming models where the graphics acceleration module 446 is shared by multiple processes and partitions: time-sliced ​​sharing and graphics direct sharing.

[0122] In this model, hypervisor 496 owns graphics acceleration module 446 and makes its functionality available to all operating systems 495. For graphics acceleration module 446 to support hypervisor 496 virtualization, it must adhere to the following requirements: 1) Application job requests must be autonomous (i.e., no state needs to be maintained between jobs), or graphics acceleration module 446 must provide a context save and restore mechanism. 2) Graphics acceleration module 446 guarantees that application job requests will complete within a specified amount of time, including any translation errors, or graphics acceleration module 446 provides the ability to preempt job processing. 3) When operating in a direct sharing programming model, fairness must be guaranteed for graphics acceleration module 446 within the process.

[0123] In one embodiment, for a shared model, application 480 is required to make an operating system 495 system call using a graphics acceleration module 446 type, a work descriptor (WD), an authorization mask register (AMR) value, and a context save / restore region pointer (CSRP). The graphics acceleration module 446 type describes the target acceleration function of the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is formatted specifically for the graphics acceleration module 446 and can take the following forms: a graphics acceleration module 446 command; an effective address pointer to a user-defined structure; an effective address pointer to a command queue; or any other data structure describing the work to be performed by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state for the current process. The value passed to the operating system is similar to the application setting the AMR. If the implementation of the accelerator integrated circuit 436 and graphics acceleration module 446 does not support the User Authorization Mask Override Register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. Before placing the AMR in the process element 483, the hypervisor 496 may optionally apply the current authorization mask override register (AMOR) value. In one embodiment, the CSRP is one of the registers 445 that contains the effective address of an area in the application address space 482 where the graphics acceleration module 446 saves and restores context state. This pointer is optional if state does not need to be saved between jobs or when a job is preempted. The context save / restore area may be plugged into system memory.

[0124] Upon receiving the system call, the operating system 495 can verify that the application 480 is registered and authorized to use the graphics acceleration module 446. The operating system 495 then calls the hypervisor 496 using the information shown in Table 3.

[0125] 1 Work Descriptor (WD) 2 Authorization Mask Register (AMR) value (may be masked) 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0126] Upon receiving the hypervisor call, the hypervisor 496 can verify that the operating system 495 has registered and is authorized to use the graphics acceleration module 446. The hypervisor 496 then places the process element 483 in the process element linked list for the corresponding graphics acceleration module 446 type. The process element can contain the information shown in Table 4.

[0127] 1 Work Descriptor (WD) 2 Authorization Mask Register (AMR) value (may be masked) 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt vector table, derived from hypervisor call parameters 9 Status register (SR) value 10 Logical Partition ID (LPID) 11 Real Address (RA) Manager Accelerator Utilizes Record Pointers 12 Storage Descriptor Register (SDR)

[0128] In one embodiment, the hypervisor initializes the plurality of accelerator integrated slices 490 of registers 445 .

[0129] like Figure 4FAs shown, one embodiment of the present invention employs a unified memory addressable via a common virtual memory address space for accessing physical processor memories 401-402 and GPU memories 420-423. In this implementation, operations executed on GPUs 410-413 utilize the same virtual / effective memory address space to access processor memories 401-402, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 401, a second portion is allocated to second processor memory 402, a third portion is allocated to GPU memory 420, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 401-402 and GPU memories 420-423, allowing any processor or GPU to access any physical memory having a virtual address mapped to that memory.

[0130] In one embodiment, bias / coherency management circuitry 494A-494E within one or more of MMUs 439A-439E ensures cache coherency between the caches of the host processor (e.g., 405) and GPUs 410-413 and implements biasing techniques that indicate physical memory where certain types of data should be stored. Figure 4F , multiple instances of bias / consistency management circuits 494A to 494E are shown, but bias / consistency circuits may also be implemented within an MMU of one or more host processors 405 and / or within an accelerator integrated circuit 436.

[0131] One embodiment allows GPU-attached memory 420-423 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, without the typical performance drawbacks associated with system-wide cache coherence. The ability to access GPU-attached memory 420-423 as system memory without incurring heavy cache coherence overhead provides a favorable operating environment for GPU offloading. This arrangement allows host processor 405 software to set operands and access computation results without the overhead of traditional I / O DMA data copies. These traditional copies involve driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are inefficient relative to simple memory accesses. At the same time, the ability to access GPU-attached memory 420-423 without cache coherence overhead can be critical to the execution time of offloaded computations. For example, in scenarios with a large amount of streaming write-to-memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 410-413. The efficiency of operand setup, result access, and GPU computation all play an important role in determining the effectiveness of GPU offloading.

[0132] In one implementation, the selection between GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which can be a page-granular structure consisting of 1 or 2 bits per GPU-attached memory page (i.e., controlled at the granularity of a memory page). The bias table can be implemented in the stolen memory range of one or more GPU-attached memories 420 to 423, with or without a bias cache in GPUs 410 to 413 (e.g., to cache frequently / recently used bias table entries). Alternatively, the entire bias table can be maintained within the GPU.

[0133] In one implementation, the bias table entry associated with each access to GPU-attached memory 420-423 is accessed before actually accessing the GPU memory, resulting in the following operations. First, local requests from GPUs 410-413 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 420-423. Local requests from the GPU whose pages are found in the host bias are forwarded to processor 405 (e.g., over a high-speed link as described above). In one embodiment, requests from processor 405 that find the requested page in the host processor bias complete the request like a normal memory read. Alternatively, requests for GPU-biased pages can be forwarded to GPUs 410-413. If the GPU is not currently using the page, the GPU can convert the page to the host processor bias.

[0134] The bias state of a page can be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, a hardware-only based mechanism.

[0135] One mechanism for changing the bias state employs an API call (e.g., OpenCL) that in turn calls the GPU device driver, which in turn sends a message (or queues a command descriptor) to the GPU, thereby directing the GPU to change the bias state and, for certain transitions, performs a cache flush operation in the host. The cache flush operation is required for transitions from host processor 405 bias to GPU bias, but not for the reverse transition.

[0136] In one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages uncacheable to host processor 405. To access these pages, processor 405 may request access from GPU 410, which may or may not grant access immediately, depending on the implementation. Therefore, to reduce communication between processor 405 and GPU 410, it is advantageous to ensure that GPU bias pages are pages required by the GPU but not by host processor 405, and vice versa.

[0137] Graphics processing pipeline

[0138] Figure 5 A graphics processing pipeline 500 according to an embodiment is shown. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 500. The graphics processor may be included in a parallel processing subsystem as described herein, such as the parallel processor 200 of FIG. 2 . In one embodiment, the parallel processor is Figure 12 . As described herein, various parallel processing systems can implement the graphics processing pipeline 500 via one or more instances of a parallel processing unit (e.g., parallel processing unit 202 of FIG. 2 ). For example, a shader unit (e.g., graphics multiprocessor 234 of FIG. 3 ) can be configured to perform the functionality of one or more of a vertex processing unit 504, a tessellation control processing unit 508, a tessellation evaluation processing unit 512, a geometry processing unit 516, and a fragment / pixel processing unit 524. The functionality of the data assembler 502, primitive assemblers 506, 514, 518, tessellation unit 510, rasterizer 522, and raster operation unit 526 can also be performed by other processing engines within a processing cluster (e.g., processing cluster 214 of FIG. 3 ) and corresponding partition units (e.g., partition units 220A through 220N of FIG. 2 ). The graphics processing pipeline 500 can also be implemented using one or more dedicated processing units for the functionality. In one embodiment, one or more portions of graphics processing pipeline 500 may be executed by parallel processing logic within a general-purpose processor (e.g., a CPU). In one embodiment, one or more portions of graphics processing pipeline 500 may access on-chip memory (e.g., parallel processor memory 222 shown in FIG. 2 ) via memory interface 528, which may be an example of memory interface 218 of FIG. 2 .

[0139] In one embodiment, the data assembler 502 is a processing unit that collects vertex data for surfaces and primitives. The data assembler 502 then outputs the vertex data, including vertex attributes, to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that executes vertex shader programs, thereby lighting and transforming the vertex data as specified by the vertex shader programs. The vertex processing unit 504 reads data stored in cache, local, or system memory for processing vertex data and can be programmed to transform vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

[0140] A first instance of primitive assembler 506 receives vertex attributes from vertex processing unit 50. Primitive assembler 506 reads the stored vertex attributes as needed and constructs graphics primitives for processing by tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches, etc. as supported by various graphics processing application programming interfaces (APIs).

[0141] The tessellation control processing unit 508 treats the input vertices as control points for a geometry patch. These control points are transformed from an input representation of the patch (e.g., a basis for the patch) into a representation suitable for surface estimation by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 may also calculate tessellation factors for the edges of the geometry patch. The tessellation factors apply to individual edges and quantify the view-dependent level of detail associated with the edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and tessellate the patch into a plurality of geometric primitives, such as lines, triangles, or quadrilaterals, which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the tessellated patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitive.

[0142] A second instance of primitive assembler 514 receives vertex attributes from tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphics primitives for processing by geometry processing unit 516. Geometry processing unit 516 is a programmable execution unit that executes geometry shader programs to transform graphics primitives received from primitive assembler 514 as specified by the geometry shader programs. In one embodiment, geometry processing unit 516 is programmed to tessellate a graphics primitive into one or more new graphics primitives and calculate parameters for rasterizing the new graphics primitives.

[0143] In some embodiments, the geometry processing unit 516 can add or delete elements from the geometry stream. The geometry processing unit 516 outputs parameters and vertices specifying new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphics primitives for processing by the viewport scaling, picking, and clipping unit 520. The geometry processing unit 516 reads data stored in parallel processor memory or system memory for processing geometry data. The viewport scaling, picking, and clipping unit 520 performs clipping, picking, and viewport scaling and outputs the processed graphics primitives to the rasterizer 522.

[0144] The rasterizer 522 can perform depth sorting and other depth-based optimizations. The rasterizer 522 also performs scan conversion on new graphics primitives to generate segments and outputs these segments and associated coverage data to the segment / pixel processing unit 524. The fragment / pixel processing unit 524 is a programmable execution unit configured to execute a fragment shader program or a pixel shader program. The fragment / pixel processing unit 524 transforms fragments or pixels received from the rasterizer 522 as specified by the fragment or pixel shader program. For example, the fragment / pixel processing unit 524 can be programmed to perform operations including, but not limited to, texture mapping, shading, blending, texture correction, and perspective correction to produce shaded fragments or pixels that are output to the raster operation unit 526. The fragment / pixel processing unit 524 can read data stored in parallel processor memory or system memory for use in processing fragment data. The fragment or pixel shader program can be configured to shade at a sample, pixel, tile, or other granularity based on the sampling rate configured for the processing unit.

[0145] The raster operation unit 526 is a processing unit that performs raster operations including but not limited to stenciling, z-testing, blending, etc., and outputs pixel data as processed graphics data for storage in graphics memory (e.g., parallel processor memory 222 in FIG. 2 , and / or as shown in FIG. 2 ). Figure 1 The raster operation unit 526 may be configured to compress the z or color data written to memory and to decompress the z or color data read from memory.

[0146] Machine Learning Overview

[0147] Machine learning algorithms are algorithms that can learn based on a set of data. Embodiments of machine learning algorithms can be designed to model high-level abstractions within a dataset. For example, image recognition algorithms can be used to determine which of several categories a given input belongs to; regression algorithms can output a numerical value given an input; and pattern recognition algorithms can be used to generate translated text or perform text-to-speech and / or speech recognition.

[0148] One example type of machine learning algorithm is a neural network. There are many types of neural networks; a simple type of neural network is a feedforward network. A feedforward network can be implemented as an acyclic graph, in which nodes are arranged in layers. Typically, a feedforward network topology includes an input layer and an output layer, separated by at least one hidden layer. The hidden layer transforms the input received by the input layer into a representation useful for generating the output in the output layer. The network nodes are fully connected to the nodes in adjacent layers via edges, but there are no edges between nodes within each layer. Data received at the nodes of the input layer of the feedforward network is propagated (i.e., "fed forward") to the nodes of the output layer via an activation function, which calculates the state of the nodes in each successive layer of the network based on coefficients ("weights") associated with each of the edges connecting these layers. Depending on the specific model represented by the algorithm being executed, the output from the neural network algorithm can take a variety of forms.

[0149] Before a machine learning algorithm can be used to model a specific problem, the algorithm is trained using a training data set. Training a neural network involves: selecting a network topology; using a set of training data representing the problem being modeled by the network; and adjusting weights until the network model behaves with minimal error for all instances of the training data set. For example, during a supervised learning training process for a neural network, the output generated by the network in response to an input representing an instance in the training data set is compared to the "correct" labeled output for the instance; an error signal representing the difference between the output and the labeled output is calculated; and as the error signal is propagated back through the layers of the network, the weights associated with the connections are adjusted to minimize the error. The network is considered "trained" when the error for each output generated from an instance of the training data set is minimized.

[0150] The accuracy of a machine learning algorithm can be greatly affected by the quality of the dataset used to train it. The training process can be computationally intensive and can require a significant amount of time on conventional general-purpose processors. Consequently, many types of machine learning algorithms are trained using parallel processing hardware. This is particularly useful for optimizing the training of neural networks, as the calculations performed when adjusting the coefficients in a neural network are naturally suited to parallel implementation. In particular, many machine learning algorithms and software applications have been adapted to use parallel processing hardware within general-purpose graphics processing devices.

[0151] Figure 66 is a generalized diagram of a machine learning software stack 600. Machine learning applications 602 can be configured to train a neural network using a training dataset or to use a trained deep neural network to implement machine intelligence. Machine learning applications 602 can include training and inference functionality for the neural network and / or specialized software that can be used to train the neural network prior to deployment. Machine learning applications 602 can implement any type of machine intelligence, including, but not limited to, image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation.

[0152] Hardware acceleration for machine learning applications 602 can be implemented via a machine learning framework 604. The machine learning framework 604 can provide a library of machine learning primitives. Machine learning primitives are the basic operations typically performed by machine learning algorithms. Without the machine learning framework 604, developers of machine learning algorithms would be required to create and optimize the main computational logic associated with the machine learning algorithm, and then re-optimize the computational logic when new parallel processors are developed. Instead, machine learning applications can be configured to use the primitives provided by the machine learning framework 604 to perform the necessary calculations. Exemplary primitives include tensor convolutions, activation functions, and pooling, which are computational operations performed when training convolutional neural networks (CNNs). The machine learning framework 604 can also provide primitives for implementing basic linear algebra subroutines, such as matrix and vector operations, performed by many machine learning algorithms.

[0153] The machine learning framework 604 can process input data received from the machine learning application 602 and generate appropriate input to the computation framework 606. The computation framework 606 can abstract the underlying instructions provided to the GPGPU driver 608 to enable the machine learning framework 604 to take advantage of hardware acceleration via the GPGPU hardware 610 without requiring the machine learning framework 604 to be intimately familiar with the architecture of the GPGPU hardware 610. In addition, the computation framework 606 can implement hardware acceleration for the machine learning framework 604 across multiple types and generations of GPGPU hardware 610.

[0154] GPGPU machine learning acceleration

[0155] Figure 7 A highly parallel general-purpose graphics processing unit 700 is shown in accordance with an embodiment. In one embodiment, the general-purpose processing unit (GPGPU) 700 can be configured to be particularly efficient in processing the type of computational workload associated with training deep neural networks. Additionally, the GPGPU 700 can be directly linked to other instances of the GPGPU to create a multi-GPU cluster, thereby improving the training speed of particularly deep neural networks.

[0156] GPGPU 700 includes a host interface 702 for connecting to a host processor. In one embodiment, host interface 702 is a PCI Express interface. However, the host interface may also be a vendor-specific communication interface or communication fabric. GPGPU 700 receives commands from the host processor and uses a global scheduler 704 to distribute the execution threads associated with those commands to a set of compute clusters 706A to 706H. Computing clusters 706A to 706H share a cache memory 708. Cache memory 708 may serve as a high-level cache within the cache memory within compute clusters 706A to 706H.

[0157] GPGPU 700 includes memory 714A-714B, which is coupled to compute clusters 706A-H via a set of memory controllers 712A-712B. In various embodiments, memory 714A-714B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory (GRAM), such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, memory units 224A-224N may also include 3D stacked memory, including, but not limited to, high bandwidth memory (HBM).

[0158] In one embodiment, each computing cluster 706A to 706H includes a set of graphics multiprocessors, such as Figure 4A The graphics multiprocessor 400 of the compute cluster includes multiple types of integer and floating-point logic units that can perform computational operations at a range of precisions, including precisions suitable for machine learning computations. For example, and in one embodiment, at least a subset of the floating-point units of each of the compute clusters 706A-H can be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units can be configured to perform 64-bit floating-point operations.

[0159] Multiple instances of GPGPU 700 can be configured to operate as a computing cluster. The communication mechanisms used by the computing cluster for synchronization and data exchange vary across embodiments. In one embodiment, multiple instances of GPGPU 700 communicate via a host interface 702. In one embodiment, GPGPU 700 includes an I / O hub 708 that couples GPGPU 700 to a GPU link 710, which enables direct connections to other instances of the GPGPU. In one embodiment, GPU link 710 is coupled to a dedicated GPU-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 700. In one embodiment, GPU link 710 is coupled to a high-speed interconnect for transmitting and receiving data to and from other GPGPUs or parallel processors. In one embodiment, multiple instances of GPGPU 700 are located in separate data processing systems and communicate via a network device accessible via host interface 702. In one embodiment, GPU link 710 can also be configured to enable connection to a host processor in addition to or as an alternative to host interface 702.

[0160] While the illustrated configuration of GPGPU 700 can be configured to train neural networks, one embodiment provides an alternative configuration of GPGPU 700 that can be configured for deployment within a high-performance or low-power inference platform. In the inference configuration, GPGPU 700 includes fewer compute clusters 706A-H relative to the training configuration. Additionally, the memory technology associated with memories 714A-714B can differ between the inference and training configurations. In one embodiment, the inference configuration of GPGPU 700 can support inference-specific instructions. For example, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which are commonly used during inference operations for deployed neural networks.

[0161] Figure 8 A multi-GPU computing system 800 according to an embodiment is shown. The multi-GPU computing system 800 may include a processor 802 coupled to a plurality of GPGPUs 806A to D via a host interface switch 804. In one embodiment, the host interface switch 804 is a PCI Express switch device that couples the processor 802 to a PCI Express bus, through which the processor 802 can communicate with the set of GPGPUs 806A to D. Each of the plurality of GPGPUs 806A to 806D may be a Figure 7GPGPU 700. GPGPUs 806A to D may be interconnected via a set of high-speed point-to-point GPU-GPU links 816. The high-speed GPU-GPU links may be connected via dedicated GPU links (e.g., Figure 7 806D. A P2P GPU link 816 enables direct communication between each of the GPGPUs 806A-806D, without requiring communication via a host interface bus (to which the processor 802 is connected). While GPU-GPU traffic is directed to the P2P GPU link, the host interface bus can still be used for system memory access or communication with other instances of the multi-GPU computing system 800 (e.g., via one or more network devices). While GPGPUs 806A-D are connected to the processor 802 via the host interface switch 804 in the illustrated embodiment, in one embodiment, the processor 802 includes direct support for the P2P GPU link 816 and can connect directly to the GPGPUs 806A-806D.

[0162] Machine Learning Neural Network Implementation

[0163] The computing architecture provided by the embodiments described herein can be configured to perform these types of parallel processing that are particularly well-suited for training and deploying neural networks for machine learning. A neural network can be generalized as a network of functions with graph relationships. As is well known in the art, there are many types of neural network implementations used in machine learning. One exemplary type of neural network is a feedforward network as previously described.

[0164] A second exemplary type of neural network is a convolutional neural network (CNN). A CNN is a specialized feedforward neural network designed to process data with a known, grid-like topology (e.g., image data). CNNs are therefore commonly used in computer vision and image recognition applications, but they can also be used for other types of pattern recognition, such as speech and language processing. The nodes in the input layer of a CNN are organized into a set of "filters" (feature detectors inspired by the receptive fields found in the retina), and the output of each set of filters is propagated to nodes in successive layers of the network. The computations used in a CNN involve applying a mathematical operation called convolution to each filter to produce its output. Convolution is a specialized mathematical operation performed by two functions to produce a third function that is a modified version of one of the two original functions. In convolutional network terminology, the first function involved in the convolution can be called the input, while the second function can be called the convolution kernel. The output can be called a feature map. For example, the input to a convolutional layer can be a multidimensional data array that defines the various color components of the input image. The convolution kernel can be a multidimensional parameter array, where the parameters are adapted through a training process for the neural network.

[0165] Recurrent neural networks (RNNs) are a type of feedforward neural network that includes feedback connections between layers. RNNs enable modeling of sequence data by sharing parameter data across different parts of the neural network. The architecture of RNNs includes loops. These loops represent the effect of the current value of a variable on its own value at future times, as at least a portion of the output data from the RNN is used as feedback for processing subsequent inputs in the sequence. This feature makes RNNs particularly useful for language processing due to the mutable nature of language data, which can be composed.

[0166] The figures described below present exemplary feedforward, CNN, and RNN networks, and describe the general process for training and deploying each of those types of networks, respectively. It will be understood that these descriptions are exemplary and non-limiting with respect to any particular embodiment described herein, and that the concepts presented can generally be applied to deep neural networks and machine learning techniques in general.

[0167] The exemplary neural network described above can be used to perform deep learning. Deep learning is machine learning performed using deep neural networks. In contrast to shallow neural networks that include only a single hidden layer, deep neural networks used in deep learning are artificial neural networks composed of multiple hidden layers. Deeper neural networks are generally more computationally intensive to train. However, the additional hidden layers of the network enable multi-step pattern recognition, which results in reduced output error compared to shallow machine learning techniques.

[0168] The deep neural networks used in deep learning typically include a front-end network for performing feature recognition coupled to a back-end network representing a mathematical model that can perform operations (e.g., object classification, speech recognition, etc.) based on the feature representations provided to the model. Deep learning enables machine learning to be performed without the need to perform manual feature engineering for the model. Instead, deep neural networks can learn features based on statistical structures or correlations within the input data. The learned features can be provided to a mathematical model that can map the detected features to an output. The mathematical model used by the network is typically dedicated to a specific task to be performed, and different models will be used to perform different tasks.

[0169] Once a neural network is structured, a learning model can be applied to the network to train it to perform a specific task. The learning model describes how to adjust the weights within the model to reduce the network's output error. Backpropagation of error is a common method for training neural networks. An input vector is presented to the network for processing. The network's output is compared to the desired output using a loss function, and an error value is calculated for each neuron in the output layer. These error values ​​are then propagated backward until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then learn from those errors using an algorithm (such as stochastic gradient descent) to update the weights of the neural network.

[0170] Figure 9A 4 to B show exemplary convolutional neural networks. Figure 9A Show the various layers in CNN. Figure 9A As shown in , an exemplary CNN for modeling image processing can receive an input 902 that describes the red, green, and blue (RGB) components of an input image. The input 902 can be processed by multiple convolutional layers (e.g., convolutional layer 904, convolutional layer 906). Optionally, the outputs from the multiple convolutional layers can be processed by a set of fully connected layers 908. The neurons in the fully connected layers have full connections to all activation functions in the previous layer, as previously described for feedforward networks. The outputs from the fully connected layers 908 can be used to generate output results from the network. Matrix multiplication can be used instead of convolution to calculate the activation functions within the fully connected layers 908. Not all CNN implementations use fully connected layers 908. For example, in some implementations, the convolutional layers 906 can generate the output of the CNN.

[0171] The convolutional layers are sparsely connected, which is different from the traditional neural network configuration found in the fully connected layer 908. Traditional neural network layers are fully connected so that every output unit interacts with every input unit. However, the convolutional layers are sparsely connected because the output of the convolution of the receptive field (rather than the corresponding state value of each node in the receptive field) is input to the nodes of the subsequent layer, as shown. The kernel associated with the convolutional layer performs a convolution operation, the output of which is sent to the next layer. The dimensionality reduction performed within the convolutional layer is one aspect that enables CNNs to scale to process large images.

[0172] Figure 9B 1 shows exemplary computational stages within a convolutional layer of a CNN. Input 912 to a convolutional layer of the CNN can be processed in three stages within a convolutional layer 914. These three stages can include a convolution stage 916, a detector stage 918, and a pooling stage 920. Convolutional layer 914 can then output data to a subsequent convolutional layer. The last convolutional layer of the network can generate output feature map data or provide input to a fully connected layer, for example, to generate a classification value for the input to the CNN.

[0173] Several convolutions are performed in parallel in the convolution stage 916 to produce a set of linear activation functions. The convolution stage 916 may include an affine transformation, which is any transformation that can be specified as a linear transformation plus a translation. Affine transformations include rotations, translations, scaling, and combinations of these transformations. The convolution stage calculates the output of a function connected to a specific region in the input (e.g., a neuron), which can be determined as a local region associated with the neuron. The neuron calculates the dot product between the neuron's weight and the region in the local input (to which the neuron is connected). The output from the convolution stage 916 defines a set of linear activation functions that are processed by successive stages of the convolution layer 914.

[0174] The linear activation function can be processed by the detector stage 918. In the detector stage 918, each linear activation function is processed by a nonlinear activation function. The nonlinear activation function increases the nonlinear nature of the overall network without affecting the receptive field of the convolutional layer. Several types of nonlinear activation functions can be used. One specific type is the rectified linear unit (ReLU), which uses an activation function defined as f(x) = max(0, x), so that the activation function is thresholded to zero.

[0175] The pooling stage 920 uses a pooling function that replaces the output of the convolutional layer 906 with a summary statistic of nearby outputs. The pooling function can be used to introduce translation invariance into the neural network so that a slight translation to the input does not change the pooled output. The invariance of local translation can be useful when the presence of features in the input data is more important than the precise location of the features. Various types of pooling functions can be used during the pooling stage 920, including maximum pooling, average pooling, and L2 norm pooling. In addition, some CNN implementations do not include a pooling stage. Instead, such implementations use an additional convolution stage with an increased stride relative to the previous convolution stage.

[0176] The output from the convolutional layer 914 may then be processed by the next layer 922. The next layer 922 may be an additional convolutional layer or one of the fully connected layers 908. For example, Figure 9A The first convolutional layer 904 can output to the second convolutional layer 906, and the second convolutional layer can output to the first layer in the fully connected layer 908.

[0177] Figure 10 An exemplary recurrent neural network 1000 is shown. In a recurrent neural network (RNN), the network's previous state influences the output of the network's current state. RNNs can be built in a variety of ways using a variety of functions. The use of RNNs generally revolves around using mathematical models to predict the future based on previous input sequences. For example, RNNs can be used to perform statistical language modeling to predict upcoming words given a previous word sequence. The shown RNN 1000 can be described as having the following: an input layer 1002, which receives an input vector; a hidden layer 1004, which implements a recursive function; a feedback mechanism 1005, which implements a 'memory' of previous states; and an output layer 1006, which outputs a result. RNN 1000 operates based on time steps. The state of the RNN at a given time step is influenced by the previous time step via the feedback mechanism 1005. For a given time step, the state of the hidden layer 1004 is defined by the previous state and the input at the current time step. The initial input (x1) at the first time step can be processed by the hidden layer 1004. The second input (x2) can be processed by the hidden layer 1004 using the state information determined during the processing of the initial input (x1). The given state can be calculated as s t =f(Ux t +Ws t-1), where U and W are parameter matrices. Function f is typically nonlinear, such as a variant of the hyperbolic tangent function (Tanh) or a modified function f(x)=max(0,x). However, the specific mathematical function used in hidden layer 1004 may vary depending on the specific implementation details of RNN 1000.

[0178] In addition to the basic CNN and RNN networks described, variations of those networks can also be implemented. An example RNN variant is the long short-term memory (LSTM) RNN. LSTM RNNs are able to learn long-term dependencies that may be necessary to process longer language sequences. A variant of CNN is the convolutional deep belief network, which has a structure similar to a CNN and is trained in a manner similar to a deep belief network. A deep belief network (DBN) is a generative neural network composed of multiple layers of stochastic (random) variables. A DBN can be trained layer by layer using greedy unsupervised learning. The learned weights of the DBN can then be used to provide a pre-trained neural network by determining a set of optimal initial weights for the neural network.

[0179] Figure 11 Demonstrates the training and deployment of deep neural networks. Once a given network has been structured for a task, the neural network is trained using a training dataset 1102. Various training frameworks 1104 have been developed to enable hardware acceleration of the training process. For example, Figure 6 The machine learning framework 604 can be configured as a training framework 604. The training framework 604 can be hooked up to the untrained neural network 1106 and enable the untrained neural network to be trained to generate a trained neural network 1108 using the parallel processing resources described herein.

[0180] To start the training process, initial weights can be chosen randomly or by pre-training with a deep belief network. The training cycle is then performed in a supervised or unsupervised manner.

[0181] Supervised learning is a learning method in which training is performed as an arbitration operation, such as when the training dataset 1102 includes inputs paired with expected outputs for those inputs, or when the training dataset includes inputs with known outputs and the outputs of the neural network are manually graded. The network processes the inputs and compares the resulting outputs to a set of expected or desired outputs. Errors are then backpropagated through the system. The training framework 1104 can be adjusted to adjust the weights of the untrained neural network 1106. The training framework 1104 can provide tools for monitoring the extent to which the untrained neural network 1106 is converging to a model that is suitable for generating the correct answer based on the known input data. The training process occurs iteratively as the network's weights are adjusted to improve the outputs generated by the neural network. The training process can continue until the neural network reaches a statistically expected accuracy associated with the trained neural network 1108. The trained neural network 1108 can then be deployed to implement any number of machine learning operations.

[0182] Unsupervised learning is a learning method in which a network attempts to train itself using unlabeled data. Therefore, for unsupervised learning, the training data set 1102 will include input data without any associated output data. The untrained neural network 1106 can learn groupings within the unlabeled inputs and can determine how individual inputs relate to the overall data set. Unsupervised training can be used to generate self-organizing maps, which are a type of trained neural network 1107 that can perform operations useful in data dimensionality reduction. Unsupervised training can also be used to perform anomaly detection, which allows for the identification of data points in the input data set that deviate from the normal pattern of the data.

[0183] Variations of supervised and unsupervised training can also be employed. Semi-supervised learning is a technique in which the training dataset 1102 includes a mixture of labeled and unlabeled data from the same distribution. Incremental learning is a variant of supervised learning in which input data is continuously used to further train the model. Incremental learning enables a trained neural network 1108 to adapt to new data 1112 without forgetting the knowledge embedded in the network during initial training.

[0184] The training process for particularly deep neural networks, whether supervised or unsupervised, can be too computationally intensive for a single compute node. The training process can be accelerated by using a distributed network of compute nodes rather than a single compute node.

[0185] Figure 12is a block diagram illustrating distributed learning. Distributed learning is a training model that uses multiple distributed computing nodes to perform supervised or unsupervised training of a neural network. The distributed computing nodes may each include one or more host processors and one or more general processing nodes, such as Figure 7 700. As shown, distributed learning can perform model parallelism 1202, data parallelism 1204, or a combination of model and data parallelism 1204.

[0186] In model parallelism 1202, different computing nodes in a distributed system can perform training computations for different parts of a single network. For example, each layer of a neural network can be trained by a different processing node of the distributed system. Benefits of model parallelism include the ability to scale to extremely large models. Splitting the computations associated with different layers of a neural network enables training of very large neural networks, where the weights for all layers will not fit into the memory of a single computing node. In some instances, model parallelism can be particularly useful in performing unsupervised training of large neural networks.

[0187] In data parallelization 1204, different nodes of the distributed network have complete instances of the model, and each node receives a different portion of the data. The results from the different nodes are then combined. Although different methods for data parallelization are possible, data parallel training methods all require a technique for combining the results and synchronizing the model parameters between each node. Exemplary methods for combining data include parameter averaging and update-based data parallelization. Parameter averaging trains each node on a subset of the training data and sets global parameters (e.g., weights, biases) to the average value of the parameters from each node. Parameter averaging uses a central parameter server that maintains parameter data. Update-based data parallelism is similar to parameter averaging, except that updates to the model are passed instead of passing parameters from the node to the parameter server. In addition, update-based data parallelism can be performed in a decentralized manner, where updates are compressed and passed between nodes.

[0188] For example, combined model and data parallelism 1206 can be implemented in a distributed system where each compute node includes multiple GPUs. Each node can have a complete instance of the model, with separate GPUs within each node used to train different parts of the model.

[0189] Distributed training has increased overhead relative to training on a single machine. However, the parallel processors and GPGPUs described herein can each implement various techniques to reduce the overhead of distributed training, including techniques for enabling high-bandwidth GPU-GPU data transfer and accelerated remote data synchronization.

[0190] Example Machine Learning Applications

[0191] Machine learning can be applied to solve a variety of technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. Applications of computer vision range from reproducing human visual capabilities (e.g., recognizing faces) to creating new categories of visual capabilities. For example, a computer vision application can be configured to identify sound waves from vibrations induced in objects visible in a video. Parallel processor-accelerated machine learning enables the use of significantly larger training data sets than were previously feasible to train computer vision applications, and enables the deployment of inference systems using low-power parallel processors.

[0192] Parallel processor-accelerated machine learning has autonomous driving applications, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train driving models based on datasets that define appropriate responses to specific training inputs. The parallel processors described herein can enable rapid training of increasingly complex neural networks for autonomous driving solutions and enable the deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

[0193] Deep neural networks accelerated by parallel processors have enabled machine learning methods for automatic speech recognition (ASR). ASR involves creating a function that computes the most likely speech sequence given a sequence of input sounds. Accelerated machine learning using deep neural networks has replaced the hidden Markov models (HMMs) and Gaussian mixture models (GMMs) previously used for ASR.

[0194] Parallel processor-accelerated machine learning can also be used to accelerate natural language processing. Automatic learning programs can use statistical inference algorithms to generate models that are robust to erroneous or unfamiliar inputs. Exemplary natural language processor applications include automatic machine translation between human languages.

[0195] Parallel processing platforms for machine learning can be divided into training platforms and deployment platforms. Training platforms are typically highly parallel and include optimizations for accelerating multi-GPU single-node training and multi-node multi-GPU training. Exemplary parallel processors suitable for training include Figure 7 Highly parallel general purpose graphics processing unit 700 and Figure 8 The multi-GPU computing system 800 of FIG. In contrast, deployed machine learning platforms typically include low-power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

[0196] Figure 13 An exemplary inference system-on-chip (SOC) 1300 suitable for performing inference using a trained model is shown. The SOC 1300 can integrate multiple processing components, including a media processor 1302, a vision processor 1304, a GPGPU 1306, and a multi-core processor 1308. The SOC 1300 can further include on-chip memory 1305, which can implement a shared on-chip data pool accessible by each of the processing components. The processing components can be optimized for low-power operation to enable deployment to a variety of machine learning platforms (including autonomous vehicles and autonomous robots). For example, an implementation of the SOC 1300 can be used as part of a main control system for an autonomous vehicle. In the case where the SOC 1300 is configured for use in an autonomous vehicle, the SOC is designed and configured to comply with the relevant functional safety standards of the deployment jurisdiction.

[0197] During operation, the media processor 1302 and the visual processor 1304 can work in concert to accelerate computer vision operations. The media processor 1302 can enable low-latency decoding of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in the on-chip memory 1305. The visual processor 1304 can then parse the decoded video and perform preliminary processing operations on the frames of the decoded video to prepare for processing the frames using the trained image recognition model. For example, the visual processor 1304 can accelerate convolution operations for CNN (for performing image recognition on high-resolution video data), while the back-end model calculations are performed by the GPGPU 1306.

[0198] The multi-core processor 1308 may include control logic to facilitate sequencing and synchronization of data transfers and shared memory operations performed by the media processor 1302 and the vision processor 1304. The multi-core processor 1308 may also serve as an application processor for executing software applications that can utilize the inference computing capabilities of the GPGPU 1306. For example, at least a portion of navigation and driving logic may be implemented in software executing on the multi-core processor 1308. Such software may directly issue computational workloads to the GPGPU 1306, or may issue computational workloads to the multi-core processor 1308, which may offload at least a portion of those operations to the GPGPU 1306.

[0199] GPGPU 1306 may include a computational cluster, such as a low-power configuration of computational clusters 706A through 706H within a highly parallel general-purpose graphics processing unit 700. The computational cluster within GPGPU 1306 may support instructions that are explicitly optimized for performing inference computations on trained neural networks. For example, GPGPU 1306 may support instructions for performing low-precision computations (e.g., 8-bit and 4-bit integer vector operations).

[0200] Autonomous Vehicle Advanced Sensing and Response

[0201] Advanced vehicle systems can be coupled with machine learning techniques to enable semi-autonomous and autonomous driving within mainstream vehicles. To enhance the capabilities of autonomous vehicles, the embodiments described herein provide a variety of advanced sensing and computing capabilities. One embodiment provides autonomous post-crash response to vehicle collisions. One embodiment implements assisted search capabilities using automated sensing capabilities. One embodiment provides technology for minimizing accident damage in autonomous vehicles via internal vehicle sensors. One embodiment enables sharing of inferred data across autonomous vehicles. The embodiments described herein can each use one or more nearby vehicles for computing before, during, or after an autonomous driving session.

[0202] Autonomous driving systems must perform extensive computations to, for example, plan routes, identify and avoid pedestrians and obstacles, detect and understand traffic lights, crosswalks, and signs, and determine the movement of objects. These tasks are not only computationally intensive but must often be performed under real-time constraints. The embodiments described herein provide techniques that enable autonomous vehicles to utilize nearby vehicles within an autonomous vehicle network. This technique can be implemented as a lower-latency or higher-reliability alternative to cloud-based computing technologies.

[0203] Vehicle-to-vehicle communication technology can be used to enable vehicles to report information such as speed, location, and road incidents to nearby vehicles via ad hoc wireless networks. The embodiments described herein extend this communication capability to enable nearby vehicles to perform distributed computing operations, thereby obtaining faster or more reliable results than would be possible using computing resources within a single vehicle. In one embodiment, to perform particularly computationally intensive operations in the presence of a sufficiently fast wireless network, an autonomous vehicle can offload a subset of computing operations to a cloud-based computing system. However, if a sufficiently fast wide-area wireless network is unavailable or an urgent computing response is required, the vehicle can attempt to wirelessly connect to surrounding vehicles to temporarily establish a distributed computing network.

[0204] The Car-to-X Alliance, a network of automakers, has developed a vehicle communication standard that enables vehicles and fixed roadside devices to exchange information and warnings over ad hoc wireless networks, thereby improving driving safety. The embodiments described herein extend the Car-to-X communication standard to enable distributed functionality for autonomous vehicles with established trust relationships.

[0205] In one embodiment, autonomous vehicles in a trusting relationship can be configured to share computing resources when needed. A baseline level of computing power exists in each autonomous vehicle. However, situations may arise where a vehicle's autonomous driving system determines that computing resources may be required that exceed the vehicle's current computing resources or that the vehicle's computing resources cannot produce the desired results within a reasonable period of time. For example, situations may arise where an autonomous vehicle might normally rely on cloud-based computing resources, but these resources are temporarily unavailable due to poor mobile wireless network reception. The techniques for computational offloading described herein build on existing technologies for inter-vehicle communication. The security and privacy of these communication technologies are addressed at the underlying communication layer. Therefore, the existence of secure wireless communication protocols and methods for determining the trust status of neighbors is always assumed.

[0206] In one embodiment, autonomous vehicles connected to a local or cloud-based network can be configured to use external sensors to assist in the distributed search function. For example, a connected vehicle can be configured to receive data from a child abduction alert system or similar emergency broadcast system. The connected vehicle can then use the onboard cameras and sensors used for autonomous driving to passively search for the identified vehicle.

[0207] In one embodiment, inferred data generated by one connected vehicle can be shared with other nearby connected vehicles. For example, a lead vehicle in a group of multiple autonomous vehicles can share inferred determinations with other vehicles that may not have access to the lead vehicle's sensor field of view. If the lead vehicle determines that an obstacle exists or a hazardous event has occurred, the vehicle can share this determination with nearby connected vehicles.

[0208] While autonomous vehicles may include sensor arrays and navigation logic to avoid collisions, in some cases, collisions between autonomous vehicles may be unavoidable. One embodiment described herein can utilize both external and internal sensors on autonomous vehicles to minimize damage to vehicle occupants. In one embodiment, connected vehicles can share internal sensor data and, if one or more of the vehicles determines that an unavoidable collision is imminent, attempt to perform multiple damage minimization procedures.

[0209] In one embodiment, an autonomous vehicle that has been involved in a collision can be configured to perform autonomous responses to one or more post-crash scenarios. The post-crash responses can be configured to be based on internal and external sensor data collected before, during, and after the collision. Damage and injury assessments can be performed based on the collected sensor data, and a machine learning model can be trained to select from a variety of possible post-crash responses.

[0210] Computing and sensing for autonomous driving using multiple vehicles

[0211] Figure 14 A vehicle communication network 1400 is shown that can be used by embodiments described herein. Multiple autonomous vehicles, including public transportation vehicles 1416 and passenger vehicles 1418, can connect to a network (e.g., the Internet 1402) via multiple access points, including satellite-based access 1404 and / or mobile radio base stations 1406. Public transportation vehicles 1416 and passenger vehicles 1418 each include wireless network devices that can be configured to connect to a wide area network and a local area network within the vehicle. Access can also be available through one or more roadside wireless access points 1412A-1412B. Roadside wireless access points 1412A-1412B and mobile radio base stations 1406 can connect to access routers 1410A-1410B that can access the Internet 1402 or another wide area network. In addition, vehicle-to-infrastructure (V2I) communications may be available. The V2I system includes multiple fixed roadside computing nodes 1414A-1414B connected to the network and grid infrastructure.

[0212] V2I systems can participate in computational offloading in a similar manner to nearby autonomous vehicles.

[0213] The embodiments described herein provide benefits over and beyond conventional inter-vehicle and computation offloading systems by leveraging the ability of autonomous vehicles to coordinate autonomous driving and navigation functions. For example, where inter-vehicle computation offloading is desired, the ability for autonomous vehicles to coordinate navigation and destination data is part of the process of selecting among possible remote computation clients. When multiple autonomous vehicles share a common route, computation management logic associated with the vehicles can coordinate and determine the amount of time the vehicles will be within wireless communication range. Furthermore, vehicles with trusted computation arrangements can autonomously maneuver into a format that better enables wireless data sharing, as long as such maneuvers do not result in deviation from predetermined paths and navigation routes.

[0214] Figure 15 A distributed computing management system 1500 according to an embodiment is shown. In one embodiment, a set of computing workloads 1510 for an autonomous vehicle can be processed partially by a local computing manager 1520 and partially by a remote computing manager 1530. Local computing manager 1520 is a computing manager executed on the autonomous vehicle's computing infrastructure, for example, via a computing system that performs inference operations on machine learning models that implement autonomous driving and navigation. The computing units described herein that perform computing workloads can be any of the computing clusters, computing units, computing blocks, streaming multiprocessors, graphics multiprocessors, or general processing logic described herein. Local computing manager 1520 can facilitate local computing operations 1525 for a portion of computing workload 1510 while distributing a portion of computing workload 1510 to a remote computing system 1535 managed by a remote computing manager 1530 of a nearby trusted autonomous vehicle.

[0215] Local compute manager 1520 and remote compute manager 1530 may include a common or compatible computing infrastructure. Local compute manager 1520 includes a runtime management unit 1526, a trust module 1527, and a remote discovery unit 1528. Remote compute manager 1530 includes modules similar to or compatible with those of the local compute manager, including a runtime management unit 1536, a trust module 1537, a remote discovery unit 1538, or equivalent modules. Runtime management units 1526 and 1536 track the execution of computational workloads 1510 and are responsible for loading and unloading computational workloads onto the associated local or remote compute units. Trust modules 1527 and 1537 maintain identity tokens and certificates used to verify the authenticity of the computing environments of the local and remote autonomous vehicles. Trust module 1527 may also include keys or certificates used to sign or encrypt secure data transmitted between local compute manager 1520 and remote compute manager 1530. Remote discovery units 1528, 1538 are used to discover and locate autonomous vehicles within wireless range that can participate in trusted computing sharing. The discovery task includes determining which autonomous vehicles can accept computing workload offloading and determining the group of autonomous vehicles that will accept the computing workload.

[0216] The local compute manager 1520 may execute offloading logic 1522, including a workload partitioning unit 1523 and a remote vehicle selection unit 1524. The offloading logic 1522 is configured to offload any of the available computational workloads 1510 to remote computing resources in response to an indication that the number of computational workloads exceeds local computing capacity. The workload partitioning unit 1523 may examine the computational workloads 1510 to determine whether any of the workloads depends on the output of any other workload within the computational workload 1510. Workloads with dependencies may be scheduled as units for local or remote execution. The remote vehicle selection unit 1524 is configured to determine which of one or more trusted autonomous vehicles within the wireless network have available computational resources and whether the latency to these vehicles is acceptable for the computational workload to be scheduled. The remote vehicle selection unit 1524 may receive periodic updates from the remote discovery unit 1528 and, based on various criteria, may select one or more available remote vehicles to offload the computational workload. In one embodiment, determining acceptable latency can be performed by measuring communication latency to the local autonomous vehicle, which determines whether the latency is below a target threshold selected based on the type of computation offload to be performed. For example, latency-sensitive computational operations, such as computations based on real-time sensory data, will have a lower latency threshold than less latency-sensitive computational operations, such as speculatively performing alternative route calculations based on updated traffic information.

[0217] The remote vehicle selection unit 1524 can use one or more of a variety of vehicle selection techniques to select a remote vehicle to which the computational workload will be offloaded. In various embodiments, the remote vehicle can be selected based on a random selection strategy, a selection strategy based on computing power, a selection strategy based on distance, or a multi-factor selection strategy using multiple selection strategies. The random selection strategy randomly selects a vehicle node and then calculates the number of computational workloads that can be executed. If the selected node will be able to complete one or more workloads, one or more workloads will be offloaded to the node. If the randomly selected node is unable to execute at least one workload, a different random node will be evaluated. A similar strategy can be implemented for a selection strategy based on computing power or a selection strategy based on distance, with the difference that the initial and subsequent selection of neighboring vehicles is based on the vehicle with the greatest available computing power or the vehicle closest to the local autonomous vehicle. The multi-factor selection strategy selects a vehicle node for offloading by considering multiple parameters of the alternative vehicle nodes.

[0218] In addition to the selection techniques described above, one embodiment described herein implements a navigation-based selection strategy. The navigation-based selection strategy considers the group of neighboring trusted autonomous vehicles and ranks the group of vehicles based on a common navigation destination or a common navigation route. Neighboring autonomous vehicles with a trust relationship can securely exchange navigation route and destination data. If one or more neighboring autonomous vehicles share a common destination or will travel along a common route for a certain period of time, the autonomous vehicles can establish a distributed computing relationship and offload computing workloads from each other during the common route. The navigation-based selection strategy adds an additional element of predictability to the relative motion of autonomous vehicles within the trusted network, allowing each local vehicle and remote vehicle to estimate when the other vehicle will enter and exit the local wireless communication range.

[0219] Connected autonomous vehicles that can connect to cloud-based data centers have access to significant computing power, at the expense of some latency due to the broadband wireless or satellite-based communication networks through which they communicate with the data centers. For workloads with high computational demands, connected autonomous vehicles can offload a portion of these workloads to the data centers via the communication network. However, situations may arise where autonomous vehicles lack access to cloud-based data centers. In such situations, the ability to establish trusted distributed computing connections to neighboring autonomous vehicles may be particularly advantageous.

[0220] Figure 16 The relationship between computing power and communication latency in a local autonomous vehicle 1602, as described herein, is shown in Figure 1600. In one embodiment, the local autonomous vehicle 1602 can connect to an autonomous vehicle cloud and data center 1606 via a wide-area communication network, such as a mobile wireless or satellite-based communication network. This connection enables the local autonomous vehicle 1602 to access increased computing power at the expense of increased communication latency. Alternatively, the local autonomous vehicle 1602 can access the computing resources of neighboring autonomous vehicles and roadside V2I computing nodes with reduced latency, although these computing resources will have reduced computing power relative to the autonomous vehicle cloud and data center 1606.

[0221] In one embodiment, computation offloading techniques are primarily optimized for situations where onboard computing resources are insufficient and cloud communication latency is excessive. The decision to offload computation to a neighboring trusted vehicle or to the cloud takes into account many factors, including the amount of computation to be performed and the communication latency from the local autonomous vehicle 1602 to the neighboring AV and V2I nodes 1604 or to the autonomous vehicle cloud and data center 1606.

[0222] Communication with neighboring AV and V2I nodes 1604 can use emerging technologies such as dedicated short-range communications (DSRC), which enable very high data transmission over short to medium ranges. DSRC can be used for data communications in the 5.725 GHz to 5.875 GHz industrial, scientific, and medical (ISM) radio frequency band. A DSRC system consists of a roadside unit and an onboard unit (OBU) with a transceiver and a transponder. The OBU is located in an autonomous vehicle, robot, and / or other machine that can communicate via the DSRC network.

[0223] Using technologies such as DSRC, vehicle-to-vehicle and V2I communication latency can often provide higher bandwidth and / or lower latency communications relative to communication links with cloud data centers, especially in situations where cloud connectivity is poor. For example, while heavy rain may halt or slow satellite internet connections, DSRC is not affected by extreme weather conditions. Furthermore, such conditions may be those where offloading computing power is most beneficial, as extreme weather can make autonomous driving tasks more challenging.

[0224] Figure 17 is a flow chart illustrating autonomous vehicle computation offloading logic 1700 according to an embodiment. In one embodiment, by Figure 15The autonomous vehicle compute offload logic 1700 is enabled by the offload logic 1522 in the autonomous vehicle. In one embodiment, the autonomous vehicle compute offload logic 1700 may determine that a computational workload is to be processed, as shown at block 1702. The autonomous vehicle compute offload logic 1700 may then determine whether the current cloud communication latency is acceptable or within an acceptable range, as shown at block 1703. If the current cloud communication latency is acceptable, the autonomous vehicle offload logic may dispatch at least a portion of the workload for processing via a remote data center, as shown at block 1704. However, if the cloud communication latency is unacceptable at block 1703, the autonomous vehicle compute offload logic 1700 may determine whether computational resources from neighboring vehicles are available and sufficient, as shown at block 1706. If the computational resources from neighboring vehicles are insufficient, the autonomous vehicle compute offload logic 1700 may use local resources to perform the computational operations, as shown at block 1705. If computational resources from neighboring vehicles are available and sufficient at block 1706, but communication latency to these vehicles is unacceptable at block 1708, then autonomous vehicle computation offload logic 1700 may utilize local resources for computation at block 1705. If communication latency is acceptable at block 1708, autonomous vehicle computation offload logic 1700 may dispatch at least a portion of the workload for processing on a neighboring autonomous vehicle or V2I node, as shown at block 1710. If only local resources are used for computation at block 1705, the capabilities of some autonomous vehicles may be limited or reduced, as shown at block 1707. For example, the maximum speed at which an autonomous vehicle can travel in fully autonomous mode may be reduced. Alternatively, the speed at which an autonomous vehicle can select an alternative route based on dynamic traffic conditions may be reduced.

[0225] In one embodiment, autonomous vehicles connected to a local or cloud-based network can be configured to use external sensors to assist in the distributed search function. For example, a connected vehicle can be configured to receive data from a child abduction alert system or similar emergency broadcast system. The connected vehicle can then use the onboard cameras and sensors used for autonomous driving to passively search for the identified vehicle.

[0226] Figure 18Demonstrates the use of autonomous vehicle sensors to assist in distributed search. In one embodiment, one or more autonomous vehicles can receive a descriptor via cloud-based, V2I, and / or neighboring autonomous vehicle networks. The descriptor identifies a search target 1802. Autonomous vehicles receiving the descriptor can initiate a background search task that passively analyzes sensor data received via external sensors (e.g., cameras, radar, lidar, etc.) used to enable the autonomous driving task. Any objects approaching the sensor detection area 1820, 1830 of the autonomous vehicle performing the search task can be classified to determine whether they match the details provided for the search target 1802. For example, a search descriptor can indicate that the search target has a specific license plate type or number. Alternatively, the descriptor for the search target 1802 can be a more general description of the vehicle, such as the make, model, and color. If a vehicle identified by the search target's descriptor enters the sensor detection area 1820, 1830 of a connected autonomous vehicle, the vehicle can send information, such as camera and sensor data, back to the initiator of the search. In one embodiment, a more general search can be enabled for search target 1802. For example, the autonomous vehicle can be configured to search for vehicles exhibiting unusual driving behavior, such as repeated unsafe lane changes or abrupt changes in vehicle speed. This data can be transmitted to relevant safety authorities in the area where the autonomous vehicle is traveling. This data can also be transmitted to nearby vehicles that are not within the detection area of ​​the vehicle's associated sensors.

[0227] Figure 19 1 shows distributed autonomous vehicle search logic 1900 according to an embodiment. In one embodiment, autonomous vehicle search logic 1900 can be executed as one of the computational workloads 1510 on the computational resources of the local autonomous vehicle, such as Figure 15 Search data and / or search workload can also be distributed to neighboring autonomous vehicles via short-range wireless networks.

[0228] In one embodiment, a computing node on an autonomous vehicle may receive a descriptor identifying a search target, as shown at block 1902. The descriptor may identify one or more of a make, model, color, or a specific digital identifier associated with the vehicle. The specific digital identifier of a vehicle includes, but is not limited to, a license plate number or a different identifier number, such as a public service vehicle identification number, a public transportation vehicle identification number, or a private transportation vehicle identification number. In one embodiment, the descriptor may identify a behavior pattern rather than a specific vehicle. For example, a search descriptor may specify a general search for erratic driving behavior. In one embodiment, the descriptor is received from a connected vehicle network. One embodiment is also configured to receive a search descriptor from an emergency broadcast system, such as a wireless emergency alert system.

[0229] In one embodiment, the descriptor may identify a search area where the search target is expected to be located. In such an embodiment, at block 1903, the computing node may reference the location data to determine whether the autonomous vehicle is within the defined search area. If the autonomous vehicle is not within the search area, the computing node may simply exit at block 1905. Alternatively, the computing node's search-related logic may enter a sleep state until a new descriptor is received at block 1902.

[0230] In one embodiment, if an autonomous vehicle is within the identified search area, the compute node may generate an instance of autonomous vehicle search logic 1900 in response to receiving the descriptor, as shown at block 1904. However, in some embodiments, autonomous vehicle search logic 1900 is generated and initialized during compute node startup and enters a sleep state until the descriptor is received. Autonomous vehicle search logic 1900 may then configure a work item for execution on the compute node to passively search for a vehicle or driving mode corresponding to the search descriptor, as shown at block 1906. If a search candidate matching the search descriptor is located, the configured work item may signal autonomous vehicle search logic 1900.

[0231] In one embodiment, autonomous vehicle search logic 1900 may propagate search data to any trusted neighboring autonomous vehicles or infrastructure vehicles that do not have the search descriptor. If a trusted autonomous vehicle or V2I node enters local wireless range, autonomous vehicle search logic 1900 may determine at block 1907 whether the neighboring autonomous vehicle or V2I node does not have the search descriptor data. Autonomous vehicle search logic 1900 may then transmit the search descriptor to a trusted neighboring autonomous vehicle or V2I node that does not have the search descriptor data at block 1908.

[0232] In one embodiment, the connected vehicles described herein can generally share inferred data with adjacent connected vehicles within a certain physical proximity. Inference sharing can be performed via a trusted short-range radio connection as described herein, including but not limited to a DSRC connection. Inference sharing can also be extended to autonomous drones, autonomous traffic robots, or any other machines capable of autonomous navigation via machine learning models beyond autonomous vehicles. In one embodiment, inference determinations performed based on real-time inputs are securely transmitted to adjacent autonomous vehicles as information notifications. Autonomous vehicles and / or machines within local wireless range can use the transmitted inference information to enhance local inference determinations based on local sensors. This information sharing can allow vehicles or machines to observe or notice surrounding hazards or conditions that cannot be directly detected by local sensors on these vehicles or machines.

[0233] Figure 20 Sharing inferred data between autonomous vehicles according to an embodiment is illustrated. In one embodiment, a group of multiple autonomous vehicles may include a lead vehicle 2010 and a trailing vehicle 2020, although the group may include more than two vehicles. One embodiment enables the group of multiple autonomous vehicles to connect via a secure wireless communication system, such as a Wi-Fi or DSRC connection. Lead vehicle 2010 has a sensor detection area 2004 that includes an area that may not be detectable by trailing vehicle 2020. When the inference module of lead vehicle 2010 detects the presence of an obstacle or hazardous event 2002 along the common path of the group of multiple autonomous vehicles, the inferred determination may be shared with all vehicles in the group, including trailing vehicle 2020.

[0234] Figure 21 is a flow chart illustrating inference sharing logic 2100 according to an embodiment. In one embodiment, as in Figure 15 In the example, the inference sharing logic 2100 can be one of the computational workloads 1510 executed on the local computation manager 1520 and can transmit inference information to the computational workload managed by the remote computation manager 1530. For example and in one embodiment, inference sharing is performed between autonomous vehicles through mutual offloading of computational workloads, which are configured to exchange inference data determined by corresponding local computational models for autonomous driving.

[0235] In one embodiment, the inference sharing logic 2100 may establish a secure wireless connection with an autonomous vehicle within physical proximity, as shown at block 2102. The inference sharing logic 2100 may then exchange trust information over the secure wireless connection to establish a trusted computing link with the autonomous vehicle, as shown at block 2104. The trust information may be identity tokens and certificates used to verify the authenticity of the computing environments of the local autonomous vehicle and the remote autonomous vehicle, and may be used by a trust module within each vehicle (e.g., a remote autonomous vehicle). Figure 15 The trust information may be maintained by the trust modules 1527 and 1537 in the autonomous vehicle. The trust information may enable the vehicles to establish a trusted distributed computing environment to enable data and workloads to be transferred between the computing environments of the vehicles. In one embodiment, after the trusted computing link is established within the autonomous vehicle, the inference sharing logic 2100 may exchange inference data processing programs between the autonomous vehicles, as shown at block 2106. Exchanging inference data processing programs may facilitate any data precision or format conversion that may be required during the exchange of inference information, for example, if the data models used by the various vehicles are not strictly compatible. Exchanging inference data processing programs between autonomous vehicles may be performed in a manner similar to offloading computing tasks between various vehicles. However, in one embodiment, the inference data exchange may be performed without the need to exchange inference data processing programs.

[0236] The inference sharing logic 2100 may then continue to perform general inference operations using the machine learning model during autonomous operation based on the local sensor data, as shown at block 2108. In parallel, the inference sharing logic 2100 may then transmit inferred determinations of obstacles or hazardous events detected by the local sensor data at block 2110 and / or receive inferred determinations of obstacles or hazardous events determined via remote sensor data at block 2112.

[0237] Minimizing damage in autonomous vehicle accidents via internal sensors

[0238] The autonomous vehicle, at least during autonomous operation, has full situational awareness of surrounding vehicles, to the extent that local or remote sensors can see or otherwise sense the autonomous vehicle's environment and the position, velocity, acceleration, and orientation of other nearby vehicles. In conventional autonomous vehicles, this capability is used to autonomously navigate between locations and to avoid collisions during navigation. However, if a scenario arises in which a machine learning model within the autonomous vehicle determines that a collision is unavoidable, the vehicle can autonomously maneuver to minimize the amount of damage (e.g., injury) to occupants resulting from the collision. If the autonomous vehicle determines that a collision is unavoidable, the vehicle can adjust its position and orientation within a permitted pre-crash timeframe to reduce the amount of force that will be applied to the occupants. For example, and in one embodiment, if the autonomous vehicle determines that a head-on collision is unavoidable, the vehicle can perform last-minute maneuvers to minimize damage by adjusting the angle at which the collision will occur. In one embodiment, the vehicle can autonomously perform one or more pre-crash activities, such as pre-inflating one or more airbags within the vehicle's passenger compartment, arming one or more damage control mechanisms within the vehicle's frame, and / or pre-inflating one or more external airbags of the autonomous vehicle. In one embodiment, the vehicle can utilize internal sensors to determine the position and orientation of the vehicle occupants. After knowing the position and orientation of the vehicle occupants, the autonomous vehicle can determine an ideal impact zone for a collision that minimizes potential damage to the vehicle occupants.

[0239] Figure 22An autonomous vehicle 2200 is shown configured to minimize damage from autonomous vehicle accidents via internal sensors, according to an embodiment. In one embodiment, autonomous vehicle 2200 includes front and rear exterior sensor detection areas 2204A-2204B for detecting other vehicles, obstacles, road signs, road markings, and other information useful for autonomous navigation. Autonomous vehicle 2200 may also include side sensor detection areas (not shown) for detecting the presence of other vehicles or obstacles (e.g., guardrails, etc.) located on either side of the vehicle. Autonomous vehicle 2200 includes a set of interior sensors 2206 for determining the location of each vehicle occupant. Interior sensors 2206 may include various sensors, including proximity sensors and / or seat sensors that can be used to determine which seats within the vehicle are occupied. Based on this sensor data, autonomous vehicle 2200 can maintain a map of occupied locations within the vehicle. If passengers move around within the vehicle during autonomous driving mode, the vehicle can periodically update this map. Using internal sensors 2206, autonomous vehicle 2200 can determine an ideal impact zone 2202 for the vehicle so that, if a collision occurs, minimal harm will be inflicted on the occupants. For example, ideal impact zone 2202 can be an unoccupied area of ​​the vehicle. Although autonomous vehicle 2200 will attempt to avoid collisions with other vehicles or objects, if the vehicle determines that a collision is unavoidable, for example due to the actions of another vehicle or an uncontrollable loss of traction, the vehicle can autonomously maneuver to a position that accepts a collision within ideal impact zone 2202.

[0240] In addition to maneuvering or attempting to maneuver to receive the unavoidable collision in the ideal impact zone 2202, autonomous vehicle 2200 may initiate one or more collision mitigation mechanisms. Collision mitigation mechanisms may include pre-inflating internal and / or external airbags prior to the collision, activating seatbelt pretensioners, and engaging any structural damage mitigation systems that may be present within the vehicle.

[0241] Figure 232 is a flow chart illustrating collision avoidance and mitigation logic 2300 according to an embodiment. In one embodiment, collision avoidance and mitigation logic 2300 may determine a set of occupied locations within an autonomous vehicle via a set of internal sensors, as shown at block 2302. Based on the set of occupied locations, collision avoidance and mitigation logic 2300 may determine an ideal impact zone for the vehicle, as shown at block 2304. In one embodiment, the ideal impact location is a location within the vehicle that is not occupied by a passenger. Collision avoidance and mitigation logic 2300 may then implement autonomous navigation with collision avoidance, as shown at block 2306. In one embodiment, collision avoidance and mitigation logic 2300 may periodically update its assessment of occupied locations within the autonomous vehicle. Collision avoidance and mitigation logic 2300 may also update its assessment of occupied locations in response to detecting movement within the vehicle. If collision avoidance and mitigation logic 2300 detects a potential collision via external sensors at block 2308, collision avoidance and mitigation logic 2300 may determine whether the collision is avoidable at block 2309. If the collision is avoidable, the collision avoidance and mitigation logic 2300 may cause the autonomous vehicle to maneuver to avoid the collision at block 2310. If the collision is unavoidable, the collision avoidance and mitigation logic 2300 may initiate collision mitigation logic at block 2312. The collision mitigation logic may cause the vehicle to perform actions including adjusting the orientation of the vehicle so that the collision zone is within the desired impact zone and / or initiating any or all of the damage mitigation techniques described herein.

[0242] Autonomous response to post-crash scenarios

[0243] In one embodiment, an autonomous vehicle that has been involved in a collision can be configured to perform autonomous responses to one or more post-crash scenarios. The post-crash responses can be configured to be based on internal and external sensor data collected before, during, and after the collision. Damage and injury assessments can be performed based on the collected sensor data, and a machine learning model can be trained to select from a variety of possible post-crash responses.

[0244] Figure 24An autonomous post-crash system 2400 according to an embodiment is shown. The autonomous post-crash system 2400 includes a set of vehicle sensors 2420 for assessing the vehicle's condition after a collision. In one embodiment, the vehicle sensors 2420 include, but are not limited to, one or more cameras 2422, a gyroscope 2424, and a lidar 2426 that can be used to determine the vehicle's position, location, orientation, and local environment. The vehicle sensors 2420 may also include damage sensors 2428 and collision detection sensors 2430 and / or collision detection logic that can be activated in response to detecting a rapid deceleration of the vehicle consistent with a physical impact detected by the gyroscope 2424. The autonomous post-crash system 2400 may also include a set of occupant health monitoring sensors 2432, including interior cameras or sensors that can collect data for assessing occupant health in a post-crash scenario. For example, and in one embodiment, the autonomous post-crash system 2400 includes one or more interior infrared cameras that can be used to detect physiological distress signs among occupants of the autonomous vehicle after a vehicle collision.

[0245] Data from vehicle sensors 2420 and passenger health monitoring sensors 2432 can be provided to a machine learning framework 2240 executed on computing resources within the autonomous vehicle. The machine learning framework can provide input data to a machine learning model 2442, which can output an inferred crash response 2450. If possible, the inferred crash response 2450 can include a set of actions that the autonomous vehicle will automatically perform in response to the current post-crash scenario.

[0246] In one embodiment, based on passenger health and vehicle capabilities, the inferred crash response 2450 includes transmitting an accident report to relevant agencies, which may include national and / or local police organizations, insurance companies, and / or vehicle manufacturers. The accident report may be transmitted via Figure 14The accident report can be transmitted via the connected vehicle communication network 1400. The accident report can include vehicle telemetry immediately before, during, and after the collision, as well as any information that can be determined about other vehicles involved in the collision. For example, information about any other vehicles involved in the collision can be determined based on data collected by vehicle sensors 2420. Additionally, the accident report can include GPS coordinates or a map location of the accident. If the passenger health monitoring sensors detect a serious injury to a passenger, an automatic message can be sent to emergency services with the passenger's injury status and the accident location. In one embodiment, the autonomous post-crash system 2400 can attempt to obtain a verbal injury report from the passenger after the collision. The passenger's verbal injury report or an indication of no response can also be transmitted to emergency services. In one embodiment, additional components of the inferred crash response 2450 can include collecting and transmitting sensor data about the vehicle's immediate environment, including sensor images of environmental hazards, such as road obstacles that could cause a collision. In one embodiment, the inferred crash response 2450 can also include automatically contacting any emergency contacts that may be configured for vehicle occupants.

[0247] Figure 25 Details of autonomous post-crash logic 2500 according to an embodiment are shown. Autonomous post-crash logic 2500 may execute on the computing resources described herein and may be initiated in response to a detected collision. In response to the detected collision, autonomous post-crash logic 2500 may compile an accident report based on sensor data, as shown at block 2502. In one embodiment, the extent of damage detected by autonomous post-crash logic 2500 determines the extent of the response. At block 2504, autonomous post-crash logic 2500 may determine the severity of the damage or injury based on the details of the injury report. In one embodiment, the accident report also includes information collected via a request for verbal status from any occupants who were inside the vehicle during the collision. However, in some embodiments, autonomous post-crash logic 2500 may be implemented following a collision in an unoccupied autonomous freight vehicle. In such a system, no occupants are expected to be injured.

[0248] If the autonomous post-crash logic 2500 determines at block 2505 that significant vehicle damage has occurred or any occupant has been injured, the autonomous post-crash logic 2500 may transmit an accident report to appropriate emergency services at the location, as shown at block 2506. The accident report may be transmitted via the vehicle network described herein or via conventional mobile wireless communication technology. Once the accident report has been transmitted, at block 2508, the autonomous post-crash logic 2500 may access any available post-crash safety features. Post-crash safety features may include hazard or warning lights. In one embodiment, the autonomous post-crash logic 2500 may also disconnect the main vehicle power while maintaining auxiliary power for computing resources. For electric vehicles, this may include disconnecting power to the main electric drive motor. For autonomous internal combustion vehicles, the main internal combustion engine may be automatically disabled. In one embodiment, one or more vehicle doors may be automatically unlocked.

[0249] In one embodiment, if the autonomous post-crash logic 2500 determines at block 2505 that no serious vehicle damage or passenger injury has occurred, the logic may bypass transmitting an incident report to emergency services. Instead, the autonomous post-crash logic 2500 may determine at block 2507 whether the vehicle has moved since the collision. This determination of vehicle mobility may be performed based on damage sensors within the vehicle that can determine the vehicle's operating state. If the autonomous post-crash logic 2500 determines at block 2507 that the vehicle is moving, the logic may autonomously maneuver the vehicle to a nearby safe location at block 2509. For example, the autonomous post-crash logic 2500 may autonomously maneuver the vehicle to the side of the road and out of the flow of traffic. In one embodiment, the vehicle may autonomously maneuver only if the maneuver can be performed without causing injury to passengers or nearby pedestrians or bystanders. If the autonomous post-crash logic 2500 determines at block 2507 that the vehicle is not moving, the logic may engage the post-crash safety features described herein at block 2508. In each scenario, in one embodiment, the autonomous post-crash logic 2500 may transmit an accident report to the vehicle manufacturer, as shown at block 2510. In one embodiment, the accident report transmitted to the vehicle manufacturer is primarily vehicle-centric and focuses on pre-crash telemetry and post-crash telemetry. Such a report may be stripped of certain personal information prior to transmission.

[0250] Additional Exemplary Graphics Processing Systems

[0251] Details of the embodiments described above may be included in the graphics processing systems and apparatus described below. Figures 26 to 39 The graphics processing systems and devices of exemplify alternative systems and graphics processing hardware that can implement any and all of the techniques described above.

[0252] Additional Exemplary Graphics Processing System Overview

[0253] Figure 26 26 is a block diagram of a processing system 2600 according to an embodiment. In various embodiments, system 2600 includes one or more processors 2602 and one or more graphics processors 2608, and can be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 2602 or processor cores 2607. In one embodiment, system 2600 is a processing platform incorporated into a system-on-chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device.

[0254] Embodiments of system 2600 may include or be incorporated into a server-based game platform, a game console, including a game and media console, a mobile game console, a handheld game console, or an online game console. In some embodiments, system 2600 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. Data processing system 2600 may also include a wearable device (such as a smart watch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device), be coupled to the wearable device, or be integrated into the wearable device. In some embodiments, data processing system 2600 is a television or set-top box device having one or more processors 2602 and a graphical interface generated by one or more graphics processors 2608.

[0255] In some embodiments, one or more processors 2602 each include one or more processor cores 2607 for processing instructions that, when executed, perform operations of the system and user software. In some embodiments, each processor core in the one or more processor cores 2607 is configured to process a specific instruction set 2609. In some embodiments, the instruction set 2609 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). Multiple processor cores 2607 can each process a different instruction set 2609, which may include instructions for facilitating emulation of other instruction sets. The processor cores 2607 may also include other processing devices, such as a digital signal processor (DSP).

[0256] In some embodiments, the processor 2602 includes a cache memory 2604. Depending on the architecture, the processor 2602 may have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among the components of the processor 2602. In some embodiments, the processor 2602 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), and known cache coherence techniques may be used to share the external cache among the processor cores 2607. Additionally, a register file 2606 is included in the processor 2602, which may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general purpose registers, while other registers may be specific to the design of the processor 2602.

[0257] In some embodiments, processor 2602 is coupled to a processor bus 2610, which is used to transmit communication signals, such as address, data, or control signals, between processor 2602 and other components within system 2600. In one embodiment, system 2600 uses an exemplary 'hub' system architecture, including a memory controller hub 2616 and an input / output (I / O) controller hub 2630. Memory controller hub 2616 facilitates communication between memory devices and other components of system 2600, while I / O controller hub (ICH) 2630 provides connectivity to I / O devices via a local I / O bus. In one embodiment, the logic of memory controller hub 2616 is integrated within the processor.

[0258] Memory device 2620 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device with suitable performance for use as processing memory. In one embodiment, memory device 2620 may operate as system memory for system 2600 to store data 2622 and instructions 2621 for use when one or more processors 2602 execute applications or processes. Memory controller hub 2616 is also coupled to an optional external graphics processor 2612, which may communicate with one or more graphics processors 2608 in processor 2602 to perform graphics and media operations.

[0259] In some embodiments, the ICH 2630 connects peripheral components to the memory device 2620 and the processor 2602 via a high-speed I / O bus. I / O peripherals include, but are not limited to, an audio controller 2646, a firmware interface 2628, a wireless transceiver 2626 (e.g., Wi-Fi, Bluetooth), a data storage device 2624 (e.g., a hard drive, flash memory, etc.), and a legacy I / O controller 2640 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. One or more Universal Serial Bus (USB) controllers 2642 connect multiple input devices, such as a keyboard and mouse 2644 combination. A network controller 2634 may also be coupled to the ICH 2630. In some embodiments, a high-performance network controller (not shown) is coupled to the processor bus 2610. It should be understood that the illustrated system 2600 is exemplary and non-limiting, as other types of data processing systems configured in different ways may also be used. For example, the I / O controller hub 2630 may be integrated within one or more of the processors 2602 , or the memory controller hub 2616 and the I / O controller hub 2630 may be integrated within a discrete external graphics processor, such as the external graphics processor 2612 .

[0260] Figure 27 is a block diagram of an embodiment of a processor 2700 having one or more processor cores 2702A through 2702N, an integrated memory controller 2714 , and an integrated graphics processor 2708 . Figure 27 Those elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. The processor 2700 may include additional cores up to and including the additional core 2702N represented by the dashed box. The processor cores 2702A to 2702N each include one or more internal cache units 2704A to 2704N. In some embodiments, each processor core may also have access to one or more shared cache units 2706.

[0261] Internal cache units 2704A to 2704N and shared cache unit 2706 represent a cache memory hierarchy within processor 2700. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level of cache is classified as LLC before external memory. In some embodiments, cache coherence logic maintains coherence between each cache unit 2706 and 2704A to 2704N.

[0262] In some embodiments, the processor 2700 may further include a set of one or more bus controller units 2716 and a system agent core 2710. The one or more bus controller units 2716 manage a set of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, PCI Express). The system agent core 2710 provides management functions for various processor components. In some embodiments, the system agent core 2710 includes one or more integrated memory controllers 2714 for managing access to various external memory devices (not shown).

[0263] In some embodiments, one or more of the processor cores 2702A through 2702N include support for simultaneous multithreading. In such embodiments, the system agent core 2710 includes components for coordinating and operating the cores 2702A through 2702N during multithreaded processing. Additionally, the system agent core 2710 may include a power control unit (PCU) that includes logic and components for regulating the power state of the processor cores 2702A through 2702N and the graphics processor 2708.

[0264] In some embodiments, processor 2700 also includes a graphics processor 2708 for performing graphics processing operations. In some embodiments, graphics processor 2708 is coupled to a shared cache unit 2706 and a system agent core 2710, which includes one or more integrated memory controllers 2714. In some embodiments, a display controller 2711 is coupled to graphics processor 2708 to drive graphics processor output to one or more coupled displays. In some embodiments, display controller 2711 can be a separate module coupled to the graphics processor via at least one interconnect, or can be integrated within graphics processor 2708 or system agent core 2710.

[0265] In some embodiments, a ring-based interconnect 2712 is used to couple the internal components of the processor 2700. However, alternative interconnects may be used, such as point-to-point interconnects, switched interconnects, or other technologies, including those well known in the art. In some embodiments, the graphics processor 2708 is coupled to the ring interconnect 2712 via an I / O link 2713.

[0266] Exemplary I / O link 2713 represents at least one of a variety of I / O interconnects, including package I / O interconnects, that facilitate communication between various processor components and high-performance embedded memory modules 2718 (e.g., eDRAM modules). In some embodiments, each of processor cores 2702A through 2702N and graphics processor 2708 utilize embedded memory modules 2718 as a shared last-level cache.

[0267] In some embodiments, the processor cores 2702A to 2702N are homogeneous cores that execute the same instruction set architecture. In another embodiment, the processor cores 2702A to 2702N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more of the processor cores 2702A to 2702N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, the processor cores 2702A to 2702N are homogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In addition, the processor 2700 can be implemented on one or more chips or as a SoC integrated circuit having the components shown in addition to other components.

[0268] Figure 28 2 is a block diagram of a graphics processor 2800, which may be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates with memory via a mapped I / O interface to registers on the graphics processor and using commands placed in processor memory. In some embodiments, the graphics processor 2800 includes a memory interface 2814 for accessing memory. The memory interface 2814 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0269] In some embodiments, the graphics processor 2800 also includes a display controller 2802 for driving display output data to a display device 2820. The display controller 2802 includes hardware for one or more overlapping planes of the display and a composition of multiple layers of video or user interface elements. In some embodiments, the graphics processor 2800 includes a video codec engine 2806 for encoding, decoding, or transcoding media to, from, or between one or more media coding formats, including but not limited to: Moving Picture Experts Group (MPEG) (such as MPEG-2), Advanced Video Coding (AVC) format (such as H.264 / MPEG-4 AVC), and Society of Motion Picture & Television Engineers (SMPTE) 421M / VC-1, and Joint Photographic Experts Group (JPEG) format (such as JPEG and Motion JPEG (MJPEG) format).

[0270] In some embodiments, graphics processor 2800 includes a block image transfer (BLIT) engine 2804 for performing two-dimensional (2D) rasterizer operations, including, for example, bit-boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 2810. In some embodiments, GPE 2810 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0271] In some embodiments, GPE 2810 includes a 3D pipeline 2812 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that operate on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 2812 includes programmable and fixed functional elements that perform various tasks within components and / or spawned execution threads to 3D / media subsystem 2815. While 3D pipeline 2812 can be used to perform media operations, embodiments of GPE 2810 also include a media pipeline 2816 specifically for performing media operations, such as video post-processing and image enhancement.

[0272] In some embodiments, the media pipeline 2816 includes fixed-function or programmable logic units to perform one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration, instead of, or on behalf of, the video codec engine 2806. In some embodiments, the media pipeline 2816 also includes a thread generation unit to generate threads for execution on the 3D / media subsystem 2815. The generated threads perform calculations for media operations on one or more graphics execution units included in the 3D / media subsystem 2815.

[0273] In some embodiments, the 3D / media subsystem 2815 includes logic for executing threads generated by the 3D pipeline 2812 and the media pipeline 2816. In one embodiment, the pipelines send thread execution requests to the 3D / media subsystem 2815, which includes thread dispatch logic for arbitrating and dispatching each request to available thread execution resources. Execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, the 3D / media subsystem 2815 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) to share data between threads and to store output data.

[0274] Exemplary Additional Graphics Processing Engines

[0275] Figure 29 is a block diagram of a graphics processing engine 2910 of a graphics processor according to some embodiments. In one embodiment, the graphics processing engine (GPE) 2910 is Figure 28 A version of the GPE 2810 is shown. Figure 29 Elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. Figure 28 2812 and media pipeline 2816. The media pipeline 2816 is optional in some embodiments of the GPE 2910 and may not be explicitly included within the GPE 2910. For example and in at least one embodiment, separate media and / or graphics processors are coupled to the GPE 2910.

[0276] In some embodiments, GPE 2910 is coupled to or includes a command streamer 2903, which provides a command stream to 3D pipeline 2812 and / or media pipeline 2816. In some embodiments, command streamer 2903 is coupled to a memory, which may be system memory or one or more of internal cache memory and shared cache memory. In some embodiments, command streamer 2903 receives commands from memory and sends these commands to 3D pipeline 2812 and / or media pipeline 2816. The commands are instructions retrieved from a ring buffer storing commands for 3D pipeline 2812 and media pipeline 2816. In one embodiment, the ring buffer may also include a batch command buffer that stores multiple batches of commands. Commands for 3D pipeline 2812 may also include references to data stored in memory, such as, but not limited to, vertex and geometry data for 3D pipeline 2812 and / or image data and memory objects for media pipeline 2816. The 3D pipeline 2812 and the media pipeline 2816 process the commands by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to the execution unit array 2914 .

[0277] In various embodiments, the 3D pipeline 2812 can execute one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 2914. The graphics core array 2914 provides a unified block of execution resources. The multi-purpose execution logic (e.g., execution units) within the graphics core array 2914 includes support for various 3D API shader languages ​​and can execute multiple simultaneous execution threads associated with multiple shaders.

[0278] In some embodiments, the graphics core array 2914 also includes execution logic for performing media functions such as video and / or image processing. In one embodiment, in addition to graphics processing operations, the execution unit also includes general logic that can be programmed to perform parallel general computing operations. The general logic can be used with Figure 26 (multiple) processor cores 2607 or Figure 27 The general logic within cores 2702A to 2702N performs processing operations in parallel or in combination.

[0279] Output data generated by threads executing on graphics core array 2914 can be output to memory in unified return buffer (URB) 2918. URB 2918 can store data for multiple threads. In some embodiments, URB 2918 can be used to send data between different threads executing on graphics core array 2914. In some embodiments, URB 2918 can also be used for synchronization between threads on the graphics core array and fixed-function logic within shared function logic 2920.

[0280] In some embodiments, graphics core array 2914 is scalable such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of GPE 2910. In one embodiment, execution resources are dynamically scalable such that execution resources can be enabled or disabled as needed.

[0281] Graphics core array 2914 is coupled to shared function logic 2920, which includes a number of resources shared between the graphics cores in the graphics core array. Shared functions within shared function logic 2920 are hardware logic units that provide specialized, supplemental functionality to graphics core array 2914. In various embodiments, shared function logic 2920 includes, but is not limited to, sampler 2921, math 2922, and inter-thread communication (ITC) 2923 logic. Additionally, some embodiments implement one or more caches 2925 within shared function logic 2920. Shared functions are implemented when the demand for a given specialized function is insufficient to be included within graphics core array 2914. Instead, a single instance of the specialized function is implemented as a separate entity within shared function logic 2920 and shared among the execution resources within graphics core array 2914. The exact set of functions shared between and included within graphics core array 2914 varies between embodiments.

[0282] Figure 30 is a block diagram of another embodiment of a graphics processor 3000 . Figure 30 Those elements having the same reference numbers (or names) as elements in any other figures herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0283] In some embodiments, graphics processor 3000 includes ring interconnect 3002, pipeline front end 3004, media engine 3037, and graphics cores 3080A through 3080N. In some embodiments, ring interconnect 3002 couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of multiple processors integrated into a multi-core processing system.

[0284] In some embodiments, the graphics processor 3000 receives batches of commands via a ring interconnect 3002. The incoming commands are interpreted by a command streamer 3003 in a pipeline front end 3004. In some embodiments, the graphics processor 3000 includes scalable execution logic for performing 3D geometry processing and media processing via graphics core(s) 3080A through 3080N. For 3D geometry processing commands, the command streamer 3003 supplies the commands to a geometry pipeline 3036. For at least some media processing commands, the command streamer 3003 supplies the commands to a video front end 3034, which is coupled to a media engine 3037. In some embodiments, the media engine 3037 includes a video quality engine (VQE) 3030 for video and image post-processing and a multi-format encoding / decoding (MFX) 3033 engine for providing hardware-accelerated media data encoding and decoding. In some embodiments, the geometry pipeline 3036 and the media engine 3037 each generate execution threads for use with thread execution resources provided by at least one graphics core 3080A.

[0285] In some embodiments, the graphics processor 3000 includes scalable thread execution resource representation module cores 3080A through 3080N (sometimes referred to as core slices), each of which has multiple sub-cores 3050A through 3050N and 3060A through 3060N (sometimes referred to as core sub-slices). In some embodiments, the graphics processor 3000 may have any number of graphics cores 3080A through 3080N. In some embodiments, the graphics processor 3000 includes a graphics core 3080A having at least a first sub-core 3050A and a second sub-core 3060A. In other embodiments, the graphics processor is a low-power processor having a single sub-core (e.g., 3050A). In some embodiments, the graphics processor 3000 includes multiple graphics cores 3080A through 3080N, each of which includes a group of first sub-cores 3050A through 3050N and a group of second sub-cores 3060A through 3060N. Each sub-core in the set of first sub-cores 3050A to 3050N includes at least a first set of execution units 3052A to 3052N and a media / texture sampler 3054A to 3054N. Each sub-core in the set of second sub-cores 3060A to 3060N includes at least a second set of execution units 3062A to 3062N and a sampler 3064A to 3064N. In some embodiments, each sub-core 3050A to 3050N, 3060A to 3060N shares a set of shared resources 3070A to 3070N. In some embodiments, the shared resources include shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0286] Exemplary Additional Execution Units

[0287] Figure 31 Thread execution logic 3100 is shown, comprising an array of processing elements employed in some embodiments of a GPE. Figure 31 Those elements having the same reference numbers (or names) as elements in any other figures herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0288] In some embodiments, thread execution logic 3100 includes a shader processor 3102, a thread dispatcher 3104, an instruction cache 3106, a scalable execution unit array including a plurality of execution units 3108A to 3108N, a sampler 3110, a data cache 3112, and a data port 3114. In one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., execution units 3108A, 3108B, 3108C, 3108D, up to any one of 3108N-1 and 3108N) based on the computational requirements of the workload. In one embodiment, the included components are interconnected via an interconnect structure that links to each of the components. In some embodiments, thread execution logic 3100 includes one or more connections to a memory (e.g., system memory or cache memory) through the instruction cache 3106, the data port 3114, the sampler 3110, and one or more of the execution unit arrays 3108A to 3108N. In some embodiments, each execution unit (e.g., 3108A) is an independently programmable general-purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 3108A through 3108N is scalable to include any number of individual execution units.

[0289] In some embodiments, execution units 3108A to 3108N are primarily used to execute shader programs. Shader processor 3102 can process various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 3104. In one embodiment, thread dispatcher includes logic for arbitrating thread initiation requests from graphics and media pipelines and instantiating the requested threads on one or more execution units 3108A to 3108N. For example, the geometry pipeline (e.g., Figure 30 3036) can dispatch vertex processing, tessellation or geometry processing threads to thread execution logic 3100 ( Figure 31 In some embodiments, the thread dispatcher 3104 may also process runtime thread generation requests from executing shader programs.

[0290] In some embodiments, execution units 3108A to 3108N support instruction sets (including native support for many standard 3D graphics shader instructions) so that shader programs from graphics libraries (e.g., Direct3D and OpenGL) can be executed with minimal conversion. These execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general processing (e.g., compute and media shaders). Each of execution units 3108A to 3108N is capable of executing multiple-issue single instruction multiple data (SIMD), and multi-threaded operations can achieve an efficient execution environment when facing memory accesses with higher latency. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread state. For pipelines with integers, single-precision floating-point operations and double-precision floating-point operations, SIMD branching functions, logical operations, transcendental operations, and other miscellaneous operations, execution is multiple-issue per clock. When waiting for data from memory or one of the shared functions, dependency logic within execution units 3108A through 3108N causes the waiting thread to sleep until the requested data has returned. While the waiting thread is sleeping, hardware resources may be dedicated to processing other threads. For example, during the delay associated with vertex shader operations, the execution unit may execute operations of a pixel shader, a fragment shader, or another type of shader program that includes a different vertex shader.

[0291] Each execution unit in execution units 3108A through 3108N operates on an array of data elements. The number of data elements is the "execution size," or the number of lanes of an instruction. An execution lane is a logical unit that performs data element access, masking, and flow control within an instruction. The number of lanes may be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) for a particular graphics processor. In some embodiments, execution units 3108A through 3108N support integer and floating point data types.

[0292] The execution unit instruction set includes SIMD instructions. Various data elements can be stored in registers as compressed data types, and the execution unit will process various elements based on the data size of the element. For example, when operating on a 256-bit wide vector, the 256-bit vector is stored in a register, and the execution unit operates on the vector as four independent 64-bit compressed data elements (data elements of quadruple word length (QW) size), eight independent 32-bit compressed data elements (data elements of double word length (DW) size), sixteen independent 16-bit compressed data elements (data elements of word length (W) size), or thirty-two independent 8-bit data elements (data elements of byte (B) size). However, different vector widths and register sizes are possible.

[0293] One or more internal instruction caches (e.g., 3106) are included in the thread execution logic 3100 to cache thread instructions for the execution unit. In some embodiments, one or more data caches (e.g., 3112) are included to cache thread data during thread execution. In some embodiments, a sampler 3110 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 3110 includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to the execution unit.

[0294] During execution, the graphics and media pipeline sends a thread initiation request to the thread execution logic 3100 via thread generation and dispatch logic. Once a set of geometric objects has been processed and rasterized into pixel data, the pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 3102 is called to further calculate output information and cause the results to be written to the output surface (e.g., color buffer, depth buffer, stencil buffer, etc.). In some embodiments, the pixel shader or fragment shader calculates the value of each vertex attribute, which is interpolated across the rasterized object. In some embodiments, the pixel processor logic within the shader processor 3102 then executes the pixel or fragment shader program supplied by the application programming interface (API). To execute the shader program, the shader processor 3102 dispatches the thread to an execution unit (e.g., 3108A) via the thread dispatcher 3104. In some embodiments, the pixel shader 3102 uses the texture sampling logic in the sampler 3110 to access texture data in the texture map stored in the memory. Arithmetic operations on texture data and input geometry data compute pixel color data for each geometry fragment, or discard one or more pixels without further processing.

[0295] In some embodiments, data port 3114 provides a memory access mechanism for thread execution logic 3100 to output processed data to memory for processing on the graphics processor output pipeline. In some embodiments, data port 3114 includes or is coupled to one or more cache memories (e.g., data cache 3112) to cache data via the data port for memory access.

[0296] Figure 32 3 is a block diagram illustrating a graphics processor instruction format 3200 according to some embodiments. In one or more embodiments, a graphics processor execution unit supports an instruction set having instructions in multiple formats. Solid-line boxes illustrate components that are typically included in execution unit instructions, while dashed lines include optional components or components that are included only in a subset of instructions. In some embodiments, the instruction format 3200 described and illustrated are macroinstructions, as they are instructions supplied to the execution unit, as opposed to micro-operations generated from instruction decoding (once the instruction is processed).

[0297] In some embodiments, the graphics processor execution unit natively supports instructions using the 128-bit instruction format 3210. A 64-bit compact instruction format 3230 may be used for some instructions based on the selected instruction, multiple instruction options, and the number of operands. The native 128-bit instruction format 710 provides access to all instruction options, while some options and operations are restricted to the 64-bit format 3230. The native instructions available in the 64-bit format 3230 vary depending on the embodiment. In some embodiments, instructions are partially compressed using a set of index values ​​in the index field 3213. The execution unit hardware references a set of compression tables based on the index values ​​and uses the compression table output to reconstruct the native instruction using the 128-bit instruction format 3210.

[0298] For each format, the instruction opcode 3212 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a synchronous add operation across each color channel, where the color channel represents a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, the instruction control field 3214 enables control of certain execution options, such as channel selection (e.g., prediction) and data channel sorting (e.g., mixing). For instructions using the 128-bit instruction format 3210, the execution size field 3216 limits the number of data channels to be executed in parallel. In some embodiments, the execution size field 3216 is not available for the 64-bit compact instruction format 3230.

[0299] Some execution unit instructions have up to three operands, including two source operands (src0 3220, src1 3222) and a destination 3218. In some embodiments, the execution unit supports dual-destination instructions, where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., src2 3224), where the instruction opcode 3212 determines the number of source operands. The last source operand of an instruction may be an immediate (e.g., hard-coded) value passed with the instruction.

[0300] In some embodiments, the 128-bit instruction format 3210 includes an access / address mode field 3226. The access / address mode information specifies, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is provided directly by bits in the instruction.

[0301] In some embodiments, the 128-bit instruction format 3210 includes an access / address mode field 3226 that specifies the address mode and / or access mode of the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, wherein the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in the first mode, the instruction can use byte-aligned addressing for source operands and destination operands, and when in the second mode, the instruction can use 16-byte aligned addressing for all source operands and destination operands.

[0302] In one embodiment, the address mode portion of the access / address mode field 3226 determines whether the instruction uses direct or indirect addressing. When direct register addressing mode is used, bits in the instruction directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0303] In some embodiments, instructions are grouped based on the opcode 3212 bit field to simplify opcode decoding 3240. For 8-bit opcodes, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is exemplary only. In some embodiments, move and logic opcode group 3242 includes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, move and logic group 3242 shares five most significant bits (MSBs), wherein the move (mov) instruction adopts the form of 0000xxxxb, and the logic instruction adopts the form of 0001xxxxb. Flow control instruction group 3244 (e.g., call (call), jump (jmp)) includes instructions using the form of 0010xxxxb (e.g., 0x20). Miscellaneous instruction group 3246 includes a mixture of instructions, including synchronization instructions (e.g., wait (wait), send (send)) using the form of 0011xxxxb (e.g., 0x30). The parallel math instruction group 3248 includes component-wise arithmetic instructions (e.g., add, mul) in the form of 0100xxxxb (e.g., 0x40). The parallel math group 3248 performs arithmetic operations in parallel across data lanes. The vector math group 3250 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic operations on vector operands, such as dot products.

[0304] Example Additional Graphics Pipeline

[0305] Figure 33 is a block diagram of another embodiment of a graphics processor 3300 . Figure 33 Those elements having the same reference numbers (or names) as elements in any other figures herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0306] In some embodiments, graphics processor 3300 includes a graphics pipeline 3320, a media pipeline 3330, a display engine 3340, thread execution logic 3350, and a render output pipeline 3370. In some embodiments, graphics processor 3300 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or by commands issued to graphics processor 3300 via ring interconnect 3302. In some embodiments, ring interconnect 3302 couples graphics processor 3300 to other processing components, such as other graphics processors or general-purpose processors. Commands from ring interconnect 3302 are interpreted by command stream converter 3303, which supplies instructions to individual components of graphics pipeline 3320 or media pipeline 3330.

[0307] In some embodiments, command stream converter 3303 directs the operation of vertex fetcher 3305, which reads vertex data from memory and executes vertex processing commands provided by command stream converter 3303. In some embodiments, vertex fetcher 3305 provides vertex data to vertex shader 3307, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, vertex fetcher 3305 and vertex shader 3307 execute vertex processing instructions by dispatching execution threads to execution units 3352A and 3352B via thread dispatcher 3331.

[0308] In some embodiments, execution units 3352A-3352B are vector processor arrays with instruction sets for performing graphics and media operations. In some embodiments, execution units 3352A-3352B have an attached L1 cache 3351, which is dedicated to each array or shared between arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0309] In some embodiments, the graphics pipeline 3320 includes a tessellation component for performing hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader 811 configures the tessellation operations. A programmable domain shader 817 provides back-end evaluation of the tessellation output. The tessellator 3313 operates under the direction of the hull shader 3311 and contains dedicated logic for generating a detailed set of geometric objects based on a coarse geometric model that is provided as input to the graphics pipeline 3320. In some embodiments, the tessellation components (e.g., hull shader 3311, tessellator 3313, domain shader 3317) can be bypassed if tessellation is not used.

[0310] In some embodiments, the complete geometric object can be processed by the geometry shader 3319 via one or more threads dispatched to the execution units 3352A-3352B, or can proceed directly to the clipper 3329. In some embodiments, the geometry shader operates on entire geometric objects (rather than vertices or vertex patches as in previous stages of the graphics pipeline). If tessellation is disabled, the geometry shader 3319 receives input from the vertex shader 3307. In some embodiments, the geometry shader 3319 can be programmed by the geometry shader program to perform geometry tessellation when the tessellation unit is disabled.

[0311] Before rasterization, the clipper 3329 processes the vertex data. The clipper 3329 can be a fixed-function clipper or a programmable clipper with clipping and geometry shader functionality. In some embodiments, the rasterizer and depth test component 3373 in the render output pipeline 3370 dispatches a pixel shader to convert geometric objects into their per-pixel representation. In some embodiments, the pixel shader logic is included in the thread execution logic 3350. In some embodiments, the application can bypass the rasterizer and depth test component 3373 and access unrasterized vertex data via the outflow unit 3323.

[0312] The graphics processor 3300 has an interconnect bus, interconnect fabric, or some other interconnect mechanism that allows data and messages to be passed between the main components of the graphics processor. In some embodiments, execution units 3352A-3352B and associated cache(s) 3351, texture and media samplers 3354, and texture / sampler cache 3358 are interconnected via data ports 3356 to perform memory accesses and communicate with the processor's rendering output pipeline components. In some embodiments, samplers 3354, caches 3351, 3358, and execution units 3352A-3352B each have separate memory access paths.

[0313] In some embodiments, the render output pipeline 3370 includes a rasterizer and depth test component 3373, which converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / masker unit for performing fixed-function triangle and line rasterization. An associated render cache 3378 and depth cache 3379 are also available in some embodiments. A pixel operation component 3377 performs pixel-based operations on data, but in some instances, pixel operations associated with 2D operations (e.g., using mixed bit-block image transfer) are performed by the 2D engine 3341 or replaced by an overlapping display plane at display time by the display controller 3343. In some embodiments, a shared L3 cache 3375 can be used for all graphics components, allowing data to be shared without using main system memory.

[0314] In some embodiments, the graphics processor media pipeline 3330 includes a media engine 3337 and a video front end 3334. In some embodiments, the video front end 3334 receives pipeline commands from the command stream converter 3303. In some embodiments, the media pipeline 3330 includes a separate command stream converter. In some embodiments, the video front end 3334 processes the media commands before sending them to the media engine 3337. In some embodiments, the media engine 3337 includes thread generation functionality for generating threads for dispatching to the thread execution logic 3350 via the thread dispatcher 3331.

[0315] In some embodiments, graphics processor 3300 includes a display engine 3340. In some embodiments, display engine 3340 is external to processor 3300 and coupled to the graphics processor via ring interconnect 3302, or some other interconnect bus or mechanism. In some embodiments, display engine 3340 includes a 2D engine 3341 and a display controller 3343. In some embodiments, display engine 3340 includes dedicated logic capable of operating independently of the 3D pipeline. In some embodiments, display controller 3343 is coupled to a display device (not shown), which can be a system-integrated display device (such as in a laptop computer) or an external display device attached via a display device connector.

[0316] In certain embodiments, graphics pipeline 3320 and media pipeline 3330 can be configured to perform operations based on multiple graphics and media programming interfaces and are not dedicated to any application programming interface (API). In certain embodiments, the driver software of the graphics processor converts the API dispatch dedicated to specific graphics or media library into a command that can be processed by the graphics processor. In certain embodiments, support is provided for all open graphics libraries (OpenGL), open computing language (OpenCL) and / or Vulkan graphics and computing APIs from Khronos Group. In certain embodiments, support can also be provided for Microsoft's Direct3D library. In certain embodiments, the combination of these libraries can be supported. Support can also be provided for open source computer vision library (OpenCV). If a mapping from the pipeline of future API to the pipeline of graphics processor can be made, the future API with compatible 3D pipelines will also be supported.

[0317] Graphics pipeline programming

[0318] Figure 34A is a block diagram illustrating a graphics processor command format 3400 according to some embodiments. Figure 34B is a block diagram illustrating a graphics processor command sequence 3410 according to an embodiment. Figure 34A Solid-line boxes in show components that are typically included in a graphics command, while dashed lines include components that are optional or included only in a subset of the graphics commands. Figure 34A The exemplary graphics processor command format 3400 includes a data field for identifying the target client 3402 of the command, a command operation code (opcode) 3404, and associated data for the command 3406. Some commands also include a sub-opcode 3405 and a command size 3408.

[0319] In some embodiments, client 3402 defines a client unit of a graphics device that processes command data. In some embodiments, a graphics processor command parser examines the client field of each command to adjust further processing of the command and routes the command data to the appropriate client unit. In some embodiments, the graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing the command. Once the command is received by the client unit, the client unit reads the opcode 3404 and sub-opcode 3405 (if any) to determine the operation to be performed. The client unit uses the information in the data field 3406 to execute the command. For some commands, it is desired to explicitly define the size of the command by a command size 3408. In some embodiments, the command parser automatically determines the size of at least some of the commands based on the command opcode. In some embodiments, the commands are aligned via multiples of the double word length.

[0320] Figure 34B The flowchart in FIG. 34 illustrates an exemplary graphics processor command sequence 3410. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses a version of the illustrated command sequence to initiate, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for exemplary purposes only, as embodiments are not limited to these specific commands or command sequences. Furthermore, the commands may be issued as a batch of commands in a command sequence such that the graphics processor processes the command sequence at least partially simultaneously.

[0321] In some embodiments, graphics processor command sequence 3410 may begin with a pipeline flush command 3412 to cause any active graphics pipeline to complete currently pending commands for that pipeline. In some embodiments, 3D pipeline 3422 and media pipeline 3424 are not operating simultaneously. A pipeline flush is performed to allow the active graphics pipeline to complete any pending commands. In response to a pipeline flush, the command parser for the graphics processor will halt command processing until the active drawing engine completes pending operations and invalidates the associated read cache. Optionally, any data marked as 'dirty' in the render cache may be flushed to memory. In some embodiments, pipeline flush command 3412 may be used for pipeline synchronization or before placing the graphics processor into a low-power state.

[0322] In some embodiments, pipeline select command 3413 is used when a command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, pipeline select command 3413 is only required once in an execution context before issuing pipeline commands, unless the context is issuing commands for two pipelines. In some embodiments, pipeline flush command 3412 is required immediately before a pipeline switch via pipeline select command 3413.

[0323] In some embodiments, pipeline control commands 3414 configure the graphics pipeline for operation and are used to program 3D pipeline 3422 and media pipeline 3424. In some embodiments, pipeline control commands 3414 configure the pipeline state of the active pipeline. In one embodiment, pipeline control commands 3414 are used for pipeline synchronization and for flushing data from one or more cache memories within the active pipeline before processing a batch of commands.

[0324] In some embodiments, return buffer status commands 3416 are used to configure a set of return buffers for the corresponding pipeline to write data to. Some pipeline operations require allocating, selecting, or configuring one or more return buffers to which the operation writes intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, return buffer status 3416 includes selecting the size and number of return buffers to use for the set of pipeline operations.

[0325] The remaining commands in the command sequence differ based on the active pipeline for operation. Based on pipeline decision 3420 , the command sequence is tailored for either the 3D pipeline 3422 starting at 3D pipeline state 3430 or the media pipeline 3424 starting at media pipeline state 3440 .

[0326] The commands for 3D pipeline state 3430 include 3D state setup commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables to be configured before processing 3D primitive commands. The values ​​of these commands are determined at least in part based on the specific 3D API in use. In some embodiments, 3D pipeline state 3430 commands can also selectively disable or bypass specific pipeline elements if those elements are not to be used.

[0327] In some embodiments, the 3D primitive 3432 command is used to submit 3D primitives to be processed by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitive 3432 command are forwarded to the vertex acquisition function in the graphics pipeline. The vertex acquisition function uses the 3D primitive 3432 command data to generate multiple vertex data structures. The vertex data structures are stored in one or more return buffers. In some embodiments, the 3D primitive 3432 command is used to perform vertex operations on the 3D primitives via the vertex shader. To process the vertex shader, the 3D pipeline 3422 dispatches the shader execution thread to the graphics processor execution unit.

[0328] In some embodiments, the 3D pipeline 3422 is triggered via an execute 3434 command or event. In some embodiments, a register write triggers command execution. In some embodiments, execution is triggered via a 'go' or 'kick' command in a command sequence. In one embodiment, a pipeline synchronization command is used to trigger command execution in order to flush the command sequence through the graphics pipeline. The 3D pipeline performs geometry processing on the 3D primitives. Once the operation is completed, the generated geometric objects are rasterized, and the pixel engine shades the generated pixels. These operations may also include additional commands for controlling pixel shading and pixel backend operations.

[0329] In some embodiments, when performing media operations, a graphics processor command sequence 3410 follows the media pipeline 3424 path. Generally, the specific purpose and manner of programming the media pipeline 3424 depends on the media or computational operation to be performed. During media decoding, specific media decoding operations can be offloaded to the media pipeline. In some embodiments, the media pipeline can also be bypassed, and media decoding can be performed in whole or in part using resources provided by one or more general-purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processor unit (GPGPU) operations, wherein the graphics processor is configured to perform SIMD vector operations using compute shader programs that are not explicitly related to rendering graphics primitives.

[0330] In some embodiments, media pipeline 3424 is configured in a similar manner to 3D pipeline 3422. A set of commands for configuring media pipeline state 3440 is dispatched or placed into a command queue before media object commands 3442. In some embodiments, media pipeline state commands 3440 include data for configuring media pipeline elements that will be used to process media objects. This includes data for configuring video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. In some embodiments, media pipeline state commands 3440 also support the use of one or more pointers to "indirect" state elements that contain a batch of state settings.

[0331] In some embodiments, media object commands 3442 supply a pointer to a media object for processing by the media pipeline. The media object includes a memory buffer that contains video data to be processed. In some embodiments, all media pipeline states must be valid before issuing media object commands 3442. Once the pipeline state is configured and media object commands 3442 are queued, media pipeline 3424 is triggered via an execute 3444 command or an equivalent execution event (e.g., a register write). The output from media pipeline 3424 can then be post-processed by operations provided by 3D pipeline 3422 or media pipeline 3424. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0332] Graphics software architecture

[0333] Figure 35 An exemplary graphics software architecture for a data processing system 3500 according to some embodiments is shown. In some embodiments, the software architecture includes a 3D graphics application 3510, an operating system 3520, and at least one processor 3530. In some embodiments, processor 3530 includes a graphics processor 3532 and one or more general-purpose processor cores 3534. Graphics application 3510 and operating system 3520 each execute in system memory 3550 of the data processing system.

[0334] In some embodiments, the 3D graphics application 3510 includes one or more shader programs that include shader instructions 3512. The shader language instructions may be in a high-level shader language, such as High-Level Shader Language (HLSL) or OpenGL Shader Language (GLSL). The application also includes executable instructions 3514 in a machine language suitable for execution by the general-purpose processor core 3534. The application also includes graphics objects 3516 defined by vertex data.

[0335] In some embodiments, operating system 3520 is from Microsoft Corporation Operating system, dedicated UNIX-style operating system, or open source UNIX-style operating system using a Linux kernel variant. Operating system 3520 can support graphics API 3522, such as Direct3D API, OpenGL API or Vulkan API. When the Direct3D API is in use, operating system 3520 uses front-end shader compiler 3524 to compile any shader instruction 3512 in HLSL into a lower-level shader language. The compilation can be just-in-time (JIT) compilation, or the application can execute shader precompilation. In some embodiments, during the compilation of 3D graphics application 3510, high-level shaders are compiled into low-level shaders. In some embodiments, shader instructions 3512 are provided in an intermediate form, such as a version of the standard portable intermediate representation (SPIR) used by the Vulkan API.

[0336] In some embodiments, the user-mode graphics driver 3526 includes a back-end shader compiler 3527 that converts shader instructions 3512 into a hardware-specific representation. When using the OpenGL API, shader instructions 3512 in the GLSL high-level language are passed to the user-mode graphics driver 3526 for compilation. In some embodiments, the user-mode graphics driver 3526 uses operating system kernel-mode functions 3528 to communicate with the kernel-mode graphics driver 3529. In some embodiments, the kernel-mode graphics driver 3529 communicates with the graphics processor 3532 to dispatch commands and instructions.

[0337] IP core implementation

[0338] One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit, such as a processor. For example, a machine-readable medium may include instructions representing the various logic within the processor. When read by a machine, the instructions may cause the machine to manufacture logic for performing the techniques described herein. This type of representation (referred to as an "IP core") is a reusable unit of logic for an integrated circuit that can be stored on a tangible, machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model may be supplied to each consumer or manufacturing facility that loads the hardware model on a manufacturing machine that manufactures the integrated circuit. The integrated circuit may be manufactured so that the circuit performs the operations described in association with any of the embodiments described herein.

[0339] Figure 36 is a block diagram illustrating an IP core development system 3600 that can be used to manufacture integrated circuits to perform operations according to an embodiment. IP core development system 3600 can be used to generate modular, reusable designs that can be incorporated into larger designs or used to build entire integrated circuits (e.g., SoC integrated circuits). Design facilities 3630 can generate software simulations 3610 of the IP core design using high-level programming languages ​​(e.g., C / C++). Software simulations 3610 can be used to design, test, and verify the behavior of the IP core using simulation models 3612. Simulation models 3612 can include functional, behavioral, and / or timing simulations. Simulation models 3612 can then be used to create or synthesize register transfer level (RTL) designs 3615. RTL designs 3615 are abstractions of the behavior of the integrated circuit that model the flow of digital signals between hardware registers (including associated logic executed using the modeled digital signals). In addition to RTL designs 3615, lower-level designs at the logic or transistor levels can also be created, designed, or synthesized. Consequently, the specific details of the initial design and simulations can vary.

[0340] The RTL design 3615 or an equivalent solution can be further synthesized by the design facility into a hardware model 3620, which can be in hardware description language (HDL) or some other representation of physical design data. The HDL can be further simulated or tested to verify the IP core design. Non-volatile memory 3640 (e.g., a hard disk, flash memory, or any non-volatile storage medium) can be used to store the IP core design for delivery to a third-party manufacturing facility 3665. Alternatively, the IP core design can be transmitted (e.g., via the Internet) via a wired connection 3650 or a wireless connection 3660. The manufacturing facility 3665 can then manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit can be configured to perform operations according to at least one embodiment described herein.

[0341] Exemplary System-on-Chip Integrated Circuit

[0342] Figures 37 to 39 An exemplary integrated circuit and related graphics processor that can be manufactured using one or more IP cores according to various embodiments described herein are shown. In addition to what is shown, other logic and circuits may also be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0343] Figure 3737 is a block diagram illustrating an exemplary system-on-chip integrated circuit 3700 that can be manufactured using one or more IP cores according to an embodiment. The exemplary integrated circuit 3700 includes one or more application processors 3705 (e.g., CPUs), at least one graphics processor 3710, and may also include an image processor 3715 and / or a video processor 3720, any of which can be modular IP cores from the same or multiple different design facilities. The integrated circuit 3700 includes peripheral or bus logic, including a USB controller 3725, a UART controller 3730, an SPI / SDIO controller 3735, and an I / O controller. 2 S / I 2 The integrated circuit may also include a display device 3745 coupled to one or more of a High-Definition Multimedia Interface (HDMI) controller 3750 and a Mobile Industry Processor Interface (MIPI) display interface 3755. Storage may be provided by a flash memory subsystem 3760 (including flash memory and a flash memory controller). A memory interface may be provided via a memory controller 3765 to access SDRAM or SRAM memory devices. Some integrated circuits may also include an embedded security engine 3770.

[0344] Figure 38 is a block diagram illustrating an exemplary graphics processor 3810 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores according to an embodiment. The graphics processor 3810 may be Figure 37 The graphics processor 3810 includes a vertex processor 3805 and one or more fragment processors 3815A through 3815N (e.g., 3815A, 3815B, 3815C, 3815D, up to 3815N-1 and 3815N). The graphics processor 3810 can execute different shader programs via separate logic, such that the vertex processor 3805 is optimized to perform operations of the vertex shader program, while the one or more fragment processors 3815A through 3815N perform fragment (e.g., pixel) shading operations for the fragment or pixel shader program. The vertex processor 3805 executes the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. The fragment processor(s) 3815A through 3815N use the primitives and vertex data generated by the vertex processor 3805 to generate a frame buffer for display on the display device. In one embodiment, the fragment processor(s) 3815A through 3815N are optimized to execute fragment shader programs provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0345] In addition, the graphics processor 3810 also includes one or more memory management units (MMUs) 3820A-3820B, one or more caches 3825A-3825B, and (multiple) circuit interconnects 3830A-3830B. The one or more MMUs 3820A-3820B provide virtual-to-physical address mappings for the integrated circuit 3810, including for the vertex processor 3805 and / or one or more fragment processors 3815A-3815N, which can reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in the one or more caches 3825A-3825B. In one embodiment, the one or more MMUs 3825A-3825B can communicate with other MMUs within the system, including with Figure 37 The graphics processor 3810 may be synchronized with one or more MMUs associated with one or more application processors 3705, image processor 3715, and / or video processor 3720 so that each processor 3705 to 3720 may participate in a shared or unified virtual memory system. In accordance with an embodiment, one or more circuit interconnects 3830A to 3830B may enable the graphics processor 3810 to interact with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0346] Figure 39 is a block diagram illustrating an additional exemplary graphics processor 3910 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores in accordance with an embodiment. The graphics processor 3910 may be Figure 37 A variant of the graphics processor 3710. The graphics processor 3910 includes Figure 38 One or more MMUs 3820A-3820B, caches 3825A-3825B, and circuit interconnects 3830A-3830B of integrated circuit 3800.

[0347] The graphics processor 3910 includes one or more shader cores 3915A to 3915N (e.g., 3915A, 3915B, 3915C, 3915D, 3915E, 3915F, all the way to 3915N-1 and 3915N), which provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code, to implement vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present may vary in embodiments and implementations. In addition, the graphics processor 3910 also includes an inter-core task manager 3905 that acts as a thread dispatcher for dispatching execution threads to the one or more shader cores 3915A to 3915N and a tiling unit 3918 for accelerating tiling operations for tile-based rendering, in which rendering operations of a scene are subdivided in image space, for example to exploit local spatial coherence within the scene or to optimize the use of internal caches.

[0348] The following clauses and / or examples refer to specific embodiments or examples thereof. The details of the examples may be used anywhere in one or more embodiments. The various features of the different embodiments or examples can be combined in different ways to suit a variety of different applications, with some features included and other features excluded. Examples may include subject matter such as methods, devices for performing the actions of the methods, and at least one machine-readable medium including instructions that, when executed by a machine, cause the machine to perform the actions of the methods or the actions of an apparatus or system according to the embodiments and examples described herein. The various components may be devices for performing the described operations or functions.

[0349] One embodiment provides a computing device within an autonomous vehicle, the computing device comprising: a wireless network device for enabling a wireless data connection to an autonomous vehicle network; a plurality of processors, including a general-purpose processor and a general-purpose graphics processor, configured to execute a compute manager to manage execution of computational workloads associated with the autonomous vehicle, the computational workloads being associated with autonomous operation of the autonomous vehicle; and offload logic configured to execute on the plurality of processors, the offload logic configured to determine to offload one or more of the computational workloads to one or more autonomous vehicles within range of the wireless network device.

[0350] One embodiment provides a method for performing machine learning operations for an autonomous vehicle, the method comprising: determining a computational workload to be processed by a computing device of the autonomous vehicle; determining a first latency to a remote data center via an autonomous vehicle network; dispatching at least a first portion of the computational workload for processing via the remote data center when the first latency is below a threshold associated with the computational workload; determining a second latency to an autonomous vehicle within range of a wireless network device in response to determining that the first latency is above the threshold associated with the computational workload; and dispatching at least a second portion of the computational workload in response to determining that the second latency is below the threshold associated with the computational workload.

[0351] One embodiment provides an autonomous vehicle comprising: a wireless network device for enabling a wireless data connection to an autonomous vehicle network; a plurality of processors, including general purpose processors and general purpose graphics processors, for executing a compute manager to manage execution of computational workloads associated with the autonomous vehicle; and offload logic configured to execute on the plurality of processors, the offload logic for determining to offload one or more of the computational workloads to one or more autonomous vehicles within range of the wireless network device.

[0352] The embodiments described herein refer to specific configurations of hardware, such as an application-specific integrated circuit (ASIC) configured to perform certain operations or have predetermined functions. Such electronic devices typically include a group of one or more processors coupled to one or more other components (e.g., one or more storage devices (non-transitory machine-readable storage media), user input / output devices (e.g., keyboard, touch screen and / or display), and network connections). The coupling of the group of processors and other components is typically through one or more buses and bridges (also known as bus controllers). The storage devices and the signals carrying network traffic represent one or more machine-readable storage media and machine-readable communication media, respectively. Therefore, the storage device of a given electronic device typically stores code and / or data for execution on the one or more processors of the group of that electronic device.

[0353] Of course, different combinations of software, firmware and / or hardware can be used to implement one or more parts of the embodiment. Throughout this detailed description, for the purpose of explanation, a large amount of specific details have been set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present embodiment can be practiced without some of these specific details. In some cases, in order to avoid blurring the inventive subject matter of the embodiment, known structure and function are not described in detail. Therefore, the scope and spirit of the present invention should be determined according to the following claims.

Claims

1. A computing device within an autonomous vehicle, the computing device comprising: a wireless networking device for enabling a wireless data connection to an autonomous vehicle network; a plurality of processors, including a general purpose processor and a general purpose graphics processor, the plurality of processors configured to execute a compute manager to manage execution of a computational workload associated with the autonomous vehicle, the computational workload enabling autonomous driving and navigation; as well as offload logic configured to execute on the set of the plurality of processors, the offload logic for determining to offload one or more of the computing workloads to one or more autonomous vehicles within range of the wireless network device, or for determining to offload one or more of the computing workloads to a remote data center via the autonomous vehicle network, The offloading logic is used to determine, based on factors including computing demand and communication delay, whether to offload one or more of the computing workloads to one of the one or more autonomous vehicles within range of the wireless network device and to the remote data center via the autonomous vehicle network.

2. The computing device according to claim 1, wherein The offloading logic is used to: in response to a notification indicating that a computing workload is to be offloaded, determine whether a first delay to the remote data center is acceptable for the computing workload to be offloaded, and in response to determining that the first delay is within an acceptable range, offload the computing workload to the remote data center.

3. The computing device according to claim 1, wherein: The offload logic is to, in response to a notification indicating that a computational workload is to be offloaded, determine whether a second latency to one of the one or more autonomous vehicles within range of the wireless network device is acceptable, and offload the computational workload to the autonomous vehicle associated with the second latency.

4. The computing device according to claim 3, wherein: The offload logic is to determine, before the computational workload is offloaded to the autonomous vehicle associated with the second delay, whether computational resources available at the autonomous vehicle associated with the second delay are sufficient to process the computational workload to be offloaded.

5. The computing device according to any one of claims 1 to 4, wherein: The offload logic is configured to determine that a secure and trusted relationship exists between the one or more autonomous vehicles within range of the wireless network device before the offload logic is configured to determine to offload one or more of the computational workloads to the one or more autonomous vehicles.

6. The computing device according to any one of claims 1 to 4, wherein: The plurality of processors is configured to receive computational workload offloaded from adjacent autonomous vehicles.

7. The computing device according to claim 6, wherein: The plurality of processors receives sensor data from a set of connected sensors, and the computational workload offloaded from the neighboring autonomous vehicle includes search operations to be performed based on the received sensor data.

8. The computing device according to claim 7, wherein: The search operation includes locating a search target within a sensor detection area of ​​an autonomous vehicle sensor.

9. A method performed by a computing device within an autonomous vehicle, the method comprising: enabling a wireless data connection to an autonomous vehicle network by a wireless network device; executing a compute manager by a group of a plurality of processors including a general purpose processor and a general purpose graphics processor to manage execution of a computational workload associated with the autonomous vehicle, the computational workload enabling autonomous driving and navigation; as well as Offloading logic executed on the set of multiple processors determines to offload one or more of the computing workloads to one or more autonomous vehicles within range of the wireless network device, or to offload one or more of the computing workloads to a remote data center via the autonomous vehicle network, wherein the offloading logic is used to: determine to offload one or more of the computing workloads to one of the one or more autonomous vehicles within range of the wireless network device and to the remote data center via the autonomous vehicle network based on factors including computing demand and communication delay.

10. One or more machine-readable storage media having stored thereon instructions that, when executed by a computing device, configure the computing device to perform the method of claim 9.

11. A data processing system for an autonomous vehicle, the data processing system comprising means for executing the method according to claim 9.

12. An autonomous vehicle comprising: a wireless networking device for enabling a wireless data connection to an autonomous vehicle network; a plurality of processors, including a general purpose processor and a general purpose graphics processor, the plurality of processors configured to execute a compute manager to manage execution of a computational workload associated with the autonomous vehicle, the computational workload enabling autonomous driving and navigation; as well as offload logic configured to execute on the set of the plurality of processors, the offload logic for determining to offload one or more of the computing workloads to one or more autonomous vehicles within range of the wireless network device, or for determining to offload one or more of the computing workloads to a remote data center via the autonomous vehicle network, The offloading logic is used to determine, based on factors including computing demand and communication delay, whether to offload one or more of the computing workloads to one of the one or more autonomous vehicles within range of the wireless network device and to the remote data center via the autonomous vehicle network.

13. The autonomous vehicle of claim 12, wherein: The offloading logic is used to: in response to a notification indicating that a computing workload is to be offloaded, determine whether a first delay to the remote data center is acceptable for the computing workload to be offloaded, and in response to determining that the first delay is within an acceptable range, offload the computing workload to the remote data center.

14. The autonomous vehicle of claim 12, wherein: The offload logic is to, in response to a notification indicating that a computational workload is to be offloaded, determine whether a second latency to one of the one or more autonomous vehicles within range of the wireless network device is acceptable, and offload the computational workload to the autonomous vehicle associated with the second latency.

15. The autonomous vehicle of claim 14, wherein: The offload logic is to determine, before the computational workload is offloaded to the autonomous vehicle associated with the second delay, whether computational resources available at the autonomous vehicle associated with the second delay are sufficient to process the computational workload to be offloaded.

16. The autonomous vehicle according to any one of claims 12 to 15, characterized in that The offload logic is configured to determine that a secure and trusted relationship exists between the one or more autonomous vehicles within range of the wireless network device before the offload logic is configured to determine to offload one or more of the computational workloads to the one or more autonomous vehicles.

17. The autonomous vehicle according to any one of claims 12 to 15, characterized in that The plurality of processors is configured to receive computational workload offloaded from adjacent autonomous vehicles.

18. The autonomous vehicle of claim 17, wherein: The plurality of processors receives sensor data from a set of connected sensors, and the computational workload offloaded from the neighboring autonomous vehicle includes search operations to be performed based on the received sensor data.

19. The autonomous vehicle of claim 18, wherein: The search operation includes locating a search target within a sensor detection area of ​​an autonomous vehicle sensor.

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