Dedicated fixed-function hardware for efficient convolution

Abstract

One embodiment provides a computing device for performing machine learning operations, the device comprising a decoding unit for decoding a single instruction into a decoded instruction, the decoded instruction being used to perform one or more machine learning operations, wherein the decoding unit is used to request a scheduler to schedule the one or more machine learning operations to one of a programmable computing unit array and a fixed-function computing unit based on parameters of the one or more machine learning operations.

Description

Technical Field

[0001] Embodiments relate generally to data processing, and more particularly to data processing via a general purpose graphics processing unit. Background Art

[0002] Current parallel graphics data processing includes systems and methods developed for performing specific operations on graphics data, such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors have used fixed-function compute units to process graphics data; however, recently, portions of graphics processors have become programmable, enabling such processors to support a wider variety of operations for processing vertex and fragment data.

[0003] To further improve performance, graphics processors typically implement processing techniques (e.g., pipelining) that attempt to process as much graphics data in parallel as possible throughout different parts of the graphics pipeline. Parallel graphics processors with a single instruction multiple thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In a SIMT architecture, multiple groups of parallel threads attempt to execute program instructions together synchronously as often as possible to improve processing efficiency. A general overview of software and hardware for a SIMT architecture can be found in the following two: Shane Cook's CUDA Programming, Chapter 3, pages 37-51 (2013); and / or Nicholas Wilt's CUDA Manual (A Comprehensive Guide to GPU Programming), sections 2.6.2 to 3.1.2 (June 2013). BRIEF DESCRIPTION OF THE DRAWINGS

[0004] In order that the features of the present invention can be understood in detail, a more particular description of the present invention may be had by reference to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings only show typical embodiments and are therefore not to be considered as limiting the scope of all embodiments.

[0005] Figure 1 is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein;

[0006] FIG. 2A to FIG. 2D A parallel processor component according to an embodiment is shown;

[0007] FIG. 3A to FIG. 3B is a block diagram of a graphics multiprocessor according to an embodiment;

[0008] 4A to 4FAn exemplary architecture is presented in which multiple GPUs are communicatively coupled to multiple multi-core processors;

[0009] Figure 5 A graphics processing pipeline according to an embodiment is shown;

[0010] Figure 6 presenting a machine learning software stack according to an embodiment;

[0011] Figure 7 A highly parallel general purpose graphics processing unit according to an embodiment is presented;

[0012] Figure 8 A multi-GPU computing system according to an embodiment is presented;

[0013] FIG. 9A to FIG. 9B The layers of an exemplary deep neural network are shown;

[0014] Fig.10 An exemplary recurrent neural network is presented;

[0015] Fig.11 Demonstrated the training and deployment of deep neural networks;

[0016] Fig.12 is a block diagram showing distributed learning;

[0017] Fig.13 An exemplary inference system-on-chip (SOC) suitable for performing inference using a trained model is presented;

[0018] Fig.14 is a block diagram of a data processing system according to an embodiment;

[0019] Fig.15 Details of machine learning instructions and acquisition units according to an embodiment are shown;

[0020] Fig.16 An exemplary convolution operation according to an embodiment is shown;

[0021] Fig.17 is a flow chart of logic for selecting a convolution implementation according to an embodiment;

[0022] Fig.18 is a flow chart showing logic for selecting between general purpose logic and fixed function logic according to an embodiment;

[0023] Fig.19A shows a portion of a convolution operation according to an embodiment;

[0024] Fig.19B Fixed function matrix multiplication logic according to an embodiment is shown;

[0025] Fig. 20 Exemplary multiply-add logic 2001 within an embodiment is shown;

[0026] Fig.21 A 1×1 convolution is shown for the embodiments described herein;

[0027] Fig. 22 A circuit for performing a multiply-add operation on a compressed data vector according to an embodiment is shown;

[0028] Fig.23 Exemplary 1×1 convolution logic for implementing sequential 1×1 convolutions is shown.

[0029] Fig.24 is a block diagram of a processing system according to an embodiment.

[0030] Fig.25 is a block diagram of a processor according to an embodiment;

[0031] Fig.26 is a block diagram of a graphics processor according to an embodiment;

[0032] Fig. 27 is a block diagram of a graphics processing engine of a graphics processor according to some embodiments;

[0033] Fig.28 is a block diagram of a graphics processor provided by an additional embodiment;

[0034] Fig.29 Thread execution logic is shown, the thread execution logic including an array of processing elements employed in some embodiments;

[0035] Fig.30 is a block diagram illustrating a graphics processor instruction format according to some embodiments;

[0036] Fig.31 is a block diagram of a graphics processor according to another embodiment;

[0037] FIG. 32A to FIG. 32B A graphics processor command format and command sequence according to some embodiments are presented;

[0038] Fig.33 An exemplary graphics software architecture for a data processing system according to some embodiments is presented;

[0039] Fig.34 is a block diagram showing an IP core development system according to an embodiment;

[0040] Fig.35 is a block diagram illustrating an exemplary system-on-chip integrated circuit according to an embodiment;

[0041] Fig.36 is a block diagram illustrating an additional graphics processor according to an embodiment; and

[0042] Fig.37 is a block diagram illustrating an additional exemplary graphics processor of a system-on-chip integrated circuit according to an embodiment. DETAILED DESCRIPTION

[0043] In some embodiments, a graphics processing unit (GPU) is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to a host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU may be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of the manner in which the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuits / logic for efficiently processing these commands / instructions.

[0044] In the following description, many specific details are set forth to provide a more comprehensive understanding. However, it will be apparent to those skilled in the art that the embodiments described herein may be practiced without one or more of these specific details. In other instances, well-known features are not described to avoid obscuring the details of the present embodiment.

[0045] System Overview

[0046] Figure 11 is a block diagram illustrating a computer system 100 configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processors 102 and a system memory 104, the one or more processors and the system memory communicating via an interconnect path, which may include a memory hub 105. The memory hub 105 may be a separate component within a chipset component or may be integrated within one or more processors 102. The memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. The I / O subsystem 111 includes an I / O hub 107, which may enable the computing system 100 to receive input from one or more input devices 108. In addition, the I / O hub 107 may enable a display controller (which may be included in one or more processors 102) to provide output to one or more display devices 110A. In one embodiment, the one or more display devices 110A coupled to the I / O hub 107 may include a local display device, an internal display device, or an embedded display device.

[0047] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112, which are coupled to the memory hub 105 via a bus or other communication link 113. The communication link 113 can be one of any number of standard-based communication link technologies or protocols (such as but not limited to PCI Express), or it can be a vendor-specific communication interface or communication structure. In one embodiment, the one or more parallel processors 112 form a computing-centric parallel or vector processing system that includes a large number of processing cores and / or processing clusters such as integrated many-core (MIC) processors. In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one of one or more display devices 110A coupled via the I / O hub 107. The one or more parallel processors 112 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 110B.

[0048] Within the I / O subsystem 111, a system storage unit 114 may be connected to the I / O hub 107 to provide a storage mechanism for the computing system 100. The I / O switch 116 may be used to provide an interface mechanism to enable connection between the I / O hub 107 and other components that may be integrated into the platform, such as a network adapter 118 and / or a wireless network adapter 119, as well as various other devices that may be added via one or more plug-in devices 120. The network adapter 118 may be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0049] Computing system 100 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 107. Figure 1 The communication paths interconnecting the various components may be implemented using any suitable protocol such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express), or any other bus or point-to-point communication interface(s) and / or protocol such as the NV-Link high-speed interconnect or an interconnect protocol known in the art.

[0050] In one embodiment, one or more parallel processors 112 incorporate circuits optimized for graphics and video processing, including, for example, video output circuits, and the circuits constitute a graphics processing unit (GPU). In another embodiment, one or more parallel processors 112 incorporate circuits optimized for general-purpose processing while retaining the basic computing architecture described in more detail herein. In yet another embodiment, the components of the computing system 100 can be integrated with one or more other system elements on a single integrated circuit. For example, one or more parallel processors 112, a memory hub 105, (multiple) processors 102, and an I / O hub 107 can be integrated into a system on a chip (SoC) integrated circuit. Alternatively, the components of the computing system 100 can be integrated into a single package to form a system in package (SIP) configuration. In other embodiments, at least a portion of the components of the computing system 100 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules to form a modular computing system.

[0051] It should be understood that the computing system 100 shown herein is illustrative and variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of (multiple) processors 102, and the number of (multiple) parallel processors 112, can be modified as needed. For example, in some embodiments, the system memory 104 is directly connected to the (multiple) processors 102 rather than through a bridge, and other devices communicate with the system memory 104 via the memory hub 105 and the (multiple) processors 102. In other alternative topologies, the (multiple) parallel processors 112 are connected to the I / O hub 107 or directly to one of the one or more processors 102, rather than to the memory hub 105. In other embodiments, the I / O hub 107 and the memory hub 105 can be integrated into a single chip. Some embodiments may include two or more groups of (multiple) processors 102 attached via multiple sockets, which can be coupled to two or more instances of (multiple) parallel processors 112.

[0052] Some specific components shown herein are optional and may not be included in all implementations of computing system 100. For example, any number of plug-in cards or peripherals may be supported, or some components may be omitted. In addition, some architectures may use different terminology to describe components related to the computing system 100. Figure 1 For example, in some architectures, memory hub 105 may be referred to as a north bridge, while I / O hub 107 may be referred to as a south bridge.

[0053] Figure 2A A parallel processor 200 according to an embodiment is shown. Various components of the parallel processor 200 may be implemented using one or more integrated circuit devices such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). According to an embodiment, the parallel processor 200 shown is Figure 1 A variation of one or more parallel processors 112 is shown.

[0054] In one embodiment, parallel processor 200 includes parallel processing unit 202. The parallel processing unit includes an I / O unit 204, which enables communication with other devices including other instances of parallel processing unit 202. I / O unit 204 can be directly connected to other devices. In one embodiment, I / O unit 204 is connected to other devices via the use of a hub or switch interface such as memory hub 105. The connection between memory hub 105 and I / O unit 204 forms communication link 113. Within parallel processing unit 202, I / O unit 204 is connected to host interface 206 and memory cross switch 216, wherein host interface 206 receives commands related to performing processing operations and memory cross switch 216 receives commands related to performing memory operations.

[0055] When the host interface 206 receives the command buffer via the I / O unit 204, the host interface 206 can direct the work operations for executing those commands to the front end 208. In one embodiment, the front end 208 is coupled with a scheduler 210, which is configured to distribute commands or other work items to the processing cluster array 212. In one embodiment, the scheduler 210 ensures that the processing cluster array 212 is properly configured and is in a valid state before distributing tasks to the processing clusters in the processing cluster array 212. In one embodiment, the scheduler 210 is implemented via firmware logic executed on a microcontroller. The scheduler 210 implemented via the microcontroller can be configured to perform complex scheduling and work distribution operations at coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on the processing array 212. In one embodiment, the host software can prove workloads for scheduling on the processing array 212 via one of a plurality of graphics processing doorbell mechanisms. These workloads can then be automatically distributed across the processing array 212 by the scheduler 210 logic within the scheduler microcontroller.

[0056] The processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B, up to cluster 214N). Each cluster 214A to 214N of the processing cluster array 212 may execute a large number of concurrent threads. The scheduler 210 may use various scheduling and / or work distribution algorithms to allocate work to the clusters 214A to 214N of the processing cluster array 212, which may vary depending on the workload caused by each type of program or calculation. Scheduling may be handled dynamically by the scheduler 210, or may be partially assisted by compiler logic in the process of compiling program logic configured to be executed by the processing cluster array 212. In one embodiment, different clusters 214A to 214N of the processing cluster array 212 may be allocated to process different types of programs or to perform different types of calculations.

[0057] Processing cluster array 212 may be configured to perform various types of parallel processing operations. In one embodiment, processing cluster array 212 is configured to perform general-purpose parallel computing operations. For example, processing cluster array 212 may include logic for performing processing tasks including filtering of video and / or audio data, performing modeling operations including physical operations, and performing data transformations.

[0058] In one embodiment, processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where parallel processor 200 is configured to perform graphics processing operations, processing cluster array 212 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations and tessellation logic and other vertex processing logic. In addition, processing cluster array 212 may be configured to execute shader programs associated with graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. Parallel processing unit 202 may transfer data from system memory via I / O unit 204 for processing. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 222) during processing and then written back to system memory.

[0059] In one embodiment, when parallel processing unit 202 is used to perform graphics processing, scheduler 210 can be configured to divide the processing workload into tasks of approximately equal size to better enable the distribution of graphics processing operations to multiple clusters 214A to 214N of processing cluster array 212. In some embodiments, portions of processing cluster array 212 can be configured to perform different types of processing. For example, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen space operations to generate a rendered image for display. Intermediate data generated by one or more of clusters 214A to 214N can be stored in a buffer to allow the intermediate data to be transferred between clusters 214A to 214N for further processing.

[0060] During operation, the processing cluster array 212 may receive processing tasks to be executed via the scheduler 210, which receives commands defining the processing tasks from the front end 208. For graphics processing operations, a processing task may include data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands (e.g., which program to execute) that define how the data is to be processed. The scheduler 210 may be configured to obtain an index corresponding to a task or may receive an index from the front end 208. The front end 208 may be configured to ensure that the processing cluster array 212 is configured to a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0061] Each of the one or more instances of the parallel processing unit 202 may be coupled to a parallel processor memory 222. The parallel processor memory 222 may be accessed via a memory crossbar switch 216, which may receive memory requests from the processing cluster array 212 and the I / O unit 204. The memory crossbar switch 216 may access the parallel processor memory 222 via a memory interface 218. The memory interface 218 may include a plurality of partition units (e.g., partition unit 220A, partition unit 220B, up to partition unit 220N), which may each be coupled to a portion (e.g., memory unit) of the parallel processor memory 222. In one implementation, the number of partition units 220A to 220N is configured to be equal to the number of memory units, such that the first partition unit 220A has a corresponding first memory unit 224A, the second partition unit 220B has a corresponding memory unit 224B, and the Nth partition unit 220N has a corresponding Nth memory unit 224N. In other embodiments, the number of partition units 220A to 220N may not be equal to the number of memory devices.

[0062] In various embodiments, the memory units 224A to 224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, the memory units 224A to 224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will appreciate that the specific implementation of the memory units 224A to 224N may vary and may be selected from one of a variety of conventional designs. Rendering targets such as frame buffers or texture maps may be stored on the memory units 224A to 224N, allowing the partition units 220A to 220N to write to portions of each rendering target in parallel to efficiently use the available bandwidth of the parallel processor memory 222. In some embodiments, in order to support a unified memory design that utilizes system memory together with local cache memory, the local instance of the parallel processor memory 222 may be excluded.

[0063] In one embodiment, any of the clusters 214A to 214N of the processing cluster array 212 can process data to be written to any of the memory units 224A to 224N within the parallel processor memory 222. The memory crossbar 216 can be configured to pass the output of each cluster 214A to 214N to any partition unit 220A to 220N or another cluster 214A to 214N, which can perform additional processing operations on the output. Each cluster 214A to 214N can communicate with the memory interface 218 through the memory crossbar 216 to perform read or write operations on various external memory devices. In one embodiment, the memory crossbar 216 can be connected to the memory interface 218 to communicate with the I / O unit 204, and can be connected to the local instance of the parallel processor memory 222, so that the processing units within different processing clusters 214A to 214N can communicate with the system memory or other memory that is not local to the parallel processing unit 202. In one embodiment, the memory crossbar switch 216 may use virtual channels to separate traffic flows between the clusters 214A to 214N and the partition units 220A to 220N.

[0064] Although a single instance of parallel processing unit 202 is shown as being within parallel processor 200, any number of instances of parallel processing unit 202 may also be included. For example, multiple instances of parallel processing unit 202 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. Even if different instances have different numbers of processing cores, different local parallel processor storage amounts, and / or other configuration differences, different instances of parallel processing unit 202 may also be configured to interoperate. For example, and in one embodiment, some instances of parallel processing unit 202 may include higher precision floating point units relative to other instances. Systems incorporating one or more instances of parallel processing unit 202 or parallel processor 200 may be implemented in various configurations and form factors, including but not limited to desktop computers, laptop computers or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0065] Figure 2B is a block diagram of a partition unit 220 according to an embodiment. In one embodiment, the partition unit 220 is Figure 2A 2 is an example of one of the partition units 220A to 220N of FIG. As shown, the partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and an ROP 226 (raster operation unit). The L2 cache 221 is a read / write cache that is configured to perform loads and store operations received from the memory crossbar switch 216 and the ROP 226. Read misses and urgent write-back requests are output by the L2 cache 221 to the frame buffer interface 225 for processing. Updates may also be sent to the frame buffer via the frame buffer interface 225 for processing. In one embodiment, the frame buffer interface 225 interfaces with one of the memory units in the parallel processor memory, such as the memory units 224A to 224N of FIG. 2 (e.g., within the parallel processor memory 222).

[0066] In graphics applications, ROP 226 is a processing unit that performs raster operations (e.g., stencil, z-test, color blending, etc.). ROP 226 then outputs processed graphics data that is stored in graphics memory. In some embodiments, ROP 226 includes compression logic that compresses depth or color data written to memory and decompresses depth or color data read from memory. The compression logic can be lossless compression logic that uses one or more of a variety of compression algorithms. The type of compression performed by ROP 226 can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta color compression is performed on depth and color data on a tile-by-tile basis.

[0067] In some embodiments, ROP 226 is included within each processing cluster (e.g., clusters 214A to 214N of FIG. 2 ) rather than within partition unit 220. In this embodiment, read and write requests for pixel data are transmitted through memory crossbar 216 rather than pixel fragment data. The processed graphics data may be displayed on a display device such as a Figure 1 to one of the one or more display devices 110, routed by the processor(s) 102 for further processing, or by Figure 2A One of the processing entities within parallel processor 200 is routed for further processing.

[0068] Figure 2C It is a block diagram of a processing cluster 214 in a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 214A to 214N of Figure 2. The processing cluster 214 can be configured to execute multiple threads in parallel, wherein the term "thread" refers to an instance of a specific program executed on a specific input data set. In some embodiments, a single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, a single instruction multiple thread (SIMT) technology is used to use a public instruction unit configured to issue instructions to a group of processing engines in each of the processing clusters to support the parallel execution of a large number of roughly synchronized threads. Different from the SIMD execution mechanism that all processing engines usually execute the same instruction, SIMT execution allows different threads to more easily follow the divergent execution path through a given thread program. It will be appreciated by those skilled in the art that the SIMD processing mechanism represents a functional subset of the SIMT processing mechanism.

[0069] The operation of the processing cluster 214 can be controlled via a pipeline manager 232 that distributes processing tasks to the SIMT parallel processors. The pipeline manager 232 receives instructions from the scheduler 210 of Figure 2 and manages the execution of those instructions via the graphics multiprocessor 234 and / or the texture unit 236. The graphics multiprocessor 234 shown is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors of different architectures can be included in the processing cluster 214. One or more instances of the graphics multiprocessor 234 can be included in the processing cluster 214. The graphics multiprocessor 234 can process data, and the data crossbar switch 240 can be used to distribute the processed data to one of multiple possible destinations including other shading units. The pipeline manager 232 can promote the distribution of processed data by specifying a destination for the data to be distributed via the data crossbar switch 240.

[0070] Each graphics multiprocessor 234 within a processing cluster 214 may include the same set of function execution logic (e.g., arithmetic logic units, load store units, etc.). The function execution logic may be configured in a pipelined manner, where a new instruction may be issued before a previous instruction is completed. The function execution logic supports a variety of operations, including integer and floating point arithmetic, comparison operations, Boolean operations, bit shifts, and calculation of various algebraic functions. In one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may exist.

[0071] The instructions transmitted to the processing cluster 214 constitute threads. A group of threads executed on a group of parallel processing engines is a thread group. A thread group executes the same program on different input data. Each thread in a thread group can be assigned to a different processing engine in the graphics multiprocessor 234. A thread group can include fewer threads than the number of processing engines in the graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle of processing the thread group. A thread group can also include more threads than the number of processing engines in the graphics multiprocessor 234. When a thread group includes more threads than the number of processing engines in the graphics multiprocessor 234, processing can be performed on consecutive clock cycles. In one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 234.

[0072] In one embodiment, the graphics multiprocessor 234 includes an internal cache memory for performing load and store operations. In one embodiment, the graphics multiprocessor 234 can abandon the internal cache and use cache memory (e.g., L1 cache 308) within the processing cluster 214. Each graphics multiprocessor 234 can also access the L2 cache within the partition unit (e.g., partition unit 220A to 220N of Figure 2) shared between all processing clusters 214, and can be used to pass data between threads. The graphics multiprocessor 234 can also access off-chip global memory, which can include one or more of the local parallel processor memory and / or system memory. Any memory outside the parallel processing unit 202 can be used as global memory. In which the processing cluster 214 includes multiple instances of the graphics multiprocessor 234, the embodiment can share common instructions and data that can be stored in the L1 cache 308.

[0073] Each processing cluster 214 may include an MMU 245 (memory management unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of the MMU 245 may reside within the memory interface 218 of FIG. 2 . The MMU 245 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles (more referred to as blocking) and optionally cache line indexes. The MMU 245 may include an address translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 234 or L1 cache or processing cluster 214. Physical addresses are processed to distribute surface data access locality to achieve efficient request interleaving between partition units. The cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0074] In graphics and computing applications, the processing clusters 214 can be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown) or in some embodiments from an L1 cache within the graphics multiprocessor 234, and is retrieved from an L2 cache, local parallel processor memory, or system memory as needed. Each graphics multiprocessor 234 outputs processed tasks to a data crossbar 240 to provide the processed tasks to another processing cluster 214 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 216. A preROP 242 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 234, direct the data to ROP units, which can be located with partition units (e.g., partition units 220A to 220N of FIG. 2 ) as described herein. The preROP 242 unit optimizes color blending, organizes pixel color data, and performs address translation.

[0075] It should be understood that the core architecture described herein is illustrative and variations and modifications are possible. Any number of processing units, such as graphics multiprocessor 234, texture unit 236, preROP 242, etc., may be included in processing cluster 214. In addition, although only one processing cluster 214 is shown, the parallel processing unit described herein may include any number of instances of processing cluster 214. In one embodiment, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, etc.

[0076] Figure 2DA graphics multiprocessor 234 is shown according to one embodiment. In such an embodiment, the graphics multiprocessor 234 is coupled to the pipeline manager 232 of the processing cluster 214. The graphics multiprocessor 234 has an execution pipeline that includes, but is not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268.

[0077] In one embodiment, the instruction cache 252 receives a stream of instructions to be executed from the pipeline manager 232. These instructions are cached in the instruction cache 252 and dispatched for execution by the instruction unit 254. The instruction unit 254 can dispatch instructions as thread groups (e.g., warps), each thread of the thread group is assigned to a different execution unit within the GPGPU core 262. Instructions can access any of the local, shared, or global address spaces by specifying an address within the unified address space. The address mapping unit 256 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 266.

[0078] The register file 258 provides a set of registers for the functional units of the graphics multiprocessor 324. The register file 258 provides temporary storage for operands for the data paths of the functional units (e.g., GPGPU core 262, load / store unit 266) connected to the graphics multiprocessor 324. In one embodiment, the register file 258 is divided between each of the functional units so that each functional unit is allocated a dedicated portion of the register file 258. In one embodiment, the register file 258 is divided between the different warps being executed by the graphics multiprocessor 324.

[0079] The GPGPU cores 262 may each include a floating point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 324. Depending on the embodiment, the architecture of the GPGPU cores 262 may be similar or different. For example, and in one embodiment, the first portion of the GPGPU core 262 includes a single-precision FPU and an integer ALU, while the second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 floating-point arithmetic standard or enable variable-precision floating-point arithmetic. In addition, the graphics multiprocessor 324 may also include one or more fixed-function or special-function units for performing specific functions such as copying rectangles or pixel blending operations. In one embodiment, one or more of the GPGPU cores may also include fixed or special-function logic.

[0080] In one embodiment, the GPGPU core 262 includes SIMD logic capable of executing a single instruction to multiple sets of data. In one embodiment, the GPGPU core 262 can physically execute SIMD4, SIMD8 and SIMD16 instructions, and logically execute SIMD1, SIMD2 and SIMD32 instructions. The SIMD instructions of the GPGPU core can be generated by the shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. Multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example and in one embodiment, eight SIMT threads can be executed in parallel via a single SIMD8 logic unit, and these eight SIMT threads perform the same or similar operations.

[0081] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 324 to the register file 258 and the shared memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to implement load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, so the data transfer between the GPGPU core 262 and the register file 258 has a very low latency. The shared memory 270 can be used to implement communication between threads executed on the functional units within the graphics multiprocessor 234. For example, the cache memory 272 can be used as a data cache to cache texture data communicated between the functional units and the texture unit 236. The shared memory 270 can also be used as a cached managed program. In addition to the automatically cached data stored in the cache memory 272, threads executing on the GPGPU core 262 can also programmatically store data in the shared memory.

[0082] FIG. 3A to FIG. 3B Additional graphics multiprocessors are shown according to embodiments. The graphics multiprocessors 325, 350 shown are Figure 2C The illustrated graphics multiprocessors 325, 350 may be configured as streaming multiprocessors (SMs) capable of executing a large number of execution threads simultaneously.

[0083] Figure 3A A graphics multiprocessor 325 is shown according to an additional embodiment. The graphics multiprocessor 325 includes Figure 2D The graphics multiprocessor 325 may include multiple additional instances of execution resource units of the graphics multiprocessor 234. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A to 332B, register files 334A to 334B, and (multiple) texture units 344A to 344B. The graphics multiprocessor 325 also includes multiple groups of graphics or compute execution units (e.g., GPGPU cores 336A to 336B, GPGPU cores 337A to 337B, GPGPU cores 338A to 338B) and multiple groups of load / store units 340A to 340B. In one embodiment, the execution resource units have a common instruction cache 330, texture and / or data cache memory 342, and shared memory 346.

[0084] Various components may communicate via the interconnect fabric 327. In one embodiment, the interconnect fabric 327 includes one or more crossbar switches to enable communication between the various components of the graphics multiprocessor 325. In one embodiment, the interconnect fabric 327 is a separate, high-speed network fabric layer on which each component of the graphics multiprocessor 325 is stacked. Components of the graphics multiprocessor 325 communicate with remote components via the interconnect fabric 327. For example, the GPGPU cores 336A-336B, 337A-337B, and 3378A-338B may each communicate with the shared memory 346 via the interconnect fabric 327. The interconnect fabric 327 may arbitrate communications within the graphics multiprocessor 325 to ensure fair bandwidth allocation between components.

[0085] Figure 3B A graphics multiprocessor 350 is shown according to an additional embodiment. Figure 2D and Figure 3A As shown, the graphics processor includes multiple groups of execution resources 356A to 356D, each of which includes multiple instruction units, register files, GPGPU cores, and load storage units. The execution resources 356A to 356D can work with (multiple) texture units 360A to 360D to perform texture operations while sharing an instruction cache 354 and a shared memory 362. In one embodiment, the execution resources 356A to 356D can share multiple instances of the instruction cache 354 and the shared memory 362 as well as texture and / or data cache memories 358A to 358B. The various components can be connected via Figure 3A The interconnect structure 327 communicates with a similar interconnect structure 352 .

[0086] Those skilled in the art will understand that Figure 1 , FIG. 2A to FIG. 2D and FIG. 3A to FIG. 3B The architecture described in is illustrative and does not limit the scope of the embodiments of the present invention. Therefore, the techniques described herein can be implemented on any appropriately configured processing unit, including but not limited to: one or more mobile application processors; one or more desktop computer or server central processing units (CPUs), including multi-core CPUs; one or more parallel processing units such as parallel processing unit 202 of FIG. 2; and one or more graphics processors or special processing units, without departing from the scope of the embodiments described herein.

[0087] In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside a package or chip). Regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuits / logic to efficiently process these commands / instructions.

[0088] Technologies for GPU to host processor interconnect

[0089] Figure 4A An exemplary architecture is shown in which multiple GPUs 410 to 413 are communicatively coupled to multiple multi-core processors 405 to 406 via high-speed links 440 to 443 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, high-speed links 440 to 443 support 4GB / s, 30GB / s, 80GB / s, or higher communication throughput, depending on the implementation. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the underlying principles of the invention are not limited to any particular communication protocol or throughput.

[0090] Furthermore, in one embodiment, two or more of the GPUs 410 to 413 are interconnected via high-speed links 444 to 445, which may be implemented using the same or different protocols / links as used for high-speed links 440 to 443. Similarly, two or more of the multi-core processors 405 to 406 may be connected via high-speed link 433, which may be a symmetric multiprocessor (SMP) bus running at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, Figure 4A All communications between the various system components shown in can be accomplished using the same protocol / links (eg, through a common interconnect structure). However, as mentioned, the underlying principles of the invention are not limited to any particular type of interconnect technology.

[0091] In one embodiment, each multi-core processor 405-406 is communicatively coupled to processor memory 401-402 via memory interconnects 430-431, respectively, and each GPU 410-413 is communicatively coupled to GPU memory 420-423 via GPU memory interconnects 450-453, respectively. The memory interconnects 430-431 and 450-453 may utilize the same or different memory access technologies. By way of example and not limitation, the processor memory 401-402 and the GPU memory 420-423 may be volatile memory such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memory such as 3D XPoint or Nano-Ram. In one embodiment, a portion of the memory may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0092] As described below, although the various processors 405-406 and GPUs 410-413 may each be physically coupled to a specific memory 401-402, 420-423, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed among all the various physical memories. For example, the processor memories 401-402 may each include 64GB of system memory address space, and the GPU memories 420-423 may each include 32GB of system memory address space (resulting in a total of 256GB of addressable storage space in the described example).

[0093] Figure 4B Additional details of the interconnection between the multi-core processor 407 and the graphics acceleration module 446 according to one embodiment are shown. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card coupled to the processor 407 via the high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

[0094] The processor 407 shown includes a plurality of cores 460A to 460D, each of which has a translation lookaside buffer 461A to 461D and one or more caches 462A to 462D. These cores may include various other components (e.g., instruction fetch units, branch prediction units, decoders, execution units, reorder buffers, etc.) for executing instructions and processing data not shown to avoid obscuring the basic principles of the present invention. Caches 462A to 462D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 426 may be included in the cache hierarchy and shared by each group of cores 460A to 460D. For example, one embodiment of the processor 407 includes 24 cores, each of which has its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 cache and the L3 cache is shared by two adjacent cores. The processor 407 and the graphics accelerator integrated module 446 are connected to the system memory 441 , which may include the processor memories 401 to 402 .

[0095] The data and instructions stored in the various caches 462A to 462D, 456, and the system memory 441 are maintained consistent via inter-core communication via the consistency bus 464. For example, each cache may have cache consistency logic / circuitry associated therewith to communicate via the consistency bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented via the consistency bus 464 to snoop cache accesses. Cache snooping / consistency techniques are well understood by those skilled in the art and will not be described in detail herein to avoid obscuring the basic principles of the present invention.

[0096] In one embodiment, the proxy circuit 425 communicatively couples the graphics acceleration module 446 to the coherence bus 464, thereby allowing the graphics acceleration module 446 to participate in the cache coherence protocol as a peer of the core. Specifically, the interface 435 provides connectivity to the proxy circuit 425 via a high-speed link 440 (e.g., a PCIe bus, NVLink, etc.), and the interface 437 connects the graphics acceleration module 446 to the link 440.

[0097] In one implementation, the accelerator integrated circuit 436 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 431, 432, 43N of the graphics acceleration module 446. The graphics processing engines 431, 432, 43N may each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, 43N may include different types of graphics processing engines such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and block image transfer engines within the GPU. In other words, the graphics acceleration module may be a GPU having multiple graphics processing engines 431, 432, 43N, or the graphics processing engines 431 to 432, 43N may be separate GPUs integrated on a common package, line card, or chip.

[0098] In one embodiment, the accelerator integrated circuit 436 includes a memory management unit (MMU) 439 for performing various memory management functions such as virtual to physical memory translation (also known as effective to real memory translation) and a memory access protocol for accessing the system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / real address translations. In one implementation, the cache 438 stores commands and data for efficient access by the graphics processing engines 431 to 432, 43N. In one embodiment, the data stored in the cache 438 and the graphics memory 433 to 434, 43N is kept consistent with the core caches 462A to 462D, 456 and the system memory 411. As mentioned, this can be accomplished via proxy circuitry 425, which participates in cache coherence mechanisms on behalf of cache 438 and memories 433 to 434, 43N (e.g., sending updates to cache 438 related to modifications / accesses of cache lines on processor caches 462A to 462D, 456 and receiving updates from cache 438).

[0099] A set of registers 445 stores context data for threads executed by the graphics processing engines 431 to 432, 43N, and a context management circuit 448 manages thread contexts. For example, the context management circuit 448 may perform save and restore operations to save and restore contexts of various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, upon context switching, the context management circuit 448 may store current register values ​​to a specified area in memory (e.g., identified by a context pointer). The context management circuit may restore register values ​​upon returning to context. In one embodiment, the interrupt management circuit 447 receives and processes interrupts received from system devices.

[0100] In one implementation, the virtual / effective address from the graphics processing engine 431 is converted to an actual / physical address in the system memory 411 by the MMU 439. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator module 446 can be dedicated to a single application executed on the processor 407, or can be shared between multiple applications. In one embodiment, a virtual graphics execution environment is presented in which the resources of the graphics processing engines 431 to 432, 43N are shared with multiple applications or virtual machines (VMs). Resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0101] Thus, the accelerator integrated circuit acts as a bridge to the system of graphics acceleration modules 446 and provides address translation and system memory cache services. In addition, the accelerator integrated circuit 436 can provide virtualization facilities for the host processor to manage virtualization of the graphics processing engine, interrupts, and memory management.

[0102] Since the hardware resources of the graphics processing engines 431-432, 43N are explicitly mapped to the actual address space seen by the host processor 407, any host processor can directly address these resources using effective address values. In one embodiment, one function of the accelerator integrated circuit 436 is the physical separation of the graphics processing engines 431-432, 43N so that they appear on the system as independent units.

[0103] As mentioned, in the illustrated embodiment, one or more graphics memories 433-434, 43M are coupled to each of the graphics processing engines 431-432, 43N, respectively. The graphics memories 433-434, 43M store instructions and data being processed by each of the graphics processing engines 431-432, 43N. The graphics memories 433-434, 43M may be volatile memories such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories such as 3D XPoint or Nano-Ram.

[0104] In one embodiment, in order to reduce data traffic on link 440, biasing techniques are used to ensure that the data stored in graphics memory 433 to 434, 43M is the data most frequently used by graphics processing engines 431 to 432, 43N, and preferably not used (at least not frequently) by cores 460A to 460D. Similarly, the biasing mechanism attempts to keep data needed by the core (and preferably not the graphics processing engines 431 to 432, 43N) within caches 462A to 462D, 456 of the core and system memory 411.

[0105] Figure 4C Another embodiment is shown in which an accelerator integrated circuit 436 is integrated into the processor 407. In this embodiment, the graphics processing engines 431 to 432, 43N communicate directly with the accelerator integrated circuit 436 via the interface 437 and the interface 435 through the high-speed link 440 (which may also utilize any form of bus or interface protocol). The accelerator integrated circuit 436 can perform operations related to Figure 4B The same operations are described, but given their close proximity to the coherency bus 462 and caches 462A to 462D, 426, it is possible to operate at a higher throughput.

[0106] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The shared programming model may include a programming model controlled by accelerator integrated circuit 436 and a programming model controlled by graphics acceleration module 446.

[0107] In one embodiment of a dedicated process model, graphics processing engines 431 to 432, 43N are dedicated to a single application or process under a single operating system. A single application can funnel other application requests to graphics engines 431 to 432, 43N, thereby providing virtualization within a VM / partition.

[0108] In a dedicated process programming model, the graphics processing engines 431 to 432, 43N can be shared by multiple VM / application partitions. The shared model requires a hypervisor that virtualizes the graphics processing engines 431 to 432, 43N to allow access by each operating system. For a single partition system without a hypervisor, the graphics processing engines 431 to 432, 43N are owned by the operating system. In both cases, the operating system can virtualize the graphics processing engines 431 to 432, 43N to provide access to each process or application.

[0109] For the shared programming model, the graphics acceleration module 446 or the individual graphics processing engines 431 to 432, 43N use a process handle to select a process element. In one embodiment, the process elements are stored in the system memory 411 and can be addressed using the effective address to real address translation techniques described herein. The process handle can be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 431 to 432, 43N (i.e., calling the system software to add a process element to the process element linked list). The lower 16 bits of the process handle can be the offset of the process element within the process element linked list.

[0110] Figure 4D An exemplary accelerator integrated slice 490 is shown. As used herein, a "slice" includes a specified portion of the processing resources of the accelerator integrated circuit 436. The application effective address space 482 within the system memory 411 stores process elements 483. In one embodiment, the process element 483 is stored in response to a GPU call 481 from an application 480 executed on the processor 407. The process element 483 contains the processing state of the corresponding application 480. The work descriptor (WD) 484 contained in the process element 483 can be a single job requested by the application, or can contain a pointer to a job queue. In the latter case, the WD 484 is a pointer to a job request queue in the application address space 482.

[0111] Graphics acceleration module 446 and / or individual graphics processing engines 431-432, 43N may be shared by all or some processes in the system. Embodiments of the present invention include an infrastructure for establishing a processing state and sending a WD 484 to the graphics acceleration module 446 to start a job in a virtual environment.

[0112] In one implementation, the dedicated process programming model is specific to a specific implementation. In this model, a single process owns the graphics acceleration module 446 or a separate graphics processing engine 431. Since the graphics acceleration module 446 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 436 to obtain the owned partition, and the operating system initializes the accelerator integrated circuit 436 to obtain the owned process when the graphics acceleration module 446 is allocated.

[0113] In operation, the WD acquisition unit 491 in the accelerator integrated slice 490 acquires the next WD 484, which includes an indication of the work to be performed by one of the graphics processing engines of the graphics acceleration module 446. As shown, the data from the WD 484 can be stored in the register 445 and used by the MMU 439, the interrupt management circuit 447 and / or the context management circuit 446. For example, one embodiment of the MMU 439 includes a segment / page walk circuit for accessing the segment / page table 486 within the OS virtual address space 485. The interrupt management circuit 447 can process the interrupt event 492 received from the graphics acceleration module 446. When performing graphics operations, the effective address 493 generated by the graphics processing engine 431 to 432, 43N is converted to an actual address by the MMU 439.

[0114] In one embodiment, the same set of registers 445 is replicated for each graphics processing engine 431 to 432, 43N and / or graphics acceleration module 446, and this set of registers can be initialized by a hypervisor or an operating system. Each of these replicated registers can be included in an accelerator integrated slice 490. Table 1 shows exemplary registers that can be initialized by a hypervisor.

[0115] Table 1 - Hypervisor Initialization Registers

[0116] 1 Slice Control Register 2 Real Address (RA) Dispatch Process Area Pointer 3 Authorization mask override register 4 Interrupt vector table entry offset 5 Interrupt vector table entry limit 6 Status Register 7 Logical Partition ID 8 Real Address (RA) Manager Accelerator Utilizes Record Pointers 9 Storage Description Register

[0117] Example registers that may be initialized by the operating system are shown in Table 2.

[0118] Table 2 - Operating System Initialization Registers

[0119] 1 Process and thread identities 2 Effective Address (EA) context save / restore pointer 3 Virtual Address (RA) Accelerator Utilizes Record Pointers 4 Virtual Address (RA) storage segment table pointer 5 Authorization Mask 6 Job Descriptor

[0120] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engine 431 to 432, 43N. The WD contains all the information needed by the graphics processing engine 431 to 432, 43N to complete its work, or the WD can be a pointer to a memory location where the application has established a command queue for work to be completed.

[0121] Figure 4E Additional details of one embodiment of the sharing model are shown. The embodiment includes a hypervisor real address space 498 in which a process element list 499 is stored. The hypervisor real address space 498 is accessible via a hypervisor 496 that virtualizes a graphics acceleration module engine of an operating system 495.

[0122] The shared programming model allows all or some processes from all or some partitions in the system to use the graphics acceleration module 446. There are two programming models where the graphics acceleration module 446 is shared by multiple processes and partitions: time-sliced ​​sharing and graphics direct sharing.

[0123] In this model, the hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. In order for the graphics acceleration module 446 to support virtualization of the hypervisor 496, the graphics acceleration module 446 may comply with the following requirements: 1) Application job requests must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 446 must provide a context save and restore mechanism. 2) The graphics acceleration module 446 guarantees that application job requests are completed within a specified amount of time, including any conversion errors, or the graphics acceleration module 446 provides the ability to preempt job processing. 3) When operating in a direct sharing programming model, fairness of the graphics acceleration module 446 in the process must be guaranteed.

[0124] In one embodiment, for the shared model, an application 480 is required to make an operating system 495 system call using a graphics acceleration module 446 type, a work descriptor (WD), an authorization mask register (AMR) value, and a context save / restore region pointer (CSRP). The graphics acceleration module 446 type describes the target acceleration function of the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is formatted specifically for the graphics acceleration module 446 and can be in the following form: a graphics acceleration module 446 command; an effective address pointer to a user-defined structure; an effective address pointer to a command queue; or any other data structure used to describe the work to be performed by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state for the current process. The value passed to the operating system is similar to the application that sets the AMR. If the implementation of the accelerator integrated circuit 436 and the graphics acceleration module 446 does not support the user authorization mask override register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. The hypervisor 496 may optionally apply the current authorization mask override register (AMOR) value before placing the AMR into the process element 483. In one embodiment, the CSRP is one of the registers 445 that contains the effective address of an area in the application address space 482 for the graphics acceleration module 446 to save and restore context state. This pointer is optional if state does not need to be saved between jobs or when a job is preempted. The context save / restore area may be a plugged in system memory.

[0125] Upon receiving the system call, the operating system 495 can verify that the application 480 is registered and authorized to use the graphics acceleration module 446. The operating system 495 then calls the hypervisor 496 with the information shown in Table 3.

[0126] Table 3 - Parameters of the operating system calling the hypervisor

[0127] 1 Work Descriptor (WD) 2 Authorization Mask Register (AMR) value (may be masked) 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0128] Upon receiving the hypervisor call, the hypervisor 496 may verify that the operating system 495 has registered and is authorized to use the graphics acceleration module 446. The hypervisor 496 then places the process element 483 into the process element linked list for the corresponding graphics acceleration module 446 type. The process element may contain the information shown in Table 4.

[0129] Table 4 - Process element information

[0130] 1 Work Descriptor (WD) 2 Authorization Mask Register (AMR) value (may be masked) 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt vector table, derived from the hypervisor call parameters 9 Status Register (SR) Value 10 Logical Partition ID (LPID) 11 Real Address (RA) Manager Accelerator Utilizes Record Pointers 12 Storage Descriptor Register (SDR)

[0131] In one embodiment, the hypervisor initializes the plurality of accelerator integrated slices 490 of registers 445 .

[0132] like Figure 4F As shown, one embodiment of the present invention employs a unified memory addressable via a common virtual memory address space for accessing physical processor memories 401-402 and GPU memories 420-423. In this implementation, operations executed on GPUs 410-413 utilize the same virtual / effective memory address space to access processor memories 401-402, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 401, a second portion is allocated to second processor memory 402, a third portion is allocated to GPU memory 420, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 401-402 and GPU memories 420-423, thereby allowing any processor or GPU to access any physical memory having a virtual address mapped to that memory.

[0133] In one embodiment, bias / coherency management circuits 494A-494E within one or more of MMUs 439A-439E ensure cache coherency between caches of a host processor (e.g., 405) and GPUs 410-413 and implement biasing techniques that indicate physical memory where certain types of data should be stored. Figure 4F 4. Although multiple instances of bias / consistency management circuits 494A to 494E are shown in FIG. 4, bias / consistency circuits may also be implemented within an MMU of one or more host processors 405 and / or within an accelerator integrated circuit 436.

[0134] One embodiment allows the GPU-attached memory 420 to 423 to be mapped as part of the system memory and accessed using shared virtual memory (SVM) technology, but without suffering from the typical performance defects associated with full system cache coherence. The ability to access the GPU-attached memory 420 to 423 as system memory does not cause heavy cache coherence overhead, which provides a favorable operating environment for GPU offloading. This arrangement allows the host processor 405 software to set operands and access calculation results without the overhead of traditional I / O DMA data copying. These traditional copies involve driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, which are inefficient relative to simple memory accesses. At the same time, the ability to access the GPU-attached memory 420 to 423 without cache coherence overhead may be critical to the execution time of the offloaded calculation. For example, in the case of a large number of streaming write memory services, the cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPU 410 to 413. The efficiency of operand setting, the efficiency of result access, and the efficiency of GPU calculation all play an important role in determining the effectiveness of GPU offloading.

[0135] In one implementation, the selection between GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table may be used, which may be a page granular structure including 1 or 2 bits per GPU attached memory page (i.e., controlled at the granularity of a memory page). The bias table may be implemented in the stolen memory range of one or more GPU attached memories 420 to 423, with or without a bias cache in GPUs 410 to 413 (e.g., to cache frequently / recently used entries of the bias table). Alternatively, the entire bias table may be maintained within the GPU.

[0136] In one implementation, the bias table entry associated with each access to the GPU attached memory 420 to 423 is accessed before the GPU memory is actually accessed, so that the following operations are performed. First, local requests from GPUs 410 to 413 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 420 to 423. Local requests from the GPU whose pages are found in the host bias are forwarded to the processor 405 (e.g., over a high-speed link as described above). In one embodiment, the request from the processor 405 to find the requested page in the host processor bias completes the request like a normal memory read. Alternatively, the request for the GPU bias page can be forwarded to the GPU 410 to 413. If the GPU is not currently using the page, the GPU can convert the page to the host processor bias.

[0137] The bias state of a page can be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, a hardware-only based mechanism.

[0138] One mechanism for changing the bias state employs an API call (e.g., OpenCL) which in turn calls a GPU device driver which in turn sends a message (or queues a command descriptor) to the GPU, thereby directing the GPU to change the bias state and, for certain transitions, perform a cache flush operation in the host. The cache flush operation is required for a transition from host processor 405 bias to GPU bias, but not for the reverse transition.

[0139] In one embodiment, cache coherency is maintained by temporarily presenting GPU bias pages that are non-cacheable to host processor 405. To access these pages, processor 405 may request access from GPU 410, which may or may not grant access immediately, depending on the implementation. Therefore, to reduce communication between processor 405 and GPU 410, it is advantageous to ensure that GPU bias pages are pages that are needed by the GPU but not by the host processor 405, and vice versa.

[0140] Graphics processing pipeline

[0141] Figure 5 2. A graphics processing pipeline 500 according to an embodiment is shown. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 500. The graphics processor may be included in a parallel processing subsystem as described herein, such as the parallel processor 200 of FIG. 2. In one embodiment, the parallel processor is Figure 12 . As described herein, various parallel processing systems may implement the graphics processing pipeline 500 via one or more instances of a parallel processing unit (e.g., parallel processing unit 202 of FIG. 2 ). For example, a shader unit (e.g., graphics multiprocessor 234 of FIG. 3 ) may be configured to perform the functions of one or more of a vertex processing unit 504, a tessellation control processing unit 508, a tessellation evaluation processing unit 512, a geometry processing unit 516, and a fragment / pixel processing unit 524. The functions of the data assembler 502, the primitive assemblers 506, 514, 518, the tessellation unit 510, the rasterizer 522, and the raster operation unit 526 may also be performed by other processing engines within a processing cluster (e.g., processing cluster 214 of FIG. 3 ) and corresponding partition units (e.g., partition units 220A to 220N of FIG. 2 ). The graphics processing pipeline 500 may also be implemented using one or more dedicated processing units for the functions. In one embodiment, one or more portions of the graphics processing pipeline 500 may be executed by parallel processing logic within a general purpose processor (e.g., a CPU). In one embodiment, one or more portions of the graphics processing pipeline 500 may access on-chip memory (e.g., parallel processor memory 222 as shown in FIG. 2 ) via a memory interface 528, which may be an example of the memory interface 218 of FIG. 2 .

[0142] In one embodiment, data assembler 502 is a processing unit that collects vertex data for surfaces and primitives. Data assembler 502 then outputs vertex data including vertex attributes to vertex processing unit 504. Vertex processing unit 504 is a programmable execution unit that executes vertex shader programs to illuminate and transform vertex data as specified by the vertex shader programs. Vertex processing unit 504 reads data stored in cache, local or system memory for processing vertex data, and can be programmed to transform vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

[0143] A first instance of primitive assembler 506 receives vertex attributes from vertex processing unit 50. Primitive assembler 506 reads the stored vertex attributes and constructs graphics primitives as needed for processing by tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches, etc. as supported by various graphics processing application programming interfaces (APIs).

[0144] The tessellation control processing unit 508 treats the input vertices as control points of a geometric patch. These control points are transformed from an input representation from the patch (e.g., a basis for the patch) to a representation suitable for surface evaluation by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 may also calculate tessellation factors for the edges of the geometric patch. The tessellation factors apply to individual edges and quantify the view-dependent level of detail associated with the edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and tessellate the patch into a plurality of geometric primitives such as lines, triangles, or quadrilateral primitives, which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the tessellated patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitive.

[0145] A second instance of primitive assembler 514 receives vertex attributes from tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphics primitives for processing by geometry processing unit 516. Geometry processing unit 516 is a programmable execution unit that executes geometry shader programs to transform graphics primitives received from primitive assembler 514 as specified by the geometry shader programs. In one embodiment, geometry processing unit 516 is programmed to tessellate the graphics primitives into one or more new graphics primitives and to compute parameters for rasterizing the new graphics primitives.

[0146] In some embodiments, the geometry processing unit 516 can add or delete elements in the geometry stream. The geometry processing unit 516 outputs parameters and vertices specifying new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs the graphics primitives for processing by the viewport scaling, picking, and clipping unit 520. The geometry processing unit 516 reads data stored in the parallel processor memory or the system memory for processing the geometry data. The viewport scaling, picking, and clipping unit 520 performs clipping, picking, and viewport scaling, and outputs the processed graphics primitives to the rasterizer 522.

[0147] The rasterizer 522 can perform depth picking and other depth-based optimizations. The rasterizer 522 also performs scan conversion on new graphics primitives to generate segments and outputs these segments and associated coverage data to the segment / pixel processing unit 524. The fragment / pixel processing unit 524 is a programmable execution unit configured to execute a fragment shader program or a pixel shader program. The fragment / pixel processing unit 524 transforms the fragments or pixels received from the rasterizer 522 as specified by the fragment or pixel shader program. For example, the fragment / pixel processing unit 524 can be programmed to perform operations including but not limited to texture mapping, shading, blending, texture correction, and perspective correction to generate shaded fragments or pixels output to the raster operation unit 526. The fragment / pixel processing unit 524 can read data stored in a parallel processor memory or system memory to use when processing fragment data. The fragment or pixel shader program can be configured to color with samples, pixels, tiles, or other granularity according to the sampling rate configured for the processing unit.

[0148] The raster operation unit 526 is a processing unit that performs raster operations including, but not limited to, stenciling, z-testing, blending, etc., and outputs pixel data as processed graphics data for storage in a graphics memory (e.g., parallel processor memory 222 in FIG. 2 , and / or as shown in FIG. Figure 1 The raster operation unit 526 may be configured to compress the z or color data written to the memory and to decompress the z or color data read from the memory.

[0149] Machine Learning Overview

[0150] A machine learning algorithm is an algorithm that can learn based on a set of data. Embodiments of machine learning algorithms can be designed to model high-level abstractions within a data set. For example, an image recognition algorithm can be used to determine which of several categories a given input belongs to; a regression algorithm can output a numerical value given an input; and a pattern recognition algorithm can be used to generate translated text or perform text-to-speech and / or speech recognition.

[0151] One example type of machine learning algorithm is a neural network. There are many types of neural networks; a simple type of neural network is a feedforward network. A feedforward network can be implemented as an acyclic graph in which nodes are arranged in layers. Typically, a feedforward network topology includes an input layer and an output layer, which are separated by at least one hidden layer. The hidden layer transforms the input received by the input layer into a representation useful for generating outputs in the output layer. The network nodes are fully connected to the nodes in the adjacent layers via edges, but there are no edges between the nodes in each layer. Data received at the nodes of the input layer of the feedforward network is propagated (i.e., "fed forward") to the nodes of the output layer via an activation function, which calculates the state of the nodes of each successive layer in the network based on coefficients ("weights"), which are respectively associated with each of the edges connecting these layers. Depending on the specific model represented by the algorithm being executed, the output from the neural network algorithm can take various forms.

[0152] Before a machine learning algorithm can be used to model a specific problem, the algorithm is trained using a training data set. Training a neural network involves: selecting a network topology; using a set of training data representing the problem being modeled by the network; and adjusting weights until the network model behaves with minimal error for all instances of the training data set. For example, during a supervised learning training process for a neural network, the output generated by the network in response to an input representing an instance in the training data set is compared to the "correct" labeled output for the instance; an error signal representing the difference between the output and the labeled output is calculated; and when the error signal is propagated back through the layers of the network, the weights associated with the connections are adjusted to minimize the error. The network is considered "trained" when the error for each output generated from an instance of the training data set is minimized.

[0153] The accuracy of a machine learning algorithm can be greatly affected by the quality of the data set used to train the algorithm. The training process can be computationally intensive and can take a significant amount of time on a conventional general purpose processor. Therefore, many types of machine learning algorithms are trained using parallel processing hardware. This is particularly useful for optimizing the training of neural networks, as the calculations performed when adjusting the coefficients in a neural network are naturally suited to parallel implementations. In particular, many machine learning algorithms and software applications have been adapted to use parallel processing hardware within general purpose graphics processing devices.

[0154] Figure 6is a generalized diagram of a machine learning software stack 600. Machine learning applications 602 may be configured to train a neural network using a training data set or to implement machine intelligence using a trained deep neural network. Machine learning applications 602 may include training and inference capabilities for a neural network and / or specialized software that may be used to train a neural network prior to deployment. Machine learning applications 602 may implement any type of machine intelligence, including but not limited to: image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation.

[0155] Hardware acceleration for machine learning applications 602 can be implemented via a machine learning framework 604. The machine learning framework 604 can provide a library of machine learning primitives. Machine learning primitives are basic operations that machine learning algorithms typically perform. Without the machine learning framework 604, developers of machine learning algorithms would be required to create and optimize the main computational logic associated with the machine learning algorithm, and then re-optimize the computational logic when a new parallel processor is developed. Instead, machine learning applications can be configured to use primitives provided by the machine learning framework 604 to perform necessary calculations. Exemplary primitives include tensor convolutions, activation functions, and pooling, which are computational operations performed when training a convolutional neural network (CNN). The machine learning framework 604 can also provide primitives for implementing basic linear algebra subroutines, such as matrix and vector operations, performed by many machine learning algorithms.

[0156] The machine learning framework 604 can process input data received from the machine learning application 602 and generate appropriate inputs to the computation framework 606. The computation framework 606 can abstract the underlying instructions provided to the GPGPU driver 608 so that the machine learning framework 604 can take advantage of hardware acceleration via the GPGPU hardware 610 without requiring the machine learning framework 604 to be intimately familiar with the architecture of the GPGPU hardware 610. In addition, the computation framework 606 can implement hardware acceleration for the machine learning framework 604 across multiple types and generations of GPGPU hardware 610.

[0157] GPGPU machine learning acceleration

[0158] Figure 7 A highly parallel general purpose graphics processing unit 700 is shown according to an embodiment. In one embodiment, a general purpose processing unit (GPGPU) 700 can be configured to be particularly efficient in processing the type of computational workload associated with training deep neural networks. In addition, GPGPU 700 can be directly linked to other instances of GPGPU for creating a multi-GPU cluster, thereby improving the training speed of particularly deep neural networks.

[0159] GPGPU 700 includes a host interface 702 for implementing a connection with a host processor. In one embodiment, host interface 702 is a PCI Express interface. However, the host interface can also be a supplier-specific communication interface or communication structure. GPGPU 700 receives commands from the host processor and uses a global scheduler 704 to distribute the execution threads associated with those commands to a group of computing clusters 706A to 706H. Computing clusters 706A to 706H share a cache memory 708. Cache memory 708 can act as a high-level cache in the cache memory within the computing clusters 706A to 706H.

[0160] GPGPU 700 includes memory 714A-714B, which is coupled to computing clusters 706A-H via a set of memory controllers 712A-712B. In various embodiments, memory 714A-714B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory (e.g., synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory). In one embodiment, memory units 224A-224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM).

[0161] In one embodiment, each computing cluster 706A to 706H includes a set of graphics multiprocessors, such as Figure 4A The graphics multiprocessor 400 of the computing cluster includes multiple types of integer and floating point logic units that can perform computational operations at a range of precisions, including precisions suitable for machine learning computations. For example and in one embodiment, at least a subset of the floating point units of each of the computing clusters 706A to H can be configured to perform 16-bit or 32-bit floating point operations, while a different subset of the floating point units can be configured to perform 64-bit floating point operations.

[0162] Multiple instances of GPGPU 700 can be configured to operate as a computing cluster. The communication mechanism used by the computing cluster for synchronization and data exchange varies across embodiments. In one embodiment, multiple instances of GPGPU 700 communicate through a host interface 702. In one embodiment, GPGPU 700 includes an I / O hub 708 that couples GPGPU 700 with a GPU link 710, which implements direct connection to other instances of GPGPU. In one embodiment, GPU link 710 is coupled to a dedicated GPU-GPU bridge, which implements communication and synchronization between multiple instances of GPGPU 700. In one embodiment, GPU link 710 is coupled to a high-speed interconnect for transmitting and receiving data to other GPGPUs or parallel processors. In one embodiment, multiple instances of GPGPU 700 are located in a separate data processing system and communicate via a network device, which can be accessed via a host interface 702. In one embodiment, in addition to host interface 702 or as an alternative to the host interface, GPU link 710 can also be configured to enable connection to a host processor.

[0163] Although the illustrated configuration of GPGPU 700 can be configured to train a neural network, one embodiment provides an alternative configuration of GPGPU 700 that can be configured for deployment in a high-performance or low-power inference platform. In the inference configuration, GPGPU 700 includes fewer computing clusters 706A to H relative to the training configuration. In addition, the memory technology associated with memory 714A to 714B may differ between the inference and training configurations. In one embodiment, the inference configuration of GPGPU 700 may support inference-specific instructions. For example, the inference configuration may provide support for one or more 8-bit integer dot product instructions, which are typically used during inference operations for deployed neural networks.

[0164] Figure 8 A multi-GPU computing system 800 is shown according to an embodiment. The multi-GPU computing system 800 may include a processor 802 coupled to a plurality of GPGPUs 806A to D via a host interface switch 804. In one embodiment, the host interface switch 804 is a PCI Express switch device that couples the processor 802 to a PCI Express bus, through which the processor 802 can communicate with the set of GPGPUs 806A to D. Each of the plurality of GPGPUs 806A to 806D may be Figure 7GPGPU 700 of the embodiment of the present invention. GPGPU 806A to D can be interconnected via a set of high-speed point-to-point GPU-GPU links 816. The high-speed GPU-GPU links can be connected via dedicated GPU links (e.g., Figure 7 806A-806D. The P2P GPU link 816 enables each of the GPGPUs 806A-806D to communicate directly with each other without having to communicate through a host interface bus (to which the processor 802 is connected). In the case where GPU-GPU traffic is directed to the P2P GPU link, the host interface bus can still be used for system memory access or communication with other instances of the multi-GPU computing system 800 (e.g., via one or more network devices). Although in the illustrated embodiment GPGPUs 806A-D are connected to the processor 802 via the host interface switch 804, in one embodiment, the processor 802 includes direct support for the P2P GPU link 816 and can be directly connected to the GPGPUs 806A-806D.

[0165] Machine Learning Neural Network Implementation

[0166] The computing architecture provided by the embodiments described herein can be configured to perform these types of parallel processing that are particularly suitable for training and deploying neural networks for machine learning. A neural network can be generalized as a network of functions with a graph relationship. As is well known in the art, there are many types of neural network implementations used in machine learning. One exemplary type of neural network is a feedforward network as previously described.

[0167] The second exemplary type of neural network is a convolutional neural network (CNN). CNN is a specialized feedforward neural network for processing data (e.g., image data) with a known, grid-like topology. Therefore, CNNs are commonly used in computer vision and image recognition applications, but they can also be used for other types of pattern recognition, such as speech and language processing. The nodes in the input layer of a CNN are organized into a set of "filters" (feature detectors inspired by the receptive field found in the retina), and the output of each set of filters is propagated to the nodes in the successive layers of the network. The calculations used for CNNs include applying a convolution mathematical operation to each filter to produce the output of the filter. Convolution is a specialized mathematical operation performed by two functions to produce a third function, which is a modified version of one of the two original functions. In convolutional network terminology, the first function about convolution can be called input, and the second function can be called a convolution kernel. The output can be called a feature map. For example, the input to a convolutional layer can be a multidimensional data array that defines the various color components of the input image. The convolution kernel can be a multidimensional parameter array, where the parameters are adapted by a training process for the neural network.

[0168] Recurrent neural networks (RNNs) are a class of feedforward neural networks that include feedback connections between layers. RNNs enable modeling of sequence data by sharing parameter data across different parts of the neural network. The architecture of RNNs includes loops. These loops represent the effect of the current value of a variable on its own value at a future time, because at least a portion of the output data from the RNN is used as feedback for processing subsequent inputs in the sequence. This feature makes RNNs particularly useful for language processing due to the mutable nature of language data that can be composed.

[0169] The figures described below present exemplary feedforward, CNN, and RNN networks, and describe the general process for training and deploying each of those types of networks, respectively. It will be understood that these descriptions are exemplary and non-limiting with respect to any specific embodiment described herein, and that the concepts presented can generally be applied to deep neural networks and machine learning techniques in general.

[0170] The exemplary neural network described above can be used to perform deep learning. Deep learning is machine learning performed using deep neural networks. In contrast to shallow neural networks that include only a single hidden layer, the deep neural networks used in deep learning are artificial neural networks composed of multiple hidden layers. Deeper neural networks are generally more computationally intensive to train. However, the additional hidden layers of the network enable multi-step pattern recognition, which results in reduced output errors relative to shallow machine learning techniques.

[0171] The deep neural network used in deep learning typically includes a front-end network for performing feature recognition coupled to a back-end network representing a mathematical model, which can perform operations (e.g., object classification, speech recognition, etc.) based on the feature representation provided to the model. Deep learning enables machine learning to be performed without the need to perform manual feature engineering for the model. In contrast, deep neural networks can learn features based on statistical structures or correlations within the input data. The learned features can be provided to a mathematical model, which can map the detected features to an output. The mathematical model used by the network is typically dedicated to a specific task to be performed, and different models will be used to perform different tasks.

[0172] Once a neural network is structured, a learning model can be applied to the network to train the network to perform a specific task. The learning model describes how to adjust the weights within the model to reduce the output error of the network. Back propagation of errors is a common method for training neural networks. An input vector is presented to the network for processing. The output of the network is compared to the desired output using a loss function, and an error value is calculated for each neuron in the output layer. These error values ​​are then propagated backward until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then learn from those errors using an algorithm (such as a stochastic gradient descent algorithm) to update the weights of the neural network.

[0173] Fig.9A 4 to 5 show exemplary convolutional neural networks. Fig.9A Show the various layers in CNN. Fig.9A As shown in , an exemplary CNN for modeling image processing can receive an input 902, which describes the red, green and blue (RGB) components of an input image. The input 902 can be processed by multiple convolutional layers (e.g., convolutional layer 904, convolutional layer 906). Optionally, the output from the multiple convolutional layers can be processed by a set of fully connected layers 908. The neurons in the fully connected layer have full connections to all activation functions in the previous layer, as previously described for feedforward networks. The output from the fully connected layer 908 can be used to generate output results from the network. Matrix multiplication can be used instead of convolution to calculate the activation function in the fully connected layer 908. Not all CNN implementations use the fully connected layer 908. For example, in some implementations, the convolutional layer 906 can generate the output of the CNN.

[0174] The convolutional layers are sparsely connected, which is different from the traditional neural network configuration found in the fully connected layer 908. Traditional neural network layers are fully connected so that each output unit interacts with each input unit. However, the convolutional layers are sparsely connected because the output of the convolution of the receptive field (rather than the corresponding state value of each node in the receptive field) is input to the nodes of the subsequent layer, as shown. The kernel associated with the convolutional layer performs a convolution operation, the output of which is sent to the next layer. The dimensionality reduction performed within the convolutional layer is one aspect that enables CNNs to scale to process large images.

[0175] Fig. 9B Exemplary computational stages within a convolutional layer of a CNN are shown. Input 912 to a convolutional layer of a CNN may be processed in three stages of a convolutional layer 914. The three stages may include a convolution stage 916, a detector stage 918, and a pooling stage 920. The convolutional layer 914 may then output data to a successive convolutional layer. The last convolutional layer of the network may generate output feature map data or provide input to a fully connected layer, for example to generate a classification value for input to the CNN.

[0176] Several convolutions are performed in parallel in the convolution stage 916 to produce a set of linear activation functions. The convolution stage 916 may include an affine transformation, which is any transformation that can be specified as a linear transformation plus a translation. Affine transformations include rotations, translations, scaling, and combinations of these transformations. The convolution stage calculates the output of a function (e.g., a neuron) connected to a specific region in the input, which can be determined as a local region associated with the neuron. The neuron calculates the dot product between the weight of the neuron and the region in the local input (the neuron is connected to the local input). The output from the convolution stage 916 defines a set of linear activation functions processed by the successive stages of the convolution layer 914.

[0177] The linear activation functions may be processed by the detector stage 918. In the detector stage 918, each linear activation function is processed by a non-linear activation function. The non-linear activation function increases the non-linear nature of the overall network without affecting the receptive field of the convolutional layer. Several types of non-linear activation functions may be used. One specific type is the rectified linear unit (ReLU), which uses an activation function defined as f(x) = max(0, x) such that the activation function is thresholded to zero.

[0178] The pooling stage 920 uses a pooling function that replaces the output of the convolutional layer 906 with a summary statistic of nearby outputs. The pooling function can be used to introduce translation invariance into the neural network so that a slight translation to the input does not change the pooled output. The invariance of local translation can be useful when the feature existence of the input data is more important than the precise location of the feature. Various types of pooling functions can be used during the pooling stage 920, including maximum pooling, average pooling, and L2 norm pooling. In addition, some CNN implementations do not include a pooling stage. On the contrary, such an implementation substitutes an additional convolution stage, which has an increased stride relative to the previous convolution stage.

[0179] The output from the convolutional layer 914 may then be processed by the next layer 922. The next layer 922 may be an additional convolutional layer or one of the fully connected layers 908. For example, Fig.9A The first convolution layer 904 can output to the second convolution layer 906, and the second convolution layer can output to the first layer in the fully connected layer 908.

[0180] Fig.10 An exemplary recurrent neural network 1000 is shown. In a recurrent neural network (RNN), the previous state of the network affects the output of the current state of the network. RNNs can be built in a variety of ways using a variety of functions. The use of RNNs generally revolves around the use of mathematical models to predict the future based on previous input sequences. For example, RNNs can be used to perform statistical language modeling to predict upcoming words given a previous word sequence. The shown RNN 1000 can be described as having the following: an input layer 1002, which receives an input vector; a hidden layer 1004, which is used to implement a recursive function; a feedback mechanism 1005, which is used to implement a 'memory' of previous states; and an output layer 1006, which is used to output a result. The RNN 1000 operates based on time steps. The state of the RNN at a given time step is affected based on the previous time step via the feedback mechanism 1005. For a given time step, the state of the hidden layer 1004 is defined by the previous state and the input at the current time step. At the initial input (x) of the first time step, the state of the hidden layer 1004 is defined by the previous state and the input at the current time step. 1 ) can be processed by the hidden layer 1004. The second input (x 2 ) can be used by the hidden layer 1004 to process the initial input (x 1 ) is used to process the state information determined during the period. The given state can be calculated as t =f(Ux t +Ws t-1), where U and W are parameter matrices. The function is typically nonlinear, such as a variant of the hyperbolic tangent function (Tanh) or a correction function f(x)=max(0,x). However, the specific mathematical function used in hidden layer 1004 may vary depending on the specific implementation details of RNN 1000.

[0181] In addition to the basic CNN and RNN networks described, variations of those networks can also be implemented. An example RNN variant is the long short-term memory (LSTM) RNN. LSTM RNN is able to learn long-term dependencies that may be necessary for processing longer language sequences. A variant of CNN is a convolutional deep belief network, which has a structure similar to that of a CNN and is trained in a manner similar to that of a deep belief network. A deep belief network (DBN) is a generative neural network consisting of multiple layers of stochastic (random) variables. Greedy unsupervised learning can be used to train DBN layer by layer. The learned weights of the DBN can then be used to provide a pre-trained neural network by determining a set of optimal initial weights for the neural network.

[0182] Fig.11 The training and deployment of a deep neural network is shown. Once a given network has been structured for a task, the neural network is trained using a training dataset 1102. Various training frameworks 1104 have been developed to enable hardware acceleration of the training process. For example, Figure 6 The machine learning framework 604 can be configured as a training framework 604. The training framework 604 can be hooked up to the untrained neural network 1106 and enable the untrained neural network to be trained to generate a trained neural network 1108 using the parallel processing resources described herein.

[0183] To start the training process, initial weights can be chosen randomly or by pre-training using a deep belief network. The training cycle is then performed in a supervised or unsupervised manner.

[0184] Supervised learning is a learning method in which training is performed as an arbitration operation, such as when the training data set 1102 includes inputs (which are paired with the expected outputs of the inputs), or when the training data set includes inputs with known outputs and the outputs of the neural network are manually graded. The network processes the inputs and compares the resulting outputs with a set of expected or desired outputs. Then, the error is back-propagated through the system. The training framework 1104 can be adjusted to adjust the weights of the untrained neural network 1106. The training framework 1104 can provide tools for monitoring the extent to which the untrained neural network 1106 converges to a model suitable for generating the correct answer based on the known input data. The training process occurs repeatedly when the weights of the network are adjusted to improve the output generated by the neural network. The training process can continue until the neural network reaches the statistically expected accuracy associated with the trained neural network 1108. Then, the trained neural network 1108 can be deployed to implement any number of machine learning operations.

[0185] Unsupervised learning is a learning method in which a network attempts to train itself using unlabeled data. Thus, for unsupervised learning, the training data set 1102 will include input data without any associated output data. The untrained neural network 1106 can learn groupings within the unlabeled inputs and can determine how individual inputs relate to the overall data set. Unsupervised training can be used to generate a self-organizing map, which is a type of trained neural network 1107 that can perform operations useful in data dimensionality reduction. Unsupervised training can also be used to perform anomaly detection, which allows identification of data points in the input data set that deviate from the normal pattern of the data.

[0186] Variations of supervised and unsupervised training may also be employed. Semi-supervised learning is a technique in which the training data set 1102 includes a mixture of labeled and unlabeled data of the same distribution. Incremental learning is a variation of supervised learning in which input data is continually used for further training the model. Incremental learning enables a trained neural network 1108 to adapt to new data 1112 without forgetting the knowledge embedded in the network during initial training.

[0187] Whether supervised or unsupervised, the training process for particularly deep neural networks may be too computationally intensive for a single computing node. The training process can be accelerated using a distributed network of computing nodes rather than a single computing node.

[0188] Fig.12is a block diagram illustrating distributed learning. Distributed learning is a training model that uses multiple distributed computing nodes to perform supervised or unsupervised training of a neural network. The distributed computing nodes may each include one or more host processors and one or more general processing nodes, such as Figure 7 A highly parallel general purpose graphics processing unit 700 in FIG. As shown, distributed learning can perform model parallelism 1202, data parallelism 1204, or a combination of model and data parallelism 1204.

[0189] In model parallelism 1202, different computing nodes in a distributed system can perform training computations for different parts of a single network. For example, each layer of a neural network can be trained by a different processing node of the distributed system. The benefits of model parallelism include the ability to scale to particularly large models. Splitting the computations associated with different layers of a neural network enables training of very large neural networks where the weights of all layers will not fit into the memory of a single computing node. In some instances, model parallelism can be particularly useful in performing unsupervised training of large neural networks.

[0190] In data parallelization 1204, different nodes of the distributed network have complete instances of the model, and each node receives a different part of the data. Then, the results from different nodes are combined. Although different methods for data parallelization are possible, data parallel training methods all require a technology for combining results and synchronizing model parameters between each node. Exemplary methods for combining data include parameter averaging and update-based data parallelization. Parameter averaging trains each node on a subset of the training data, and sets global parameters (e.g., weights, biases) to the average value of the parameters from each node. Parameter averaging uses a central parameter server that maintains parameter data. Update-based data parallelism is similar to parameter averaging, except that updates to the model are transmitted instead of parameters from the node being transmitted to the parameter server. In addition, update-based data parallelism can be performed in a decentralized manner, where updates are compressed and transmitted between nodes.

[0191] For example, the combined model and data parallelism 1206 can be implemented in a distributed system where each computing node includes multiple GPUs. Each node can have a complete instance of the model, with separate GPUs within each node used to train different parts of the model.

[0192] Distributed training has increased overhead relative to training on a single machine. However, the parallel processors and GPGPUs described herein can each implement various techniques for reducing the overhead of distributed training, including techniques for implementing high-bandwidth GPU-GPU data transfer and accelerated remote data synchronization.

[0193] Example Machine Learning Applications

[0194] Machine learning can be applied to solve a number of technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. Applications of computer vision range from reproducing human visual capabilities (e.g., recognizing faces) to creating new categories of visual capabilities. For example, computer vision applications can be configured to recognize sound waves from vibrations induced in objects visible in a video. Parallel processor-accelerated machine learning enables the use of significantly larger training data sets than previously feasible training data sets to train computer vision applications, and enables the use of low-power parallel processors to deploy inference systems.

[0195] Parallel processor-accelerated machine learning has autonomous driving applications, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train a driving model based on a data set that defines the appropriate response to a specific training input. The parallel processors described herein can enable rapid training of increasingly complex neural networks for autonomous driving solutions and enable the deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

[0196] Deep neural networks accelerated by parallel processors have enabled machine learning methods for automatic speech recognition (ASR). ASR involves creating a function that computes the most likely speech sequence given a sequence of input sounds. Accelerated machine learning using deep neural networks has been implemented to replace the hidden Markov models (HMMs) and Gaussian mixture models (GMMs) previously used for ASR.

[0197] Parallel processor accelerated machine learning can also be used to accelerate natural language processing. Automatic learning programs can use statistical inference algorithms to produce models that are robust to erroneous or unfamiliar inputs. Exemplary natural language processor applications include automatic machine translation between human languages.

[0198] Parallel processing platforms for machine learning can be divided into training platforms and deployment platforms. Training platforms are typically highly parallel and include optimizations for accelerating multi-GPU single-node training and multi-node multi-GPU training. Exemplary parallel processors suitable for training include Figure 7The highly parallel general purpose graphics processing unit 700 and Figure 8 The multi-GPU computing system 800 of FIG. In contrast, deployed machine learning platforms typically include low-power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

[0199] Fig.13 An exemplary inference system on chip (SOC) 1300 suitable for performing inference using a training model is shown. The SOC 1300 can integrate multiple processing components, including a media processor 1302, a visual processor 1304, a GPGPU 1306, and a multi-core processor 1308. The SOC 1300 can additionally include an on-chip memory 1305, which can implement a shared on-chip data pool accessible by each of the processing components. The processing components can be optimized for low-power operation to enable deployment to a variety of machine learning platforms (including autonomous vehicles and autonomous robots). For example, an implementation of the SOC 1300 can be used as part of a master control system for an autonomous vehicle. In the case where the SOC 1300 is configured for use in an autonomous vehicle, the SOC is designed and configured to comply with the relevant functional safety standards of the deployment jurisdiction.

[0200] During operation, the media processor 1302 and the visual processor 1304 can work in unison to accelerate computer vision operations. The media processor 1302 can enable low-latency decoding of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in the on-chip memory 1305. The visual processor 1304 can then parse the decoded video and perform preliminary processing operations on the frames of the decoded video in preparation for processing the frames using the trained image recognition model. For example, the visual processor 1304 can accelerate convolution operations for CNN (for performing image recognition on high-resolution video data), while the back-end model calculations are performed by the GPGPU 1306.

[0201] The multi-core processor 1308 may include control logic for facilitating the sequencing and synchronization of data transfers and shared memory operations performed by the media processor 1302 and the vision processor 1304. The multi-core processor 1308 may also act as an application processor for executing software applications that may use the inference computing capabilities of the GPGPU 1306. For example, at least a portion of navigation and driving logic may be implemented in software executing on the multi-core processor 1308. Such software may issue computational workloads directly to the GPGPU 1306, or may issue computational workloads to the multi-core processor 1308, which may offload at least a portion of those operations to the GPGPU 1306.

[0202] GPGPU 1306 may include a computing cluster, such as a low-power configuration of computing clusters 706A to 706H within a highly parallel general purpose graphics processing unit 700. The computing cluster within GPGPU 1306 may support instructions that are explicitly optimized for performing inference calculations on trained neural networks. For example, GPGPU 1306 may support instructions for performing low-precision calculations (e.g., 8-bit and 4-bit integer vector operations).

[0203] Dedicated fixed-function hardware for efficient convolution

[0204] The embodiments described herein provide high-order machine learning computing primitives that can be used to abstract many of the underlying computational details of performing machine learning computations. The high-order primitives described herein enable software logic to request high-order machine learning operations while abstracting the underlying implementation details of those operations. For example and in one embodiment, software logic may request to perform a convolution operation on an image using a given set of filters. A single high-order instruction may be executed, the high-order instruction having operands for defining input and output buffer addresses and addresses of buffers storing filter and / or kernel data. The GPGPU may then divide the high-order convolution instruction into multiple sub-operations performed by the underlying computational units of the GPGPU. In one embodiment, direct hardware support is provided for one or more subroutines of the basic linear arithmetic subroutines (BLAS), although embodiments may provide hardware support for other libraries of subroutines. The compiler logic and associated runtime libraries may compile source code that uses the supported high-order computational subroutines, and output calls to the compiled source code placed in the machine learning macroinstruction unit.

[0205] Machine learning acceleration logic with automatic hardware selection for convolutional logic

[0206] Fig.1414 is a block diagram of a data processing system 1400 according to an embodiment. The data processing system 1400 is a heterogeneous processing system having a processor 1402, a unified memory 1410, and a GPGPU 1420 including machine learning acceleration logic. The processor 1402 and the GPGPU 1420 may be any of a processor and a GPGPU / parallel processor as described herein. The processor 1402 may execute instructions for a compiler 1415 stored in a system memory 1412. The compiler 1415 is executed on the processor 1402 to compile a source code 1414A into a compiled code 1414B. The compiled code 1414B may include code that may be executed by the processor 1402 and / or code that may be executed by the GPGPU 1420. During compilation, the compiler 1415 may perform operations for inserting metadata, including hints about the degree of data parallelism present in the compiled code 1414B and / or hints about data locality associated with threads to be dispatched based on the compiled code 1414B. Compiler 1415 may include the information necessary to perform such operations, or may perform these operations with the help of runtime library 1416. Runtime library 1416 may also facilitate compiler 1415 to compile source code 1414A, and may also include instructions that are associated with compiled code 1414B at runtime to facilitate execution of the compiled instructions on GPGPU 1420.

[0207] Unified memory 1410 represents a unified address space accessible by processor 1402 and GPGPU 1420. Unified memory includes system memory 1412 and GPGPU memory 1418. GPGPU memory 1418 includes GPGPU local memory 1428 within GPGPU 1420, and may also include some or all of system memory 1412. For example, compiled code 1414B stored in system memory 1412 may also be mapped into GPGPU memory 1418 for access by GPGPU 1420.

[0208] GPGPU 1420 includes a plurality of computing blocks 1424A to 1424N, which may be Figure 6 and Figure 71420. GPGPU 1420 also includes a set of registers 1424, a cache memory 1426, and a power and performance module 1425, which can be used as a shared resource for computing blocks 1424A to 1424N. The power and performance module 1425 can be configured to adjust the power delivery and clock frequency of computing blocks 1424A to 1424N to power idle components within computing blocks 1424A to 1424N under heavy workloads. GPGPU 1420 includes GPGPU local memory 1428, which is physical memory that shares a graphics card or multi-chip module with GPGPU 1420.

[0209] In one embodiment, GPGPU 1420 includes machine learning acceleration logic, including a machine learning instruction acquisition and decoding unit 1421, a machine learning scheduler unit 1422, and a machine learning fixed function unit 1423. The machine learning instruction acquisition and decoding unit 1421 is an acquisition and decoding unit that includes logic for acquiring and decoding machine learning macro instructions that define complex behaviors. The macro instructions can be sequenced and / or serialized via the machine learning scheduler unit 1422 to be executed via the computing blocks 1424A to 1424N and / or the machine learning fixed function unit 1423.

[0210] In one embodiment, the machine learning fixed function unit 1423 is an application specific integrated circuit that is explicitly and exclusively configured to perform a large number of parallel matrix multiplication operations. In one embodiment, the machine learning fixed function unit 1423 is configured to perform matrix multiplication for convolution filters with non-quadratic filter sizes. In one embodiment, the machine learning fixed function unit 1423 is a field programmable gate array (FPGA) that provides fixed function logic that can be updated between workloads.

[0211] Fig.15Details of the machine learning instruction and acquisition unit 1421 according to an embodiment are shown. In one embodiment, the machine learning instruction acquisition & decoding unit 1421 includes a cache memory 1502, a machine learning instruction acquisition unit 1504, and a machine learning instruction decoding unit 1506. The machine learning instruction acquisition unit 1504 can acquire one or more machine learning macroinstructions and store the macroinstructions in the cache memory 1502. The machine learning instruction decoding unit 1506 can decode the machine learning macroinstructions and determine a set of operations to be performed in response. In one embodiment, the machine learning instruction acquisition and decoding unit 1421 includes a microcontroller 1510 for implementing complex operations, such as selecting one of multiple techniques for performing a specific machine learning operation (e.g., a convolution operation). The microcontroller 1510 can also determine whether to perform operations for macroinstructions via programmable logic within the GPGPU or via dedicated machine learning logic within the GPGPU.

[0212] In one embodiment, the microcontroller 1510 may load firmware logic from the machine learning firmware module 1508 to define operations to be performed in response to machine learning macros. In one embodiment, the machine learning firmware module 1508 may be updated via the driver logic of the GPGPU to expand a set of operations supported via machine learning macros and / or expand the capabilities of supported macros. In one embodiment, the microcontroller 1510 implements explicit support for convolution operations via convolution acceleration logic 1516.

[0213] The calculations for CNNs include applying a convolution mathematical operation to each filter to produce the output of the filter. Each filter is a kernel with trainable weights that is convolved across the width and height of the input volume to calculate the dot product between the entries of the filter and the input at any location. When the filter is convolved on the input volume, a two-dimensional activation map is generated to indicate the filter response at each spatial location. An activation map is generated for each filter applied to the input volume. The filter size used within a CNN can vary based on the implementation details of the neural network.

[0214] In one embodiment, the convolution parameter analysis logic 1512 can analyze the parameters of the requested convolution operation. The convolution operation has two inputs, input data and a convolution filter. The input data includes a batch of image data having H×W pixels and C number of input feature maps. The convolution filter has R rows and S columns. In one embodiment, the convolution parameter analysis logic 1512 determines whether to perform at least a portion of the convolution via dedicated convolution logic based on the size R×S of the convolution filter, for example, whether the size of the convolution filter indicates that the convolution will be performed less efficiently via the GPGPU programmable logic. In one embodiment, based on the convolution parameters (including the convolution filter size, the input image or feature map size, and the current operating indicators of the GPGPU collected via the GPGPU resource monitor 1514), the convolution acceleration logic 1516 can select an algorithm for performing the requested convolution operation.

[0215] For example, the convolution acceleration logic 1516 can be configured to select one of several possible algorithms for implementing convolution. In one embodiment, convolution is performed via convolution based on fast Fourier transform (FFT). FFT convolution uses the following principle: multiplication in the frequency domain corresponds to convolution in the time domain. Therefore, the Fourier transform of the convolution of two functions is the product of the Fourier transforms of those functions. The input data can be transformed into the frequency domain using a discrete Fourier transform (DFT), multiplied by the frequency response of the filter, and then transformed back into the time domain using an inverse DFT. For example and in one embodiment, for convolution using a smaller filter size (e.g., 1×1, 3×3), Winograd's minimum filtering algorithm can be used to perform convolution. Larger filter sizes (e.g., 4×4) can be performed via other FFT algorithms. Convolution for even larger filter sizes (5×5, 7×7) can be performed via dedicated fixed-function convolution hardware. Alternatively, direct convolution can be performed in the original domain of the data using batched matrix operations via hardware acceleration of the general matrix multiplication (GEMM) subroutine.

[0216] Fig.16 An exemplary convolution operation according to an embodiment is shown. Input volume buffer 1604 represents a 2D channel of input data. Although a 2D convolution is shown, a three-dimensional filter can also be used to perform convolution on a three-dimensional volume of the input. Receptive field tile 1602 highlights a portion of the input volume. A dot product is performed between the data within the receptive field tile 1602 and the convolution filter to generate data points within the output buffer 1606. The combination of data points within the output buffer 1606 represents an activation map generated by the convolution. Each point within the activation map is generated by sliding the receptive field tile across the input volume 1604. The activation map data can be input to an activation function to determine an output activation value.

[0217] In one embodiment, the convolution of the input volume buffer 1604 is performed via a set of high-order matrix operations 1605. The high-order matrix operations can be performed via primitive operations, such as BLAS operations, which are accelerated via macro instructions that can be decoded via the machine learning instruction fetch and decode unit 1421. The machine learning instruction fetch and decode unit 1421 can dispatch operations to the machine learning scheduler unit 1322 for scheduling. These operations can then be dispatched to the machine learning fixed function unit 1423 or one or more computation blocks 1424A to 1424N.

[0218] Fig.17 is a flow chart of logic 1700 for selecting a convolution implementation according to an embodiment. In one embodiment, the convolution implementation may be selected as in Figure 14 to Figure 15 The logic 1700 may be implemented by hardware within the machine learning instruction acquisition and decoding unit 1421 in the GPGPU. The logic 1700 may acquire and decode a convolution macroinstruction to be executed within the GPGPU, as shown at block 1702. A convolution macroinstruction is an instruction that specifies a set of multiple other instructions or microinstructions to be executed by the computing hardware of the data processing system described herein. The logic 1700 may then analyze the convolution parameters of the convolution macroinstruction at block 1704, for example, via Fig.15 The convolution parameter analysis logic 1512 in FIG. Then, the logic 1700 can be performed as follows: Fig.15 The GPGPU resource monitor 1514 in samples the hardware resource utilization from the GPGPU performance counters, as shown at block 1706. The logic 1700 can then select a convolution implementation based on the convolution parameters and the resource utilization, as shown at block 1708. For example, a first subset of available convolution implementations can be computationally intensive and memory efficient. A second subset of available implementations can be computationally efficient and memory intensive. Based on the computational or memory load of the GPGPU analysis consistent with the convolution parameters, a specific convolution implementation can be selected to maximize overall system efficiency. In one embodiment, if the convolution parameters suggest a convolution implementation that is less efficient than an alternative convolution implementation based on current GPGPU computation and / or memory utilization, then the alternative convolution implementation can be used, at least until the computation and / or memory utilization indicators suggest that a more resource-intensive algorithm can be efficiently used. However, some convolution parameters suggest that a dedicated fixed function unit (e.g., Fig.14 and Fig.16 The machine learning fixed function unit 1423 in the FPGA is most likely to achieve the best performance.

[0219] Fig.18is a flow chart showing logic 1800 for selecting between general purpose logic and fixed function logic, according to an embodiment. Fig.15 The logic 1800 shown is executed by the convolution parameter analysis logic 1512 and the convolution acceleration logic 1516 in the convolution macroinstruction to determine the logic unit to which the convolution operation will be directed. In one embodiment, the logic 1800 can determine a set of operations to be performed for the convolution macroinstruction, as shown at 1802. Then, the logic 1800 can analyze the parameters of this set of operations to determine the computing module to which the operations will be scheduled, as shown at block 1804. Various parameters can be analyzed, including the size of the input image data, the number of data channels of the image data, the number of filters to be applied, and the size of the filters within a set of filters (e.g., minimum, maximum, average). In one embodiment, the determination is a multi-axis, multi-dimensional determination, where the filter size is an element that can be used to determine the logic unit to receive a set of convolution operations. The logic 1800 can determine whether the size of a given filter is above a threshold at block 1805. In one embodiment, the threshold is determined based on the maximum width of the SIMD logic used to implement this set of operations and / or the maximum width of the underlying instructions used to perform those operations. In one embodiment, the filter size threshold may vary based on the size of the element storing data for the neural network (e.g., FP16, FP32, etc.). If the filter size is below the threshold at block 1805, the logic 1800 may perform the set of operations via a general purpose GPGPU compute block, as shown at block 1806. If the filter size is above the threshold at block 1805, the logic 1800 may perform the set of operations via a fixed function unit at block 1808.

[0220] Efficient matrix multiplication for convolution on GPGPU

[0221] The embodiments described herein implement hardware acceleration for high-order matrix multiplication operations on GPGPU. In one embodiment, high-order convolution macroinstructions are decomposed into standard instructions provided by the instruction set architecture of the GPGPU. Such instructions can be scheduled as multiple threads on the GPGPU. For multi-element instructions with operands of arrays or vectors of specified input elements, multiple simultaneous threads can be assigned to computing units in the GPGPU. The multiple threads can be executed as thread groups on the underlying SIMD hardware of the GPGPU.

[0222] Fig.19A A portion of a convolution operation performed via a programmable computing unit according to an embodiment is shown. The operation shown is in response to Fig.161605 is shown in the figure and acts on the receptive field tile 1602 of the input volume buffer 1604. When a 4×4 filter 1902 is used, a portion of the convolution operation can be performed by calculating the dot product between the 16 elements within the 4×4 receptive field tile 1602 and the 4×4 filter 1902. A group of SIMT threads 1904 can be generated for each element, and the SIMT threads can be executed simultaneously using 16-element vector dot product logic (DOT 16) 1906. The 16-element vector dot product logic 1906 can then dispatch the instructions of the thread to four underlying fused multiply-add or fused multiply-accumulate units (FMA 1908A to 1908D).

[0223] Fig.19B 1 shows a fixed function matrix multiplication logic 1900 according to an embodiment. The fixed function matrix multiplication logic 1900 may be as follows: Fig.14 and Fig.16 The fixed-function matrix multiplication logic 1900 is a portion of the machine learning fixed-function unit 1423 in FIG. The fixed-function matrix multiplication logic 1900 is an example of hardware logic included in one embodiment, and other embodiments may use different fixed-function implementations. In addition, various embodiments may use various techniques to implement the fixed-function matrix multiplication logic 1900. In one embodiment, the fixed-function matrix multiplication logic 1900 is included in an ASIC embedded in a general-purpose graphics processing unit. In one embodiment, the fixed-function matrix multiplication logic 1900 is implemented via an FPGA coupled to a general-purpose graphics processing unit.

[0224] Fixed function matrix multiplication logic 1900 can be configured to perform a variety of matrix operations to produce vector and scalar product outputs. In one embodiment, fixed function matrix multiplication logic 1900 is implemented as a systolic array matrix operation unit, which is constructed by multiple blocks of repeated logic units that process multiple matrix elements simultaneously. In one embodiment, each block of fixed function matrix multiplication logic 1900 includes input element row element 1911, input column element 1915, multiplication accumulation logic unit 1912 and output element 1913. Multiple rows of input column data are provided via column buffer 1914. During output to the output matrix, a row of output data can be temporarily stored in row output buffer 1916. The logic shown can be configured to perform matrix multiplication between two multidimensional matrices. Input data can be moved in and out of row and column input elements, and the data in those elements is processed by multiplication accumulation logic unit afterwards. Then, output data can be moved out via output data element. An N×N logic unit is shown, where the specific size of the fixed-function matrix multiplication logic 1900 varies across embodiments. In one embodiment, the fixed-function matrix multiplication logic 1900 is sized to perform matrix operations for specific matrix sizes that would be inefficient to process using a programmable logic unit (e.g., matrix operations associated with 5×5 or 7×7 convolutions).

[0225] Fig. 20Exemplary multiply-add logic 2001 within an embodiment is shown. Although fused multiply-add is generally described with respect to floating point operations, the combined multiply-add operations are not limited to floating point operations, and the logic can be configured to perform integer and / or fixed point operations. Multiply-add operations can be performed on multiple data elements in the same number of clock cycles as a single multiply on uncompressed data. The multiply-add logic accepts multiple inputs, including source 1 [63:0] 2031, source 2 [63:0] 2033, and enable 2080. Operation control 2002 processes the input control signals of the multiply-add logic 2001 and provides an enable 2080 input for activating the multiply-add logic 2011. The multiply-add logic 2001 includes four 16×16 multiplier circuits (e.g., 16×16 multiplier A 2010A, 16×16 multiplier B 2010B, 16×16 multiplier C 2010C, and 16×16 multiplier D 2010D). The 32-bit intermediate results generated by the 16×16 multiplier A 2010A and the 16×16 multiplier B 2010B are received by the adder 2020A, while the 32-bit intermediate results generated by the 16×16 multiplier C 2010C and the 16×16 multiplier D 2010D are received by the adder 2020B. The output of adder 2020B (i.e., bits 31 to 0 of the result) and the output of adder 2020A (i.e., bits 63 to 32 of the result) are combined into a 64-bit result and communicated to result register 2030. In one embodiment, each of adder 2051 and adder 2050 consists of an 8-bit adder with appropriate propagation extension. However, alternative embodiments may implement adders 2020A-2020B in any number of ways (e.g., two 32-bit adders and / or redundant arithmetic compression circuitry).

[0226] Fig.21 A 1×1 convolution is shown performed on an embodiment described herein. Given an input of size H×W and having C channels, a 1×1 convolution with K features produces a new image of size H×W for each of the K features. Each of the K features consists of C filters, which are scalar values ​​for the 1×1 convolution. The convolution of an input image with a feature is the convolution sum of the individual channels with the corresponding filters that make up the feature. In one embodiment, the 1×1 convolution can be efficiently performed via macros to order multiple operations for performing a 1×1 convolution on an input volume. The state weight vector 2104 can store the weights of the 1×1 convolution filters.

[0227] The number of weights that can be stored can be determined based on the precision of each of the individual weight values ​​and the size of the static weight vector. For example and in one embodiment, 16 8-bit weight values ​​are stored in a 128-bit weight vector 2104. In such an embodiment, the static weight vector 2104 can also store eight 16-bit weight values. Depending on the SIMD width of the underlying computing logic, channel data batches 2106 can be selected for input to the SIMD computing unit. The dot product between the weight channel data batches and a set of feature data channels 2108 within the input volume 2110 can be performed. A set of operations are automatically sorted to perform a 1×1 convolution operation across the input volume 2110.

[0228] Fig.23 An exemplary 1×1 convolution logic 2300 for implementing sequential 1×1 convolution is shown in FIG. Fig.15 The convolution acceleration logic 1516 of the convolution logic 2300 is used to perform the 1×1 convolution logic 2300. In one embodiment, the 1×1 convolution logic 2300 can load the weights of the 1×1 convolution filter into a vector register configured to store the static weight vector 2104, as shown at block 2302. The vector register can be a large register, such as a 256-byte or 512-byte register. If all the weights of the convolution filter cannot be stored in the static weight vector 2104, the convolution logic 2300 can load the first N weights, where N is the number of elements that can be stored in the register for storing the static weight vector 2104 (e.g., sixteen 16-bit weight values ​​for a 256-bit static weight vector 2104 width, sixteen 8-bit weight values ​​for a 128-bit weight vector 2104 width). The same number of N elements can be loaded into a second vector register (the second vector register stores data from a set of values ​​of the feature data channel 2108 at a position (x, y) within the input volume 2110), as shown at block 2304. The precision of the feature data channel can be the same as the precision of the weight data channel batch 2106, or can have different precision. For example, the values ​​from the feature data channel 2108 can be 16 bits, while the weight data is 8 bits. The values ​​from the feature data channel 2108 can be 8 bits, while the weight values ​​can be 1-bit bipolar binary (-1, +1) or 2-bit ternary (-1, 0, +1) values.

[0229] A subset of feature data and weight values ​​may be processed via dot product logic, as shown at block 2306. The number of dot product and accumulation operations required to process the entire data set is based on the ratio of weights to feature vectors and the number of elements that can be processed by the dot product logic within the GPGPU computing element. In one embodiment, the number of elements within the weight channel data batch 2106 corresponds to the number of elements that can be processed by the underlying SIMD hardware in a single instruction. In one embodiment, the weight channel data batch 2106 may slide down the static weight vector 2104 during each dot product to multiply all weight values ​​of the 1×1 convolution filter with the value of the feature data channel. Additional sliding operations may be performed to capture all values ​​of the feature data channel 2018. If all channels of weight values ​​have been multiplied by the corresponding feature data channel located at the position determined as in block 2307, the 1×1 convolution logic 2300 may output the value of the accumulator register as the output feature map value of the position, as shown at block 2312. The logic 2300 may then load the feature data channels 2108 for the next position (e.g., x+1, y), as shown at block 2314, and may begin performing additional dot products at block 2306. If dot products are not performed for all data values ​​at the position at block 2307, then intermediate values ​​may be stored in an accumulation register, and the logic 2300 may select a next subset of values ​​at block 2311, such as by sliding a batch 2106 of weight channel data along a static weight vector 2104 and loading a new batch 2106 of weight channel data into an input register for processing by the dot product logic using a previously processed set of feature data channels 2108.

[0230] Embodiments described herein may use combined or fused multiply-add logic of various designs to perform multiply-add operations. Fig. 22 A circuit 2201 for performing a multiply-add operation on a compressed data vector according to an embodiment is shown. The circuit 2201 accepts a first source (source 1 [63:0] 2231) and a second source (source 2 [63:0] 2232). In one embodiment, the first and second sources are stored in N-bit long SIMD registers within the GPGPU. For two input vectors 2231 and 2232, a multiply-add instruction implemented on such a register will produce a result [63:0] 2290, which can be stored in a destination register or added to an accumulation register for a multiply-accumulate operation. The logic example shown shows an 8-bit byte to 16-bit word embodiment of a multiply-add operation. Although the compressed data source and destination are represented as having 64 bits, it will be appreciated that the principles disclosed herein can be extended to other conveniently selected lengths, such as 80 bits, 128 bits, or 256 bits.

[0231] For an alternative embodiment, the source register with unsigned data is also the destination register with a 16-bit multiply-accumulate result, although convolution operations typically work on floating point or signed integer data. Operation control 2200 outputs enable signal 2280 for controlling operations performed by packed multiplier-accumulator circuit 2201. In one embodiment, operation control 2200 includes a decoder and instruction pointer register or additional circuitry not necessary for understanding the embodiments described herein.

[0232] The multiplication and addition circuit 2201 includes 8×8 multipliers 2202 to 8×8 multipliers 2209. The 8×8 multiplier 2202 has an 8-bit input A0 of source 1 2231 and an 8-bit input B0 of source 2 2233. The 8×8 multiplier 2203 has 8-bit inputs A1 and B1. The 8×8 multiplier 2204 has 8-bit inputs A2 and B2. The 8×8 multiplier 2205 has 8-bit inputs A3 and B3. The 8×8 multiplier 2206 has 8-bit inputs A4 and B4. The 8×8 multiplier 2207 has 8-bit inputs A5 and B5. The 8×8 multiplier 2208 has 8-bit inputs A6 and B6. The 8×8 multiplier 2209 has 8-bit inputs A7 and B7. The 16-bit intermediate result generated by the 8×8 multiplier 2202 and the 8×8 multiplier 2203 is received by adder 2252, the 16-bit intermediate result generated by the 8×8 multiplier 2204 and the 8×8 multiplier 2205 is received by adder 2254, the 16-bit intermediate result generated by the 8×8 multiplier 2206 and the 8×8 multiplier 2206 is received by adder 2256, and the 16-bit intermediate result generated by the 8×8 multiplier 2208 and the 8×8 multiplier 2209 is received by adder 2258. The output of adder 2252 (i.e., bits 15 to 0 of the result), the output of adder 2254 (i.e., bits 31 to 16 of the result), the output of adder 2256 (i.e., bits 47 to 32 of the result), and the output of adder 2258 (i.e., bits 63 to 48 of the result) are combined into a 64-bit compressed result and communicated to result [63:0] 2290.

[0233] Alternative embodiments may include instances of the multiply-add circuit 2201 that support instructions for 16-bit signed word pairs for producing 32-bit signed products. In some embodiments, the multiply-add circuit 2201 supports saturated results. In some embodiments, the multiply-add circuit 2201 may truncate the result.

[0234] Details of the embodiments described above may be included in the graphics processing systems and apparatus described below. Figures 24 to 37 The graphics processing systems and devices of exemplify alternative systems and graphics processing hardware that can implement any and all of the techniques described above.

[0235] Fig.242400 is a block diagram of a processing system 2400 according to an embodiment. In various embodiments, the system 2400 includes one or more processors 2402 and one or more graphics processors 2408, and may be a single processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 2402 or processor cores 2407. In one embodiment, the system 2400 is a processing platform incorporated into a system on a chip (SoC) integrated circuit for use in a mobile device, handheld device, or embedded device.

[0236] Embodiments of system 2400 may include or incorporate a server-based game platform, a game console, including a game and media console, a mobile game console, a handheld game console, or an online game console. In some embodiments, system 2400 is a mobile phone, a smart phone, a tablet computing device, or a mobile Internet device. Data processing system 2400 may also include a wearable device (such as a smart watch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device), coupled with the wearable device, or integrated in the wearable device. In some embodiments, data processing system 2400 is a television or set-top box device having one or more processors 2402 and a graphical interface generated by one or more graphics processors 2408.

[0237] In some embodiments, one or more processors 2402 each include one or more processor cores 2407 for processing instructions, and the instructions perform the operation of the system and user software when executed. In some embodiments, each processor core in the one or more processor cores 2407 is configured to process a specific instruction set 2409. In some embodiments, the instruction set 2409 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or calculation via very long instruction words (VLIW). Multiple processor cores 2407 can each process different instruction sets 2409, and the instruction set may include instructions for facilitating emulation of other instruction sets. The processor core 2407 may also include other processing devices, such as a digital signal processor (DSP).

[0238] In some embodiments, the processor 2402 includes a cache memory 2404. Depending on the architecture, the processor 2402 may have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among the components of the processor 2402. In some embodiments, the processor 2402 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), and known cache coherence techniques may be used to share the external cache among the processor core 2407. Additionally, a register file 2406 is included in the processor 2402, which may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general purpose registers, while other registers may be specific to the design of the processor 2402.

[0239] In some embodiments, the processor 2402 is coupled to a processor bus 2410, which is used to transmit communication signals, such as address, data, or control signals, between the processor 2402 and other components within the system 2400. In one embodiment, the system 2400 uses an exemplary 'hub' system architecture, including a memory controller hub 2416 and an input-output (I / O) controller hub 2430. The memory controller hub 2416 facilitates communication between memory devices and other components of the system 2400, while the I / O controller hub (ICH) 2430 provides connections to I / O devices via a local I / O bus. In one embodiment, the logic of the memory controller hub 2416 is integrated within the processor.

[0240] The memory device 2420 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device having suitable properties for use as processing memory. In one embodiment, the memory device 2420 may operate as system memory for the system 2400 to store data 2422 and instructions 2421 for use when one or more processors 2402 execute applications or processes. The memory controller hub 2416 is also coupled to an optional external graphics processor 2412, which may communicate with one or more graphics processors 2408 in the processor 2402 to perform graphics and media operations.

[0241] In some embodiments, the ICH 2430 enables peripheral components to be connected to the memory devices 2420 and the processor 2402 via a high-speed I / O bus. The I / O peripherals include, but are not limited to, an audio controller 2446, a firmware interface 2428, a wireless transceiver 2426 (e.g., Wi-Fi, Bluetooth), a data storage device 2424 (e.g., a hard drive, flash memory, etc.), and a traditional I / O controller 2440 for coupling traditional (e.g., Personal System 2 (PS / 2)) devices to the system. One or more Universal Serial Bus (USB) controllers 2442 connect multiple input devices, such as a keyboard and mouse 2444 combination. A network controller 2434 may also be coupled to the ICH 2430. In some embodiments, a high-performance network controller (not shown) is coupled to the processor bus 2410. It should be understood that the system 2400 shown is exemplary and not limiting, as other types of data processing systems configured in different ways may also be used. For example, I / O controller hub 2430 may be integrated within one or more processors 2402 , or memory controller hub 2416 and I / O controller hub 2430 may be integrated within a discrete external graphics processor, such as external graphics processor 2412 .

[0242] Fig.25 is a block diagram of an embodiment of a processor 2500 having one or more processor cores 2502A- 2502N, an integrated memory controller 2514, and an integrated graphics processor 2508. Fig.25 Those elements having the same reference number (or name) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. Processor 2500 may include additional cores up to and including additional core 2502N represented by a dashed box. Processor cores 2502A to 2502N each include one or more internal cache units 2504A to 2504N. In some embodiments, each processor core may also access one or more shared cache units 2506.

[0243] Internal cache units 2504A to 2504N and shared cache unit 2506 represent a cache memory hierarchy within processor 2500. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level of cache is classified as LLC before external memory. In some embodiments, cache coherence logic maintains coherence between each cache unit 2506 and 2504A to 2504N.

[0244] In some embodiments, the processor 2500 may also include a set of one or more bus controller units 2516 and a system agent core 2510. The one or more bus controller units 2516 manage a set of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, PCI Express). The system agent core 2510 provides management functions for each processor component. In some embodiments, the system agent core 2510 includes one or more integrated memory controllers 2514 for managing access to each external memory device (not shown).

[0245] In some embodiments, one or more of the processor cores 2502A to 2502N include support for simultaneous multithreading. In such embodiments, the system agent core 2510 includes components for coordinating and operating the cores 2502A to 2502N during multithreading. In addition, the system agent core 2510 may also include a power control unit (PCU) including logic and components for adjusting the power state of the processor cores 2502A to 2502N and the graphics processor 2508.

[0246] In some embodiments, in addition, the processor 2500 also includes a graphics processor 2508 for performing graphics processing operations. In some embodiments, the graphics processor 2508 is coupled to a set of shared cache units 2506 and a system agent core 2510, which includes one or more integrated memory controllers 2514. In some embodiments, a display controller 2511 is coupled to the graphics processor 2508 to drive the graphics processor output to one or more coupled displays. In some embodiments, the display controller 2511 can be a separate module coupled to the graphics processor via at least one interconnect, or can be integrated within the graphics processor 2508 or the system agent core 2510.

[0247] In some embodiments, a ring-based interconnect unit 2512 is used to couple the internal components of the processor 2500. However, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies, including those well known in the art. In some embodiments, the graphics processor 2508 is coupled to the ring interconnect 2512 via an I / O link 2513.

[0248] Exemplary I / O link 2513 represents at least one of a plurality of varieties of multiple I / O interconnects, including a package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 2518 (such as an eDRAM module). In some embodiments, each of processor cores 2502A to 2502N and graphics processor 2508 use embedded memory module 2518 as a shared last-level cache.

[0249] In some embodiments, the processor cores 2502A to 2502N are homogeneous cores that execute the same instruction set architecture. In another embodiment, the processor cores 2502A to 2502N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more of the processor cores 2502A to 2502N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, the processor cores 2502A to 2502N are homogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In addition, the processor 2500 can be implemented on one or more chips or as a SoC integrated circuit having the components shown in addition to other components.

[0250] Fig.26 26 is a block diagram of a graphics processor 2600, which may be a discrete graphics processing unit or may be a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates with memory via a mapped I / O interface to registers on the graphics processor and using commands placed in processor memory. In some embodiments, the graphics processor 2600 includes a memory interface 2614 for accessing memory. The memory interface 2614 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0251] In some embodiments, the graphics processor 2600 also includes a display controller 2602 for driving display output data to a display device 2620. The display controller 2602 includes hardware for one or more overlapping planes of the display and a composition of multiple layers of video or user interface elements. In some embodiments, the graphics processor 2600 includes a video codec engine 2606 for encoding, decoding, or media code conversion to, from, or between one or more media coding formats, including but not limited to: Moving Picture Experts Group (MPEG) (such as MPEG-2), Advanced Video Coding (AVC) format (such as H.264 / MPEG-4 AVC), and Society of Motion Picture & Television Engineers (SMPTE) 421M / VC-1, and Joint Photographic Experts Group (JPEG) format (such as JPEG, and Motion JPEG (MJPEG) format).

[0252] In some embodiments, graphics processor 2600 includes a block image transfer (BLIT) engine 2604 for performing two-dimensional (2D) rasterizer operations including, for example, bit-boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 2610. In some embodiments, GPE 2610 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0253] In some embodiments, GPE 2610 includes a 3D pipeline 2612 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 2612 includes programmable and fixed functional elements that perform various tasks within the elements and / or generated execution threads to 3D / media subsystem 2615. Although 3D pipeline 2612 can be used to perform media operations, embodiments of GPE 2610 also include a media pipeline 2616 that is specifically used to perform media operations, such as video post-processing and image enhancement.

[0254] In some embodiments, the media pipeline 2616 includes fixed-function or programmable logic units to replace or perform one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration, on behalf of the video codec engine 2606. In some embodiments, in addition, the media pipeline 2616 also includes a thread generation unit to generate threads for execution on the 3D / media subsystem 2615. The generated threads perform calculations for media operations on one or more graphics execution units included in the 3D / media subsystem 2615.

[0255] In some embodiments, the 3D / media subsystem 2615 includes logic for executing threads generated by the 3D pipeline 2612 and the media pipeline 2616. In one embodiment, the pipeline sends thread execution requests to the 3D / media subsystem 2615, which includes thread dispatch logic for arbitrating and dispatching each request to available thread execution resources. The execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, the 3D / media subsystem 2615 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) to share data between threads and for storing output data.

[0256] Additional Exemplary Graphics Processing Engines

[0257] Fig. 27is a block diagram of a graphics processing engine 2710 of a graphics processor according to some embodiments. In one embodiment, the graphics processing engine (GPE) 2710 is Fig.26 A version of the GPE 2610 is shown. Fig. 27 Those elements having the same reference number (or name) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. Fig.26 2610. The 3D pipeline 2612 and the media pipeline 2616 of the GPE 2710. The media pipeline 2616 is optional in some embodiments of the GPE 2710 and may not be explicitly included in the GPE 2710. For example and in at least one embodiment, separate media and / or image processors are coupled to the GPE 2710.

[0258] In some embodiments, GPE 2710 is coupled to or includes a command stream converter 2703, which provides a command stream to 3D pipeline 2612 and / or media pipeline 2616. In some embodiments, command stream converter 2703 is coupled to a memory, which may be a system memory, or one or more cache memories of an internal cache memory and a shared cache memory. In some embodiments, command stream converter 2703 receives commands from the memory and sends these commands to 3D pipeline 2612 and / or media pipeline 2616. The commands are instructions obtained from a ring buffer storing commands for 3D pipeline 2612 and media pipeline 2616. In one embodiment, in addition, the ring buffer may also include a batch command buffer storing multiple batches of multiple commands. Commands for 3D pipeline 2612 may also include references to data stored in memory, such as, but not limited to, vertex and geometry data for 3D pipeline 2612 and / or image data and memory objects for media pipeline 2616. The 3D pipeline 2612 and the media pipeline 2616 process the commands by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to the execution unit array 2714 .

[0259] In various embodiments, the 3D pipeline 2612 can execute one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 2714. The graphics core array 2714 provides a unified execution resource block. The multi-purpose execution logic (e.g., execution unit) within the graphics core array 2714 includes support for various 3D API shader languages ​​and can execute multiple simultaneous execution threads associated with multiple shaders.

[0260] In some embodiments, graphics core array 2714 also includes execution logic for performing media functions such as video and / or image processing. In one embodiment, in addition to graphics processing operations, the execution unit also includes general logic that can be programmed to perform parallel general computing operations. The general logic can be connected to Fig.24 (multiple) processor cores 2407 or Fig.25 The general logic within cores 2502A to 2502N performs processing operations in parallel or in combination.

[0261] Output data generated by threads executing on graphics core array 2714 can output data to memory in unified return buffer (URB) 2718. URB 2718 can store data for multiple threads. In some embodiments, URB 2718 can be used to send data between different threads executing on graphics core array 2714. In some embodiments, URB 2718 can also be used for synchronization between threads on the graphics core array and fixed function logic within shared function logic 2720.

[0262] In some embodiments, graphics core array 2714 is scalable such that the array includes a variable number of graphics cores each having a variable number of execution units based on the target power and performance level of GPE 2710. In one embodiment, execution resources are dynamically scalable such that execution resources can be enabled or disabled as needed.

[0263] The graphics core array 2714 is coupled to a shared function logic 2720, which includes a plurality of resources shared between the graphics cores in the graphics core array. The shared functions within the shared function logic 2720 are hardware logic units that provide dedicated supplementary functions to the graphics core array 2714. In various embodiments, the shared function logic 2720 includes, but is not limited to, a sampler 2721, a math 2722, and an inter-thread communication (ITC) 2723 logic. In addition, some embodiments implement one or more caches 2725 within the shared function logic 2720. The shared functions are implemented in the case where the demand for a given dedicated function is insufficient to be included in the graphics core array 2714. Instead, a single instance of the dedicated function is implemented as an independent entity in the shared function logic 2720 and shared between the execution resources within the graphics core array 2714. The exact set of functions shared between and included within the graphics core array 2714 varies between embodiments.

[0264] Fig.28 is a block diagram of another embodiment of a graphics processor 2800 . Fig.28Those elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0265] In some embodiments, graphics processor 2800 includes ring interconnect 2802, pipeline front end 2804, media engine 2837, and graphics cores 2880A to 2880N. In some embodiments, ring interconnect 2802 couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of multiple processors integrated into a multi-core processing system.

[0266] In some embodiments, the graphics processor 2800 receives batches of commands via a ring interconnect 2802. Incoming commands are interpreted by a command stream converter 2803 in a pipeline front end 2804. In some embodiments, the graphics processor 2800 includes scalable execution logic for performing 3D geometry processing and media processing via (multiple) graphics cores 2880A to 2880N. For 3D geometry processing commands, the command stream converter 2803 supplies the commands to a geometry pipeline 2836. For at least some media processing commands, the command stream converter 2803 supplies the commands to a video front end 2834, which is coupled to a media engine 2837. In some embodiments, the media engine 2837 includes a video quality engine (VQE) 2830 for video and image post-processing and a multi-format encoding / decoding (MFX) 2833 engine for providing hardware accelerated media data encoding and decoding. In some embodiments, the geometry pipeline 2836 and the media engine 2837 each generate an execution thread, which is used for thread execution resources provided by at least one graphics core 2880A.

[0267] In some embodiments, the graphics processor 2800 includes an extensible thread execution resource characterization module core 2880A to 2880N (sometimes referred to as a core slice), each of which has a plurality of sub-cores 2850A to 2850N, 2860A to 2860N (sometimes referred to as a core sub-slice). In some embodiments, the graphics processor 2800 may have any number of graphics cores 2880A to 2880N. In some embodiments, the graphics processor 2800 includes a graphics core 2880A, which has at least a first sub-core 2850A and a second sub-core 2860A. In other embodiments, the graphics processor is a low-power processor with a single sub-core (e.g., 2850A). In some embodiments, the graphics processor 2800 includes a plurality of graphics cores 2880A to 2880N, each of which includes a group of first sub-cores 2850A to 2850N and a group of second sub-cores 2860A to 2860N. Each of the group of first sub-cores 2850A to 2850N includes at least a first group of execution units 2852A to 2852N and media / texture samplers 2854A to 2854N. Each of the group of second sub-cores 2860A to 2860N includes at least a second group of execution units 2862A to 2862N and samplers 2864A to 2864N. In some embodiments, each sub-core 2850A to 2850N, 2860A to 2860N shares a group of shared resources 2870A to 2870N. In some embodiments, the shared resources include shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0268] Additional Exemplary Execution Units

[0269] Fig.29 Thread execution logic 2900 is shown, which includes an array of processing elements employed in some embodiments of a GPE. Fig.29 Those elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0270] In some embodiments, the thread execution logic 2900 includes a shader processor 2902, a thread dispatcher 2904, an instruction cache 2906, a scalable execution unit array including a plurality of execution units 2908A to 2908N, a sampler 2910, a data cache 2912, and a data port 2914. In one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., any one of execution units 2908A, 2908B, 2908C, 2908D, up to 2908N-1 and 2908N) based on the computational requirements of the workload. In one embodiment, the included components are interconnected via an interconnect structure that links to each of the components. In some embodiments, the thread execution logic 2900 includes one or more connections to a memory (such as a system memory or a cache memory) through the instruction cache 2906, the data port 2914, the sampler 2910, and one or more of the execution unit arrays 2908A to 2908N. In some embodiments, each execution unit (e.g., 2908A) is an independently programmable general-purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 2908A to 2908N is scalable to include any number of separate execution units.

[0271] In some embodiments, execution units 2908A to 2908N are primarily used to execute shader programs. Shader processor 2902 can process various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 2904. In one embodiment, thread dispatcher includes logic for arbitrating thread initiation requests from graphics and media pipelines and instantiating the requested threads on one or more execution units 2908A to 2908N. For example, the geometry pipeline (e.g., Fig.28 2836) can dispatch vertex processing, tessellation or geometry processing threads to thread execution logic 2900 ( Fig.29 ) for processing. In some embodiments, thread dispatcher 2904 can also process runtime thread generation requests from executing shader programs.

[0272] In some embodiments, execution units 2908A to 2908N support instruction sets (the instruction sets include native support for many standard 3D graphics shader instructions), so that shader programs from graphics libraries (e.g., Direct3D and OpenGL) are executed with minimal conversion. These execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general processing (e.g., compute and media shaders). Each of execution units 2908A to 2908N is capable of executing multiple-issue single instruction multiple data (SIMD), and multi-threaded operations can achieve an efficient execution environment in the face of high latency memory access. Each hardware thread within each execution unit has a dedicated high-bandwidth register stack and associated independent thread state. For pipelines with integers, single-precision floating-point operations and double-precision floating-point operations, SIMD branch functions, logical operations, transcendental operations, and other miscellaneous operations, execution is multiple releases per clock. While waiting for data from memory or one of the shared functions, dependency logic within execution units 2908A to 2908N puts the waiting thread to sleep until the requested data has returned. While the waiting thread is sleeping, hardware resources may be dedicated to processing other threads. For example, during a delay associated with a vertex shader operation, an execution unit may execute operations of a pixel shader, a fragment shader, or another type of shader program including a different vertex shader.

[0273] Each of the execution units 2908A to 2908N operates on an array of data elements. The number of data elements is the "execution size," or number of channels of an instruction. An execution channel is a logical unit that performs data element access, masking, and flow control within an instruction. The number of channels may be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) for a particular graphics processor. In some embodiments, the execution units 2908A to 2908N support integer and floating point data types.

[0274] The execution unit instruction set includes SIMD instructions. Various data elements can be stored in registers as compressed data types, and the execution unit will process various elements based on the data size of the element. For example, when operating on a 256-bit wide vector, the 256-bit vector is stored in a register, and the execution unit operates on the vector as four separate 64-bit compressed data elements (data elements of quadruple word length (QW) size), eight separate 32-bit compressed data elements (data elements of double word length (DW) size), sixteen separate 16-bit compressed data elements (data elements of word length (W) size), or thirty-two separate 8-bit data elements (data elements of byte (B) size). However, different vector widths and register sizes are possible.

[0275] One or more internal instruction caches (e.g., 2906) are included in the thread execution logic 2900 to cache thread instructions for the execution unit. In some embodiments, one or more data caches (e.g., 2912) are included to cache thread data during thread execution. In some embodiments, a sampler 2910 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 2910 includes a specialized texture or media sampling function to process texture or media data during the sampling process before providing the sampled data to the execution unit.

[0276] During execution, the graphics and media pipeline sends a thread initiation request to the thread execution logic 2900 via the thread generation and dispatch logic. Once a set of geometric objects has been processed and rasterized into pixel data, the pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 2902 is called to further calculate output information and cause the result to be written to the output surface (e.g., color buffer, depth buffer, stencil printing buffer, etc.). In some embodiments, the pixel shader or fragment shader calculates the value of each vertex attribute, which is interpolated across the rasterized object. In some embodiments, the pixel processor logic within the shader processor 2902 then executes the pixel or fragment shader program supplied by the application programming interface (API). In order to execute the shader program, the shader processor 2902 dispatches the thread to the execution unit (e.g., 2908A) via the thread dispatcher 2904. In some embodiments, the pixel shader 2902 uses the texture sampling logic in the sampler 2910 to access the texture data in the texture map stored in the memory. Arithmetic operations on texture data and input geometry data compute pixel color data for each geometry fragment, or discard one or more pixels without further processing.

[0277] In some embodiments, data port 2914 provides a memory access mechanism for thread execution logic 2900 to output processed data to memory for processing on the graphics processor output pipeline. In some embodiments, data port 2914 includes or is coupled to one or more cache memories (e.g., data cache 2912) to cache data via the data port for memory access.

[0278] Fig.303000 is a block diagram illustrating a graphics processor instruction format 3000 according to some embodiments. In one or more embodiments, a graphics processor execution unit supports an instruction set having instructions in multiple formats. Solid line boxes illustrate components that are typically included in execution unit instructions, while dashed lines include optional components or components that are only included in a subset of instructions. In some embodiments, the instruction format 3000 described and illustrated are macroinstructions because they are instructions supplied to the execution unit, as opposed to micro-operations generated from instruction decoding (once the instruction is processed).

[0279] In some embodiments, the graphics processor execution unit natively supports instructions in 128-bit instruction format 3010. 64-bit compact instruction format 3030 can be used for some instructions based on the selected instruction, multiple instruction options and the number of operands. The native 128-bit instruction format 710 provides access to all instruction options, while some options and operations are limited to 64-bit format 3030. The native instructions available in 64-bit format 3030 vary according to the embodiment. In some embodiments, the instructions are partially compressed using a set of index values ​​in index field 3013. The execution unit hardware references a set of compression tables based on the index values ​​and uses the compression table output to reconstruct the native instructions in 128-bit instruction format 3010.

[0280] For each format, the instruction opcode 3012 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a synchronous add operation across each color channel, and the color channel represents a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, the instruction control field 3014 enables control of certain execution options, such as channel selection (e.g., prediction) and data channel sorting (e.g., mixing). For instructions using the 128-bit instruction format 3010, the execution size field 3016 limits the number of data channels that will be executed in parallel. In some embodiments, the execution size field 3016 is not available for the 64-bit compact instruction format 3030.

[0281] Some execution unit instructions have up to three operands, including two source operands (src0 3020, src1 3022) and a destination 3018. In some embodiments, the execution unit supports dual destination instructions, where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 3024), where the instruction opcode 3012 determines the number of source operands. The last source operand of an instruction may be an immediate (e.g., hard-coded) value passed with the instruction.

[0282] In some embodiments, the 128-bit instruction format 3010 includes an access / address mode field 3026, which defines, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is provided directly by bits in the instruction.

[0283] In some embodiments, the 128-bit instruction format 3010 includes an access / address mode field 3026, which specifies the address mode and / or access mode of the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes, including 16-byte aligned access modes and 1-byte aligned access modes, wherein the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in the first mode, the instruction can use byte-aligned addressing for source operands and destination operands, and when in the second mode, the instruction can use 16-byte aligned addressing for all source operands and destination operands.

[0284] In one embodiment, the address mode portion of the access / address mode field 3026 determines whether the instruction uses direct addressing or indirect addressing. When direct register addressing mode is used, the bits in the instruction directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0285] In some embodiments, instructions are grouped based on the opcode 3012 bit field to simplify opcode decoding 3040. For 8-bit opcodes, the 4th, 5th, and 6th bits allow the execution unit to determine the type of opcode. The precise opcode grouping shown is exemplary only. In some embodiments, the move and logic opcode group 3042 includes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 3042 shares five most significant bits (MSBs), wherein the move (mov) instruction adopts the form of 0000xxxxb, and the logic instruction adopts the form of 0001xxxxb. The flow control instruction group 3044 (e.g., call (call), jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 3046 includes a mixture of instructions, including synchronization instructions (e.g., wait (wait), send (send)) in the form of 0011xxxxb (e.g., 0x30). The parallel math instruction group 3048 includes component-wise arithmetic instructions (e.g., add, mul) in the form of 0100xxxxb (e.g., 0x40). The parallel math group 3048 performs arithmetic operations in parallel across data lanes. The vector math group 3050 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic operations on vector operands, such as dot product operations.

[0286] Additional Example Graphics Pipeline

[0287] Fig.31 is a block diagram of another embodiment of a graphics processor 3100 . Fig.31 Those elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0288] In some embodiments, the graphics processor 3100 includes a graphics pipeline 3120, a media pipeline 3130, a display engine 3140, a thread execution logic 3150, and a rendering output pipeline 3170. In some embodiments, the graphics processor 3100 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or is controlled via commands issued to the graphics processor 3100 via a ring interconnect 3102. In some embodiments, the ring interconnect 3102 couples the graphics processor 3100 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 3102 are interpreted by a command stream converter 3103, which supplies instructions to separate components of the graphics pipeline 3120 or the media pipeline 3130.

[0289] In some embodiments, command stream converter 3103 directs the operation of vertex fetcher 3105, which reads vertex data from memory and executes vertex processing commands provided by command stream converter 3103. In some embodiments, vertex fetcher 3105 provides vertex data to vertex shader 3107, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, vertex fetcher 3105 and vertex shader 3107 execute vertex processing instructions by dispatching execution threads to execution units 3152A to 3152B via thread dispatcher 3131.

[0290] In some embodiments, execution units 3152A-3152B are vector processor arrays with instruction sets for performing graphics and media operations. In some embodiments, execution units 3152A-3152B have an attached L1 cache 3151 that is dedicated to each array or shared between arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0291] In some embodiments, the graphics pipeline 3120 includes a tessellation component for performing hardware accelerated tessellation of 3D objects. In some embodiments, the programmable hull shader 811 configures the tessellation operation. The programmable domain shader 817 provides back-end evaluation of the tessellation output. The tessellation 3113 operates at the direction of the hull shader 3111 and contains dedicated logic for generating a detailed set of geometric objects based on a coarse geometric model that is provided as input to the graphics pipeline 3120. In some embodiments, if tessellation is not used, the tessellation components (e.g., hull shader 3111, tessellation 3113, domain shader 3117) can be bypassed.

[0292] In some embodiments, the complete geometric object may be processed by the geometry shader 3119 via one or more threads dispatched to the execution units 3152A-3152B, or may proceed directly to the clipper 3129. In some embodiments, the geometry shader operates on entire geometric objects (rather than vertices or vertex patches as in previous stages of the graphics pipeline). If tessellation is disabled, the geometry shader 3119 receives input from the vertex shader 3107. In some embodiments, the geometry shader 3119 may be programmed by a geometry shader program to perform geometry tessellation when the tessellation unit is disabled.

[0293] Before rasterization, the clipper 3129 processes the vertex data. The clipper 3129 can be a fixed function clipper or a programmable clipper with clipping and geometry shader functions. In some embodiments, the rasterizer and depth test component 3173 in the render output pipeline 3170 dispatches a pixel shader to convert the geometric object into its per-pixel representation. In some embodiments, the pixel shader logic is included in the thread execution logic 3150. In some embodiments, the application can bypass the rasterizer and depth test component 3173 and access the unrasterized vertex data via the outflow unit 3123.

[0294] The graphics processor 3100 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to be passed among the main components of the graphics processor. In some embodiments, execution units 3152A-3152B and associated cache(s) 3151, texture and media samplers 3154, and texture / sampler cache 3158 are interconnected via data ports 3156 to perform memory accesses and communicate with the processor's rendering output pipeline components. In some embodiments, samplers 3154, caches 3151, 3158, and execution units 3152A-3152B each have a separate memory access path.

[0295] In some embodiments, the rendering output pipeline 3170 includes a rasterizer and a depth test component 3173, which converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a window device / masker unit for performing fixed-function triangle and line rasterization. Associated rendering caches 3178 and depth caches 3179 are also available in some embodiments. Pixel operation components 3177 perform pixel-based operations on data, but in some instances, pixel operations associated with 2D operations (e.g., using mixed bit block image transfer) are performed by 2D engines 3141, or replaced by display controllers 3143 using overlapping display planes at display time. In some embodiments, a shared L3 cache 3175 can be used for all graphics components, thereby allowing data to be shared without using main system memory.

[0296] In some embodiments, the graphics processor media pipeline 3130 includes a media engine 3137 and a video front end 3134. In some embodiments, the video front end 3134 receives pipeline commands from the command stream converter 3103. In some embodiments, the media pipeline 3130 includes a separate command stream converter. In some embodiments, the video front end 3134 processes the media commands before sending the commands to the media engine 3137. In some embodiments, the media engine 3137 includes a thread generation function for generating threads for dispatching to the thread execution logic 3150 via the thread dispatcher 3131.

[0297] In some embodiments, the graphics processor 3100 includes a display engine 3140. In some embodiments, the display engine 3140 is external to the processor 3100 and is coupled to the graphics processor via a ring interconnect 3102, or some other interconnect bus or mechanism. In some embodiments, the display engine 3140 includes a 2D engine 3141 and a display controller 3143. In some embodiments, the display engine 3140 includes dedicated logic that can operate independently of the 3D pipeline. In some embodiments, the display controller 3143 is coupled to a display device (not shown), which can be a system integrated display device (such as in a laptop computer), or an external display device attached via a display device connector.

[0298] In some embodiments, graphics pipeline 3120 and media pipeline 3130 can be configured to perform operations based on multiple graphics and media programming interfaces and are not dedicated to any application programming interface (API). In some embodiments, the driver software of graphics processor converts the API dispatch dedicated to specific graphics or media library into a command that can be processed by graphics processor. In some embodiments, support is provided for all open graphics libraries (OpenGL), open computing language (OpenCL) and / or Vulkan graphics and computing API from Khronos Group. In some embodiments, support can also be provided for Microsoft's Direct3D library. In some embodiments, the combination of these libraries can be supported. Support can also be provided for open source computer vision library (OpenCV). If the mapping from the pipeline of future API to the pipeline of graphics processor can be made, the future API with compatible 3D pipeline will also be supported.

[0299] Graphics pipeline programming

[0300] Fig.32A is a block diagram illustrating a graphics processor command format 3200 according to some embodiments. Fig.32B is a block diagram illustrating a graphics processor command sequence 3210 according to an embodiment. Fig.32A The solid-line boxes in show components that are typically included in a graphics command, while the dashed lines include components that are optional or included only in a subset of the graphics commands. Fig.32A The exemplary graphics processor command format 3200 includes a data field for identifying the target client 3202 of the command, a command operation code (opcode) 3204, and associated data 3206 for the command. Some commands also include a sub-opcode 3205 and a command size 3208.

[0301] In some embodiments, client 3202 defines the client unit of the graphics device that processes command data. In some embodiments, the graphics processor command parser checks the client field of each command to adjust the further processing of the command and routes the command data to the appropriate client unit. In some embodiments, the graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline that processes the command. Once the command is received by the client unit, the client unit reads the opcode 3204 and the sub-opcode 3205 (if present) to determine the operation to be performed. The client unit uses the information in the data field 3206 to execute the command. For some commands, it is expected that the command size 3208 explicitly defines the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands in the command based on the command opcode. In some embodiments, the command is aligned via a multiple of a double word length.

[0302] Fig.32B An exemplary graphics processor command sequence 3210 is shown in the flowchart in FIG. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses a version of the command sequence shown to initiate, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for exemplary purposes only, as the embodiments are not limited to these specific commands or this command sequence. Moreover, the commands may be issued as a batch of commands in a command sequence so that the graphics processor will process the command sequence in an at least partially simultaneous manner.

[0303] In some embodiments, the graphics processor command sequence 3210 may begin with a pipeline flush command 3212 to cause any active graphics pipeline to complete currently pending commands for that pipeline. In some embodiments, the 3D pipeline 3222 and the media pipeline 3224 are not operating simultaneously. The pipeline flush is performed to cause the active graphics pipeline to complete any pending commands. In response to the pipeline flush, the command parser for the graphics processor will stop command processing until the active drawing engine completes pending operations and invalidates the associated read cache. Optionally, any data marked as 'dirty' in the render cache may be flushed to memory. In some embodiments, the pipeline flush command 3212 may be used for pipeline synchronization or before placing the graphics processor in a low power state.

[0304] In some embodiments, pipeline select command 3213 is used when a command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, pipeline select command 3213 is only required once in an execution context before issuing pipeline commands, unless the context is to issue commands for two pipelines. In some embodiments, pipeline flush command 3212 is required just before a pipeline switch via pipeline select command 3213.

[0305] In some embodiments, pipeline control commands 3214 configure the graphics pipeline for operation and are used to program 3D pipeline 3222 and media pipeline 3224. In some embodiments, pipeline control commands 3214 configure the pipeline state of the active pipeline. In one embodiment, pipeline control commands 3214 are used for pipeline synchronization and for clearing data from one or more cache memories within the active pipeline before processing a batch of commands.

[0306] In some embodiments, return buffer state command 3216 is used to configure a set of return buffers for corresponding pipelines to write data. Some pipeline operations require allocating, selecting, or configuring one or more return buffers, and the operation writes intermediate data to the one or more return buffers during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, return buffer state 3216 includes selecting the size and number of return buffers for the set of pipeline operations.

[0307] The remaining commands in the command sequence differ based on the active pipeline for operation. Based on pipeline decision 3220 , the command sequence is tailored for either 3D pipeline 3222 starting at 3D pipeline state 3230 , or media pipeline 3224 starting at media pipeline state 3240 .

[0308] Commands for 3D pipeline state 3230 include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables to be configured before processing 3D primitive commands. The values ​​of these commands are determined at least in part based on the specific 3D API in use. In some embodiments, 3D pipeline state 3230 commands can also selectively disable or bypass specific pipeline elements if those elements are not to be used.

[0309] In some embodiments, 3D primitive 3232 commands are used to submit 3D primitives to be processed by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitive 3232 commands will be forwarded to the vertex acquisition function in the graphics pipeline. The vertex acquisition function uses the 3D primitive 3232 command data to generate multiple vertex data structures. The vertex data structures are stored in one or more return buffers. In some embodiments, 3D primitive 3232 commands are used to perform vertex operations on 3D primitives via vertex shaders. In order to process vertex shaders, the 3D pipeline 3222 dispatches the shader execution thread to the graphics processor execution unit.

[0310] In some embodiments, the 3D pipeline 3222 is triggered via an execution 3234 command or event. In some embodiments, a register write triggers the command execution. In some embodiments, the execution is triggered via a 'go' or 'kick' command in the command sequence. In one embodiment, the command execution is triggered using a pipeline synchronization command to dump and clear the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing for the 3D primitives. Once the operation is completed, the generated geometric objects are rasterized and the pixel engine shades the generated pixels. For these operations, additional commands for controlling pixel shading and pixel backend operations may also be included.

[0311] In some embodiments, when performing media operations, the graphics processor command sequence 3210 follows the media pipeline 3224 path. Generally, the specific purpose and manner of programming for the media pipeline 3224 depends on the media or computing operation to be performed. During the media decoding process, specific media decoding operations can be offloaded to the media pipeline. In some embodiments, the media pipeline can also be bypassed, and the media decoding can be performed in whole or in part using resources provided by one or more general processing cores. In one embodiment, the media pipeline also includes elements for general purpose graphics processor unit (GPGPU) operations, wherein the graphics processor is used to perform SIMD vector operations using a compute shader program that is not explicitly related to rendering graphics primitives.

[0312] In some embodiments, the media pipeline 3224 is configured in a similar manner to the 3D pipeline 3222. A set of commands for configuring the media pipeline state 3240 is dispatched or placed into the command queue, before the media object commands 3242. In some embodiments, the media pipeline state commands 3240 include data for configuring the media pipeline elements that will be used to process the media objects. This includes data for configuring the video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. In some embodiments, the media pipeline state commands 3240 also support the use of one or more pointers to an "indirect" state element that contains a batch of state settings.

[0313] In some embodiments, media object commands 3242 supply pointers to media objects for processing by the media pipeline. The media object includes a memory buffer that contains video data to be processed. In some embodiments, all media pipeline states must be valid before issuing media object commands 3242. Once the pipeline state is configured and media object commands 3242 are queued, media pipeline 3224 is triggered via an execute 3244 command or an equivalent execution event (e.g., a register write). The output from media pipeline 3224 can then be post-processed by operations provided by 3D pipeline 3222 or media pipeline 3224. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0314] Graphics Software Rack Structure

[0315] Fig.33 An exemplary graphics software architecture of a data processing system 3300 according to some embodiments is shown. In some embodiments, the software architecture includes a 3D graphics application 3310, an operating system 3320, and at least one processor 3330. In some embodiments, processor 3330 includes a graphics processor 3332 and one or more general purpose processor cores 3334. Graphics application 3310 and operating system 3320 are each executed in a system memory 3350 of the data processing system.

[0316] In some embodiments, the 3D graphics application 3310 includes one or more shader programs that include shader instructions 3312. The shader language instructions may be in a high-level shader language, such as a high-level shader language (HLSL) or an OpenGL shader language (GLSL). The application also includes executable instructions 3314 in a machine language suitable for execution by a general purpose processor core 3334. The application also includes graphics objects 3316 defined by vertex data.

[0317] In some embodiments, operating system 3320 is from Microsoft Corporation Operating system, dedicated UNIX operating system, or open source UNIX operating system using Linux kernel variant. Operating system 3320 can support graphics API 3322, such as Direct3D API, OpenGL API or Vulkan API. When Direct3D API is in use, operating system 3320 uses front-end shader compiler 3324 to compile any shader instruction 3312 in HLSL into a lower-level shader language. The compilation can be just-in-time (JIT) compilation, or the application can execute shader precompilation. In some embodiments, in the process of compiling 3D graphics application 3310, high-level shaders are compiled into low-level shaders. In some embodiments, shader instructions 3312 are provided in an intermediate form, such as a version of the standard portable intermediate representation (SPIR) used by Vulkan API.

[0318] In some embodiments, the user mode graphics driver 3326 includes a backend shader compiler 3327 that converts shader instructions 3312 into hardware-specific representations. When using the OpenGL API, shader instructions 3312 in the GLSL high-level language are passed to the user mode graphics driver 3326 for compilation. In some embodiments, the user mode graphics driver 3326 uses operating system kernel mode functions 3328 to communicate with the kernel mode graphics driver 3329. In some embodiments, the kernel mode graphics driver 3329 communicates with the graphics processor 3332 to dispatch commands and instructions.

[0319] IP Core Implementation

[0320] One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium, which represents and / or defines logic within an integrated circuit such as a processor. For example, a machine-readable medium may include instructions representing the various logics within a processor. When read by a machine, the instructions may enable the machine to manufacture logic for performing the techniques described herein. This type of representation (referred to as an "IP core") is a reusable unit of logic for an integrated circuit, which may be stored on a tangible, machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model may be supplied to each consumer or manufacturing facility that loads the hardware model on a manufacturing machine that manufactures the integrated circuit. The integrated circuit may be manufactured so that the circuit performs the operations described in association with any of the embodiments described herein.

[0321] Fig.34 34 is a block diagram showing an IP core development system 3400 that can be used to manufacture an integrated circuit to perform operations according to an embodiment. The IP core development system 3400 can be used to generate a modular, reusable design that can be incorporated into a larger design or used to build an entire integrated circuit (e.g., a SOC integrated circuit). The design facility 3430 can use a high-level programming language (e.g., C / C++) to generate a software simulation 3410 for the IP core design. The software simulation 3410 can be used to design, test and verify the behavior of the IP core using a simulation model 3412. The simulation model 3412 can include functional, behavioral and / or timing simulations. Then the register transfer level (RTL) design 3415 can be created or synthesized by the simulation model 3412. The RTL design 3415 is an abstraction of the behavior of an integrated circuit (including associated logic executed using the modeled digital signals) that models the flow of digital signals between hardware registers. In addition to the RTL design 3415, a lower level design at a logic level or transistor level can also be created, designed or synthesized. Thus, the specific details of the initial design and simulation can change.

[0322] The RTL design 3415 or equivalent can be further synthesized into a hardware model 3420 by the design facility, which can adopt a hardware description language (HDL) or some other representation of physical design data. The HDL can be further simulated or tested to verify the IP core design. Non-volatile memory 3440 (e.g., a hard disk, flash memory, or any non-volatile storage medium) can be used to store the IP core design for delivery to a third-party manufacturing facility 3465. Alternatively, the IP core design can be transmitted (e.g., via the Internet) via a wired connection 3450 or a wireless connection 3460. The manufacturing facility 3465 can then manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit can be configured to perform operations according to at least one embodiment described herein.

[0323] Exemplary System-on-Chip Integrated Circuit

[0324] Figure 35 to Figure 37 An exemplary integrated circuit and related graphics processor that can be manufactured using one or more IP cores according to various embodiments described herein are shown. In addition to what is shown, other logic and circuits may also be included, including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores.

[0325] Fig.3535 is a block diagram illustrating an exemplary system-on-chip integrated circuit 3500 that can be manufactured using one or more IP cores according to an embodiment. The exemplary integrated circuit 3500 includes one or more application processors 3505 (e.g., CPUs), at least one graphics processor 3510, and may additionally include an image processor 3515 and / or a video processor 3520, any of which may be modular IP cores from the same or multiple different design facilities. The integrated circuit 3500 includes peripheral or bus logic, including a USB controller 3525, a UART controller 3530, an SPI / SDIO controller 3535, and an I 2 S / I 2 The integrated circuit may also include a display device 3545 coupled to one or more of a high-definition multimedia interface (HDMI) controller 3550 and a mobile industry processor interface (MIPI) display interface 3555. Storage may be provided by a flash memory subsystem 3560 (including flash memory and a flash memory controller). A memory interface may be provided via a memory controller 3565 to access SDRAM or SRAM memory devices. In addition, some integrated circuits also include an embedded security engine 3570.

[0326] Fig.36 is a block diagram illustrating an exemplary graphics processor 3610 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores according to an embodiment. The graphics processor 3610 may be Fig.35 A variation of the graphics processor 2210 of FIG. The graphics processor 3610 includes a vertex processor 3605 and one or more fragment processors 3615A to 3615N (e.g., 3615A, 3615B, 3615C, 3615D, all the way to 3615N-1 and 3615N). The graphics processor 3610 can execute different shader programs via separate logic, so that the vertex processor 3605 is optimized to perform operations of the vertex shader program, while one or more fragment processors 3615A to 3615N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. The vertex processor 3605 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. (Multiple) fragment processors 3615A to 3615N use the primitives and vertex data generated by the vertex processor 3605 to generate a frame buffer displayed on a display device. In one embodiment, the fragment processor(s) 3615A to 3615N are optimized to execute fragment shader programs provided in the OpenGL API, which can be used to perform operations similar to pixel shader programs provided in the Direct 3D API.

[0327] In addition, graphics processor 3610 also includes one or more memory management units (MMUs) 3620A-3620B, one or more caches 3625A-3625B, and (multiple) circuit interconnects 3630A-3630B. One or more MMUs 3620A-3620B provide virtual to physical address mappings for integrated circuit 3610 including for vertex processor 3605 and / or one or more fragment processors 3615A-3615N, which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more caches 3625A-3625B. In one embodiment, one or more MMUs 3625A-3625B may communicate with other MMUs within the system including with Fig.35 The graphics processor 3610 may be synchronized with one or more MMUs associated with one or more application processors 3505, image processor 3515, and / or video processor 3520 so that each processor 3505 to 3520 may participate in a shared or unified virtual memory system. According to an embodiment, one or more circuit interconnects 3630A to 3630B may enable the graphics processor 3610 to interact with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0328] Fig.37 is a block diagram illustrating an additional exemplary graphics processor 3710 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores in accordance with an embodiment. The graphics processor 3710 may be Fig.35 A variation of the graphics processor 3510. The graphics processor 3710 includes Fig.36 One or more MMUs 3620A-3620B, caches 3625A-3625B, and circuit interconnects 3630A-3630B of integrated circuit 3600.

[0329] The graphics processor 3710 includes one or more shader cores 3715A to 3715N (e.g., 3715A, 3715B, 3715C, 3715D, 3715E, 3715F, all the way to 3715N-1 and 3715N), which provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code including shader program code to implement vertex shaders, fragment shaders and / or compute shaders. The exact number of shader cores present may vary in embodiments and implementations. In addition, the graphics processor 3710 also includes an inter-core task manager 3705, which acts as a thread dispatcher for dispatching execution threads to one or more shader cores 3715A to 3715N and a tiling unit 3718 for accelerating tiling operations for tile-based rendering, wherein the rendering operations of a scene are subdivided in image space, for example to exploit local spatial coherence within a scene or to optimize the use of internal caches.

[0330] The following clauses and / or examples refer to specific embodiments or examples thereof. The details of the examples may be used anywhere in one or more embodiments. The various features of the different embodiments or examples may be combined in different ways with some features included and other features excluded to accommodate various different applications. Examples may include subject matter such as methods, devices for performing the actions of the methods, and at least one machine-readable medium including instructions that, when executed by a machine, cause the machine to perform the actions of the methods or the actions of the device or system according to the embodiments and examples described herein. The various components may be devices for performing the described operations or functions.

[0331] One embodiment provides a computing device for performing machine learning operations, the device comprising a decoding unit for decoding a single instruction into a decoded instruction, the decoded instruction being used to perform one or more machine learning operations, wherein the decoding unit is used to request a scheduler to schedule the one or more machine learning operations to one of a programmable computing unit array and a fixed-function computing unit based on parameters of the one or more machine learning operations.

[0332] One embodiment provides a method for performing machine learning operations, the method comprising: obtaining and decoding a first instruction specifying a set of multiple operations to be performed via a data processing system, at least a portion of the set of multiple operations being performed via a general-purpose graphics processing unit of the data processing system; analyzing parameters associated with the first instruction; sampling hardware resource utilization of the general-purpose graphics processing unit of the data processing system; and selecting a set of instructions to implement the set of multiple operations.

[0333] One embodiment provides a data processing system, comprising: a non-transitory machine-readable medium for storing instructions for execution by one or more processors of the data processing system; and a general-purpose graphics processing unit, comprising a decoding unit for decoding a single instruction into a decoded instruction, wherein the decoded instruction is used to perform one or more machine learning operations, wherein the decoding unit is used to request a scheduler to schedule the one or more machine learning operations to one of a programmable computing unit array and a fixed-function computing unit based on parameters of the one or more machine learning operations.

[0334] The embodiments described herein refer to specific configurations of hardware, such as application specific integrated circuits (ASICs), which are configured to perform certain operations or have predetermined functions. Such electronic devices typically include a group of one or more processors coupled to one or more other components (e.g., one or more storage devices (non-transitory machine-readable storage media), user input / output devices (e.g., keyboards, touch screens and / or displays), and network connectors). The coupling of the group of processors to the other components is typically achieved through one or more buses and bridges (also referred to as bus controllers). The storage device and the signal carrying the network service represent one or more machine-readable storage media and machine-readable communication media, respectively. Therefore, the storage device of a given electronic device typically stores code and / or data for execution on a group of one or more processors of the electronic device.

[0335] Of course, different combinations of software, firmware and / or hardware can be used to implement one or more parts of the embodiment. Throughout this detailed description, for the purpose of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to those skilled in the art that this embodiment can be practiced without some of these specific details. In some instances, well-known structures and functions are not set forth in detail to avoid obscuring the inventive subject matter of the embodiment. Therefore, the scope and spirit of the present invention should be determined according to the following claims.

Claims

1. A computing device for performing a machine learning operation, the computing device include: a decoding unit for decoding a single instruction into a decoded instruction for performing one or more machine learning operations, wherein the decoding unit is configured to request a scheduler to schedule the one or more machine learning operations to one of a programmable computing unit array and a fixed function computing unit based on parameters of the one or more machine learning operations, wherein the single instruction is a machine learning computing instruction, wherein the machine learning computing instruction is a convolution instruction, and the one or more machine learning operations include a convolution operation, wherein the convolution operation includes multiple matrix operations, and The decoding unit is used to request the scheduler to schedule the multiple matrix operations to one of the programmable computing unit array and the fixed function computing unit based on the size of the convolution filter.

2. The computing device of claim 1, in, The decode unit includes fetch logic for fetching the single instruction.

3. The computing device of claim 1, in, The decoding unit is used to request the scheduler to schedule the multiple matrix operations to the fixed-function computing unit for performing 5×5 or 7×7 convolution operations.

4. The computing device of claim 1, in, The decoding unit is used to request the scheduler to schedule the multiple matrix operations to the programmable computing unit array for performing 3×3 or 1×1 convolution operations.

5. The computing device of claim 1, in, The fixed function computing unit is a systolic array matrix operation unit including a fixed function computing logic array.

6. The computing device of claim 5, in, The fixed function computation logic array includes multiplication and accumulation computation logic.

7. A data processing system, include: a non-transitory machine-readable medium for storing instructions for execution by one or more processors of the data processing system; as well as A general purpose graphics processing unit, comprising a decoding unit for decoding a single instruction into a decoded instruction, the decoded instruction being used to perform one or more machine learning operations, wherein the decoding unit is used to request a scheduler to schedule the one or more machine learning operations to one of a programmable computing unit array and a fixed function computing unit based on parameters of the one or more machine learning operations, wherein the single instruction is a machine learning computing instruction, wherein the machine learning computing instruction is a convolution instruction, and the one or more machine learning operations include a convolution operation, wherein the convolution operation includes multiple matrix operations, and The decoding unit is used to request the scheduler to schedule the multiple matrix operations to one of the programmable computing unit array and the fixed function computing unit based on the size of the convolution filter.

8. The data processing system according to claim 7, in, The decode unit includes fetch logic for fetching the single instruction.

9. The data processing system according to claim 7, in, The decoding unit is used to request the scheduler to schedule the multiple matrix operations to the fixed-function computing unit for performing 5×5 or 7×7 convolution operations.

10. The data processing system according to claim 7, in, The decoding unit is used to request the scheduler to schedule the multiple matrix operations to the programmable computing unit array for performing 3×3 or 1×1 convolution operations.

11. The data processing system according to claim 7, in, The fixed function computing unit is a systolic array matrix operation unit including a fixed function computing logic array.

12. The data processing system according to claim 11, in, The fixed function computation logic array includes multiplication and accumulation computation logic.

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