Semiconductor devices and manufacturing methods thereof

Abstract

This invention provides a semiconductor device and a method for manufacturing the same, which improves the insulation withstand voltage of a transformer without complicating the manufacturing process. The method for manufacturing the semiconductor device includes the following steps: patterning a conductor film formed on an interlayer insulating film (IL4); after forming coils (CL1b) and conductor patterns (CP) on the same layer, using the coils (CL1b) and conductor patterns (CP) as masks to etch a portion of the interlayer insulating film (IL4), thereby forming a raised / lowered shape (US) on the surface of the interlayer insulating film (IL4).

Description

Technical Field

[0001] This invention relates to semiconductor devices and manufacturing techniques thereof, for example to techniques effective for semiconductor devices and manufacturing techniques thereof capable of transmitting signals between different potentials using a pair of inductively coupled inductors. Background Technology

[0002] Japanese Patent Application Publication No. 2014-22600 (Patent Document 1) discloses a technology that can improve the surface insulation withstand voltage without increasing the overall area occupied by the isolator, including the insulating region. Specifically, Patent Document 1 discloses a technology that improves the surface insulation withstand voltage by forming an uneven shape between the stacked insulating layers, thereby increasing the creepage distance.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2014-22600 Summary of the Invention

[0004] The problem that the invention aims to solve

[0005] For example, there exists a transformer (miniature isolator) capable of transmitting signals without electrical contact using a pair of inductively coupled inductors. According to this transformer, signal transmission can be performed without electrical contact, thus providing the advantage of suppressing the adverse effects of electrical noise from one circuit on the other. Furthermore, in such a transformer, non-contact signal transmission is possible even between circuits with significantly different potentials, which is expected to improve insulation withstand voltage.

[0006] Other topics and novel features will become clear from the description in this specification and the accompanying drawings.

[0007] Technical solutions for solving the problem

[0008] A method for manufacturing a semiconductor device in one embodiment includes the following steps: patterning a conductor film formed on an interlayer insulating film; after forming inductors and conductor patterns on the same layer, using the inductors and conductor patterns as a mask to etch a portion of the interlayer insulating film, thereby forming a concave-convex shape on the surface of the interlayer insulating film.

[0009] Invention Effects

[0010] According to one implementation method, it is possible to improve the insulation withstand voltage of the transformer without complicating the manufacturing process. Attached Figure Description

[0011] Figure 1 This is a diagram showing an example of the structure of the drive control unit that drives the load.

[0012] Figure 2This is an explanatory diagram showing an example of signal transmission.

[0013] Figure 3 This is a cross-sectional view illustrating a schematic structure of a semiconductor chip in which a transformer is formed in an associated technology.

[0014] Figure 4 This is a cross-sectional view illustrating the schematic device structure of the semiconductor chip in Embodiment 1.

[0015] Figure 5 It is shown in magnification Figure 4 A diagram showing a portion of a region of a semiconductor chip.

[0016] Figure 6 This is a cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1.

[0017] Figure 7 It shows the next step. Figure 6 A cross-sectional view of the manufacturing process of a semiconductor device.

[0018] Figure 8 It shows the next step. Figure 7 A cross-sectional view of the manufacturing process of a semiconductor device.

[0019] Figure 9 It shows the next step. Figure 8 A cross-sectional view of the manufacturing process of a semiconductor device.

[0020] Figure 10 It shows the next step. Figure 9 A cross-sectional view of the manufacturing process of a semiconductor device.

[0021] Figure 11 This is a cross-sectional view illustrating the schematic structure of a semiconductor chip in a modified example.

[0022] Figure 12 This is a cross-sectional view showing the manufacturing process of a semiconductor device in a modified example.

[0023] Figure 13 It shows the next step. Figure 12 A cross-sectional view of the manufacturing process of a semiconductor device.

[0024] Figure 14 It shows the next step. Figure 13 A cross-sectional view of the manufacturing process of a semiconductor device.

[0025] Figure 15 It shows the next step. Figure 14 A cross-sectional view of the manufacturing process of a semiconductor device.

[0026] Figure 16This is a schematic diagram showing the planar layout of coil and conductor patterns formed on the same layer in Embodiment 2.

[0027] Figure 17 This is a schematic diagram showing the planar layout in a variation of Embodiment 2, Example 1.

[0028] Figure 18 This is a schematic diagram showing the planar layout in a variation of embodiment 2.

[0029] Figure 19 This is a diagram showing an example of the structure of the drive control unit that drives the load.

[0030] Figure 20 This is a cross-sectional view illustrating the schematic structure of the semiconductor device in Embodiment 3.

[0031] Figure 21 This is a cross-sectional view illustrating the schematic structure of the semiconductor device in the modified example.

[0032] Label Explanation

[0033] CHP1 semiconductor chip

[0034] CHP2 Semiconductor Chip

[0035] CL1a coil

[0036] CL1b coil

[0037] CL2a coil

[0038] CL2b coil

[0039] CP conductor pattern

[0040] CP1 conductor pattern

[0041] CP2a conductor pattern

[0042] CP2b conductor pattern

[0043] CP3 conductor pattern

[0044] IL1 interlayer insulating film

[0045] IL2 interlayer insulating film

[0046] IL3 interlayer insulating film

[0047] IL4 interlayer insulating film

[0048] R1 area

[0049] R2 area

[0050] R3 area

[0051] US concave-convex shape Detailed Implementation

[0052] In the following embodiments, for ease of explanation, they are divided into multiple parts or embodiments as needed. However, unless otherwise explicitly stated, they are not unrelated to each other, but are related as variations, detailed descriptions, supplementary descriptions, etc., in which one is a part or all of the other.

[0053] Furthermore, in the following embodiments, when referring to the quantity of elements (including number, value, quantity, range, etc.), except where specifically stated or where the quantity is explicitly limited to a specific quantity in principle, the quantity may be above or below that specific quantity.

[0054] Furthermore, in the following embodiments, the structural elements (including element steps, etc.) are not necessarily necessary except in cases where they are specifically stated or where they are clearly considered necessary in principle.

[0055] Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of structural elements, etc., the terms include shapes that are substantially similar or analogous to their shape, except where specifically stated or where it is clearly believed in principle that this is not the case. The same applies to the values ​​and ranges mentioned above.

[0056] Furthermore, in all the accompanying drawings used to illustrate the embodiments, the same reference numerals are generally used for the same parts, and repeated descriptions are omitted. In addition, for ease of understanding of the drawings, sometimes even top views are shaded.

[0057] (Implementation Method 1)

[0058] <Circuit Structure>

[0059] Figure 1 This is a diagram illustrating an example of the structure of a drive control unit for loads such as drive motors. (Example) Figure 1 As shown, the drive control unit in this embodiment 1 includes a control circuit CC, transformer TR1, transformer TR2, drive circuit DR, and inverter INV, which are electrically connected to the load LOD. Specifically, as... Figure 1 As shown, in this embodiment 1, the control circuit CC, transformer TR1 and transformer TR2 are formed on the semiconductor chip CHP1, and the drive circuit DR is formed on the semiconductor chip CHP2.

[0060] Specifically, such as Figure 1As shown, at the semiconductor chip CHP1, for example, a control circuit CC is formed, and a transmitting circuit TX1 and a receiving circuit RX1 are formed, and a receiving circuit RX2 and a transmitting circuit TX2 are also formed. On the other hand, as... Figure 1 As shown, a driving circuit DR is formed on the semiconductor chip CHP2.

[0061] Transmitting circuit TX1 and receiving circuit RX1 are used to transmit the control signal output from control circuit CC to drive circuit DR. Conversely, transmitting circuit TX2 and receiving circuit RX2 are used to transmit the signal output from drive circuit DR to control circuit CC. Control circuit CC is a circuit that controls drive circuit DR, which in turn operates the inverter INV that controls load LOD based on the control from control circuit CC.

[0062] A power supply potential VCC1 is supplied to the circuits within the semiconductor chip CHP1, including the transmitting circuits TX1 and TX2 and the receiving circuits RX1 and RX2, and grounded through a grounding potential GND1. Conversely, a power supply potential VCC2 is supplied to the inverter INV, and grounded through a grounding potential GND2. At this time, for example, the power supply potential VCC1 supplied to the semiconductor chip CHP1 is less than the power supply potential VCC2 supplied to the inverter INV. In other words, the power supply potential VCC2 supplied to the inverter INV is greater than the power supply potential VCC1 supplied to the semiconductor chip CHP1.

[0063] A transformer TR1, consisting of inductively coupled (magnetically coupled) coils CL1a and CL1b, is positioned between the transmitting circuit TX1 and the receiving circuit RX1. Therefore, in this embodiment 1, signals can be transmitted from the transmitting circuit TX1 to the receiving circuit RX1 via the transformer TR1. As a result, the drive circuit DR formed on the semiconductor chip CHP2 can receive control signals output from the control circuit CC formed on the semiconductor chip CHP1 via the transformer TR1.

[0064] Thus, in this embodiment 1, by utilizing the transformer TR1, which is electrically insulated through inductive coupling, the control signal can be transmitted from the control circuit CC to the drive circuit DR. Therefore, the transmission of electrical noise from the control circuit CC to the drive circuit DR can be suppressed, and the control signal can be transmitted. Therefore, according to this embodiment 1, the malfunction of the drive circuit DR caused by electrical noise superimposed on the control signal can be suppressed, thereby improving the operational reliability of the semiconductor device.

[0065] In this embodiment 1, the coils CL1a and CL1b constituting the transformer TR1 are both formed on the semiconductor chip CHP1. That is, the transformer TR1 is formed by the coils CL1a and CL1b formed on the semiconductor chip CHP1. The coils CL1a and CL1b function as inductors, respectively, and the transformer TR1 functions as a magnetic coupling element composed of the inductively coupled coils CL1a and CL1b.

[0066] Similarly, a transformer TR2, consisting of inductively coupled coils CL2b and CL2a, is positioned between the transmitting circuit TX2 and the receiving circuit RX2. Therefore, in this embodiment 1, a signal can be transmitted from the transmitting circuit TX2 to the receiving circuit RX2 via the transformer TR2. As a result, the control circuit CC formed on the semiconductor chip CHP1 can receive the signal output from the drive circuit DR formed on the semiconductor chip CHP2 via the transformer TR2.

[0067] Thus, in this embodiment 1, by utilizing the transformer TR2, which is electrically insulated through inductive coupling, the signal can be transmitted from the drive circuit DR to the control circuit CC. Therefore, the transmission of electrical noise from the drive circuit DR to the control circuit CC can be suppressed, and the signal can be transmitted. Therefore, according to this embodiment 1, the malfunction of the control circuit CC caused by electrical noise superimposed on the signal can be suppressed, thereby improving the operational reliability of the semiconductor device.

[0068] Transformer TR1 is formed by coils CL1a and CL1b formed on semiconductor chip CHP1. Coils CL1a and CL1b are not connected by a conductor but are magnetically coupled. Therefore, when current flows through coil CL1a, an induced electromotive force is generated in coil CL1b in response to the change in current, resulting in an induced current. At this time, coil CL1a is the primary coil, and coil CL1b is the secondary coil. Thus, in this embodiment 1, the electromagnetic induction phenomenon generated between coils CL1a and CL1b is utilized. That is, in this embodiment 1, a signal is sent from transmitting circuit TX1 to coil CL1a of transformer TR1, causing current to flow. Correspondingly, receiving circuit RX1 detects the induced current generated in coil CL1b of transformer TR1, thereby enabling receiving circuit RX1 to receive a signal corresponding to the control signal output from transmitting circuit TX1.

[0069] Similarly, transformer TR2 is formed by coils CL2a and CL2b formed on semiconductor chip CHP1. Coils CL2a and CL2b are not connected by conductors but are magnetically coupled. Therefore, when current flows through coil CL2b, an induced electromotive force is generated in coil CL2a in response to the change in current, resulting in an induced current. Thus, in this embodiment 1, a signal is sent from transmitting circuit TX2 to coil CL2b of transformer TR2, causing current to flow. Correspondingly, receiving circuit RX2 detects the induced current generated in coil CL2a of transformer TR2, thereby enabling receiving circuit RX2 to receive a signal corresponding to the control signal output from transmitting circuit TX2.

[0070] Signal transmission and reception between semiconductor chips CHP1 and CHP2 are achieved using paths from transmitting circuit TX1 via transformer TR1 to receiving circuit RX1 and from transmitting circuit TX2 via transformer TR2 to receiving circuit RX2. Specifically, receiving circuit RX1 receives the signal transmitted by transmitting circuit TX1, and receiving circuit RX2 receives the signal transmitted by transmitting circuit TX2, thus enabling signal transmission and reception between semiconductor chips CHP1 and CHP2. As described above, transformer TR1 is used in the signal transmission from transmitting circuit TX1 to receiving circuit RX1, and transformer TR2 is used in the signal transmission from transmitting circuit TX2 to receiving circuit RX2. Therefore, drive circuit DR can drive inverter INV, which operates the load LOD, according to the signal transmitted from semiconductor chip CHP1 to semiconductor chip CHP2.

[0071] The reference potential voltage levels of semiconductor chips CHP1 and CHP2 are different. That is, in semiconductor chip CHP1, the reference potential is fixed to the ground potential GND1. On the other hand, as... Figure 1As shown, the semiconductor chip CHP2 is electrically connected to the inverter INV, and the drive circuit DR that drives the inverter INV is formed on the semiconductor chip CHP2. The inverter INV has, for example, a high-side IGBT (Insulated Gate Bipolar Transistor) and a low-side IGBT. Furthermore, in the inverter INV, the on / off control of the high-side IGBT and the low-side IGBT is performed by the drive circuit DR formed on the semiconductor chip CHP2, thereby realizing the load LOD control implemented by the inverter INV. Specifically, the on / off control of the high-side IGBT is performed by controlling the potential applied to the gate electrode of the high-side IGBT by the drive circuit DR formed on the semiconductor chip CHP2. Similarly, the on / off control of the low-side IGBT is performed by controlling the potential applied to the gate electrode of the low-side IGBT by the drive circuit DR formed on the semiconductor chip CHP2.

[0072] Here, for example, the turn-on control of the low-side IGBT is achieved by applying an "emitter potential (0V) + threshold voltage (15V)" to the gate electrode, using the emitter potential (0V) of the low-side IGBT connected to ground potential GND2 as a reference. On the other hand, for example, the turn-off control of the low-side IGBT is achieved by applying an "emitter potential (0V)" to the gate electrode, using the emitter potential (0V) of the low-side IGBT connected to ground potential GND2 as a reference. Therefore, the turn-on / turn-off control of the low-side IGBT is performed based on 0V as a reference potential, depending on whether a threshold voltage (15V) is applied to the gate electrode.

[0073] On the other hand, for example, the on-state control of the high-side IGBT is also based on the emitter potential of the high-side IGBT as a reference potential, and the gate electrode is controlled by applying a "reference potential + threshold voltage (15V)" relative to this reference potential. However, the emitter potential of the high-side IGBT is not fixed to the ground potential GND2 like the emitter potential of the low-side IGBT. That is, in the inverter INV, the high-side IGBT and the low-side IGBT are connected in series between the power supply potential VCC2 and the ground potential GND2. Furthermore, in the inverter INV, control is performed to turn off the low-side IGBT when the high-side IGBT is turned on, and to turn on the low-side IGBT when the high-side IGBT is turned off. Therefore, when the high-side IGBT is turned off, since the low-side IGBT is turned on, the emitter potential of the high-side IGBT becomes the ground potential GND2 through the turned-on low-side IGBT. On the other hand, when the high-side IGBT is turned on, since the low-side IGBT is turned off, the emitter potential of the high-side IGBT becomes the power supply potential VCC2. At this time, the on / off control of the high-side IGBT is based on the emitter potential of the high-side IGBT as a reference potential and is performed according to whether "reference potential + threshold voltage (15V)" is applied to the gate electrode.

[0074] As described above, the emitter potential of the high-side IGBT varies when the high-side IGBT is on and off. That is, the emitter potential of the high-side IGBT varies between the ground potential GND2 (0V) and the power supply potential VCC2 (e.g., 600V). Therefore, in order to turn on the high-side IGBT, it is necessary to apply a "reference potential (600V) + threshold voltage (15V)" to the gate electrode, using the emitter potential of the high-side IGBT as a reference potential. Therefore, the drive circuit DR, which controls the on / off state of the high-side IGBT, needs to know the emitter potential of the high-side IGBT. Therefore, the drive circuit DR is configured to input the emitter potential of the high-side IGBT. As a result, a reference potential of 600V is input to the drive circuit DR formed on the semiconductor chip CHP2, and the drive circuit DR applies a threshold voltage of 15V (15V) to the gate electrode of the high-side IGBT relative to this 600V reference potential, thereby controlling the high-side IGBT to be turned on. Therefore, a high potential of approximately 600V is applied to the semiconductor chip CHP2. Thus, a circuit for handling low potentials (tens of V) is formed in the semiconductor chip CHP1 of this embodiment, while a circuit for handling high potentials (hundreds of V) is formed in the semiconductor chip CHP2 of this embodiment. Therefore, signal transmission between semiconductor chips CHP1 and CHP2 requires signal transfer between circuits at different potentials.

[0075] In this respect, in this embodiment 1, the signal transmission between semiconductor chip CHP1 and semiconductor chip CHP2 is carried out by placing transformer TR1 and transformer TR2 between them, so that signals can be transmitted between circuits with different potentials.

[0076] As mentioned above, in transformers TR1 and TR2, a large potential difference sometimes occurs between the primary and secondary coils. Conversely, because this large potential difference sometimes occurs, the primary and secondary coils, which are magnetically coupled without being connected by conductors, are used for signal transmission. Therefore, when forming transformer TR1, it is important to maximize the insulation withstand voltage between coils CL1a and CL1b, from the viewpoint of improving the operational reliability of the semiconductor device. Similarly, when forming transformer TR2, it is also important to maximize the insulation withstand voltage between coils CL2b and CL2a, from the viewpoint of improving the operational reliability of the semiconductor device.

[0077] <Example of signal transmission>

[0078] Figure 2 This is an explanatory diagram illustrating an example of signal transmission. In Figure 2 In the process, the transmitting circuit TX1 extracts the edge portion of the square wave signal SG1 input to the transmitting circuit TX1, generates a constant pulse width signal SG2, and sends it to the coil CL1a (primary coil) of the transformer TR1. When the current based on this signal SG2 flows through the coil CL1a (primary coil) of the transformer TR1, the corresponding signal SG3 flows through the coil CL1b (secondary coil) of the transformer TR1 due to the induced electromotive force. The receiving circuit RX1 amplifies this signal SG3 and further modulates it into a square wave, thereby outputting the square wave signal SG4 from the receiving circuit RX1. Thus, the receiving circuit RX1 can output the signal SG4 corresponding to the signal SG1 input to the transmitting circuit TX1. In this way, the signal can be transmitted from the transmitting circuit TX1 to the receiving circuit RX1. The transmission of the signal from the transmitting circuit TX2 to the receiving circuit RX2 can also be performed in the same way.

[0079] <Related Technology Description>

[0080] Next, we will explain the related technologies associated with the device construction of transformers.

[0081] Figure 3 This is a cross-sectional view illustrating a schematic structure of the semiconductor chip CHP1 in which a transformer is formed in the associated technology. Figure 3In the related technology, the semiconductor chip CHP1 has a semiconductor substrate 1S on which a transistor (not shown) is formed. Then, a contact interlayer insulating film CIL is formed on the semiconductor substrate 1S where the transistor is formed, and an interlayer insulating film IL1 is formed on the contact interlayer insulating film CIL. Further, an interlayer insulating film IL2 is formed on the interlayer insulating film IL1, and an interlayer insulating film IL3 is formed on the interlayer insulating film IL2. Then, an interlayer insulating film IL4 is formed on the interlayer insulating film IL3, and a surface protective film (passivation film) PAS is formed on the interlayer insulating film IL4. Further, a polyimide resin film PIF is formed on the surface protective film PAS.

[0082] Next, in Figure 3 The diagram illustrates regions R1, R2, and R3 within the semiconductor chip CHP1. Coils CL1a and CL1b, constituting a transformer, are formed in region R1. Specifically, as shown... Figure 3 As shown, coil CL1a is formed by connecting a wiring pattern formed on the interlayer insulating film CIL in region R1 and a wiring pattern formed on the interlayer insulating film IL1 in region R1 via a pin. On the other hand, above coil CL1a, as shown... Figure 3 As shown, a coil CL1b is formed by a wiring pattern formed on an interlayer insulating film IL4 in region R1, and a pad PD is formed on the same layer as the coil CL1b.

[0083] Next, as Figure 3 As shown, in region R2, multiple grooves DT are formed that extend from the surface of the polyimide resin film PIF through the polyimide resin film PIF, the surface protective film PAS, and the interlayer insulating film IL4 to the interlayer insulating film IL3. Furthermore, insulating material is embedded within the interior of these grooves DT.

[0084] And, as Figure 3 As shown, in region R3, a sealing ring SR is formed that functions as a protective wall to prevent moisture from penetrating into the interior of the semiconductor chip CHP1.

[0085] By using the semiconductor chip CHP1 in the associated technology constructed as described above, the following advantages can be obtained. That is, for example, as when using... Figure 1As explained, a signal is transmitted between semiconductor chips CHP1 and CHP2, i.e., between circuits at different potentials, via transformer TR1. At this time, coils CL1a (primary coil) and CL1b (secondary coil), constituting transformer TR1, are formed on semiconductor chip CHP1, which operates at a low potential. Coil CL1b (secondary coil) formed on semiconductor chip CHP1 is electrically connected to pad PD, and coil CL1b is electrically connected to the drive circuit DR formed on semiconductor chip CHP2 via pad PD. Furthermore, a high potential is applied to the drive circuit DR formed on semiconductor chip CHP2; therefore, a high potential is also applied to coil CL1b, which is electrically connected to the drive circuit DR. This... Figure 3 In the semiconductor chip CHP1 shown, a large potential difference is generated between the coil CL1b, which is subjected to a high potential, and the sealing ring SR, which is electrically connected to the ground potential (0V).

[0086] Here, a low potential is applied to coil CL1a, while a high potential is applied to coil CL1b. Therefore, the insulation withstand voltage between coils CL1a and CL1b could potentially become a problem. However, after investigation, the inventors of this application discovered that, for example, before the insulation withstand voltage between coils CL1a and CL1b becomes a problem, Figure 3 In this process, insulation breakdown between the coil CL1b, which is subjected to a high potential, and the sealing ring SR, which is electrically connected to the semiconductor substrate 1S, which is supplied with a ground potential GND1, becomes apparent as a problem point. That is, based on the inventor's speculation, for example in Figure 3 In this process, at the interface between the interlayer insulating film IL4 and the surface protective film PAS, leakage current easily flows along the interface. As a result, insulation breakdown occurs between the coil CL1b, which is subjected to a high potential, and the sealing ring SR, which is supplied with ground potential GND1, before the insulation withstand voltage between coil CL1a and coil CL1b becomes a problem.

[0087] Therefore, in related technologies, such as Figure 3 As shown, in region 2, which is sandwiched between region R1, where coils CL1a and CL1b are formed, and region R3, where sealing ring SR is formed, multiple grooves DT are formed, and insulating material is embedded inside these grooves DT. Thus, as... Figure 3As shown, an uneven shape is formed at the interface between the interlayer insulating film IL4 and the surface protective film PAS. This means that the distance between the coil CL1b and the sealing ring SR along the interface between the interlayer insulating film IL4 and the surface protective film PAS increases. As a result, the distance between the coil CL1b and the sealing ring SR along the interface between the interlayer insulating film IL4 and the surface protective film PAS can be increased without increasing the size of the semiconductor chip CHP1. Consequently, the distance between the coil CL1b, which is subjected to a high potential, and the sealing ring SR, which is subjected to a ground potential GND1, becomes longer, thereby, according to the associated technology, insulation breakdown between the coil CL1b and the sealing ring SR can be suppressed.

[0088] <Research on Improvements in Linkage Technology>

[0089] However, after studying the related technologies, the inventors of this application have realized that there is room for improvement in the related technologies, and therefore, this will be explained below.

[0090] like Figure 3 As shown, in the correlation technique, a groove DT in which insulating material is embedded is formed in region R2, which is sandwiched between region R1 where the coil CL1b is formed and region R3 where the sealing ring SR is formed. Therefore, according to the correlation technique, the distance between the coil CL1b and the sealing ring SR along the interface between the interlayer insulation film IL4 and the surface protective film PAS can be increased. As a result, according to the correlation technique, the advantage of suppressing insulation breakdown between the coil CL1b and the sealing ring SR can be obtained.

[0091] However, in the semiconductor device manufacturing method of the related technology, additional steps are required to form a trench DT and to embed insulating material into the trench DT. In particular, the trench DT formation process requires photolithography and etching processes using masks, and further, the process of embedding insulating material into the trench DT requires a process of depositing insulating material and a process of removing insulating material from the surface of the polyimide film PIF.

[0092] Thus, in this associated technology, by forming a groove DT in which insulating material is embedded, it is possible to suppress insulation breakdown between the coil CL1b and the sealing ring SR. On the other hand, as mentioned above, additional manufacturing steps are required, leading to increased manufacturing complexity. Furthermore, this increased complexity means the corresponding addition of new manufacturing steps, thus increasing the likelihood of a decrease in manufacturing yield. Moreover, since additional manufacturing steps are required and a mask for forming the groove DT is also manufactured, manufacturing costs also increase.

[0093] That is, in the related technology, insulation breakdown between coil CL1b and sealing ring SR can be suppressed. On the other hand, from the viewpoint of suppressing the decrease in manufacturing yield and the increase in manufacturing cost due to the complexity of the manufacturing process, there is room for improvement. Therefore, in this embodiment 1, research is carried out to suppress the decrease in manufacturing yield and the increase in manufacturing cost while achieving the suppression of insulation breakdown between coil CL1b and sealing ring SR. The technical idea of ​​this embodiment 1 obtained by carrying out this research will be explained below.

[0094] <Structure of Semiconductor Chips>

[0095] Figure 4 This is a cross-sectional view illustrating the schematic device structure of the semiconductor chip CHP1 in Embodiment 1. Figure 4 In this embodiment 1, the semiconductor chip CHP1 has a semiconductor substrate 1S on which a transistor (e.g., a field-effect transistor) is formed. Then, on the semiconductor substrate 1S where the transistor is formed, a contact interlayer insulating film CIL, for example made of a silicon oxide film, is formed. On the contact interlayer insulating film CIL, an interlayer insulating film IL1, for example made of a silicon oxide film, is formed. Further, on the interlayer insulating film IL1, an interlayer insulating film IL2, for example made of a silicon oxide film, is formed. On the interlayer insulating film IL2, an interlayer insulating film IL3, for example made of a silicon oxide film, is formed. Then, on the interlayer insulating film IL3, an interlayer insulating film IL4, for example made of a silicon oxide film, is formed. On the interlayer insulating film IL4, a surface protective film (passivation film) PAS, for example made of a silicon nitride film, is formed. A polyimide resin film PIF is formed on the surface protective film PAS.

[0096] Next, in Figure 4 The diagram illustrates regions R1, R2, and R3 within the semiconductor chip CHP1. In region R1, coils CL1a and CL1b, constituting a transformer, are formed. Specifically, as shown... Figure 4 As shown, coil CL1a is formed by connecting a wiring pattern formed on the interlayer insulating film CIL in region R1 and a wiring pattern formed on the interlayer insulating film IL1 in region R1 via a pin. On the other hand, above coil CL1a, as shown... Figure 4As shown, a coil CL1b is formed by a wiring pattern formed on the interlayer insulating film IL4 in region R1, and a pad PD is formed on the same layer as the coil CL1b. In this way, coils CL1a and CL1b are formed in region R1 of the semiconductor chip CHP1, and a transformer is formed by these coils CL1a and CL1b. That is, a transformer capable of transmitting signals between different potentials using inductive coupling is formed in region R1 of the semiconductor chip CHP1.

[0097] Next, as Figure 4 As shown, a convex-concave shape US is formed in the boundary region between the interlayer insulating film IL4 and the surface protective film PAS in region R2 of semiconductor chip CHP1. This convex-concave shape consists of adjacent convex and concave portions. Furthermore, as... Figure 4 As shown, a conductor pattern CP is formed on the protrusion that constitutes the concave-convex shape. This conductor pattern CP is formed on the same layer as the coil CL1b formed in region R1 of the semiconductor chip CHP1. Furthermore, the potential of the conductor pattern CP is a floating potential.

[0098] Next, as Figure 4 As shown, a sealing ring SR is formed in region R3 of the semiconductor chip CHP1, functioning as a protective wall to prevent moisture from penetrating into the interior of the semiconductor chip CHP1. Thus, coils CL1a (inductor) and CL1b (inductor) constituting the transformer are formed in region R1 of the semiconductor chip CHP1, and a conductor pattern disposed on the same layer as coil CL1b is formed in region R2 of the semiconductor chip CHP1. That is, as... Figure 4 As shown, in cross-section, region R2 is the area sandwiched between the end of the semiconductor chip CHP1 and region R1, and a conductor pattern CP is formed in region R2. The conductor pattern CP formed in region R2 is formed on the protrusion constituting the concave-convex shape US. More specifically, the semiconductor chip CHP1 has region R1 where coils CL1a and CL1b constituting a transformer are formed, region R2 where the conductor pattern CP is formed, and region R3 where a sealing ring SR is formed. Furthermore, as... Figure 4 As shown, in cross-section, region R2 is the region sandwiched between region R1 and region R3. In region R2, a concave-convex shape US is formed between the interlayer insulating film IL4 and the surface protective film PAS. A conductor pattern CP is formed on the protrusion constituting the concave-convex shape.

[0099] As described above, the semiconductor device in Embodiment 1 includes a semiconductor chip CHP1 having structural elements capable of transmitting signals between different potentials via inductive coupling. Furthermore, the semiconductor chip CHP1 is, for example, as shown below... Figure 4As shown, the semiconductor substrate 1S includes an interlayer insulating film IL4 formed on top of the semiconductor substrate 1S, a wiring layer formed on the interlayer insulating film IL4 as the uppermost wiring layer, an interlayer insulating film (surface protective film PAS) covering the wiring layer and formed on the interlayer insulating film IL4, a coil CL1b (inductor) formed on the wiring layer, and a conductor pattern CP formed on the wiring layer. Further, as... Figure 4 As shown, the semiconductor chip CHP1 in this embodiment 1 has a lower wiring layer located below the uppermost wiring layer, and a coil CL1a capable of inductively coupling with the coil CL1b is formed in the lower wiring layer.

[0100] At this time, as Figure 4 As shown, a convex-concave shape US is formed between the interlayer insulating film IL4 and the surface protective film PAS (interlayer insulating film). This convex-concave shape includes adjacent convex portions and concave portions, on which a conductor pattern CP is disposed. Here, the interlayer insulating film IL4 and the surface protective film PAS (interlayer insulating film) are composed of different types of films. Specifically, the interlayer insulating film IL4 is composed of a silicon oxide film, while the surface protective film PAS is composed of a silicon nitride film.

[0101] Next, Figure 5 It is shown in magnification Figure 4 A diagram showing a portion of region R2 of the semiconductor chip CHP1. Figure 5 In this process, a convex-concave shape US, consisting of adjacent protrusions and concave portions, is formed between the interlayer insulating film IL4 and the surface protective film PAS. A conductor pattern CP is formed on the protrusions constituting the convex-concave shape US. At this time, as... Figure 5 As shown, when the width of the upper surface of the convex part constituting the concave-convex shape US is set to "w" and the height from the bottom surface of the concave part constituting the concave-convex shape US to the upper surface of the convex part is set to "h", the relationship w < 2 × h holds.

[0102] <Methods for Manufacturing Semiconductor Devices>

[0103] The semiconductor device including the semiconductor chip CHP1 in Embodiment 1 is configured as described above. Hereinafter, its manufacturing method will be described with reference to the accompanying drawings.

[0104] First, by using semiconductor manufacturing technology, forming Figure 6 The structure shown. Specifically, in Figure 6In the illustrated configuration, for example, a contact interlayer insulating film CIL made of silicon oxide film is formed on a semiconductor substrate 1S. An interlayer insulating film IL1, also made of silicon oxide film, is then formed on the contact interlayer insulating film CIL. An interlayer insulating film IL2, also made of silicon oxide film, is then formed on the interlayer insulating film IL1. An interlayer insulating film IL3, also made of silicon oxide film, is then formed on the interlayer insulating film IL2. Finally, an interlayer insulating film IL4, also made of silicon oxide film, is formed on the interlayer insulating film IL3. Furthermore, a coil CL1a is formed in region R1, and a sealing ring SR is formed in region R3.

[0105] In forming the above Figure 6 After the construction shown, as Figure 7 As shown, a conductor film CF is formed on the interlayer insulating film IL4. The conductor film CF is made of, for example, an aluminum film or an aluminum alloy film, and can be formed, for example, by using a sputtering method.

[0106] Next, as Figure 8 As shown, the conductor film CF is patterned using photolithography and etching techniques. The patterning of the conductor film CF is performed by forming the coil CL1b (inductor) and pad PD in region R1, the conductor pattern CP in region R2, and the uppermost layer of the sealing ring in region R3. Thus, the coil CL1b, pad PD, conductor pattern CP, and the uppermost layer of the sealing ring can be formed on the interlayer insulating film IL4 in the same layer.

[0107] Next, as Figure 9 As shown, a portion of the interlayer insulating film IL4 is etched using the patterned conductor film CF as a hard mask, thus forming a textured shape US on the surface of the interlayer insulating film IL4. Specifically, as... Figure 9 As shown, a portion of the interlayer insulating film IL4 is etched using the coil CL1b, pad PD, conductor pattern CP, and the uppermost layer of the sealing ring, which constitute the patterned conductor film CF, as a hard mask. Consequently, in region R1, a groove is formed on the surface of the interlayer insulating film IL4 exposed from the coil CL1b and pad PD. Similarly, in region R2, a groove is formed on the surface of the interlayer insulating film IL4 exposed from the conductor pattern CP, and in region R3, a groove is formed on the surface of the interlayer insulating film IL4 exposed from the uppermost layer of the sealing ring SR.

[0108] Subsequently, as Figure 10As shown, a surface protective film (PAS) is formed to cover the coil CL1b, pad PD, conductor pattern CP, and sealing ring on the interlayer insulating film IL4, which is formed with an uneven shape. This surface protective film PAS is, for example, made of silicon nitride film, and can be formed, for example, using a CVD (Chemical Vapor Deposition) method. Then, openings are formed in the surface protective film PAS to expose the surface of the pad PD using photolithography and etching techniques. Then, as... Figure 4 As shown, a photosensitive polyimide resin film (PIF) is formed on a surface protective film (PAS) with openings. The openings are then formed in the PIF using photolithography. Thus, as... Figure 4 As shown, the surface of the pad PD is exposed through the openings formed in the surface protective film PAS and the openings formed in the polyimide resin film PIF.

[0109] Subsequent processes can manufacture a semiconductor device including the semiconductor chip CHP1 in Embodiment 1 using conventional semiconductor manufacturing techniques.

[0110] <Features in Implementation Method 1>

[0111] Next, the feature points in this embodiment 1 will be explained. First, the first feature point in this embodiment 1 is, for example, as follows: Figure 4 As shown, the uneven shape US is formed in the region R2 sandwiched between region R1, where the semiconductor chip CHP1 containing the coils CL1a and CL1b constituting the transformer, and region R3, where the semiconductor chip CHP1 containing the sealing ring SR is formed. Specifically, the first feature of this embodiment 1 is that the uneven shape US is formed between the interlayer insulating film IL4 and the surface protective film PAS. Thus, for example, as... Figure 4 As shown, the creepage distance between the interlayer insulating film IL4 and the surface protective film PAS at the interface between the coil CL1b (secondary coil) with applied high potential and the sealing ring SR with applied reference potential (0V) can be increased. According to the first feature of this embodiment 1, this means that the leakage current flowing between the coil CL1b with applied high potential and the sealing ring SR with applied reference potential (0V) can be reduced, thereby improving the insulation withstand voltage between the coil CL1b and the sealing ring SR. As a result, according to the first feature of this embodiment 1, the reliability of the semiconductor device can be improved.

[0112] Next, the second feature of this embodiment 1 is, for example, as Figure 4As shown, a conductor pattern CP is formed on the uneven shape US of region R2 formed in the semiconductor chip CHP1. Specifically, the second feature of this embodiment 1 is that the conductor pattern CP, formed on the same layer as the coil CL1b of region R1, is formed on the protrusion of the uneven shape US constituting region R2. Regarding this point, after studying the manufacturing method of the semiconductor device in this embodiment 1, the structure of the second feature point is reflected in the final structure of the semiconductor chip CHP1. That is, the essence of the second feature point in this embodiment 1 lies in the study point in the manufacturing method of the semiconductor device in this embodiment 1.

[0113] Specifically, the focus of the research in the semiconductor device manufacturing method of this embodiment 1 is, for example, as Figures 8-9 As shown, a portion of the interlayer insulating film IL4 is etched using a patterned conductor film, comprising a conductor pattern CP and a coil CL1b formed on the same layer, as a hard mask. In this case, firstly, as... Figure 8 As shown, by making the conductor film CF (refer to) formed on the interlayer insulating film IL4 Figure 7 Patterning is performed to form a coil CL1b in region R1 and a conductor pattern CP in region R2. In this case, during the process of forming the coil CL1b on the interlayer insulating film IL4 in region R1, the conductor pattern CP is formed on the interlayer insulating film IL4 in region R2. Therefore, in this embodiment 1, it is not necessary to add a new process for forming the conductor pattern CP (first advantage).

[0114] Furthermore, in the semiconductor device manufacturing method of Embodiment 1, such as Figure 9 As shown, a portion of the interlayer insulating film IL4 in region R2 is etched by setting the aforementioned conductor pattern CP as a hard mask, thereby forming a raised / lower shape US on the surface of the interlayer insulating film IL4 in region R2. In this case, the raised / lower shape US is also formed using the conductor pattern CP formed on the same layer as the coil CL1b. Therefore, in this embodiment 1, it is not necessary to add a new mask for forming the raised / lower shape US (second advantage).

[0115] Therefore, according to the research point in the semiconductor device manufacturing method of Embodiment 1, in order to form the uneven shape US, it is not necessary to add a dedicated manufacturing process solely for forming the uneven shape US. According to the semiconductor device manufacturing method of Embodiment 1, this means that the uneven shape US can be formed on the surface of the interlayer insulating film IL4 while suppressing the complexity of the manufacturing process. Therefore, according to Embodiment 1, it is possible to suppress the decrease in manufacturing yield and the increase in manufacturing cost caused by the complexity of the manufacturing process, and to suppress the insulation breakdown between the coil CL1b and the sealing ring SR caused by forming the uneven shape US. That is, in Embodiment 1, by combining the first feature point and the second feature point (reflection of the research point in the manufacturing method), a significant effect can be achieved whereby the decrease in manufacturing yield and the increase in manufacturing cost can be suppressed even while suppressing the insulation breakdown between the coil CL1b and the sealing ring SR.

[0116] Next, the third feature in this embodiment 1 is, for example, as Figure 5 As shown, when the width of the upper surface of the convex portion constituting the concave-convex shape US is set to "w" and the height from the bottom surface of the concave portion constituting the concave-convex shape US to the upper surface of the convex portion is set to "h", the relationship w < 2 × h holds true. Therefore, according to the third feature point in Embodiment 1, it is possible to increase the substantial creepage distance between the interlayer insulating film IL4 and the surface protective film PAS at the interface between the coil CL1b (secondary coil) to which a high potential is applied and the sealing ring SR to which a reference potential (0V) is applied. This is because, in Embodiment 1, for example, as... Figure 5 As shown, a conductor pattern CP is formed on the protrusion constituting the uneven shape US. Therefore, the upper surface of the protrusion is in close contact with the conductor pattern CP. It is assumed that the distance equivalent to the width of the upper surface of the protrusion is based on the conduction path of the conductor pattern, and therefore, it is difficult to help increase the substantial creepage distance. That is, even if the uneven shape US is formed on the surface of the interlayer insulating film IL4, it is difficult to ensure a substantial increase in the creepage distance if the relationship w>2×h holds. In this regard, according to the third feature point in Embodiment 1, by providing the uneven shape US, the substantial creepage distance can be reliably increased, and therefore, it is easy to achieve an increase in the insulation withstand voltage between the coil CL1b and the sealing ring SR. Therefore, it can be said that when the first and second feature points in Embodiment 1 are combined, it is further desirable to adopt the third feature point in Embodiment 1, based on the viewpoint that a substantial increase in the creepage distance can be easily ensured.

[0117] <Variation Example>

[0118] Next, a variation of this embodiment 1 will be described.

[0119] <<Structure of Semiconductor Chips>>

[0120] Figure 11 This is a cross-sectional view illustrating the schematic structure of the semiconductor chip CHP1 in this modified example. (See attached image.) Figure 11 As shown, in this modified example, the uneven shape US is formed between interlayer insulating films IL3 and IL4, not between the interlayer insulating film IL4 and the surface protective film PAS. Furthermore, the coil CL1b and conductor pattern CP are formed on the same layer, not on the interlayer insulating film IL4, but on the interlayer insulating film IL3. Therefore, unlike Embodiment 1, in this modified example, the coil CL1b and conductor pattern CP are not formed on the uppermost wiring layer, but on an intermediate wiring layer. In other words, other wiring layers exist above the wiring layer where the coil CL1b and conductor pattern CP are formed.

[0121] Here, interlayer insulating film IL3 and interlayer insulating film IL4 are composed of the same type of film. Specifically, interlayer insulating film IL3 is composed of a silicon oxide film, and interlayer insulating film IL4 is also composed of a silicon oxide film.

[0122] <<Methods for Manufacturing Semiconductor Devices>>

[0123] The semiconductor chip CHP1 in this modified example is constructed as described above. The manufacturing method will be described below with reference to the accompanying drawings.

[0124] First, such as Figure 12 As shown, after forming a coil CL1b and a conductor pattern CP on the interlayer insulating film IL3 formed above the semiconductor substrate 1S, the coil CL1b and conductor pattern CP formed on the same layer are used as a hard mask to etch a portion of the interlayer insulating film IL3 exposed from the conductor pattern CP. Thus, as... Figure 12 As shown, a concave-convex shape US can be formed on the surface of the interlayer insulating film IL3.

[0125] Next, as Figure 13 As shown, the interlayer insulating film IL4 is formed to cover the conductor pattern CP and coil CL1b formed on the interlayer insulating film IL3, which has an uneven shape. The interlayer insulating film IL4 is, for example, made of silicon oxide film, and is formed, for example, by using a CVD method. At this time, as Figure 13 As shown, the surface of the interlayer insulating film IL4 has a shape that reflects the uneven shape US of the surface of the interlayer insulating film IL3 formed in the lower layer.

[0126] Subsequently, as Figure 14 As shown, for example, the surface of the interlayer insulating film IL4 is planarized using a chemical mechanical polishing (CMP) method. Then, as... Figure 15As shown, a surface protective film PAS, for example made of silicon nitride, is formed on the interlayer insulating film IL4, which is formed by planarizing the surface. Subsequent processes are omitted. As described above, a semiconductor device including the semiconductor chip CHP1 in this modified example can be manufactured.

[0127] <<Unique Advantages of the Variation>>

[0128] In this modified example, since the first feature point and the second feature point in the above embodiment 1 are included, it is possible to obtain a significant effect that, despite achieving the suppression of insulation breakdown between the coil CL1b and the sealing ring SR, the manufacturing yield rate can still be suppressed and the manufacturing cost can still be increased.

[0129] Furthermore, according to this modification, the following advantages are provided. That is, in the method for manufacturing the semiconductor device in this modification, for example as... Figures 13-14 As shown, when the coil CL1b and conductor pattern CP are formed on the lower layer, a planarization process is performed on the surface of the interlayer insulating film IL4. The planarization of the interlayer insulating film IL4 is performed using the CMP method. However, in the CMP method, depending on the density of the patterns (coil CL1b and conductor pattern CP) formed on the substrate, the surface of the interlayer insulating film IL4 on sparsely patterned surfaces experiences a depression, a so-called indentation. Regarding this, when the conductor pattern CP is not formed in region R2, no pattern is formed on the lower layer of the interlayer insulating film IL4 in region R2; therefore, indentation is more likely to occur on the surface of the interlayer insulating film IL4 in region R2. In contrast, in this modified example, as... Figures 13-14 As shown, when the coil CL1b and conductor pattern CP are formed on the lower layer, the surface planarization treatment of the interlayer insulating film IL4 is performed. That is, in this modified example, the surface planarization treatment of the interlayer insulating film IL4 is performed when the density of the pattern on the lower layer is low. As a result, according to this modified example, the flatness of the surface of the interlayer insulating film IL4 can be improved in the planarization process of the interlayer insulating film IL4 using the CMP method.

[0130] (Implementation Method 2)

[0131] In this second embodiment, with reference to the accompanying drawings, the study points related to the planar layout of the coil CL1b and the conductor pattern CP will be explained.

[0132] Figure 16 This is a schematic diagram showing the planar layout of the coil CL1b and conductor pattern CP1 (CP) formed on the same layer in this embodiment 2. Figure 16As shown, in top view, the conductor pattern CP1 is composed of a closed pattern surrounding the coil CL1b (inductor). Thus, the conductor pattern CP1 is formed in all directions centered on the coil CL1b. This means that a concave-convex shape is formed in all directions surrounding the coil CL1b, matching the conductor pattern CP1. As a result, according to Embodiment 2, regardless of which direction the sealing ring with a reference potential (0V) is located on the coil CL1b, there will always be a concave-convex shape matching the conductor pattern CP1 between them. Therefore, regardless of which direction the sealing ring is located relative to the position where the coil CL1b is positioned, leakage current flowing between the coil CL1b with a high potential and the sealing ring SR with a reference potential (0V) is applied can be reduced. Therefore, according to the planar layout of the coil CL1b and the conductor pattern CP in Embodiment 2, the insulation withstand voltage between the coil CL1b and the sealing ring SR can be improved. That is, according to Embodiment 2, the reliability of the semiconductor device can be improved.

[0133] Furthermore, by forming the conductor pattern CP1 with a closed pattern surrounding the coil CL1b, the following advantages can be obtained. Specifically, according to this embodiment 2, the degree of freedom in the arrangement of the coil CL1b to which a high potential is applied can be increased. For example, the location of the coil CL1b on the semiconductor chip depends on the layout design, but if the conductor pattern CP1 is not formed with a closed pattern surrounding the coil CL1b, depending on the layout design, the arrangement of the coil CL1b may be close to wiring patterns with different potentials applied in the direction where the conductor pattern CP1 is not formed. In this case, the possibility of insulation breakdown between the coil CL1b to which a high potential is applied and the wiring pattern increases. To prevent such a situation, when the conductor pattern CP1 is not formed with a closed pattern surrounding the coil CL1b, the layout design needs to take into account the situation where wiring patterns with different potentials applied in the direction where the conductor pattern CP1 is not formed are close to each other. This means that the design rules must be carefully determined, which leads to the complexity of the layout design.

[0134] In contrast, as shown in Embodiment 2, when the conductor pattern CP1 is formed by a closed pattern surrounding the coil CL1b, any direction centered on the coil CL1b is equivalent. Therefore, it means that the potential for insulation breakdown can be reliably reduced simply by setting design rules, for example, to arrange wiring patterns with different potentials applied at a predetermined distance from the coil CL1b's location. That is, according to Embodiment 2, the wiring pattern's orientation is no longer necessary to prevent insulation breakdown. This means improved ease of layout design, thereby increasing layout design efficiency and shortening turnaround time (TAT). Therefore, according to Embodiment 2, manufacturing costs can be reduced due to shorter turnaround time.

[0135] <Variation Example 1>

[0136] Next, a variation of embodiment 2, example 1, will be described. Figure 17 This is a schematic diagram showing the planar layout of the coil CL1b and conductor pattern CP, which are formed on the same layer in this modified example 1. Figure 17 As shown, the conductor pattern CP surrounding the coil CL1b has a conductor pattern CP2a that has multiple gaps when viewed from above and surrounds the coil CL1b, and a conductor pattern CP2b that has multiple gaps and surrounds the conductor pattern CP2a.

[0137] According to this modified example 1, the increase of noise at coil CL1b can be suppressed. That is, if the conductor pattern CP is formed by a closed pattern surrounding coil CL1b, it is assumed that a reverse electromotive force is generated in conductor pattern CP due to electromagnetic induction caused by the change in magnetic flux generated from coil CL1b, and the noise caused by this reverse electromotive force is applied to coil CL1b.

[0138] In contrast, according to this Modification 1, neither the conductor patterns CP2a nor CP2b constituting the conductor pattern CP are composed of closed patterns. Therefore, the overlap of noise caused by the above mechanism with the coil CL1b can be suppressed. Furthermore, in this Modification 1, the gaps formed in the conductor pattern CP2a and the gaps formed in the conductor pattern CP2b are staggered. Thus, according to this Modification 1, it is possible to prevent the gaps formed in the conductor pattern CP2a and the gaps formed in the conductor pattern CP2b from being arranged in a straight line. As a result, for example, it is possible to suppress the absence of uneven shapes on the line segment connecting the coil CL1b and the sealing ring, thereby suppressing insulation breakdown between the coil CL1b and the sealing ring. That is, according to this Modification 1, although noise caused by the presence of the conductor pattern CP is prevented from being applied to the coil CL1b, insulation breakdown between the coil CL1b and the sealing ring can still be reliably suppressed.

[0139] <Variation Example 2>

[0140] Next, a variation of embodiment 2 will be described. Figure 18 This is a schematic diagram showing the planar layout of the coil CL1b and conductor pattern CP3 (CP) formed on the same layer in this modified example 2. Figure 18 As shown, the conductor pattern CP3 surrounding the coil CL1b is composed of a spiral pattern that surrounds the coil CL1b when viewed from above. Because the conductor pattern CP3 is not a closed pattern, the overlap of noise to the coil CL1b caused by the aforementioned mechanism can also be suppressed. That is, through this modified example 2, it is also possible to prevent noise caused by the presence of the conductor pattern CP3 from being applied to the coil CL1b, and reliably suppress insulation breakdown between the coil CL1b and the sealing ring.

[0141] (Implementation Method 3)

[0142] Next, this implementation method 3 will be described.

[0143] Figure 19 This diagram illustrates a structural example of the drive control unit for loads such as drive motors in Embodiment 3. Figure 19 As shown, the drive control unit in this embodiment 3 includes a control circuit CC, transformer TR1, transformer TR2, drive circuit DR, and inverter INV, which are electrically connected to the load LOD. Specifically, as... Figure 19 As shown, in this embodiment 3, the control circuit CC, the transmitting circuit TX1, the coil CL1a constituting transformer TR1, the receiving circuit RX2, and the coil CL2a constituting transformer TR2 are formed on the semiconductor chip CHP1. On the other hand, as... Figure 19 As shown, in this embodiment 3, the receiving circuit RX1, the coil CL1b constituting the transformer TR1, the transmitting circuit TX2, and the coil CL2b constituting the transformer TR2 are formed on the semiconductor chip CHP2.

[0144] Figure 20 This is a cross-sectional view illustrating the schematic structure of the semiconductor device in Embodiment 3. (Example) Figure 20 As shown, in the semiconductor device of this embodiment 3, a semiconductor chip CHP2 is stacked on a semiconductor chip CHP1 with the direct contact film DAF in between.

[0145] First, such as Figure 20As shown, in the semiconductor chip CHP1, in the uppermost wiring layer, the coil CL1a and the conductor pattern CP are formed on the same layer, and a concave-convex shape US is formed to match the conductor pattern CP. Furthermore, a sealing ring SR1a is formed at the left end of the semiconductor chip CHP1, and a sealing ring SR1b is formed at the right end of the semiconductor chip CHP1.

[0146] Next, as Figure 20 As shown, in the semiconductor chip CHP2, a coil CL1b is formed on the topmost wiring layer. Furthermore, a sealing ring SR2b is formed at the left end of the semiconductor chip CHP2, and a sealing ring SR2a is formed at the right end of the semiconductor chip CHP2.

[0147] In particular, in the semiconductor device of this embodiment 3, in order to enable the coil CL1a formed on the semiconductor chip CHP1 and the coil CL1b formed on the semiconductor chip CHP2 to be inductively coupled, the semiconductor chip CHP2 is stacked on top of the semiconductor chip CHP1.

[0148] Here, in this embodiment 3, the coils CL1a and CL1b, which are inductively coupled to each other, are formed on different semiconductor chips (CHP1, CHP2). Therefore, it is not as shown in embodiment 1 above (see...). Figure 4 The semiconductor chip CHP1 contains a coil CL1b with a high potential and a sealing ring with a reference potential (0V). That is, in the structure of the semiconductor device in this embodiment 3, the coil CL1a formed in the semiconductor chip CHP1 is a coil with a low potential; therefore, it is assumed that insulation breakdown between the coil CL1a and the sealing ring with the applied reference potential (0V) will not become a significant problem.

[0149] However, the inventors of this application have made a new discovery after research, such as Figure 20 As shown, the sealing ring SR1a, formed on the semiconductor chip CHP1 and subjected to a reference potential (0V), and the coil CL1b, formed on the semiconductor chip CHP2 and subjected to a high potential ("reference potential (600V) + specified voltage"), carry leakage current through the leakage path through the end of the semiconductor chip CHP2, as indicated by the thick arrow. Therefore, in the semiconductor device of this embodiment 3, leakage current also flows as... Figure 20As shown, the technical significance of employing a concave-convex shape that matches the conductor pattern CP formed in the same layer as the coil CL1a is fully apparent from the viewpoint of suppressing insulation breakdown between the coil CL1b formed on the semiconductor chip CHP2 and the sealing ring SR1a formed on the semiconductor chip CHP1. That is, the technical concept in Embodiment 1 described above is useful not only for the semiconductor device in Embodiment 1 described above, but also for the semiconductor device in this Embodiment 3. In particular, in Figure 20 In the structure shown, an uneven shape US is formed between the interlayer insulating film (silicon oxide film) IL4 and the surface protective film (silicon nitride film) PAS. Therefore, it is effective when the interface between the interlayer insulating film (silicon oxide film) IL4 and the surface protective film (silicon nitride film) PAS is the main leakage path.

[0150] In addition, Figure 20 In this context, the insulation withstand voltage between the coil CL1b formed on the semiconductor chip CHP2 and the sealing ring SR2b, which is also formed on the semiconductor chip CHP2, does not become a significant issue. This is because the reference potential (for the high side) at the semiconductor chip CHP2 is, for example, not 0V but 600V. Applying a "reference potential (600V) + specified voltage" to the coil CL1b results in a potential difference between the sealing ring SR2b and the coil CL1b that is small enough not to become a significant issue compared to the potential difference between the coil CL1b and the sealing ring SR1a.

[0151] <Variation Example>

[0152] Next, a variation of implementation 3 will be described.

[0153] Figure 21 This is a cross-sectional view illustrating the schematic structure of the semiconductor device in this modified example. Figure 21 In the variant shown, the coil CL1a and conductor pattern CP are formed on the same layer as the wiring layer below the top wiring layer of the semiconductor chip CHP1, not on the topmost wiring layer.

[0154] In the semiconductor device of this modified example, the viewpoint of suppressing insulation breakdown in the event that leakage current flows through the sealing ring SR1a formed on the semiconductor chip CHP1 and the coil CL1b formed on the semiconductor chip CHP2 via the leakage path indicated by the thick arrow through the end of the semiconductor chip CHP2 is effective. That is, in this modified example, an uneven shape US is formed between the interlayer insulating film (silicon oxide film) IL3 and the interlayer insulating film (silicon oxide film) IL4, thus it is effective when the interface between the interlayer insulating film (silicon oxide film) IL3 and the interlayer insulating film (silicon oxide film) IL4 is the main leakage path.

[0155] The invention made by the inventor of this application has been specifically described above according to its implementation method. However, the present invention is not limited to the above implementation method. Various modifications can be made within the scope of its spirit, which goes without saying.

Claims

1. A semiconductor device capable of signal transmission using inductive coupling, wherein the semiconductor device comprises a first semiconductor chip, and the first semiconductor chip includes: a first interlayer insulating film; a wiring layer formed on the first interlayer insulating film; a second interlayer insulating film covering the wiring layer and formed on the first interlayer insulating film, the second interlayer insulating film spanning two layers, namely the wiring layer and the first interlayer insulating film; a first inductor formed on the wiring layer; and a conductor pattern formed on the wiring layer, wherein an uneven shape is formed between the first interlayer insulating film and the second interlayer insulating film, the uneven shape includes a convex portion and a concave portion adjacent to each other, and the convex portion and the concave portion are located on the first interlayer insulating film, the conductor pattern is disposed on the convex portion, the first interlayer insulating film is formed above a semiconductor substrate, a conductor film is formed on the first interlayer insulating film, the first inductor is formed in a first region by patterning the conductor film, and the conductor pattern is formed in a second region. By using the patterned conductor film as a mask to etch a part of the first interlayer insulating film, the uneven shape is formed on the surface of the first interlayer insulating film, covering the patterned conductor film, and the second interlayer insulating film is formed on the surface of the first interlayer insulating film where the uneven shape is formed.

2. The semiconductor device according to claim 1, wherein the first interlayer insulating film and the second interlayer insulating film are made of films of different types from each other.

3. The semiconductor device according to claim 2, wherein the first interlayer insulating film is a silicon oxide film, and the second interlayer insulating film is a silicon nitride film.

4. The semiconductor device according to claim 1, wherein when the width of the upper surface of the convex portion is set as w and the height from the bottom surface of the concave portion to the upper surface of the convex portion is set as h, the relationship w < h×2 holds.

5. The semiconductor device according to claim 1, wherein the first semiconductor chip has a lower-layer wiring layer located below the wiring layer, and a second inductor capable of inductive coupling with the first inductor is formed in the lower-layer wiring layer.

6. The semiconductor device according to claim 1, wherein the semiconductor device includes a second semiconductor chip, and a second inductor capable of inductive coupling with the first inductor formed in the first semiconductor chip is formed in the second semiconductor chip.

7. The semiconductor device according to claim 1, wherein the wiring layer is the uppermost wiring layer.

8. The semiconductor device according to claim 1, wherein there are other wiring layers above the wiring layer.

9. The semiconductor device according to claim 1, wherein the first inductor is formed in a first region of the first semiconductor chip, the conductor pattern is formed in a second region of the first semiconductor chip, and in a cross-sectional view, the second region is a region sandwiched between an end portion of the first semiconductor chip and the first region.

10. The semiconductor device according to claim 1, wherein, The first semiconductor chip has: The first region is in which the first inductor is formed; The second region has the conductor pattern formed thereon; as well as The third region has a sealing ring. In cross-section, the second region is the region sandwiched between the first region and the third region.

11. The semiconductor device according to claim 1, wherein, When viewed from above, the conductor pattern is a closed pattern surrounding the first inductor.

12. The semiconductor device according to claim 1, wherein, When viewed from above, the conductor pattern has: A first pattern having multiple gaps and surrounding the first inductor; and The second pattern has multiple gaps and surrounds the first pattern.

13. The semiconductor device according to claim 12, wherein, The gaps formed in the first pattern and the gaps formed in the second pattern are arranged to be staggered from each other.

14. The semiconductor device according to claim 1, wherein, When viewed from above, the conductor pattern is a spiral pattern surrounding the first inductor.

15. The semiconductor device according to claim 1, wherein, The potential of the conductor pattern is a floating potential.

16. The semiconductor device according to claim 1, wherein, The first interlayer insulating film and the second interlayer insulating film are made of the same type of film.

17. The semiconductor device according to claim 16, wherein, The first interlayer insulating film is a silicon oxide film. The second interlayer insulating film is also a silicon oxide film.

18. A method for manufacturing a semiconductor device, comprising the following steps: In step a, a first interlayer insulating film is formed on top of the semiconductor substrate; Step b involves forming a conductor film on the first interlayer insulating film; Step c involves patterning the conductor film to form an inductor in the first region and a conductor pattern in the second region. In step d, a portion of the first interlayer insulating film is etched using the patterned conductor film as a mask, thereby forming an uneven shape on the surface of the first interlayer insulating film. as well as In step e, after step d, the patterned conductor film is covered, and a second interlayer insulating film is formed on the surface of the first interlayer insulating film having the irregular shape.

19. The method of manufacturing a semiconductor device according to claim 18, wherein, The method for manufacturing the semiconductor device further includes a step of planarizing the surface of the second interlayer insulating film by using a chemical mechanical polishing method after step e.

Images