Semiconductor device and method of manufacturing the same

Abstract

This invention provides a semiconductor device and a method for manufacturing the same, which improves the performance of the semiconductor device. One embodiment of the semiconductor device includes a wire (12) bonded at multiple locations on a bonding surface (SEt1) at an opening (13H1) formed on an insulating film of a semiconductor chip. Additionally, the semiconductor device includes a sealing body that seals the semiconductor chip and the wire (12) in contact with the bonding surface (SEt1). The bonding surface (SEt1) has a region (SER1) for bonding portions (12B1) of the wire (12), a region (SER2) for bonding portions (12B2) of the wire (12), and a region (SER3) located between regions (SER1) and (SER2). The width (WH3) of region (SER3) is smaller than the width (WH1) of region (SER1) and the width (WH2) of region (SER2).

Description

Technical Field

[0001] This invention relates to semiconductor devices and methods of manufacturing the same, for example to semiconductor devices in which a portion of a lead connected to a wire is sealed with a resin encapsulant. Background Technology

[0002] Japanese Patent Publication No. 2000-503491 (Patent Document 1) discloses a power semiconductor device in which multiple wires are connected to multiple electrode pads located on the upper surface of a semiconductor chip. Additionally, Patent Document 1 discloses a structure in which wires are connected to multiple locations on a portion of the multiple electrode pads.

[0003] In addition, Japanese Patent Application Publication No. 61-290747 (Patent Document 2) discloses a structure in which bonding pads and test pads are connected by wiring.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Publication No. 2000-503491

[0007] Patent Document 2: Japanese Patent Application Publication No. 61-290747 Summary of the Invention

[0008] The inventors of this application have conducted research on improving the performance of semiconductor devices. For example, there is a technique for bonding a wire at multiple locations on an electrode pad of a semiconductor chip. When the electrode forming surface of the semiconductor chip is covered by an insulating film as a protective film and the wire is bonded at multiple locations on the electrode pad, increasing the opening area of ​​the opening formed in the protective film facilitates wire connection. However, it has been determined that because the bonding interface between the metal material constituting the electrode pad and the resin material used to seal the wire is weak, the portion of the electrode pad where no wire is connected and exposed from the protective film will peel off from the resin sealing the wire (resin sealant). Even if the electrode pad peels off from the resin sealant, the function of the semiconductor device is not immediately impaired. However, considering long-term product quality such as the product lifespan of the semiconductor device, it is preferable to be able to suppress peeling between the electrode pad and the resin sealant.

[0009] Other topics and new features can be identified from the description and accompanying drawings in this specification.

[0010] One embodiment of the semiconductor device includes conductive wires that are bonded to multiple portions of a bonding surface at a first opening formed on an insulating film of a semiconductor chip. Additionally, the semiconductor device includes a sealing material that seals the semiconductor chip and the conductive wires in contact with the bonding surface. The bonding surface includes a first region that bonds to a first bonding portion of the conductive wires, a second region that bonds to a second bonding portion of the conductive wires, and a third region located between the first and second regions. The width of the third region is smaller than the width of both the first and second regions.

[0011] Invention Effects

[0012] According to the above-described embodiment, the performance of semiconductor devices can be improved. Attached Figure Description

[0013] Figure 1 This is an explanatory diagram schematically showing an example of a circuit possessed by a semiconductor device according to one embodiment.

[0014] Figure 2 It is shown Figure 1 A partial cross-sectional view of an example of the component structure of a field-effect transistor shown.

[0015] Figure 3 yes Figure 1 The diagram shows a top view of the semiconductor device.

[0016] Figure 4 yes Figure 3 The semiconductor device shown is viewed from below.

[0017] Figure 5 Is it to Figure 3 The diagram shows a perspective top view of the internal structure of a semiconductor device after the sealing solid has been removed.

[0018] Figure 6 It is along Figure 5 A cross-sectional view along line AA.

[0019] Figure 7 It is Figure 5 The enlarged top view showing the upper surface periphery of the semiconductor chip is shown.

[0020] Figure 8 It is along Figure 7 An enlarged sectional view of line AA.

[0021] Figure 9 yes Figure 7 An enlarged top view of the opening for the source electrode pads shown.

[0022] Figure 10 It is shown in Figure 9The enlarged top view shows the state of the source wire being bonded on the bonding surface.

[0023] Figure 11 It is along Figure 10 An enlarged sectional view of line AA.

[0024] Figure 12 It is aimed at Figure 10 An enlarged top view of the mating surface of the research example.

[0025] Figure 13 It is Figure 10 The enlarged top view shows the periphery of the loop when the connection position of the wire is deviated.

[0026] Figure 8 It shows that it is aimed at Figure 5 An enlarged sectional view of the research example.

[0027] Figure 9 It shows the use Figure 10 An explanatory diagram illustrating the general manufacturing process of a semiconductor device.

[0028] Figure 7 Therefore Figure 7 The diagram shows a top view of the surface (exposed electrode surface) of a semiconductor chip prepared during the semiconductor chip preparation process.

[0029] Figure 6 It will be with Figure 7 An enlarged top view of a portion of the lead frame prepared during the lead frame preparation process is shown.

[0030] Figure 8 It is shown in Figure 7 The enlarged top view shows the state of the sealing solid that encapsulates the semiconductor chip and wires during the sealing process.

[0031] Figure 7 It is along Figure 7 The section along line AA shows an enlarged sectional view of the state in which the lead frame is arranged within the forming mold.

[0032] Figure 9 This is an enlarged cross-sectional view showing the periphery of a wire that is sealed with resin during the sealing process.

[0033] Figure 10 It shows that it is aimed at Figure 8 An enlarged top view of a variant example.

[0034] Figure 5 It is shown in Figure 7 An enlarged top view of an example of a joint surface with wires attached.

[0035] Figure 5 It is shown in Figure 5 An enlarged top view of other examples of joint surfaces with wires.

[0036] Figure 9 It shows that it is aimed at Figure 10 An enlarged top view of a variant example.

[0037] Figure 10 It is shown in Figure 7 An enlarged top view of an example of a joint surface with wires attached.

[0038] Figure 5 It shows that it is aimed at Figure 5 An enlarged top view of a variant example.

[0039] Explanation of reference numerals in the attached figures

[0040] 10 Semiconductor chips

[0041] 10b Back side (front, main face, bottom surface)

[0042] 10s Side view (front view)

[0043] 10t Surface (Face, Main Face, Top Surface)

[0044] 11. Chip bonding materials (adhesive materials)

[0045] 12, 12G, 12S, 12S1, 12S2 wires (metallic wires, conductive components, metal wires)

[0046] 12B1, 12B2, 12B3 Joints (Connecting Parts, Pin-type Joints)

[0047] 12L1, 12L2 ring section (middle section, extension section)

[0048] 13. Insulating film (protective film)

[0049] Openings 13H1, 13H2, 13H3, 13H4, 13H5

[0050] 20 Chip pads (metal plate, chip mounting section, heat sink)

[0051] 20b Lower surface (front, main surface, back, exposed surface, mounting surface)

[0052] 20s, 20s1, 20s2 Side view

[0053] 20t upper surface (face, main surface, surface, chip mounting surface)

[0054] 21, 31 Substrate

[0055] 22, 32 Metal film (coating)

[0056] 30, 30D, 30G, 30S leads (terminals)

[0057] 30b Lower surface (face)

[0058] 30M Internal (Inner Lead Section, Sealed Section)

[0059] 30s side view

[0060] 30t upper surface (surface, conductor mating surface)

[0061] 30W Wire Connection (Lead Post, Pad, Bonding Pad, Wire Connector, Joint)

[0062] 30X External (external lead section, exposed section)

[0063] 40. Sealing solids (resin sealing solids, resin bodies, molding resins)

[0064] 40b Lower surface (mounting surface)

[0065] 40s side view

[0066] 40t upper surface

[0067] 62 Forming mold

[0068] 62B Lower Mold (Second Mold)

[0069] 62C chamber

[0070] 62T Upper Mold (First Mold)

[0071] CH channel formation area

[0072] D drain

[0073] DE Drain electrode (electrode)

[0074] EP epitaxial layer

[0075] G gate electrode

[0076] GE gate electrode pads (electrode, gate electrode)

[0077] GEt, SEt1, SEt2, SEt3, SEt4, SEtH: Joint surfaces (exposed surfaces, joint portions)

[0078] GI gate insulating film

[0079] GP1 and GP2 separation distance

[0080] GP3 length

[0081] Gate wiring (GW)

[0082] HS1, HS2, HS3, HS4 (partial)

[0083] HSM1, HSM2, HSM3, HSM4 protrusions

[0084] HSM5, HSM6 concave part

[0085] HSP1, HSP2, HSP3, HSP4, HSP5, HSP21, HSP22, HSP23, HSP24, and HSP25 (partial list)

[0086] HSM1, HSM2, HSM3, HSM4 protrusions

[0087] HSM5, HSM6 concave part

[0088] HSP1, HSP2, HSP3, HSP4, HSP5, HSP21, HSP22, HSP23, HSP24, and HSP25 (partial list)

[0089] HT1 ring height

[0090] LE1 ring length

[0091] LE2 Length

[0092] LF lead frame

[0093] LFd device formation section

[0094] LFf frame section (frame section)

[0095] LFt tie rod

[0096] Lengths of LM1, LM2, LM3, LM4, LM5, and LM6

[0097] PKG1 semiconductor device

[0098] PRM probe traces

[0099] Q1 transistor

[0100] S source pole

[0101] SE Source electrode pad (electrode, source electrode)

[0102] SR source region

[0103] SW cabling (source cabling)

[0104] TR1 Groove (opening, slot)

[0105] VL1 and VL2 extension lines (imaginary lines)

[0106] WC1, WC2, WH1, WH2, WH3, WH4, WH5, WR1, WR2, WR3, WR4, WR5, WR6, WRP, WW1, WW2 Width (Length, Thickness)

[0107] WH Semiconductor Substrate

[0108] WHt Main side

[0109] WS1 and WS2 distance Detailed Implementation

[0110] (Explanation of the format, basic terminology, and usage of this application)

[0111] In this application, the description of embodiments is divided into multiple parts for convenience, but these parts are not independent of each other, unless otherwise explicitly stated. Regardless of the order of description, each part of a single example may be a detailed description of another part or a partial or complete variation thereof. Furthermore, repeated descriptions of identical parts are generally omitted. Additionally, the constituent elements in the embodiments are not essential unless otherwise explicitly stated, except where their quantity is theoretically limited or where the context clearly indicates otherwise.

[0112] Similarly, in descriptions of embodiments, etc., regarding materials, composition, etc., the phrase "X composed of A" does not exclude the inclusion of elements other than A, unless specifically stated otherwise or clearly not stated otherwise based on the context. For example, the term "composition" means "X containing A as a main component." For example, "silicon component" is not limited to pure silicon, but also includes SiGe (silicon-germanium) alloys or other multi-element alloys with silicon as the main component, components containing other additives, etc. Furthermore, the terms gold plating, Cu layer, nickel plating, etc., include not only components made of pure materials, but also components with gold, Cu, nickel, etc., as main components, respectively, unless specifically stated otherwise.

[0113] Furthermore, when referring to a specific value or quantity, it can be a value exceeding or below that specific value, unless it is specifically stated otherwise, is theoretically limited to that quantity, or is clearly not true from the context.

[0114] In addition, in the various figures of the embodiments, the same or equivalent parts are indicated by the same or similar reference numerals or drawing symbols, and in principle, they are not described repeatedly.

[0115] Furthermore, in the accompanying drawings, where this would complicate matters or where the distinction from a gap is clear, there are instances where even cross-sectional views omit shaded lines. Relatedly, in situations known from the description, there are instances where even closed holes viewed from above are omitted from the background outline. Additionally, even if it is not a cross-section, shaded lines or dotted patterns are sometimes used to clearly indicate that it is not a gap or to show the boundaries of an area.

[0116] In the following description, the terms "contact," "adhesion," "joining," "peeling," and "connection" are used, and their meanings are as follows: "Contact" refers to a state in which at least a portion of two separable components are in contact with each other. "Adhesion" refers to a state in which at least a portion of two separable components (joined materials) are bonded together and fixed by an adhesive. "Joining" refers to a state in which at least a portion of two separable components (joined materials) are bonded together and fixed. The aforementioned "joining" includes mechanical bonding such as anchoring effects, physical bonding such as intermolecular forces, and chemical bonding such as covalent bonding. Furthermore, "joining" includes cases where other components (e.g., adhesives) exist between the joined materials, as well as cases where no other components are present. That is, "joined state" includes "adhesive state." "Peeling" refers to the release of the aforementioned "joined" state, becoming a state in which the components can be separated. Furthermore, the case described only as "peeling" includes not only cases where the entire bond at the joint of the two components is released, but also cases where a portion of the bond at the joint is released. Finally, "connection" refers to a state in which two components are connected (a continuous connection where the connection path is not interrupted midway). This is independent of whether there are other components between the two components. For example, "the state where component A and component B are electrically connected" means that component A and component B can conduct electricity, and it also includes the case where component C is sandwiched between component A and component B. Furthermore, simply stating "the state where component A and component B are connected" means that component A and component B are fixed, and it also includes the case where component C is sandwiched between component A and component B. Additionally, "the state where component A and component B are connected" also includes the case where component A and component B are formed as an inseparable single unit and their shapes or functions can be distinguished. As mentioned above, this also includes the case where the state where component A and component B are formed as a single unit is denoted as "connected".

[0117] Furthermore, in the following description, the terms "solder," "soldering material," "welding material," or "solder composition" refer to, for example, lead (Pb)-containing Sn-Pb solder or so-called lead-free solder that does not actually contain Pb. Examples of lead-free solder include, for example, tin-only (Sn), tin-bismuth (Sn-Bi), tin-copper-silver (Sn-Cu-Ag), tin-copper (Sn-Cu), etc. Here, lead-free solder refers to solder with a lead (Pb) content of 0.1 wt% or less, which is determined according to the RoHS (Restriction of Hazardous Substances) directive standard.

[0118] In this embodiment, as an example of a semiconductor device, a power device or a semiconductor device referred to as a power semiconductor device assembled in a power control circuit such as a power supply circuit will be described. The semiconductor device described below is assembled in a power conversion circuit and functions as a switching element.

[0119] <Circuit Construction Example>

[0120] Figure 5 This is an explanatory diagram schematically showing an example of the circuitry included in the semiconductor device of this embodiment. Additionally, Figure 1 It is shown Figure 8 A partial cross-sectional view of an example of the component structure of a field-effect transistor shown.

[0121] Power control semiconductor devices, also known as power semiconductor devices, include semiconductor elements such as diodes, thyristors, or transistors. Transistors are used in various fields; as shown in this embodiment, a transistor that operates as a switching element within a power control circuit carrying a high current of, for example, 1A (amperes) or more, is called a power transistor. The semiconductor device PKG1 in this embodiment is as follows... Figure 6 As shown, a semiconductor chip 10 has a transistor Q1 formed thereon, which serves as a power transistor. Figure 6 and Figure 7 In the example shown, the transistor Q1 formed on the semiconductor chip 10 is a field-effect transistor, specifically a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In power semiconductor devices, transistors are used as, for example, switching elements. MOSFETs used in power semiconductor devices are called power MOSFETs.

[0122] The term MOSFET is used broadly to refer to a field-effect transistor having a gate electrode made of a conductive material disposed on a gate insulating film. Therefore, the use of MOSFET does not exclude gate insulating films other than oxide films. Furthermore, the use of MOSFET does not exclude gate electrode materials other than metals, such as polysilicon.

[0123] in addition, Figure 5 The transistor Q1 shown is, for example, made of Figure 7 The n-channel field-effect transistor shown is formed. Figure 10 It means Figure 6 A partial cross-sectional view of an example of the component structure of a field-effect transistor shown.

[0124] exist Figure 7 In the example shown, an n-type monocrystalline silicon substrate WH has an n-type monocrystalline silicon substrate WH on its principal surface WHt. - The epitaxial layer EP. The semiconductor substrate WH and the epitaxial layer EP constitute the drain region of the MOSFET (and... Figure 6 The region corresponding to the drain D shown. This drain region is electrically connected to the drain electrode DE formed on the back side of the semiconductor chip 10.

[0125] A p-type layer is formed on the epitaxial layer EP. + The channel formation region CH of the type semiconductor region, on which a n-type semiconductor is formed. + The source region of the semiconductor region (and) Figure 7 The source region SR is shown as the corresponding region of the source S. The source region SR is electrically connected to the source electrode pad (electrode, source electrode) SE formed on the main surface side of the semiconductor chip 10 via lead-out wiring. In addition, a trench (opening, groove) TR1 is formed in the semiconductor region stacked on the semiconductor substrate WH. The trench TR1 extends from the upper surface of the source region SR through the channel formation region CH to the interior of the epitaxial layer EP.

[0126] Additionally, a gate insulating film GI is formed on the inner wall of the trench TR1. Furthermore, a gate electrode G is formed on the gate insulating film GI in a manner that fills the trench TR1. The gate electrode G is electrically connected to the gate electrode pad (electrode, gate electrode) GE of the semiconductor chip 10 via lead-out wiring.

[0127] Furthermore, transistor Q1 has its drain region and source region SR arranged along the thickness direction with the channel region CH separated from it, thus forming a channel along the thickness direction (hereinafter referred to as a vertical channel structure). In this case, compared with a field-effect transistor that forms a channel along the main surface WHt, the area occupied by the device when viewed from above can be reduced. Therefore, the planar size of the semiconductor chip 10 can be reduced.

[0128] Furthermore, with the aforementioned longitudinal channel structure, the channel width per unit area can be increased when viewed from above, thus reducing the conduction resistance. In addition, Figure 10 This is a diagram showing the component structure of a field-effect transistor. Figure 7 The semiconductor chip 10 shown has, for example, Figure 7 The device shown consists of multiple transistors Q1 connected in parallel. This allows the construction of a power MOSFET capable of carrying a large current, such as more than 1 ampere.

[0129] As described above, when multiple transistors Q1 with a vertical channel structure are connected in parallel to form a MOSFET, the electrical characteristics of the MOSFET (mainly its voltage withstand characteristics, on-resistance characteristics, and capacitance characteristics) vary according to the planar dimensions of the semiconductor chip 10. For example, increasing the planar area of ​​the semiconductor chip 10 will increase the number of parallel transistors Q1 (i.e., the number of elements), thus reducing the on-resistance and increasing the capacitance.

[0130] In addition, Figure 12 and Figure 10 The example shown is a MOSFET, which is a power transistor in a power semiconductor device, but various variations can be used. For example, an insulated gate bipolar transistor (IGBT) can be used instead of a MOSFET.

[0131] Semiconductor Devices

[0132] Below, on Figure 12 The packaging structure of the semiconductor device PKG1 shown will be explained. Figure 12 yes Figure 12 A top view of the semiconductor device shown. Additionally, Figure 12 yes Figure 12 The image shows a bottom view of the semiconductor device. Additionally... Figure 12 Is it to Figure 6 The diagram shows a perspective top view of the internal structure of a semiconductor device with the sealing material removed. Additionally, Figure 12 It is along Figure 6 A cross-sectional view along line AA.

[0133] The semiconductor device PKG1 in this embodiment includes a semiconductor chip 10 (see reference). Figure 7 , Figure 9 ), chip pads (metal plate, chip mounting part, heat sink) 20 for mounting semiconductor chip 10 (refer to) Figure 9 The semiconductor chip 10 and the multiple leads (terminals) 30 serve as external terminals. The semiconductor chip 10 and the multiple leads 30 are connected by multiple wires 12 (see reference 12).Figure 9 , Figure 9 Electrical connection. Additionally, the upper surface 20t of the semiconductor chip 10, the chip pad 20, and the interior (inner lead portion, encapsulated portion) 30M of the multiple leads 30 (refer to...) Figure 9 , Figure 10 ) Use sealing solids (resin sealing solids, resin bodies, molding resins) 40 for sealing.

[0134] In this embodiment, such as Figure 10 As shown, when viewed from above, multiple leads 30 are arranged side-by-side with the chip pads 20 along the Y direction, and intersect the Y direction (in... Figure 10 In the example, the X-direction is arranged side-by-side (orthogonally). Additionally, in... Figure 10 In the example shown, when viewed from above, multiple source leads (source leads, source terminals) 30S, drain leads (drain leads, drain terminals) 30D, and gate leads (gate leads, gate terminals) 30G are arranged sequentially along the X direction. Each of the multiple leads 30 has an interior 30M encapsulated by a sealing solid 40 and an exterior (exposed portion, outer lead portion) 30X exposed from the sealing solid 40. Furthermore, as... Figure 10 As shown, the multiple leads 30 each have an upper surface 30t and a lower surface 30b on the opposite side of the upper surface 30t.

[0135] In addition, such as Figure 10 As shown, the semiconductor chip 10 has a surface (upper surface) 10t and a back surface (lower surface) 10b located on the opposite side of the surface 10t. Additionally, as... Figure 10 As shown, the surface 10t (or Figure 6 The rear side 10b) shown is quadrilateral when viewed from above, and has four sides 10s at its perimeter. Figure 7 In the example shown, the semiconductor chip 10 appears rectangular when viewed from above, with its long side arranged along the X direction.

[0136] In addition, such as Figure 9 As shown, a gate electrode G (referencing) is formed on the surface 10t of the semiconductor chip 10. Figure 9 The gate electrode pads GE and S are electrically connected (refer to...). Figure 9 The source electrode pad SE is electrically connected. Additionally, as... Figure 9 As shown, a junction is formed on the back surface 10b of the semiconductor chip 10, corresponding to the drain D (see reference). Figure 7 The drain electrode (electrode) DE is electrically connected. Figure 6 In the example shown, the entire back side 10b of the semiconductor chip 10 becomes the drain electrode DE.

[0137] like Figure 9As shown, when the semiconductor chip 10 is configured with a vertical channel structure, it is possible to reduce the thickness of the semiconductor chip 10 (reducing the thickness of the semiconductor chip 10). Figure 13 The distance between the surface 10t and the back surface 10b shown is used to reduce the on-resistance. On the other hand, from the perspective of increasing the heat capacity of the chip pad 20 or increasing the cross-sectional area of ​​the conductive path for current flow, it is preferable that the chip pad 20 is thicker. Therefore, in Figure 13 In the example shown, the thickness of the chip pad 20 is greater than the thickness of the semiconductor chip 10.

[0138] Additionally, the semiconductor device PKG1 has chip pads (metal plate, chip mounting portion, heat sink) 20 for mounting the semiconductor chip 10. For example... Figure 10 As shown, the chip pad 20 has an upper surface (face, main surface, surface, chip mounting surface) 20t on which the semiconductor chip 10 is mounted by means of a chip bonding material 11, and a lower surface (face, main surface, back surface, exposed surface, mounting surface) 20b opposite to the upper surface 20t. Figure 13 In the example shown, the planar dimension of the semiconductor chip 10 (the area of ​​surface 10t) is smaller than the planar dimension of the chip pad 20 (the area of ​​the upper surface 20t). Additionally, as... Figure 9 As shown, the chip pad 20 has multiple side surfaces 20s at its periphery that are connected to the lower surface 20b.

[0139] In addition, such as Figure 10 As shown, the chip pad 20 is integrally formed with the lead 30D, which serves as the drain terminal. The lead 30D is... Figure 13 The drain D is connected to the external terminal shown. Figure 6 As shown, a transistor Q1 (refer to) serving as a MOSFET is formed on the back side 10b of the semiconductor chip 10. Figure 10 The drain electrode DE is connected to the drain D of the semiconductor chip 10. The drain electrode DE is electrically connected to the chip pad 20 via a chip bonding material 11 made of a conductive material. The chip bonding material 11 is a conductive resin, which is a cured mixture of conductive particles such as solder or silver (Ag) particles and resin. The lead 30D is connected to the chip pad 20 and is electrically connected to the drain electrode DE of the semiconductor chip 10 via the chip pad 20 and the chip bonding material 11. In addition, the lead 30D connected to the chip pad 20 functions as a suspension lead supporting the chip pad 20 in the semiconductor device manufacturing process described later.

[0140] Furthermore, in this embodiment, since the lower surface 20b of the chip pad 20 is exposed from the encapsulating solid 40, the chip pad 20 itself can be considered as a drain terminal. Also, in this embodiment, an implementation using a MOSFET is described as an example of a power transistor; therefore, the lead 30 and the chip pad 20 operate as the drain terminal of the semiconductor device PKG1 in the circuit. However, as a variation, when an IGBT is used as the power transistor, a collector is formed on the back side of the semiconductor chip. Therefore, when the power transistor is an IGBT, the lead 30 and the chip pad 20 operate as the collector terminal of the semiconductor device PKG1 in the circuit.

[0141] In addition, such as Figure 10 As shown, the chip pad 20 has multiple sides 20s, including side 20s1, which is positioned opposite to the multiple leads 30 when viewed from above, and is sealed by a sealing solid 40. Additionally, the multiple sides 20s include side 20s2, which is located on the opposite side of side 20s1, exposed from the sealing solid 40, and sealed by a metal film 22 (see reference). Figure 10 )cover.

[0142] In addition, such as Figure 13 and Figure 10 As shown, the lower surface 20b of the chip pad 20 is exposed from the encapsulating solid 40 on the side of the lower surface 40b of the encapsulating solid 40. Figure 10 In the example shown, the area of ​​the lower surface 20b of the chip pad 20 is less than or equal to the area of ​​the lower surface 40b of the encapsulant 40. Additionally, as... Figure 14 As shown, in a top view taken from the upper surface 20t side of the chip pad 20, a portion of the chip pad 20 protrudes outward from one of the multiple sides 40s of the encapsulating solid 40. Furthermore, as... Figure 14 and Figure 11 As shown, a portion of the upper surface 20t of the chip pad 20 and a portion of the plurality of sides 20s (at least side 20s2) are exposed from the encapsulating solid 40. As shown in this embodiment, by increasing the planar size of the chip pad 20 and exposing a portion of the chip pad 20 from the encapsulating solid 40, the heat dissipation efficiency of heat generated in the semiconductor chip 10 can be improved.

[0143] Furthermore, by exposing the lower surface 20b of the chip pad 20, which is connected to the lead 30D as an external terminal, from the encapsulating solid 40, the cross-sectional area of ​​the current-carrying conduction path can be increased. Therefore, the impedance in the conduction path can be reduced. In particular, when the lead 30D becomes an external terminal corresponding to the output node of the circuit of the semiconductor device PKG1, the power loss of the output wiring can be directly reduced by decreasing the impedance component of the conduction path connected to the lead 30D, which is preferable.

[0144] The chip pad 20 has a substrate 21 made of the same metal material as the multiple leads 30, such as copper (Cu) or an alloy material with copper (Cu) as the main component. In addition, each of the multiple leads 30 has a substrate 31 made of the same metal material as the chip pad 20, such as copper (Cu) or an alloy material with copper (Cu) as the main component.

[0145] Furthermore, the portion of the chip pad 20 exposed from the encapsulating solid 40 (exterior, exposed portion) is covered by a metal film 22. Similarly, the portion of the lead 30 exposed from the encapsulating solid 40 (exterior 30X) is covered by a metal film 32. These metal films 22 and 32 are used to improve the wettability of the soldering material used as a bonding material when mounting the semiconductor device PKG1 to the mounting substrate. The metal films 22 and 32 are, for example, metal plating formed by electroplating. As detailed below, the metal films 22 and 32 are made of, for example, a soldering material containing tin (Sn).

[0146] in addition, Figure 14 and Figure 11 The chip bonding material (adhesive) 11 shown is a conductive component (chip bonding material) used to fix the semiconductor chip 10 to the chip pad 20 and to electrically connect the semiconductor chip 10 to the chip pad 20. The chip bonding material 11 can be, for example, a soldering material. Alternatively, the chip bonding material 11 can also be a conductive resin adhesive material containing a plurality of silver (Ag) particles (Ag filler), known as silver (Ag) paste. Furthermore, although not shown in the figure, a metal film (not shown) with a higher adhesion to the chip bonding material 11 than copper (Cu) or a copper alloy, which serves as the substrate of the chip pad 20, can be formed on a portion of the upper surface 20t of the chip pad 20. This improves the bonding strength between the chip bonding material 11 and the chip pad 20.

[0147] In addition, such as Figure 14As shown, the gate electrode pad GE of the semiconductor chip 10 and the lead 30G are electrically connected via a wire 12 (specifically, wire 12G). Similarly, the source electrode pad SE of the semiconductor chip 10 and the lead 30S are electrically connected via a wire (conductive component, metal wire) 12 (specifically, wire 12S). The wire 12 is a conductive component used to connect the electrode pads on the surface 10t side of the semiconductor chip 10 to the lead 30, and is primarily composed of, for example, aluminum (Al). Furthermore, the material of the wire 12 can have various variations, for example, it can be primarily composed of metals such as copper (Cu), silver (Ag), or gold (Au).

[0148] like Figure 11 As shown, one end of the wire 12G is bonded to the gate electrode pad GE of the semiconductor chip 10. On the other hand, the other end of the wire 12G, which is opposite to the aforementioned end, is bonded to the upper surface 30t of the wire connection portion (lead post, pad, bonding pad, wire connection portion, connection portion) 30W, which is formed as part of the lead 30G.

[0149] In addition, such as Figure 14 and Figure 11 As shown, one end of the wire 12S is bonded to the source electrode pad SE of the semiconductor chip 10. On the other hand, the other end of the wire 12S, which is opposite to the aforementioned end, is bonded to the upper surface 30t of the wire connection portion (lead post, pad, bonding pad, wire connection portion, connection portion) 30W, which is formed as part of the lead 30S.

[0150] Furthermore, in power semiconductor devices, the wiring path connected to the source electrode pad SE carries a larger current than the wiring path connected to the gate electrode pad GE. Therefore, in Figure 11 In the example shown, wire 12S is thicker than wire 12G. Furthermore, the shape and number of wires 12 are not limited to... Figure 14 The method shown has various variations. For example, the wires 12G and 12S can be of the same thickness. Alternatively, the source electrode pad SE and the lead 30S can be electrically connected using multiple wires 12S. Specifically, as described later, in this embodiment, multiple wires 12S are connected to the source electrode pad SE of the semiconductor chip 10. Therefore, by connecting multiple thicker wires 12S to the source electrode pad SE, the electrical resistance to... Figure 11 The impedance of the conductive path connected to the source S is shown.

[0151] Furthermore, the semiconductor chip 10, multiple leads 30, and multiple wires 12 are encapsulated by an encapsulating solid 40. The encapsulating solid 40 is a resin body used to encapsulate the semiconductor chip 10 and the multiple wires 12. Specifically, the encapsulating solid 40 is as described later... Figure 14The resin body encapsulating the semiconductor chip 10 and multiple wires 12 is shown in a manner where the exposed surfaces of the source electrode pads SE, i.e., the bonding surfaces SEt1 and SEt2, are in contact. The encapsulating solid 40 has an upper surface 40t (refer to...). Figure 11 , Figure 14 ) and the lower surface (mounting surface) 40b located on the opposite side of the upper surface 40t (refer to) Figure 11 , Figure 14 Additionally, such as Figure 11 and Figure 11 As shown, the upper surface 40t of the sealing solid 40 (refer to) Figure 14 ) and lower surface 40b (refer to) Figure 5 Each of the solids has multiple side surfaces 40s at its periphery. Furthermore, the sealing solid 40 contains an organic insulating material as its main material. For example, it mainly contains a thermosetting resin such as an epoxy resin. In this embodiment, to improve the properties of the sealing solid 40 (e.g., its thermal expansion characteristics), filler particles such as silica (silicon dioxide; SiO2) particles are mixed into the resin material.

[0152] <Details on the connection between the conductor and the electrode pad>

[0153] Here, we will explain in detail the connection between the electrode pads and the wires of the semiconductor chip. Figure 11 It is Figure 6 An enlarged top view showing a portion of the multiple wires connected to the semiconductor chip. Additionally, Figure 7 It is along Figure 7 An enlarged sectional view of line AA. Additionally... Figure 1 to Figure 11 yes Figure 15 An enlarged top view of the opening for the source electrode pads shown. Figure 15 It is shown in Figure 1 to Figure 11 An enlarged top view showing the active electrode wire bonded to the bonding surface. Additionally, Figure 1 to Figure 14 It is along Figure 15 An enlarged sectional view of line AA. Additionally... Figure 16 It is aimed at Figure 16 An enlarged top view of the mating surface of the research example. Additionally, Figure 15 It is Figure 6 The enlarged top view shows the periphery of the loop when the wire connection position is off-center. Figure 16 In the diagram, two transistors Q1 out of the plurality of transistors Q1 in the semiconductor chip 10 are shown as representative examples. Furthermore, [the diagram shows...] Figure 16 The multiple contact surfaces exposed on a portion of the source electrode SE, and the multiple wires 12 connected to these contact surfaces, all have the same structure. Therefore, in Figure 6 and Figure 1 In the example, it is used as a representative example. Figure 6The mating surface SEt1 and the wire 12S1 connected thereto will be described, while the construction of other mating surfaces (and wires) will be omitted.

[0154] like Figure 9 As shown, an insulating film 13 having a surface 10t is formed on the semiconductor chip 10. The insulating film 13 is a protective film for protecting the surface 10t side of the semiconductor chip 10. The upper surface of the insulating film (protective film) 13 constitutes most of the surface 10t of the semiconductor chip 10. In this embodiment, the insulating film 13 is an organic film made of an organic material (organic insulating material), such as a polyimide film. When the insulating film 13 is an organic film, the insulating film 13 and the sealing solid 40 (refer to) which is mainly composed of an organic insulating material are bonded together. Figure 16 The bonding strength between the insulating film 13 and the encapsulating solid 40 is particularly high. However, there are various variations of the material constituting the insulating film 13. For example, it can be an organic film other than a polyimide film. Alternatively, it can be an inorganic insulating film such as silicon dioxide (SiO2) or silicon nitride (SiN). Considering the bonding strength with the encapsulating solid 40, an organic film is more preferred than an inorganic insulating film. However, compared with the bonding strength between a metal material and the encapsulating solid 40, the bonding strength between an inorganic insulating film and the encapsulating solid 40 is higher.

[0155] In addition, multiple openings are formed on the insulating film 13. Figure 2 In the example shown, openings 13H1, 13H2, and 13H3 are formed on the insulating film 13. A portion of the conductor pattern formed on the lower layer of the insulating film 13 is exposed at each of the openings 13H1, 13H2, and 13H3. Specifically, as... Figure 2 As shown, at opening 13H1, the bonding surface (exposed surface, bonding portion) SEt1, which is part of the source electrode pad SE, is exposed from the insulating film 13. Additionally, at opening 13H2, the bonding surface (exposed surface, bonding portion) SEt2, which is another part of the source electrode pad SE, is exposed from the insulating film 13. Furthermore, at opening 13H3, the bonding surface GEt, which is part of the gate electrode pad GE, is exposed from the insulating film 13. Bonding surfaces SEt1, SEt2, and GEt are exposed from the insulating film 13, thus forming part of the surface 10t of the semiconductor chip 10.

[0156] In addition, such as Figure 8 As shown, wires 12 are connected to the junction surfaces SEt1, SEt2, and GGet, respectively. Specifically, a wire (source wire) 12S1 is connected to the junction surface SEt1, and a wire (source wire) 12S2 is connected to the junction surface SEt2. Additionally, a wire (gate wire) 12G is connected to the junction surface GGet. Figure 8Among the multiple conductors 12 shown, conductor 12S1 is in multiple locations (in Figure 8 The conductor 12S1 (divided into two parts) is joined to the joint surface SEt1. In this case, the total joint area of ​​the conductor 12S1 and the joint surface SEt1 increases, thus reducing the impedance of the supply path of the potential supplied through the conductor 12S1.

[0157] Specifically, such as Figure 16 As shown, the mating surface SEt1 has a region (marching region) SER1, a region (marching region) SER2, and a region (intermediate region, non-marching region) SER3 located between region SER1 and region SER2 when viewed from above. Additionally, as... Figure 6 As shown, the conductor 12S1 has a joint portion (connecting portion, pin-type joint portion) 12B1 that engages with the region SER1 of the joint surface SEt1, a joint portion (connecting portion, pin-type joint portion) 12B2 that engages with the region SER2 of the joint surface SEt1, and a loop portion (intermediate portion) 12L1 located between the joint portion 12B1 and the joint portion 12B2 when viewed from above.

[0158] Both junction 12B1 and junction 12B2 are portions of the conductor 12 that are thermo-pressed onto the electrode pads of the semiconductor chip 10. The lower surfaces of each junction 12B1 and junction 12B2 are bonded to the same (common) bonding surface SEt1. Additionally, the ring portion 12L1 connects junction 12B1 and junction 12B2 and is separate from the bonding surface SEt1 (see reference). Figure 6 Additionally, conductor 12S1 has the same characteristics as... Figure 16 The part where the wire joint 30W of the lead wire 30S is joined is the joint (connection part, pin-type joint) 12B3. Additionally, the lead wire 12S1 has a loop portion 12L2, which is located at... Figure 7 The joint 12B2 and joint 12B3 shown (refer to) Figure 16 Between ), used to connect joint 12B2 and joint 12B3.

[0159] Figure 16 The four exposed bonding surfaces of the source electrode pad SE shown are all connected to... Figure 15 and Figure 17 The bonding surface SEt1 shown has the same structure. Furthermore, the four conductors 12, which are bonded to the four bonding surfaces that expose the source electrode pad SE, are all... Figure 17 The conductor 12S1 shown has the same construction.

[0160] in addition, Figure 15The conductor 12G, which is connected to the gate electrode pad GE among the multiple conductors 12 shown, has a different structure than conductors 12S1 and 12S2. That is, conductor 12G is joined to a bonding surface GEt at one location. Specifically, conductor 12G has a bonding portion (connection portion, pin-type bonding portion) 12B2 that engages with the bonding surface GEt, and a lead 30G (see reference 12S1). Figure 17 ) wire joint 30W (refer to) Figure 5 ) Joint (connecting part, pin joint) 12B3 (refer to) Figure 17 ), and a ring portion 12L2 located between junction 12B2 and junction 12B3. However, wire 12G does not have a portion equivalent to junction 12B1 and ring portion 12L1 in wire 12S1. Used to control transistor Q1 (refer to Figure 3 The switching signal (gate signal) is transmitted to the wire 12G. Compared to the transmission path via the wire 12S1, the transmission path via the wire 12G has a relatively smaller impact on the performance of the switching circuit, even if the impedance in the transmission path is increased. Therefore, the wire 12G is bonded to a junction surface GEt at one location. By simplifying the construction of the connection between the wire 12G and the semiconductor chip 10, the manufacturing process can be simplified.

[0161] like Figure 15 As shown, in this embodiment, the bonding surfaces SEt1 and SEt2 are each part of a source electrode pad SE covered by the insulating film 13. In other words, bonding surface SEt1 is the first part of the source electrode pad SE, and bonding surface SEt2 is the second part of the source electrode pad SE. When multiple wires 12 are connected to a source electrode pad SE, the following method can be considered: for example, increasing the opening area of ​​the opening 13H1, and bonding wires 12S1 and 12S2 on the bonding surface SEt1 exposed at the opening 13H1. In this case, the margin (allowable range) for positional deviation when the wires 12 are bonded to the bonding surface SEt1 can be increased.

[0162] However, according to the research of the inventors of this application, due to the fact that the sealing solid 40 (refer to) is mainly composed of organic materials, Figure 17The bonding strength between the encapsulant 40 and the source electrode pad SE, which is mainly composed of a metallic material (e.g., aluminum), is low, making it prone to peeling at the bonding interface between the encapsulant 40 and the source electrode pad SE. Furthermore, due to the large difference in the coefficients of linear expansion between the source electrode pad SE and the encapsulant 40, peeling is easily caused by temperature changes applied to the package after the encapsulant 40 is formed. As described above, filler particles such as silicon particles are mixed into the resin material in the encapsulant 40. Therefore, a coefficient of linear expansion similar to that of silicon (Si), which serves as the semiconductor substrate, can be obtained. However, in this case, due to the large difference in the coefficient of linear expansion between the encapsulant 40 and the source electrode pad SE, which is made of a metallic material, peeling is also prone to occur.

[0163] Even if the source electrode pad SE is stripped from the encapsulating solid 40, the semiconductor device PKG1 will not be immediately damaged (see reference). Figure 6 However, considering the product quality over a long period of time, such as the product lifespan of the semiconductor device PKG1, it is preferable to be able to suppress the peeling between the source electrode pad SE and the encapsulating solid 40.

[0164] As described above, the interface between the insulating film 13 and the sealing solid 40 is less prone to peeling compared to the interface between the source electrode pad SE (which is a metal film) and the sealing solid 40. For example, when the insulating film 13 is made of polyimide, an organic material, the adhesion to the sealing solid 40 can be improved, thus increasing the bonding strength. Furthermore, as a variation, even when the insulating film 13 is made of inorganic insulating materials such as silicon dioxide or silicon nitride, the adhesion to the sealing solid 40 is improved compared to a metal film. Additionally, when the insulating film 13 is made of inorganic insulating films such as silicon dioxide or silicon nitride, the difference in the coefficient of linear expansion between it and the sealing solid 40 can be reduced, thus reducing the likelihood of peeling.

[0165] As described above, from the perspective of suppressing the peeling between the source electrode pad SE and the encapsulating solid 40, it is preferable to reduce the area of ​​the portion of the source electrode pad SE exposed from the insulating film 13.

[0166] Furthermore, according to the research of the inventors of this application, in such cases... Figure 6 When multiple conductors 12 are arranged at a high density as shown, stripping can easily occur between adjacent conductors 12. In this embodiment, from the perspective of improving the electrical characteristics of the transmission path electrically connected to the source electrode pad SE, multiple conductors 12S with a wire diameter thicker than conductor 12G are connected to the source electrode pad SE at a high density. By connecting multiple conductors 12S with a larger wire diameter, the cross-sectional area of ​​the transmission path electrically connected to the source electrode pad SE can be increased, thereby reducing the impedance component.

[0167] In example Figure 15The example shown illustrates four wires 12S connected according to their relationship to the area of ​​the surface 10t of the semiconductor chip 10. However, the number of wires 12S is not limited to four; it can be less than four or more. Furthermore, in Figure 5 In the example shown, the wire diameters of conductors 12S1 and 12S2 are 500 μm. Furthermore, the center-to-center distance between adjacent conductors 12S1 and 12S2 in the X direction is 850 μm. Additionally, the width (length of conductor 12 in the X direction) WW2 of conductors 12S1 and 12S2 at the loop 12L1 is equal to the wire diameter of conductors 12S1 and 12S2, both being 500 μm. The width (length of conductor 12 in the X direction) WW1 of conductors 12S1 and 12S2 at the joints 12B1 and 12B2 (refer to...) Figure 6 The diameters of the wires 12S1 and 12S2 are approximately 600 μm each. Therefore, the separation distance between adjacent wires 12S1 and 12S2 is approximately 150 μm (the distance WS1 between adjacent joints 12B1) to 350 μm (the distance WS2 between adjacent loops 12L1). In other words, the separation distance between wires 12S1 and 12S2 is smaller than the diameter of wire 12S1.

[0168] Figure 6 The encapsulating solid 40 shown is formed by supplying softened resin material and encapsulating the semiconductor chip 10, wires 12, and a portion (internal 30M) of the lead 30, followed by curing of the resin material. At this time, in... Figure 15 When the multiple wires 12 are arranged with a small spacing, the force applied between adjacent wires 12 during the supply of raw resin to the encapsulating solid 40 is smaller than the force applied to other parts (e.g., portions of the surface 10t of the semiconductor chip 10 not covered by the wires 12). Therefore, in the region between adjacent wires 12, the adhesion strength between the encapsulating solid 40 and the semiconductor chip 10 is weaker compared to other regions. Consequently, the region between adjacent wires 12 is particularly prone to peeling compared to other regions.

[0169] According to the inventors' research, when the length (width) of the source electrode pad SE exposed from the insulating film 13 between adjacent conductors 12 is 150 μm or more in the X direction, the sealing solid 40 (refer to...) Figure 5 Peeling between the source electrode pad 12 and the bonding surface SEt1 is particularly prone to occur. Therefore, the inventors of this application have conducted technical research to reduce the exposed area of ​​the bonding surface between adjacent conductors 12. Furthermore, "the length (width) of the portion of the source electrode pad SE exposed from the insulating film 13 between adjacent conductors 12 in the X direction" refers to the portion located at... Figure 5 The length in the X direction of the portion of the region between adjacent conductors 12S that is not covered by the insulating film 13. For example, inFigure 7 The length WR1 at the opening 13H1 shown, from the junction 12B1 of the conductor 12S1 to the portion HSP1 of the edge HS1 of the opening 13H1, is equivalent to "the length (width) of the portion of the source electrode pad SE exposed from the insulating film 13 between adjacent conductors 12 in the X direction". Additionally, at the opening 13H2 (see reference...) Figure 7 From point 12S2 (reference) Figure 7 The length WR2 from the joint 12B1 to the edge HS2 of the opening 13H2 up to a portion HSP21 is equivalent to the length (width) of the portion of the source electrode pad SE exposed from the insulating film 13 between adjacent conductors 12 in the X direction.

[0170] First, such as Figure 7 As a case study, the case where the width in the X direction is set to be relatively small in a mating surface SEtH with a rectangular opening shape was investigated. Figure 16 and Figure 5 In this configuration, the dimensions of the conductors 12S1 are identical. Specifically, the width (length) WW2 of the conductor 12S1 in the X direction at the ring portion 12L1 is 500 μm. Furthermore, the width (length) WW1 of the conductor 12S1 in the X direction at the joint portions 12B1 and 12B2 is approximately 600 μm each. Additionally, the width WH1 of the joint surface SEtH in the X direction (in other words, the opening width of the opening 13H1) is 700 μm.

[0171] When viewed from above, Figure 10 The peripheral portion of the mating surface SEtH shown has an edge (partial) HS1 located at one end of the opening 13H1 in the X direction, and an edge (partial) HS2 located at the opposite end of edge HS1. Figure 5 As shown in the example, when the joint 12B1 is joined to the center of the joint surface SEtH in the X direction, the width WR1 (the length of the exposed surface of the joint surface SEtH in the X direction) between edge HS1 and joint 12B1 and the width WR2 (the length of the exposed surface of the joint surface SEtH in the X direction) between edge HS2 and joint 12B1 are both 50 μm. Although repeated descriptions are omitted, Figure 10 In the middle, the relationship between the joint 12B2 and the edges HS1 and HS2 is the same as described above. Additionally, in... Figure 11 In the example shown, the width between edge HS1 and ring 12L1 (the length of the exposed surface of the joint surface SEtH in the X direction) WR3 and the width between edge HS2 and ring 12L1 (the length of the exposed surface of the joint surface SEtH in the X direction) WR4 are both 100 μm.

[0172] like Figure 10 As shown, as long as the wire 12S1 can be joined at the center of the joint surface SEtH in the X direction, the width of the portion of the joint surface SEtH exposed from the insulating film 13 and the wire 12S1 in the X direction is less than 150 μm. Therefore, the aforementioned sealing solid 40 (refer to...) is less likely to occur. Figure 10 The separation between the conductor 12S1 and the bonding surface SEtH is addressed. However, when bonding the conductor 12S1 to the bonding surface SEtH, positional deviation can occur. Therefore, a positional deviation margin (allowable range) of approximately 50 μm is required for a stable bonding of the conductor 12S1.

[0173] exist Figure 11 In the example shown, when the connection position of conductor 12S1 is offset by 50 μm towards either side HS1 or side HS2, one of the widths WR3 and WR4 is 150 μm. It is known that in this case, the sealing solid 40 (refer to...) between adjacent conductors 12... Figure 11 The peeling between the joint 12B1 and the bonding surface SEtH becomes significant. On the other hand, when the width WH1 of the bonding surface SEtH is set to less than 700 μm in order to reduce the widths WR3 and WR4, the margin for wire bonding is small. As a result, depending on the degree of positional deviation during wire bonding, a portion of the joint 12B1 or the joint 12B2 may come into contact with the insulating film 13 (see reference 12B2). Figure 11 Overlap. When a portion of the conductor 12S1 overlaps with the insulating film 13, it can cause a decrease in the electrical characteristics of the transmission path.

[0174] In this embodiment, such as Figure 11 As shown, the planar shape of the mating surface SEt1, or in other words, the opening shape of the opening 13H1, is not quadrilateral. When viewed from above, the mating surface SEt1 has a neck (region SER3) between region SER1 and region SER2.

[0175] Figure 10 The shape of the mating surface SEt1 (in other words, the opening 13H1) shown can be represented as follows. When viewed from above, the width WH1 of region SER1 in the X direction and the width WH2 of region SER2 in the X direction are larger than the width WH3 of region SER3 in the X direction. Furthermore, when viewed from above, the mating surface SEt1 (opening 13H1) has an edge (partial) HS1 located at one end of the opening 13H1 in the X direction, and an edge (partial) HS2 located at the opposite end of edge HS1. Additionally, the mating surface SEt1 (opening 13H1) intersects the X direction (in... Figure 11In the Y direction (orthogonal to the center), there is a side (part) HS3 located at one end of the opening 13H1, and a side (part) HS4 located at the opposite end of side HS3. Sides HS3 and HS4 extend along the X direction. In addition, sides HS1 and HS2 extend along the Y direction, but are not straight, but curved between regions SER1 and SER3 and between regions SER2 and SER3. In other words, the mating surface SEt1 has necks on the side of side HS1 and side of side HS2.

[0176] exist Figure 10 In the example shown, the width WH1 of region SER1 and the width WH2 of region SER2 in the X direction are both 700 μm. On the other hand, the width WH3 of region SER3 is 500 μm.

[0177] in addition, Figure 10 The shape of the mating surface SEt1 (opening 13H1) shown can be represented as follows. When viewed from above, the edge HS1 of the mating surface SEt1 (opening 13H1) has a portion HSP1 extending along the Y direction, a portion HSP2 extending along the Y direction, and a portion HSP3 located between portions HSP1 and HSP2 and extending along the Y direction. Additionally, as... Figure 11 As shown, in a top view, the joint 12B1 is located in the X direction between the portion HSP1 of side HS1 and side HS2. In a top view, the joint 12B2 is located in the X direction between the portion HSP2 of side HS1 and side HS2. Furthermore, as... Figure 5 As shown, when viewed from above, the ring portion 12L1 is located in the X direction between the portion HSP3 of side HS1 and side HS2. Furthermore, when viewed from above, the length (width WH1) in the X direction from the portion HSP1 of side HS1 to side HS2, and the length (width WH2) in the X direction from the portion HSP2 of side HS1 to side HS2, are both greater than the length (width WH3) in the X direction from the portion HSP3 to side HS2.

[0178] In addition, Figure 5 In the example shown, when viewed from above, portions of HSP1 and HSP2 of edge HS1 lie on the same extension line VL1. In other words, portion of HSP2 of edge HS1 lies on the extension line VL1 of portion of HSP1. Additionally, portion of HSP3 of edge HS1 lies between the extension line VL1 of portion of HSP1 and edge HS2. Furthermore, when viewed from above, portions of HSP21 and HSP22 of edge HS2 lie on the same extension line VL2. In other words, portion of HSP22 of edge HS2 lies on the extension line VL2 of portion of HSP21. Additionally, portion of HSP23 of edge HS2 lies between the extension line VL2 of portion of HSP21 and edge HS1.

[0179] like Figure 11 As shown, when the joint 12B1 is joined to the center of the joint surface SEt1 in the X direction, the width between the edge HS1 and the joint 12B1 (the length of the exposed surface of the joint surface SEt1 in the X direction) WR1 and the width between the edge HS1 and the joint 12B1 (the length of the exposed surface of the joint surface SEt1 in the X direction) WR2 are both 50 μm. Although repeated descriptions are omitted, Figure 7 The relationship between the central joint 12B2 and the edges HS1 and HS2 is the same as described above. Additionally, in Figure 7 In the example shown, the width between edge HS1 and ring 12L1 (the length of the exposed surface of the mating surface SEt1 in the X direction) and the width between edge HS2 and ring 12L1 (the length of the exposed surface of the mating surface SEt1 in the X direction) are both 0 μm.

[0180] Therefore, assuming in Figure 9 In the example shown, when the connection position of wire 12S1 is offset by 50 μm towards side HS1, the width in the X direction between side HS2 and ring 12L1 (the length of the exposed surface of the joint surface SEt1 in the X direction) is 50 μm. Furthermore, when the connection position of wire 12S1 is offset by 50 μm towards side HS2, the width in the X direction between side HS1 and ring 12L1 (the length of the exposed surface of the joint surface SEt1 in the X direction) is 50 μm. In other words, when the positional accuracy margin of the wire connection in the X direction is set to 50 μm, the length of the exposed surface of the joint surface SEt1 in the X direction is less than 50 μm, thus suppressing the sealing solid 40 (refer to...). Figure 10 Peeling between the wires and the bonding surface SEt1. Furthermore, by setting a 50 μm margin for the positional accuracy of the wire bonding in the X direction, it is possible to suppress the bonding portions 12B1 and 12B2 of the wires 12S1 from separating from the insulating film 13 (see reference 12S1). Figure 5 (overlapping cases)

[0181] In addition, Figure 5 In the example shown, the mating surface SEt1 (opening 13H1) has a region SER4 between region SER3 and region SER1. Additionally, the mating surface SEt1 (opening 13H1) has a region SER5 between region SER3 and region SER2. In regions SER4 and SER5, the widths (lengths) WH4 and WH5 in the X direction are not constant. In region SER4, the value of the width WH4 is smaller closer to region SER3 and larger closer to region SER1. Similarly, in region SER5, the value of the width WH4 is smaller closer to region SER3 and larger closer to region SER2.

[0182] In addition, Figure 5 In the example shown, edge HS1 has a portion HSP5 located between portions HSP3 and HSP1, extending in a direction intersecting the Y and X directions (the third direction) when viewed from above. Additionally, edge HS1 has a portion HSP4 located between portions HSP3 and HSP2, extending in a direction intersecting the Y and X directions (the fourth direction) when viewed from above. Furthermore, when viewed from above, edge HS2 of the mating surface SEt1 (opening 13H1) has portions HSP21 extending in the Y direction, portions HSP22 extending in the Y direction, and a portion HSP23 located between portions HSP21 and HSP22 and extending in the Y direction. Additionally, edge HS2 has a portion HSP24 located between portions HSP23 and HSP21, extending in a direction intersecting the Y and X directions (the fifth direction) when viewed from above. Additionally, edge HS2 has a portion HSP25 located between portions HSP23 and HSP22 and extending along a direction (the sixth direction) that intersects the Y and X directions.

[0183] However, as a variation, there are also cases where regions SER4 and SER5 are absent. In this case, Figure 5 The portions HSP4 and HSP5 of edge HS1 and the portions HSP24 and HSP25 of edge HS2 shown extend along the X direction, respectively.

[0184] In addition, Figure 5 In the example shown, the width WH3 of region SER3 in the X direction is 500 μm. As mentioned above, in Figure 10 Between adjacent conductors 12 shown, when the length (width) of the portion of the source electrode pad SE exposed from the insulating film 13 in the X direction is 150 μm or more, the sealing solid 40 (refer to) Figure 5 The bonding surface SEt1 is particularly prone to peeling. Therefore, with a positional accuracy margin of 50 μm in the X direction for the wire bonding, if the width WH3 is less than 700 μm, the exposed portion of the bonding surface SEt1 in the X direction will be less than 150 μm even considering positional deviation.

[0185] However, from the perspective of reliable suppression Figure 17 Regarding the angle at which the SER3 region is stripped, a smaller value for the width WH3 is preferable. For example, as... Figure 15 As shown, consider the case where the connection position of wire 12S1 is close to the side HS2 of the opening 13H1. Figure 5In the example shown, the bonding position of wire 12S1 is offset by approximately 40 μm towards edge HS2 in the X direction. In this case, the portion of the bonding surface SEt1 that should take into account the aforementioned peeling effect is the portion of the bonding surface SEt1 sandwiched between edge HS1 and wire 12S1 at opening 13H1. The portion HSP1 of edge HS1 and the bonding portion 12B1 of wire 12S1 (refer to...) Figure 19 The width WR1 between them is approximately 90 μm. Additionally, in Figure 18 In the example shown, the width (length) WC1 between the extension line VL1 of part HSP1 and part HSP3 is 100 μm. Therefore, the width (length) WR3 between part HSP3 of edge HS1 and the loop 12L1 of conductor 12S1 is approximately 40 μm. In this case, with Figure 18 Compared to region SER2, region SER3 is less prone to the aforementioned stripping.

[0186] As described above, from the perspective of suppressing the probability of peeling in the SER3 region, it is preferable that the width WC1 between the extension line VL1 of part HSP1 and part HSP3 is larger than the width WR3 between part HSP3 of side HS1 and the loop portion 12L1 of conductor 12S1. Similarly, from the perspective of suppressing the probability of peeling in the SER3 region, it is preferable that the width WC2 between the extension line VL2 of part HSP21 of side HS2 and part HSP23 is larger than the width WR4 between part HSP23 of side HS2 and the loop portion 12L1 of conductor 12S1.

[0187] In addition, Figure 15 In the example shown, when viewed from above, one side of the ring 12L1 overlaps with the position of part HSP3 of the opening 13H1, therefore... Figure 19 The width WR3 shown is 0 μm.

[0188] In addition, as mentioned above, Figure 18 The peeling between the sealing solid 40 and the mating surface SEt1 shown is prone to occur between adjacent wires 12. Therefore, even if the exposed area of ​​the mating surface SEt1 is... Figure 20 Even when the distance between the wire 12S1 and the edge HS3 of the opening 13H1 is large, the aforementioned peeling is less likely to occur. Therefore, in Figure 19In the example shown, the width WR5 in the Y direction between edge HS3 and joint 12B1 (the length of the exposed surface of joint surface SEtH in the Y direction) is greater than the width WR1 in the X direction between edge HS1 and joint 12B1 (the length of the exposed surface of joint surface SEtH in the X direction). Width WR5 is also greater than the width WR2 in the X direction between edge HS2 and joint 12B1 (the length of the exposed surface of joint surface SEtH in the X direction). Furthermore, in Figure 19 In the example shown, the width WR1 in the X direction between edge HS1 and joint 12B1 is 50 μm. Additionally, in Figure 19 In the example shown, the width WR1 is approximately 90 μm. In contrast, Figure 19 The width WR5 shown is approximately 150μm to 200μm. For example... Figure 18 As shown, in the part where peeling is not likely to occur, by increasing the value of the width WR5, a larger margin can be made for the positional deviation during wire bonding, thus relaxing the manufacturing conditions in the wire bonding process.

[0189] In addition, from the perspective of reducing the exposed area of ​​the source electrode pad SE, other considerations were also taken into account. Figure 20 The construction of the research example shown. Figure 20 It shows that it is aimed at Figure 10 An enlarged sectional view of the research example. Figure 7 In the illustrated example, a wire 12S is bonded to the bonding surfaces SEt3 and SEt4, which are separated by the insulating film 13. This is consistent with... Figure 7 The implementation methods shown are different. In other words, in Figure 18 In the example shown, on the surface 10t of the semiconductor chip 10, the conductive line 12S is bonded to the source electrode pad SE at two locations, and the bonding surfaces SEt3 and SEt4 bonded to the conductive line 12S are separate from each other. On the other hand, in Figure 15 In the example shown, the joints 12B1 and 12B2 of the conductor 12S1 are joined to a joint surface SEt1 that is not separated by the insulating film 13. In other words, in Figure 18 In the example shown, the loop 12L1 of the conductor 12S crosses the insulating film 13 above the source electrode pad SE. On the other hand, in Figure 6 In the example shown, the loop 12L1 of the conductor 12S1 does not cross the insulating film 13 above the source electrode pad SE. Figure 6 In the example shown, since the bonding surfaces SEt3 and SEt4 on surface 10t are separated by the insulating film 13, therefore... Figure 18 Compared to the example of this embodiment shown, the exposed area of ​​the source electrode pad SE can be further reduced.

[0190] However,Figure 18 and Figure 15 It can be seen from the comparison that the following points are preferred. Figure 18 The example shown. That is, in Figure 18 In the example shown, the loop portion 12L1 of the conductor 12S must be in a shape that does not contact the insulating film 13. Therefore, if the distance from the furthest point of the loop portion 12L1 to the exposed surface of the source electrode pad SE is set as the loop height HT1, it is possible to make Figure 18 The ring height HT1 in the example shown is... Figure 6 In the example shown, the ring height HT1 is small. Furthermore, if the length of the ring portion 12L1 in the Y direction (in other words, the separation distance between the joint portion 12B1 and the joint portion 12B2) is defined as the ring length LE1, then it is possible to make... Figure 6 The loop length LE1 in the example shown is... Figure 15 The example shown has a short loop length LE1. This can be achieved by making... Figure 3 In the example shown, the ring height HT1 is relatively low. Furthermore, if the ring length LE1 can be shortened, the length LE2 of the source electrode pad SE in the Y direction can be shortened (including the portion covered by the insulating film 13).

[0191] Therefore, according to Figure 3 The example shown is similar to... Figure 18 The example shown can reduce the size of the source electrode pad SE, thus reducing the planar area (area of ​​surface 10t) of the semiconductor chip 10. Reducing the planar area of ​​the semiconductor chip 10 offers several advantages. For example, it allows for a reduction in the size of the semiconductor device PKG1 mounted on the semiconductor chip 10 (see reference). Figure 6 The planar area of ​​a semiconductor wafer. Furthermore, for example, in the manufacture of semiconductor chips, the manufacturing efficiency of semiconductor chips is improved because the number of semiconductor chips obtained from a single semiconductor wafer (obtaining rate) can be increased.

[0192] Furthermore, it is preferable to shorten the length LE2 of the source electrode pad SE in the Y direction, as the stress caused by the difference in the coefficients of linear expansion between the source electrode pad SE and the encapsulating solid 40 increases proportionally to the length of the source electrode pad SE. Therefore, as... Figure 18 As shown, according to this embodiment, since the length LE2 of the source electrode pad SE in the Y direction can be shortened, the stress caused by the difference in the coefficients of linear expansion between the source electrode pad SE and the encapsulating solid 40 can be reduced. As a result, peeling between the source electrode pad SE and the encapsulating solid 40 caused by this stress can be suppressed.

[0193] in addition, Figure 18 The sealing solid 40 shown is with Figure 6The exposed surface of the gate electrode pad GE, i.e., the bonding surface GEt, is formed in contact with the gate electrode pad GE. Therefore, from the perspective of suppressing peeling between the bonding surface GEt and the encapsulating solid 40, it is preferable to reduce the area of ​​the region in the bonding surface GEt that does not overlap with the conductor 12G. However, in this embodiment, the wire diameter of the conductor 12G is smaller than that of the conductors 12S1 and 12S2, for example, about 125 to 150 μm. In addition, the conductor 12G is bonded at one location on the gate electrode pad GE, but not at other locations. Therefore, the area of ​​the bonding surface GEt of the gate electrode pad GE is smaller than the area of ​​the bonding surfaces SEt1 and SEt2 of the source electrode pad SE. For example, in Figure 3 In the example shown, the area of ​​the bonding surface GEt of the gate electrode pad GE is less than 1 / 4 of the area of ​​each of the bonding surfaces SEt1 and SEt2 of the source electrode pad SE. In other words, the area of ​​each of the bonding surfaces SEt1 and SEt2 is more than 4 times the area of ​​the bonding surface GEt. Thus, the area of ​​the bonding surface GEt is sufficiently small compared to the bonding surfaces SEt1 and SEt2 of the source electrode pad SE, and therefore, the bonding surface GEt is less likely to peel off from the encapsulant 40 compared to the bonding surfaces SEt1 and SEt2. Therefore, in the surface 10t of the semiconductor chip 10, regarding the location where countermeasures are taken against peeling from the encapsulant 40, the bonding surfaces SEt1 and SEt2 of the source electrode pad SE have a higher priority than the bonding surface GEt of the gate electrode pad GE.

[0194] <Semiconductor Device Manufacturing Methods>

[0195] The following is about the use Figure 9 The manufacturing process of the semiconductor device PKG1 will be described. The semiconductor device PKG1 is manufactured according to... Figure 10 The process shown is used for manufacturing. Figure 9 It shows the use Figure 21 This is an explanatory diagram outlining the manufacturing process of a semiconductor device. In the following description, when illustrating the components of the semiconductor device PKG1, references to previously described components may be made as needed. Figure 9 The situation needs to be explained.

[0196] <Semiconductor chip preparation process>

[0197] exist Figure 22 In the semiconductor chip preparation process shown, preparation Figure 23 The semiconductor chip 10 shown. Figure 21 Therefore Figure 21 The diagram shows a top view of the surface (exposed electrode surface) of a semiconductor chip prepared during the semiconductor chip preparation process.

[0198] Semiconductor chips 10 prepared using this process, such as Figure 7As shown, it has a surface 10t and a back surface 10b located on the opposite side of the surface 10t. Additionally, as... Figure 10 As shown, the surface 10t of the semiconductor chip 10 includes the upper surface of the insulating film 13 and the bonding surfaces (exposed surfaces) SEt1, SEt2, SEt3, and SEt4 of the source electrode pads (electrodes) SE exposed from the insulating film 13. The source electrode pads SE have bonding surfaces SEt1 exposed from the insulating film 13 at the opening 13H1 formed in the insulating film 13, and bonding surfaces SEt2 exposed from the insulating film 13 at the opening 13H2 formed in the insulating film 13. Additionally, in Figure 21 In the example shown, the source electrode pad SE has a bonding surface SEt3 exposed from the insulating film 13 at an opening 13H4 formed in the insulating film 13, and a bonding surface SEt4 exposed from the insulating film 13 at an opening 13H5 formed in the insulating film 13. The bonding surfaces SEt1, SEt2, SEt3, and SEt4 are arranged in a manner that extends along the Y direction and is adjacent to each other in the X direction that intersects the Y direction.

[0199] Additionally, a gate electrode pad (electrode) GE is formed on the surface 10t of the semiconductor chip 10. The gate electrode pad GE has a bonding surface GEt exposed from the insulating film 13 at an opening 13H3 formed in the insulating film 13. Furthermore, as... Figure 22 As shown, a junction is formed on the back surface 10b of the semiconductor chip 10, corresponding to the drain D (see reference). Figure 23 The drain electrode (electrode) DE is electrically connected. ​ In the example shown, the entire back side 10b of the semiconductor chip 10 becomes the drain electrode DE.

[0200] The shapes and structures of the mating surfaces SEt1, SEt2, SEt3, and SEt4 have been used. ​ Explanation has already been provided, so repeated explanations will be omitted.

[0201] ​ The semiconductor chip 10 shown is manufactured, for example, in the following manner. A semiconductor substrate WH (refer to) made of n-type single-crystal silicon is prepared. ​ ) main surface WHt (refer to ​ n is formed on ) - Semiconductor wafers with epitaxial layers EP (illustration omitted), such as ​ As shown, multiple transistors Q1 are formed on the epitaxial layer EP. The semiconductor wafer includes multiple chip regions, and multiple transistors Q1 are formed in each of these chip regions. Additionally, source electrode pads SE and gate electrode pads GE are formed on the transistors Q1. The source electrode pad SE is connected to multiple source regions SR, and the gate electrode pad GE is connected to multiple gate electrodes G. ​The example shown illustrates a direct connection between the source region SR and the source electrode pad SE. However, as a variation, a lead-out trace (source trace) can also be placed between the source region and the source electrode pad SE. Additionally, ​ Although not shown in the diagram, the gate electrode pad GE and the gate electrode G are connected via lead-out wiring (gate wiring) not shown. Next, an insulating film 13 is formed to cover the entire source electrode pad SE and the gate electrode pad GE. Then, a... ​ The openings 13H1, 13H2, 13H3, 13H4, and 13H5 shown expose portions of the source electrode pads SE (junction surfaces SEt1, SEt2, SEt3, SEt4) and a portion of the gate electrode pads GE (junction surface GET) from the insulating film 13. Then, after necessary tests (wafer testing) such as electrical tests for the circuit, the wafer is diced into multiple semiconductor chips 10. Furthermore, as... ​ When a metal film is to be formed on the back side 10b for the drain electrode DE shown, the metal film used as the drain electrode DE can be formed at any time between the semiconductor wafer preparation process and the semiconductor wafer dicing process. For example, after the openings 13H1, 13H2, 13H3, 13H4, and 13H5 are formed, and the back side of the semiconductor wafer is to be ground before wafer testing to reduce the thickness of the semiconductor chip 10, after grinding the back side, a metal film is formed on the back side 10b (refer to...). ​ A metal film is formed to serve as the drain electrode DE. This step can be omitted if a metal film is not used as the drain electrode DE.

[0202] Furthermore, in the semiconductor chip preparation process, wafer testing is performed before dicing the semiconductor wafer to obtain multiple semiconductor chips 10. This wafer testing includes an electrical test to verify the electrical characteristics of the circuitry formed on the semiconductor chip 10. In this electrical test, for example, a test terminal (probe) (not shown) is brought into contact with the source electrode pad SE. If the test terminal then penetrates the source electrode pad SE, a trace of the test terminal penetration will remain on the source electrode pad SE. ​ The probe traces (PRM) are shown.

[0203] The mating surfaces SEt1, SEt2, SEt3, and SEt4, as described above, each have regions SER1, SER2, and SER3, respectively. Regions SER1 and SER2 are connected to conductor 12 (see reference). ​ The area where the wire 12 is joined. Considering the connection stability of the wire 12, it is preferable that there are no probing marks (PRM) or other irregularities in the area where the wire 12 is joined. Therefore, as... ​As shown, probe traces (PRM) are formed in region SER3 of a predetermined area that is not connected by wires.

[0204] In addition, ​ In the example shown, mating surfaces SEt1, SEt2, SEt3, and SEt4 are electrically connected to each other, thus representing an example of mating surface SEt4 contacting the test terminal. However, there are also cases where probe marks PRM are formed on all mating surfaces SEt1, SEt2, SEt3, and SEt4. In this case, probe marks PRM are formed on the region SER3 of each of mating surfaces SEt1, SEt2, SEt3, and SEt4.

[0205] <Leader Frame Preparation Process>

[0206] In addition, ​ The lead frame preparation process shown in the diagram is as follows: ​ The lead frame LF is shown. Additionally... ​ It will be with ​ An enlarged top view of a portion of the lead frame prepared during the lead frame preparation process is shown.

[0207] like ​ As shown, the lead frame LF prepared in this process includes a device forming section LFd connected to the frame portion (frame portion) LFf. One device forming section LFd and... ​ The semiconductor device PKG1 shown is equivalent to this. In ​ The diagram illustrates a device forming section LFd, but the lead frame LF has multiple device forming sections LFd connected via a frame portion LFf. In this way, by using a lead frame LF with multiple device forming sections LFd, multiple semiconductor devices PKG1 (see reference) can be manufactured simultaneously. ​ Therefore, it can improve manufacturing efficiency.

[0208] The lead frame LF is, for example, made of a metallic material with copper (Cu) as the main component, with a thickness of, for example, approximately 125 μm to 400 μm. Additionally, multiple device forming sections LFd are connected to the frame section LFf. The frame section LFf is located in... ​ The support section shown is used to support the components formed in the device forming section LFd during the period before the lead separation process.

[0209] In addition, such as ​ As shown, a chip pad 20 and multiple leads 30 are formed in the device forming section LFd. The chip pad 20 is connected to and supported on the frame section LFf via one of the multiple leads 30 (lead 30D). In addition, the chip pad 20 has an upper surface 20t that serves as a chip mounting surface.

[0210] In addition, multiple leads 30 are connected to and supported on the frame portion LFf. The multiple leads 30 are arranged side by side in a manner that extends along the Y direction and is adjacent to each other in the X direction. The multiple leads 30 are interconnected by means of tie rods LFt.

[0211] The plurality of leads 30 includes a plurality of leads 30S serving as source leads. The plurality of leads 30S are arranged adjacent to each other in the X direction and are connected to conductor junctions (lead posts, pads, bonding pads, conductor connections, junctions) 30W. Additionally, the plurality of leads 30 includes a lead 30G serving as a gate lead. A conductor junction 30W is provided at the front end of the lead 30G on the chip pad 20 side. Furthermore, the plurality of leads 30 includes a lead 30D serving as a drain lead. The lead 30D is arranged between the leads 30G and 30S in the X direction, and its front end on the chip pad 20 side in the Y direction is connected to the chip pad 20.

[0212] In this embodiment, the upper surface 20t of the chip pad 20 and the upper surface 30t of the conductor junction 30W of the lead 30 are positioned at different heights. The lead 30D supporting the chip pad 20 and the portion connecting the chip pad 20 to the frame portion LFf are bent, causing the chip pad 20 to offset. In this embodiment, the chip pad 20 is offset downwards relative to other components of the lead frame LF. Therefore, as... ​ As shown, the upper surface 20t of the chip pad 20 is positioned below the upper surface 30t of the lead 30. This is achieved by offsetting the chip pad 20 downwards, as... ​ As shown, the lower surface 20b of the chip pad 20 is exposed from the encapsulating solid 40.

[0213] <Semiconductor chip assembly process>

[0214] Next, in ​ In the semiconductor chip mounting process shown, such as ​ As shown, a semiconductor chip 10 is mounted on the chip pad 20 of the lead frame LF.

[0215] In this process, a semiconductor chip 10 is mounted (bonded) on the upper surface 20t of a chip pad 20 integrally formed with the lead 30D, which serves as the drain terminal, using a chip bonding material 11. Furthermore, the semiconductor chip 10 has a drain electrode DE (see reference). ​ The back of 10b (refer to) ​ The upper surface 20t of the chip pad 20, which serves as the chip mounting surface, is bonded and fixed using a chip bonding material 11. Thus, the drain electrode DE of the semiconductor chip 10 is electrically connected to the chip pad 20 via the chip bonding material 11, which is a conductive connection material.

[0216] In this process, after applying chip bonding material 11 to the upper surface 20t of chip pad 20, a semiconductor chip 10 is disposed on the chip bonding material 11. Then, the semiconductor chip 10 and the chip pad 20 are fixed by curing the chip bonding material.

[0217] The chip bonding material 11 can be, for example, a soldering material. Alternatively, the chip bonding material 11 can be a conductive resin adhesive material called silver (Ag) paste, containing a plurality of silver (Ag) particles (Ag filler). When the chip bonding material 11 is a soldering material, a reflow soldering process is performed as a method to cure the chip bonding material. Alternatively, when the chip bonding material 11 is a conductive resin adhesive material, the thermosetting resin component contained in the chip bonding material 11 is heated to cure it.

[0218] <Wire splicing process>

[0219] Next, in ​ In the wire bonding process shown, such as ​ As shown, multiple electrode pads (gate electrode pad GE and source electrode pad SE) of the semiconductor chip 10 are electrically connected to multiple leads 30 via wires (metal wires) 12.

[0220] like ​ As shown, in this process, the gate electrode pad GE of the semiconductor chip 10 is electrically connected to the lead 30G via a wire 12G. Additionally, in this process, the source electrode pad SE of the semiconductor chip 10 is electrically connected to the lead 30S via a wire 12S. Specifically, at the bonding surface GEt (refer to...), which is part of the gate electrode pad GE... ​ The joint portion 12B2 of the upper connecting wire 12G (refer to) ​ On the upper surface (joining surface) 30t of the conductor connection portion 30W of the lead 30G, the joining portion 12B3 of the conductor 12G is joined. Additionally, on the joining surface SEt1 (refer to...), which is part of the source electrode pad SE... ​ ) Connecting wire 12S1 (refer to) ​ The joint portions 12B1 and 12B2 of the lead wire 30S are joined on the upper surface (joint surface) 30t of the lead wire connection portion 30W, and the joint portion 12B3 of the lead wire 12S1 is joined on the upper surface (joint surface) 30t of the lead wire 30S. Similar to the joint surface SEt1, in ​ The wires 12 are respectively joined on the mating surfaces SEt2, SEt3, and SEt4 shown (refer to...). ​ ).

[0221] Various variations of the connection method for wire 12 can be applied, but in this embodiment, a joining tool (not shown) called a wedge tool is used to join the aluminum wire 12. The following is an example of a wire joining process utilizing the wedge joining method, to illustrate the connection process. ​ The wire 12S1 shown connects the source electrode pad SE to... ​ The following explanation uses the method of electrically connecting the lead 30S as an example.

[0222] First, in the wire splicing process, a wedge tool is used to... ​ and ​ The junction 12B1 of the conductor 12S1 shown is connected to the region SER1 of the junction surface SEt1 exposed at the opening 13H1 in the source electrode pad SE (see reference). ​ Joining (first joining step). In the case of the wedge joining method, the wire 12S1 is thermally pressed onto the joining surface SEt1 by clamping the front end face of the wedge tool and applying pressure and heat from the front end face. Alternatively, at this time, applying ultrasonic waves from the front end face facilitates joining of the wire 12S1. The wire 12S1, pressed by the wedge tool, deforms to form a joint 12B1. The joint 12B1 formed by deforming a wire with a circular cross-section in this manner is called a stitch joint.

[0223] Next, in the wire bonding process, the wedge tool is moved in its own... ​ and ​ After the shown bonding surface SEt1 leaves, it moves along the Y direction to form a ring 12L1 (first ring formation process). In this process, the wedge tool rises above the lead frame LF while releasing the wire 12S1, thereby increasing the distance between the wedge tool and the semiconductor chip 10. Then, after moving the wedge tool along the Y direction toward the area where the second bonding is performed, the wedge tool is lowered again. Thus, a ring is formed. ​ The ring portion 12L1 is shown. At this time, if using... ​ As explained, in this embodiment, no insulating film 13 is sandwiched between the loop portion 12L1 of the conductor 12 and the source electrode pad SE. Therefore, the height to which the wedge tool WT rises can be reduced. This allows for a shorter [time period]. ​ The length of the ring shown is LE1.

[0224] Next, in the wire splicing process, a wedge tool is used to... ​ and ​ The junction 12B2 of the conductor 12S1 shown is connected to the region SER2 of the junction surface SEt1 exposed at the opening 13H1 in the source electrode pad SE (see reference). ​) Joining (Second Joining Step). In the second joining step, similar to the first joining step, the wire 12S1 is heat-pressed onto the joining surface SEt1. At this time, ultrasonic waves may also be applied.

[0225] Next, in the wire bonding process, the wedge tool is moved in its own... ​ and ​ After the mating surface SEt1 is removed, it faces the lead wire 30S (refer to...). ​ ) wire joint 30W (refer to) ​ ) moves, thereby forming the ring 12L2 (refer to ​ (Second ring formation process). The ring portion 12L2 extends from the semiconductor chip 10 toward the lead 30. Therefore, after the second ring formation process, as... ​ As shown, when viewed from above, the ring portion 12L2 intersects with one of the multiple sides of the opening portion 13H1. ​ In the example shown, the loop portion 12L2 of the conductor 12S1 and the edge HS4 of the opening portion 13H1 (refer to...) ​ (Intersecting)

[0226] Next, in the wire bonding process, a wedge tool is used to bond wire 12S1 (refer to...) ​ The joint 12B3 (refer to) ​ ) and as a lead 30S (refer to) ​ ) wire joint 30W (refer to) ​ The upper surface of the mating surface of ) 30t (refer to) ​ ) Joining (3rd joining process).

[0227] Next, in the wire splicing process, the wire 12S1 is cut using the wire cutter provided with the wedge tool (wire cutting process).

[0228] Through the above processes, with the help of ​ The wire 12S shown electrically connects the source electrode pad SE of the semiconductor chip 10 to the lead 30S.

[0229] Furthermore, in this embodiment, the margin for positional deviation of the connection position of the wires 12S is relatively small. Therefore, in the wire connection process, it is preferable to confirm the degree of positional deviation of the connection position of the wires 12S after the first wire 12S is connected, and adjust the wire connection position (changing it as needed) based on the confirmation result. The confirmation of positional deviation is at least... ​ This is performed after the junction 12B1 of the wire 12S1 shown is joined. However, it can also be performed after the wire 12S1 is joined with... ​The connection of the lead wires 30S shown is performed after the connection. This improves the positional accuracy of the subsequent lead wires 12S. Additionally, in a lead frame LF (refer to...), ​ When multiple device forming sections LFd are formed on a device, the positional deviation is checked and adjusted on the device forming section LFd where the wire bonding process is performed first. Therefore, it is not necessary to check the positional deviation of device forming sections LFd where the wire bonding process is performed for the second and subsequent times.

[0230] <Sealing Process>

[0231] Next, in ​ In the sealing process shown, ​ The semiconductor chip 10, a portion of the chip pad 20, and a portion of each of the multiple leads 30 shown are shown. ​ The internal 30M shown, and multiple wires 12 are sealed with insulating resin to form ​ The sealing solid shown is 40. ​ It is shown in ​ The image shown is an enlarged top view of the state of the sealing solid formed during the sealing process, which seals the semiconductor chip and wires. Additionally, ​ It is shown along ​ An enlarged sectional view of the AA line showing the lead wire frame positioned within the forming mold. Additionally, ​ This is an enlarged cross-sectional view showing the periphery of a wire that is sealed with resin during the sealing process.

[0232] In this process, for example, ​ As shown, a forming mold 62 comprising an upper mold (first mold) 62T and a lower mold (second mold) 62B is used to form a sealed solid 40 using a so-called transfer molding method.

[0233] exist ​ In the example shown, the lead frame LF is configured such that a portion of the chip pad 20 of the device forming section LFd and a portion of each of the multiple leads 30 are located within the cavity 62C formed by the upper mold 62T and the lower mold 62B. Then, the lead frame LF is clamped (insulated) by the upper mold 62T and the lower mold 62B. In this state, when a raw material containing a softened (plasticized) thermosetting resin (insulating resin) is pressed into the cavity 62C of the forming mold 62, the insulating resin is supplied into the space formed by the cavity 62C and the lower mold 62B, shaping it to mimic the shape of the cavity 62C.

[0234] At this time, as ​As shown, a portion of the front end side, connected to the offset portion in the upper surface 20t of the chip pad 20 and positioned at a relatively high position, is pressed by the upper mold 62T. Additionally, the lower surface 20b of the chip pad 20 is pressed by the lower mold 62B. ​ In the example shown, the lower surface 20b of the offset portion in the chip pad 20 is in close contact with the lower mold 62B. Therefore, as ​ As shown, after this process, a portion of the lower surface 20b of the chip pad 20 is exposed from the encapsulating solid 40.

[0235] In addition, such as ​ As shown, in this process, the sealing solid 40 is formed by contacting the resin constituting the sealing solid 40 with the bonding surface SEt1. In addition, in this process, the resin also penetrates between the loop portion 12L1 of the conductor 12 and the bonding surfaces SEt1 and SEt2, and the sealing solid 40 is sandwiched between the loop portion 12L1 of the conductor 12 and the bonding surfaces SEt1 and SEt2.

[0236] However, when viewed from above, in the area where the loop portion 12L1 of the conductor 12S1 overlaps with the mating surface SEt1, such as ​ As shown, the mating surface SEt1 is exposed from the insulating film 13 and the conductor 12S1 and is in close contact with the sealing body 40. However, in the area where the loop portion 12L1 of the conductor 12S1 overlaps with the mating surface SEt1, since the sealing body 40 is held by the loop portion 12L1 of the conductor 12S1 by the mating surface SEt1, peeling between the mating surface SEt1 and the sealing body 40 is not easily observed in this area. Therefore, considering peeling between the sealing body 40 and the mating surface SEt1, it is important to reduce... ​ The area of ​​the exposed surface in the region of the mating surface SEt1 that does not overlap with the conductor 12S1 when viewed from above is shown. Furthermore, in the region of the mating surface SEt1 that does not overlap with the conductor 12S1, it is preferable to... ​ The exposed area of ​​the mating surface SEt1 in the region between adjacent conductors 12, as shown, is particularly small.

[0237] As described above, when the contact area between the sealing solid 40 and the mating surface SEt1 made of metal is large, there is a possibility that peeling may occur at the mating interface between the sealing solid 40 and the mating surface SEt1 after this process. Especially in cases such as... ​ When the separation distance between adjacent conductors 12 is small, as shown, peeling is likely to occur between adjacent conductors 12. However, according to this embodiment, as described above, the area of ​​the portion of the contact interface between the sealing solid 40 and the mating surface SEt1 that is prone to peeling can be reduced, thus suppressing peeling.

[0238] After the sealing solid 40 is formed, a portion of the thermosetting resin contained in the sealing solid 40 is heated to cure (referred to as temporary curing). When the lead frame LF can be removed from the molding die 62 through this temporary curing, the lead frame LF is removed from the molding die 62. It is then transported to a heating oven for further heat treatment (cure bake). This allows the remaining portion of the thermosetting resin to cure, resulting in... ​ The sealing solid shown is 40.

[0239] In addition, the sealing solid 40 is mainly composed of an insulating resin, but by mixing filler particles such as silica (silica; SiO2) particles into the thermosetting resin, the performance of the sealing solid 40 (e.g., resistance to warping deformation) can be improved.

[0240] <Plating Process>

[0241] Next, in ​ In the plating process shown, ​ The lead frame LF shown is immersed in a plating solution (not shown) to form a metal film on the surface of the metal portion (exterior) exposed from the sealing solid 40. ​ The metal film 22 and metal film 32 shown.

[0242] In this process, an electroplating method is used to form a metal film 22, 32 (refer to) made of, for example, solder on the surface of the metal part exposed from the resin. ​ Although the illustration is omitted, the lead frame LF (see reference) will be used as the workpiece to be plated in the electroplating process. ​ The workpiece is placed in a plating tank filled with plating solution. At this time, the workpiece is connected to the cathode in the plating tank. For example, the frame portion LFf of the lead frame LF (refer to...) ​ The cathode is electrically connected to the metal. Then, by applying, for example, a DC voltage between the cathode and the anode disposed in the same plating bath, metal films 22 and 32 are formed on the exposed surfaces of the metal components connected to the frame portion LFf of the lead frame LF. In this embodiment, the metal films 22 and 32 are formed using a so-called electroplating method.

[0243] In addition, ​ Although the illustration is omitted, this pretreatment method can be used as a pretreatment step before immersing the lead frame LF in the plating solution during the plating process. ​ The surfaces of the chip pads 20 and leads 30 shown are subjected to chemical polishing. By performing a pretreatment before immersing the lead frame LF in the plating solution, it is possible to remove, for example, solids from the encapsulating solid 40 (see reference). ​ The exposed lead frame LF surface shows oxide film and tiny burrs.

[0244] The metal films 22 and 32 in this embodiment, as described above, are composed of so-called lead-free solder that is practically lead-free (Pb), such as tin (Sn), tin-bismuth (Sn-Bi), or tin-copper-silver (Sn-Cu-Ag). Therefore, the plating solution used in this plating process contains, for example, Sn. 2+ , or Bi 3+ Electroplating solutions containing metal salts. Furthermore, in the following description, Sn-Bi alloy metal plating will be described as an example of lead-free solder plating, but bismuth (Bi) can be replaced with metals such as copper (Cu) or silver (Ag), or with an electroplating solution containing bismuth (Bi) plus copper (Cu) or silver (Ag).

[0245] In this embodiment, ​ Chip pad 20 shown (refer to) ​ The plating process is performed while the lead frame LFf is electrically connected to the lead wire 30. When a voltage is applied between the anode and cathode while the lead frame LF is immersed in the plating solution, the lead wire 30 connected to the cathode and the chip pad 20 are energized with respect to the anode through the plating solution. At this time, Sn in the plating solution... 2+ and Bi 3+ The deposited material is deposited at a specified ratio onto the exposed surfaces of the lead 30 and chip pad 20 from the encapsulating solid 40, forming... ​ The metal films 22 and 32 are shown.

[0246] <Single-piece manufacturing process>

[0247] Next, in ​ In the single-chip process shown, it will be combined with ​ The semiconductor device PKG1 shown (refer to) ​ A comparable assembly from ​ The lead frame LF shown is separated from the frame portion LFf and the tie rod LFt to make it a single piece.

[0248] In this process, the chip pad 20 (refer to) will be... ​ The connected frame part LFf (refer to) ​ The chip is cut to separate multiple chip pads 20 connected by the frame portion LFf. Additionally, in this process, the connecting rod LFt (refer to...) ​ The junction between the multiple leads 30 and the frame portion LFf is cut off, thereby enabling the multiple leads 30 to be separated individually.

[0249] For the cutting method of the tie rod LFt, frame LFf, and lead wire 30, a processing method (stamping) can be used to press the cutting fixture against the part to be cut. This process is performed after the plating process, so the newly formed side surface from the cut in this process is cut from the plating ( ​The metal films 22 and 32 shown are exposed.

[0250] After this process, necessary inspections and tests such as appearance inspection and electrical tests are carried out, and the qualified products are ​ the completed semiconductor device PKG1 shown. Then, the semiconductor device PKG1 is shipped out or installed on a mounting substrate not shown.

[0251] The invention proposed by the inventor of the present application has been specifically described based on the embodiments, but the present invention is of course not limited to the above embodiments or the modified examples described in the above embodiments, and various changes can be made without departing from its gist. Representative modified examples will be described below.

[0252] <Variant Example 1>

[0253] As described using ​ and ​ when reducing the exposed area of the bonding surface SEt1, in the wire bonding process, the margin for the positional deviation of the bonding position of the wire is reduced. Therefore, in the wire bonding process, it is preferable to confirm the positional relationship between the bonding portions 12B1 and 12B2 of the wire 12S1 and the bonding surface SEt1 by visual observation or using an image sensor, etc., and fine-tune the wire bonding position based on the confirmation result. In addition, when confirming the positional relationship between the bonding portions 12B1 and 12B2 of the wire 12S1 and the bonding surface SEt1, if there are marks near the bonding portions 12B1 and 12B2 that can grasp the degree of positional deviation, fine-tuning can be easily implemented. In this variant example, a structural example in which marks for grasping the degree of positional deviation are formed on a part of the bonding surface SEt1 shown in ​ will be described. ​ is an enlarged top view showing a variant example of ​ . In addition, ​ and ​ are enlarged top views showing a state example in which wires are bonded on the bonding surface shown in ​ .

[0254] In the case of the variant example shown in ​ , the region SER1 of the bonding surface SEt1 has a protruding portion HSM1 that protrudes along the X direction at the side HS1 of the opening 13H1, and a protruding portion HSM2 that protrudes along the X direction at the side HS2 of the opening 13H1. In addition, the region SER2 of the bonding surface SEt1 has a protruding portion HSM3 that protrudes along the X direction at the side HS1 of the opening 13H1, and a protruding portion HSM4 that protrudes along the X direction at the side HS2 of the opening 13H1.

[0255] Protrusions HSM1, HSM2, HSM3, and HSM4 extend from the in-plane of the mating surface SEt1 toward the insulating film 13 (see reference). ​ The protrusions HSM1, HSM2, HSM3, and HSM4 are reference marks used to confirm the degree of positional deviation of the bonding position of wire 12S1 during the aforementioned wire bonding process. Specifically, during the wire bonding process, the length (width) WRP of the protrusions HSM1, HSM2, HSM3, or HSM4 in the X direction is used to confirm... ​ The positional deviation of the junction 12B1 or junction 12B2 of the conductor 12S1 shown. ​ The length (width) WRP of the protrusions HSM1, HSM2, HSM3, or HSM4 shown is equal in the X direction, for example, 50 μm. This value of 50 μm is the upper limit of the allowable positional deviation during the wire bonding process.

[0256] Furthermore, when viewed from above, the lengths LM1 and LM2 of protrusion HSM1 in the Y direction are both shorter than the length of region SER1 in the Y direction. In other words, protrusion HSM1 is formed on a portion of edge HS1 of region SER1. Similarly, protrusion HSM2 is formed on a portion of edge HS2 of region SER1. Additionally, the lengths LM3 and LM4 of protrusion HSM3 and HSM4 in the Y direction are both shorter than the length of region SER2 in the Y direction. Since protrusion HSM1 is formed on a portion of region SER1, therefore... ​ and ​ As shown, the separation distance GP1 between edge HS1 and joint 12B1 and the length WRP of protrusion HSM1 in the X direction can be compared. The same applies to protrusions HSM2, HSM3, and HSM4.

[0257] In the case where, as shown in this modified example, a mark is formed in the region SER1 of the mating surface SEt1 as a standard for the amount of positional deviation, as in... Figure 22 and Figure 23 When the position of the shown joint 12B1 deviates from the specified position of the area SER1 of the joint surface SEt1, the amount of deviation can be easily determined. For example, in Figure 22 When the joint 12B1 is close to the side HS1 of the opening 13H1 as shown, the degree of deviation relative to the allowable value can be easily confirmed by comparing the separation distance GP1 between the side HS1 and the joint 12B1 with the length WRP of the protrusion HSM1 in the X direction.

[0258] In addition, in such Figure 23When the shown joint 12B1 is near the side HS2 of the opening 13H1, by comparing the separation distance GP2 between the side HS2 and the joint 12B1 with the length WRP of the protrusion HSM2 in the X direction, the degree of deviation relative to the allowable value can be easily confirmed. Figure 21 As shown, when protrusions HSM1 and HSM2 are formed on the HS1 side and the HS2 side, the deviation can be accurately measured.

[0259] However, in such Figure 23 When the joint 12B1 is close to the side HS2 of the opening 13H1, the separation distance GP1 between the side HS1 and the joint 12B1 and the length WRP of the protrusion HSM1 in the X direction can be compared. In this case, the degree of positional deviation of the joint 12B1 can also be determined.

[0260] In addition, Figure 21 In the example shown, protrusions HSM3 and HSM4 are formed in region SER2 of the mating surface SEt1. Figure 10 As shown, the joint portion 12B1, the loop portion 12L1, and the joint portion 12B2 of the conductor 12S1 are arranged in a straight line along the Y direction. Therefore, as long as it is formed Figure 21 The deviation can be determined by at least one of the protrusions HSM1, HSM2, HSM3, and HSM4 shown. However, if... Figure 21 As shown, protrusions are formed in regions SER1 and SER2 respectively. Figure 10 When the extension direction of the conductor 12S1 shown is tilted relative to the Y direction, it is easy to grasp the degree of this tilt angle.

[0261] in addition, Figure 21 The lengths (WRP) of the protrusions HSM1, HSM2, HSM3, and HSM4 shown can be varied according to the allowable range set in the wire bonding process. However, if the value is too large, protrusions HSM1, HSM2, HSM3, or HSM4 may become the starting point of the aforementioned peeling. Therefore, it is preferable that the length WRP is small enough to prevent peeling from occurring. Figure 21 In the example shown, the length WRP is 50 μm, shorter than the lengths LM1, LM2, LM3, and LM4. The lengths LM1, LM2, LM3, and LM4 are, for example, around 200 μm. Furthermore, it is preferable that the length WRP is shorter than... Figure 22 and Figure 23 The larger of the separation distances GP1 and GP2 shown is smaller. For example... Figure 22 and Figure 23In the example shown, the sum of separation distances GP1 and GP2 is 100 μm. Therefore, if the length WRP is 50 μm, the above conditions are satisfied except when the separation distance GP1 is 50 μm.

[0262] In addition, Figures 21 to 23 In the middle, for conductor 12S1 (refer to Figure 22 An example has been illustrated where a mark for indicating the amount of positional deviation is disposed near the joint 12B1, but the mark can also be formed on... Figure 9 In the area SER3 shown. Figure 24 It shows that it is aimed at Figure 21 An enlarged top view of a variant example. Figure 25 It is shown in Figure 24 An enlarged top view of an example of a joint surface with wires attached.

[0263] exist Figure 24 In the case of the modified example shown, the region SER3 of the mating surface SEt1 has a recess HSM5 that is recessed toward the region SER3 in the X direction at the edge HS1 of the opening 13H1, and a recess HSM6 that is recessed toward the region SER3 in the X direction at the edge HS2 of the opening 13H1.

[0264] Recesses HSM5 and HSM6 are recessed in a manner that penetrates into region SER3 of the mating surface SEt1. Furthermore, recesses HSM5 and HSM6 are marks referenced during the aforementioned wire bonding process when confirming the degree of positional deviation of the bonding position of wire 12S1. Specifically, during the wire bonding process, the length (width) WRP of recesses HSM5 and HSM6 in the X direction is checked against... Figure 10 The positional relationship of the loop portion 12L1 of the conductor 12S1 shown is used to confirm the amount of positional deviation. Figure 24 The recesses HSM5 and HSM6 shown have the same length (width) WRP value in the X direction, for example, 50 μm. This 50 μm value, as described above, is the upper limit of the allowable positional deviation during the wire bonding process.

[0265] Furthermore, when viewed from above, the lengths LM5 and LM6 of the recess HSM5 and HSM6 in the Y direction are both shorter than the length of region SER3 in the X direction. In other words, the recess HSM5 is formed on a portion of edge HS1 of region SER3. Concave HSM6 is formed on a portion of edge HS2 of region SER3. Because the recess HSM5 is formed on a portion of region SER3, therefore... Figure 25 As shown, the length GP3 of the portion of the recess HSM5 exposed from the ring 12L1 in the X direction can be easily determined when viewed from above.

[0266] As shown in this modified example, when a mark is formed in region SER3 of the mating surface SEt1 as a standard for the amount of positional deviation, such as Figure 25 As shown, when the position of the ring portion 12L1 deviates from the specified position of the region SER3 of the mating surface SEt1, the amount of deviation can be easily confirmed. Furthermore, as described above, Figure 10 The joint 12B1, loop 12L1, and joint 12B2 of the wire 12S1 shown are arranged in a straight line along the Y direction. Therefore, as long as the deviation of the loop 12L1 is known, the deviation of the joints 12B1 and 12B2 can be predicted.

[0267] In addition, Figure 21 In the example shown, compared to the case where no protrusions HSM1, HSM2, HSM3, and HSM4 are formed, the opening area of ​​opening 13H1 is larger. Therefore, for example, Figure 7 As shown, when the separation distance between adjacent openings 13H1 and 13H2 is small, the layout needs to be considered in such a way that the protrusions HSM1, HSM2, HSM3 and HSM4 formed in openings 13H1 and 13H2 are not connected to each other.

[0268] On the other hand, Figure 24 In the example shown, compared to the examples where the recesses HSM5 and HSM6 are not formed, the opening area of ​​the opening 13H1 is smaller. Therefore, even in the case of... Figure 7 When the separation distance between adjacent openings 13H1 and 13H2 is small, as shown, the degree of freedom in layout is also high.

[0269] In addition, in such Figure 25 When the conductor 12S1 is positioned close to the side HS2 of the opening 13H1, the recess HSM6 provided on the side HS2 cannot be visually identified. Conversely, when the conductor 12S1 is positioned close to the side HS1 of the opening 13H1, the recess HSM5 provided on the side HS1 cannot be visually identified. Therefore, from the perspective of controlling the deviation even when the conductor 12S1 is positioned close to either side HS1 or HS2, it is preferable to... Figure 24 As shown, recesses are formed on both sides HS1 and HS2.

[0270] In addition, Figure 24 In the example shown, no usage was formed. Figure 21 The protrusions described are HSM1, HSM2, HSM3, and HSM4. However, as a variation, it is also possible to... Figure 25 Based on the recesses HSM5 and HSM6 shown, a structure is formed. Figure 21At least one of the protrusions HSM1, HSM2, HSM3, and HSM4 shown.

[0271] <Variation Example 2>

[0272] Furthermore, in the above embodiments, such as Figure 9 The example shown is an embodiment in which a neck is formed on both sides HS1 and HS2 of the opening 13H1. However, as a variation, it is also possible to... Figure 26 As shown, a neck is formed on one of the edges HS1 and HS2. Figure 26 It shows that it is aimed at Figure 13 An enlarged top view of a variant example.

[0273] Figure 26 The mating surface SEt1 shown has no edge HS2 on the side of the opening 13H1. Figure 13 The portion shown is HSP23, and the edge HS2 extends in a straight line, which is consistent with... Figure 13 The mating surface SEt1 shown is different.

[0274] Even if Figure 26 In the modified example shown, when the joint position of the conductor 12S1 is close to the side HS2, the value of the width WR4 between the side HS2 and the loop portion 12L1 of the conductor 12S1 is also less than 100 μm. On the other hand, although the figure is omitted, when the joint position of the conductor 12S1 is close to the side HS1, there is a case where the value of the width WR4 is 150 μm.

[0275] However, as Figure 5 As shown, multiple conductors 12S are arranged adjacent to each other, as... Figure 7 As shown, wire 12S1 is arranged at the end of the arrangement. However, wire 12S is not arranged on the side HS2 of the opening 13H1. Therefore, with... Figure 12 Compared to the case where the width WR3 value is 150 μm in the research example shown, in Figure 26 In the example shown, peeling is less likely to occur when the width WR3 value is 150μm.

[0276] As described above, when the mating surfaces (openings) are arranged adjacent to each other, or when the mating surfaces are arranged at the ends of the arrangement, there is also a case where the neck is arranged on one of the sides HS1 and HS2.

[0277] <Variation Example 3>

[0278] Furthermore, in the above embodiments, for example... Figure 8 An embodiment in which multiple portions of a source electrode pad SE are exposed at multiple openings 13H1 provided in the insulating film 13, as shown, has been described. However, Figure 8 The bonding surface SEt1 shown may be part of the first source electrode pad (electrode, source electrode) SE1 covered by the insulating film 13, and the bonding surface SEt2 may be part of the second source electrode pad (electrode, source electrode) SE2 covered by the insulating film 13.

[0279] <Variation Example 4>

[0280] Furthermore, in the above embodiments, for example, Figure 7 The case where the mating surfaces SEt1 and SEt2 are rectangular has been described as shown. However, the shapes of the mating surfaces SEt1 and SEt2 are not limited to rectangles; for example, there are various variations such as polygons, circles (including ellipses).

[0281] <Variation Example 5>

[0282] Additionally, although the illustration is omitted, it serves as a reference for... Figure 7 In another variation, the conductor 12S1 may be joined to a joint surface SEt1 at three or more locations. In this case, since the joint area between the conductor 12S1 and the joint surface SEt1 is increased, the impedance of the conductive path through the conductor 12S1 can be reduced. The same applies to the conductor 12S2.

[0283] However, when there are many joints between the conductor 12S1 and the joint surface SEt1, the length of the joint surface SEt1 in the Y direction (e.g.) Figure 7 In the example shown, the lengths of sides HS1 and HS2 are relatively long. In this case, because the sealing solid 40 (refer to...) Figure 20 The stress caused by the difference in the linear expansion coefficients of the source electrode pad SE and the joint surface SEt1 is located at both ends in the Y direction. Figure 7 The area near edge HS3 and edge HS4 is particularly large. Therefore, from the perspective of shortening the length of the source electrode pad SE in the Y direction, it is particularly preferable to have the following characteristics. Figure 7 As shown, the conductor 12S1 is joined to a joint surface SEt1 at two locations.

[0284] <Variation Example 6>

[0285] Furthermore, in the above embodiments, a MOSFET was exemplified as an example of a power transistor included in a power semiconductor device, but various modifications can be applied. For example, an IGBT can be used instead of a MOSFET. In this case, the drain of the MOSFET described in the above embodiments can be replaced with the collector of the IGBT, and the source of the MOSFET can be replaced with the emitter of the IGBT. Additionally, when using an IGBT, it is common to mount the diode (FWD, Free Wheeling Diode) chip used to control the direction of load current flow independently of the IGBT chip. Therefore, in Figure 5 The chip pad 20 shown is equipped with an IGBT chip and an FWD chip.

[0286] Furthermore, in the above embodiments, power semiconductor devices were described as an example of semiconductor devices that are prone to having excessively high requirements for resistance to ambient temperature and temperature cycling loads. However, even in cases of semiconductor devices other than power semiconductor devices (such as semiconductor devices for control systems or communication systems), when the requirements for resistance to ambient temperature or temperature cycling loads are high, the performance related to resistance to ambient temperature or temperature cycling loads can be improved by applying the techniques described in the above embodiments or variations. Additionally, in semiconductor devices other than power semiconductor devices, it is common to use gold (Au) wires as conductors and ball-type bonding methods as conductor bonding methods.

[0287] <Variation Example 7>

[0288] Furthermore, in the above embodiments, for example... Figure 7 The embodiment shown is described in which the X direction, which is the arrangement direction of the bonding surfaces SEt1 and SEt2, and the Y direction, which is the extension direction of the bonding surfaces SEt1 and SEt2, extend along each edge of the surface 10t of the semiconductor chip 10. However, the above configurations can also be applied to cases where the X direction and the Y direction intersect each edge of the surface 10t of the semiconductor chip 10 at angles other than orthogonal.

[0289] <Variation Example 8>

[0290] Furthermore, while various modifications have been described above, these modifications can be combined. Alternatively, a portion of each modification can be extracted and combined.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor chip includes electrode pads and an insulating film, the electrode pads having a first bonding surface and the insulating film having a first opening that exposes the first bonding surface of the electrode pads. The first conductor is engaged with the first mating surface of the electrode pad; as well as A sealing solid is used to seal the semiconductor chip and the first conductive wire in a manner that contacts the first bonding surface of the electrode pads. The first mating surface is made of metal. The sealing solid is made of insulating material. When viewed from above, the first mating surface has a first region, a second region, and a third region located between the first region and the second region. The first conductor has a first joint portion that engages with a first region of the first joint surface, a second joint portion that engages with a second region of the first joint surface, and a first intermediate portion located between the first joint portion and the second joint portion. When viewed from above, the first middle portion extends along the first direction, and the first middle portion is separated from the third region. When viewed from above, the width of the first region in the second direction orthogonal to the first direction and the width of the second region in the second direction are greater than the width of the third region in the second direction.

2. The semiconductor device according to claim 1, characterized in that, The first opening has a first side and a second side, the first side being located at one end of the first opening in the second direction and extending along the first direction, and the second side being located at the opposite end of the first side and extending along the first direction. The first edge bends between the first region and the third region, and between the second region and the third region, respectively. The second side bends between the first region and the third region, and between the second region and the third region.

3. The semiconductor device according to claim 1, characterized in that, When viewed from above, the width of the third region in the second direction is less than or equal to the width of the first middle portion of the first conductor in the second direction.

4. The semiconductor device according to claim 1, characterized in that, In the second direction, the second conductor is positioned next to the first conductor. The separation distance between the first conductor and the second conductor in the second direction is smaller than the diameter of the first conductor.

5. The semiconductor device according to claim 1, characterized in that, When viewed from above, the first opening has a first side extending along the first direction and a second side located on the opposite side of the first side. When viewed from above, the first side has a first portion extending along the first region, a second portion extending along the second region, and a third portion located between the first portion and the second portion and extending along the third region. The width between the extension of the first portion of the first side and the third portion is greater than the width between the third portion of the first side and the first middle portion of the first conductor.

6. The semiconductor device according to claim 1, characterized in that, When viewed from above, the first opening has a first side extending along the first direction and a second side located on the opposite side of the first side. When viewed from above, the first side has a first portion extending along the first region, a second portion extending along the second region, and a third portion located between the first portion and the second portion and extending along the third region. The second side, when viewed from above, has a fourth portion extending along the first region, a fifth portion extending along the second region, and a sixth portion located between the fourth and fifth portions and extending along the third region. The third part of the first side is located between the extension of the first part and the second side. The sixth part of the second side is located between the extension of the fourth part and the first side.

7. The semiconductor device according to claim 1, characterized in that, The first region of the first mating surface has a first protrusion protruding along the second direction. When viewed from above, the length of the first protrusion in the first direction is shorter than the length of the first region in the first direction.

8. The semiconductor device according to claim 7, characterized in that, When viewed from above, the length of the first protrusion in the second direction is shorter than the length of the first protrusion in the first direction.

9. The semiconductor device according to claim 1, characterized in that, When viewed from above, the first opening has a first side extending along the first direction and a second side located on the opposite side of the first side. The first region of the first mating surface has a first protrusion protruding along the second direction at the first side of the first opening, and a second protrusion protruding along the second direction at the second side of the first opening. When viewed from above, the lengths of the first protrusion and the second protrusion in the first direction are respectively shorter than the length of the first region in the first direction.

10. The semiconductor device according to claim 9, characterized in that, The second region of the first mating surface has a third protrusion protruding along the second direction at the first side of the first opening, and a fourth protrusion protruding along the second direction at the second side of the first opening. When viewed from above, the lengths of the third protrusion and the fourth protrusion in the first direction are respectively shorter than the length of the second region in the first direction.

11. The semiconductor device according to claim 1, characterized in that, The third region of the first mating surface has a first recess that is recessed toward the third region along the second direction. When viewed from above, the length of the first recess in the first direction is shorter than the length of the third region in the first direction.

12. The semiconductor device according to claim 1, characterized in that, When viewed from above, the first opening has a first side extending along the first direction and a second side located on the opposite side of the first side. The third region of the first mating surface has a first recess recessed at the first side of the first opening along the second direction toward the second side, and a second recess recessed at the second side of the first opening along the second direction toward the second side. When viewed from above, the lengths of the first recess and the second recess in the first direction are respectively shorter than the length of the third region in the first direction.

13. The semiconductor device according to claim 1, characterized in that, The third region showed signs of intrusion by the test terminal.

14. A semiconductor device, characterized in that, include: A semiconductor chip includes electrode pads and an insulating film. The electrode pads have a first bonding surface, and the insulating film has a first opening that exposes the first bonding surface of the electrode pads. The first conductor is engaged with the first mating surface of the electrode pad; as well as A sealing solid is used to seal the semiconductor chip and the first conductive wire in a manner that contacts the first bonding surface of the electrode pads. The first mating surface is made of metal. The sealing solid is made of insulating material. The first conductor has a first joint portion that engages with the first joint surface, a second joint portion that engages with the first joint surface, and a first intermediate portion located between the first joint portion and the second joint portion. When viewed from above, the first intermediate portion extends along the first direction, and the first intermediate portion is separated from the first mating surface. When viewed from above, the first opening has a first side extending along the first direction, a second side located on the opposite side of the first side, a third side extending along a second direction orthogonal to the first direction, and a fourth side located on the opposite side of the third side. When viewed from above, the first side has a first portion extending along the first direction, a second portion extending along the first direction, and a third portion located between the first portion and the second portion and extending along the first direction. In the second direction viewed from above, the first joint is located between the first portion of the first side and the second side. In the second direction when viewed from above, the second joint is located between the second portion of the first side and the second side. In the second direction when viewed from above, the first middle portion is located between the third portion of the first side and the second side. When viewed from above, the length from the first part of the first side to the second side in the second direction and the length from the second part of the first side to the second side in the second direction are both greater than the length from the third part to the second side in the second direction.

15. The semiconductor device according to claim 14, characterized in that, When viewed from above, the second side has a fourth portion extending along the first direction, a fifth portion extending along the first direction, and a sixth portion located between the first portion and the second portion and extending along the first direction. The third part of the first side is located between the extension of the first part and the second side. The sixth part of the second side is located between the extension of the fourth part and the first side.

16. The semiconductor device according to claim 14, characterized in that, The area of ​​the first mating surface that overlaps with the first middle portion of the first conductor has traces of intrusion by a test terminal.

17. A method for manufacturing a semiconductor device, characterized in that, The process includes the following steps: (a) Step in which a semiconductor chip is prepared, the semiconductor chip including a first surface, a first back surface located on the opposite side of the first surface, an electrode pad having a first bonding surface, and an insulating film having the first surface and including a first opening that exposes the first bonding surface of the electrode pad. (b) Step, in which a lead frame including a chip mounting portion and a first lead is prepared, the chip mounting portion being used to fix the semiconductor chip, and the first lead being separated from the chip mounting portion; (c) Step (a) and step (b) wherein, in step (c), the semiconductor chip is mounted on the chip mounting portion such that the first back surface of the semiconductor chip is opposite to the chip mounting portion; Step (d), which follows step (c), in which a first wire is bonded on the first bonding surface of the semiconductor chip; and Step (e), which follows step (d), involves sealing the semiconductor chip and the first conductive wire with an insulating material in contact with the first bonding surface of the electrode pads. The first mating surface is made of metal. When viewed from above, the first mating surface has a first region, a second region, and a third region located between the first region and the second region. The (d) process includes: (d1) step, in which the first joint portion of the first conductor is joined to the first region of the first joint surface; Step (d2), which follows step (d1), involves forming a first intermediate portion of the first conductor that is connected to the first joint and extends along the first direction, across the third region of the first joint surface; and Step (d3), which follows step (d2), involves joining the second joint portion of the first conductor, which is connected to the first intermediate portion of the first conductor, to the second region of the first joint surface. The first middle portion of the first conductor separates from the third region. When viewed from above, the width of the first region in the second direction orthogonal to the first direction and the width of the second region in the second direction are greater than the width of the third region in the second direction.

18. The method for manufacturing a semiconductor device according to claim 17, characterized in that, The first region of the first mating surface has a first protrusion protruding along the second direction. When viewed from above, the length of the first protrusion in the first direction is shorter than the length of the first region in the first direction. Step (d) includes step (d4), which follows step (d1). In step (d4), the positional relationship between the first conductor and the first mating surface is confirmed, and the conductor mating position is adjusted according to the confirmation result. In the (d4) step, the deviation of the position of the first joint of the first conductor is confirmed by referring to the length of the first protrusion in the second direction.

19. The method for manufacturing a semiconductor device according to claim 17, characterized in that, The third region of the first mating surface has a first recess that is recessed toward the third region along the second direction. When viewed from above, the length of the first recess in the first direction is shorter than the length of the third region in the first direction. Step (d) includes step (d4), which follows step (d1). In step (d4), the positional relationship between the first conductor and the first mating surface is confirmed, and the conductor mating position is adjusted according to the confirmation result. In step (d4), the positional relationship between the length of the first recess in the second direction and the first middle portion of the first conductor is confirmed.

20. The method for manufacturing a semiconductor device according to claim 17, characterized in that, The process (a) includes the process of bringing the test terminal into contact with the third region.

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