Electric drive power converter with low-distortion dead-time insertion

Abstract

An electric drive system for an electric vehicle has a power converter, the power converter having phase leg switching devices controlled by pulse width modulation to supply polyphase AC to an electric traction motor. A dead time interval is inserted into the gate drive signals of the switching devices without introducing any significant distortion into the output of the converter. The direction of current between the phase leg and the motor is detected. When the current direction is positive, the lower gate signal of the lower switching device in the phase leg has a delayed rising edge and an advanced falling edge, while the upper gate signal is unmodified. When the current direction is negative, the upper gate signal of the upper switching device in the phase leg has a delayed rising edge and an advanced falling edge, while the lower gate signal is unmodified.

Description

Technical Field

[0001] The present invention generally relates to a power converter including an inverter for an electric drive system of an electric vehicle, and more particularly, to inserting a dead time interval into a gate drive signal without causing any significant distortion of the output current of the converter. Background Art

[0002] Electric vehicles such as hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs), and battery electric vehicles (BEVs) use inverter-driven motors to provide traction torque and regenerative braking torque. A typical electric drive system includes a DC (direct current) power source (such as a battery pack or a fuel cell), which is connected to a variable voltage converter (VVC) through a contactor switch to regulate the main bus voltage across the main DC link capacitor. The inverter is connected between the main bus of the DC link and the traction motor to convert DC power into AC (alternating current) power that is connected to the motor windings to propel the vehicle. A second inverter can also be connected between the main bus and a generator (if any) to provide another power flow path from a prime mover (usually an internal combustion engine) to the DC link.

[0003] The inverter includes transistor switch devices (such as insulated gate bipolar transistors (IGBTs)) connected in a bridge configuration having a plurality of phase legs. A typical bridge configuration includes a three-phase motor driven by an inverter having three phase legs. The electric controller opens and closes the switches to convert the DC voltage from the bus into an AC voltage applied to the motor, or to rectify the AC voltage from the generator into a DC voltage on the bus. In each case, the inverter is controlled in response to various sensed conditions, including the rotational position of the motor and the current in each phase leg.

[0004] The inverter for the motor can preferably perform pulse width modulation on the DC link voltage to deliver an approximation of a sinusoidal current output to drive the motor at a desired speed and torque. The pulse width modulation (PWM) control signal applied to the IGBT gate turns it on and off as needed so that the resulting current matches the desired current.

[0005] Since each phase leg of the inverter has a pair of upper and lower switching devices across the DC link, it is important to prevent the two devices from conducting (i.e., turning on) simultaneously. Otherwise, the resulting "shoot-through" of the phase leg may cause damage to the switching devices. To prevent shoot-through, a short time interval (referred to as dead time) during which both the upper and lower switching devices of the phase leg are off is typically used in combination with the PWM control of the inverter. However, inserting the dead time causes distortion of the output current waveform delivered to the load and introduces a control delay. Summary of the Invention

[0006] In one aspect of the present invention, a power converter includes a phase leg having an upper switching device and a lower switching device, wherein a connection point between the upper and lower switching devices is configured to be connected to a load. A current sensor of the phase leg detects a positive or negative direction of a current from the connection point to the load. A gate driver is connected to the phase leg to activate the upper switching device according to an upper gate signal and to activate the lower switching device according to a lower gate signal. A controller compares a PWM carrier signal with a commanded duty cycle signal to generate nominal upper and lower timing signals. When the positive direction of the current is detected, the controller 1) generates a positive-offset duty cycle that is greater than the commanded duty cycle by a predetermined positive offset, 2) compares the PWM carrier signal with the positive-offset duty cycle signal to generate a positive-offset timing signal, 3) generates the upper gate signal according to the nominal upper timing signal, and 4) generates the lower gate signal according to a logical inversion of the positive-offset timing signal. When the negative direction of the current is detected, the controller 1) generates a negative-offset duty cycle that is less than the commanded duty cycle by a predetermined negative offset, 2) compares the PWM carrier signal with the negative-offset duty cycle signal to generate a negative-offset timing signal, 3) generates the upper gate signal according to the negative-offset timing signal, and 4) generates the lower gate signal according to the nominal lower timing signal.

[0007] According to the present invention, there is provided a power converter, comprising:

[0008] A phase leg including an upper switching device and a lower switching device, wherein a connection point between the upper switching device and the lower switching device is configured to be connected to a load;

[0009] A current sensor for the phase leg, the current sensor being configured to detect a positive or negative direction of a current from the connection point to the load; and

[0010] A gate driver connected to the phase leg, the gate driver activating the upper switching device according to an upper gate signal and activating the lower switching device according to a lower gate signal; and

[0011] A controller that compares a PWM carrier signal with a commanded duty cycle signal to generate a nominal upper timing signal and a nominal lower timing signal, wherein when the positive direction of the current is detected, the controller performs the following operations:

[0012] Generating a positive-offset duty cycle that is greater than the commanded duty cycle by a predetermined positive offset;

[0013] Comparing the PWM carrier signal with the positive-offset duty cycle signal to generate a positive-offset timing signal;

[0014] Generating the upper gate signal according to the nominal upper timing signal; and

[0015] Generating the lower gate signal according to a logical inversion of the positive-offset timing signal;

[0016] And when the controller detects a negative direction of the current, the following operations are performed:

[0017] Generate a negative offset duty cycle that is smaller than the commanded duty cycle by a predetermined negative offset;

[0018] Compare the PWM carrier signal with the negative offset duty cycle signal to generate a negative offset timing signal;

[0019] Generate an upper gate signal based on the negative offset timing signal; and

[0020] Generate a lower gate signal based on the nominal lower timing signal.

[0021] According to an embodiment of the present invention, the PWM carrier signal has a predetermined slope, where the predetermined positive offset divided by the predetermined slope is equal to a predetermined dead time t D , and where the predetermined negative offset divided by the predetermined slope is equal to a predetermined dead time t D .

[0022] According to an embodiment of the present invention, the PWM carrier signal includes a triangular wave.

[0023] According to an embodiment of the present invention, the load includes an electric traction motor of a road vehicle, and where the commanded duty cycle corresponds to the required torque from the traction motor.

[0024] According to the present invention, there is provided a power conversion method, including:

[0025] Generate a PWM upper gate signal and a PWM lower gate signal for driving a phase leg including an upper switching device and a lower switching device;

[0026] Activate the upper switching device according to the upper gate signal and activate the lower switching device according to the lower gate signal;

[0027] Detect the current direction from the phase leg;

[0028] When the direction is positive, delay the rising edge of the lower gate signal and advance the falling edge of the lower gate signal and use the unmodified upper gate signal; and

[0029] When the direction is negative, delay the rising edge of the upper gate signal and advance the falling edge of the upper gate signal and use the unmodified lower gate signal.

[0030] According to an embodiment of the present invention, the steps of advancing and delaying the edges of the lower gate signal include:

[0031] Compare the PWM carrier signal with the commanded duty cycle signal to generate a nominal upper timing signal and a nominal lower timing signal;

[0032] Generate a positive offset duty cycle that is a predetermined positive offset greater than the duty cycle of the command;

[0033] Compare the PWM carrier signal with the positive offset duty cycle signal to generate a positive offset timing signal;

[0034] Generate an upper gate signal based on the nominal upper timing signal; and

[0035] Generate a lower gate signal based on the logical inversion of the positive offset timing signal.

[0036] According to one embodiment of the present invention, the steps of advancing and delaying the edge of the upper gate signal include:

[0037] Generate a negative offset duty cycle that is a predetermined negative offset less than the duty cycle of the command;

[0038] Compare the PWM carrier signal with the negative offset duty cycle signal to generate a negative offset timing signal;

[0039] Generate a lower gate signal based on the nominal lower timing signal; and

[0040] Generate an upper gate signal based on the negative offset timing signal.

[0041] According to one embodiment of the present invention, the PWM carrier signal has a predetermined slope, where the predetermined positive offset divided by the predetermined slope is equal to a predetermined dead time t D and where the predetermined negative offset divided by the predetermined slope is equal to a predetermined dead time t D .

[0042] According to the present invention, there is provided an electric drive for a transport vehicle, comprising:

[0043] A multi-phase electric traction motor;

[0044] A DC link configured to receive a DC supply voltage;

[0045] A plurality of phase legs connected between the DC link and the motor, wherein each phase leg includes:

[0046] A corresponding upper switching device and a corresponding lower switching device, wherein a connection point between the upper switching device and the lower switching device is connected to the motor;

[0047] A current sensor for the phase leg, the current sensor being configured to detect the positive or negative direction of the current from the connection point to the load; and

[0048] A gate driver connected to the phase leg, the gate driver activating the upper switching device according to the upper gate signal and activating the lower switching device according to the lower gate signal; and

[0049] A controller that compares a PWM carrier signal with a commanded duty cycle signal to generate a corresponding nominal upper timing signal and a corresponding nominal lower timing signal, wherein when the controller detects a positive direction of a corresponding current, it performs the following operations:

[0050] Generate a corresponding positive offset duty cycle that is a predetermined positive offset greater than the commanded duty cycle;

[0051] Compare the PWM carrier signal with the corresponding positive offset duty cycle signal to generate a corresponding positive offset timing signal;

[0052] Generate a corresponding upper gate signal based on the corresponding nominal upper timing signal; and

[0053] Generate a corresponding lower gate signal based on the logical inversion of the corresponding positive offset timing signal;

[0054] And wherein when the controller detects a negative direction of the corresponding current, it performs the following operations:

[0055] Generate a corresponding negative offset duty cycle that is a predetermined negative offset less than the commanded duty cycle;

[0056] Compare the PWM carrier signal with the corresponding negative offset duty cycle signal to generate a corresponding negative offset timing signal;

[0057] Generate a corresponding upper gate signal based on the corresponding negative offset timing signal; and

[0058] Generate a corresponding lower gate signal based on the corresponding nominal lower timing signal.

[0059] According to one embodiment of the present invention, the PWM carrier signal has a predetermined slope, wherein the predetermined positive offset divided by the predetermined slope is equal to a predetermined dead time t D , and wherein the predetermined negative offset divided by the predetermined slope is equal to a predetermined dead time t D .

[0060] According to one embodiment of the present invention, the PWM carrier signal includes a triangular wave.

[0061] According to the present invention, there is provided a power conversion method, including:

[0062] Generate a PWM upper gate signal and a PWM lower gate signal for driving a phase leg;

[0063] Detect the current direction from the phase leg;

[0064] When the direction is positive, drive the phase leg with a delayed rising edge and an advanced falling edge of the lower gate signal and an unmodified upper gate signal; and

[0065] When the direction is negative, drive the phase leg with the rising edge of the delay and the falling edge of the advance of the upper gate signal and the unmodified lower gate signal.

[0066] According to one embodiment of the present invention, the steps of advancing and delaying the edges of the lower gate signal include:

[0067] Compare the PWM carrier signal with the commanded duty cycle signal to generate a nominal upper timing signal and a nominal lower timing signal;

[0068] Generate a positive offset duty cycle that is a predetermined positive offset greater than the commanded duty cycle;

[0069] Compare the PWM carrier signal with the positive offset duty cycle signal to generate a positive offset timing signal;

[0070] Generate an upper gate signal based on the nominal upper timing signal; and

[0071] Generate a lower gate signal based on the logical inversion of the positive offset timing signal.

[0072] According to one embodiment of the present invention, the steps of advancing and delaying the edges of the upper gate signal include:

[0073] Generate a negative offset duty cycle that is a predetermined negative offset less than the commanded duty cycle;

[0074] Compare the PWM carrier signal with the negative offset duty cycle signal to generate a negative offset timing signal;

[0075] Generate a lower gate signal based on the nominal lower timing signal; and

[0076] Generate an upper gate signal based on the negative offset timing signal.

[0077] According to one embodiment of the present invention, the PWM carrier signal has a predetermined slope, where the predetermined positive offset divided by the predetermined slope is equal to a predetermined dead time t D , and where the predetermined negative offset divided by the predetermined slope is equal to a predetermined dead time t D . BRIEF DESCRIPTION OF THE DRAWINGS

[0078] Figure 1 is a schematic block diagram showing a power transmission system of an electric vehicle according to one embodiment of the present invention;

[0079] FIG. 2 is a waveform diagram showing the generation of gate signals with and without inserting a dead time;

[0080] Figure 3 is a waveform diagram showing an alternative method of generating a dead time;

[0081] FIG. 4 is according toFigure 3 Schematic block diagram for generating gate signals;

[0082] FIG. 5 is a graph showing the current amplitude from a phase leg during PWM operation and the thresholds for detecting positive and negative currents;

[0083] FIG. 6 is a schematic diagram of a phase leg and a comparator circuit for detecting the positive or negative current of FIG. 5;

[0084] Figure 7 is a waveform diagram showing the generation of gate signals with dead time insertion according to the present invention;

[0085] Figure 8 is a block diagram showing a multiplexer configured to select gate signals according to the present invention. DETAILED DESCRIPTION

[0086] Figure 1 Hybrid electric vehicle 10 of a type for implementing dead time insertion according to the present invention is shown. Wheel 11 can be driven by internal combustion engine 12 and / or traction motor 13 through transmission 14. To provide electric propulsion, motor 13 can be driven by inverter 15 that receives a DC link voltage at DC link capacitor 16. The DC link voltage can be generated by converter 18, known in the art, to convert DC power from battery pack 17.

[0087] Inverter 15 includes phase legs 20, 21, and 22 connected to motor phase windings 23, 24, and 25 in a bridge configuration. Phase leg 20 has upper switch device 26 and lower switch device 27 connected in series across DC link 16, and connection point 28 between devices 26 and 27 that connects to winding 23 of motor 13. Phase legs 21 and 22 have a similar construction.

[0088] The switching devices can be composed of IGBTs, anti-parallel diodes, wide bandgap field effect transistors (FETs), or other devices. Each upper and lower switching device has a corresponding gate terminal connected to a driver 31 in the controller 30. A current sensor 32 connected to each connection point of the phase leg measures the current flowing through each phase winding. The measured current amplitude is provided from the sensor 32 to a logic circuit 33 in the controller 30, and the logic circuit 33 is used to determine the PWM switching signal applied to the switching device by the driver 31. As is known in the art, the measured current can be compared with the required motor current determined based on the torque demand 34, which can be derived from the operator input terminal (such as an accelerator pedal) that allows the operator to control the vehicle speed. Therefore, the current feedback determines the PWM duty cycle within the logic circuit 33, and the logic circuit 33 is then used to generate the timing of the PWM switching signal for the phase leg switching device. The logic circuit 33 can be configured to be based on the following combination Figure 7 and 8 The invention described introduces dead time.

[0089] FIG2 shows a PWM carrier signal 35 generated as a triangular waveform at a high frequency (e.g., about 5 kHz) relative to the motor rotation frequency. A gate drive switch signal is generated based on current control using a known PWM method, and a PWM duty cycle signal 36 is generated in response to an error between the detected current and the target current. The duty cycle 36 is compared with the PWM carrier signal 35 to generate a PWM signal according to the change of the signal shown in FIG2 below. Signal 37 is a raw upper device gate signal G having a low logic level when the PWM carrier signal 35 is greater than the duty cycle signal 36, and having a high logic level when the duty cycle signal 36 is greater than the PWM carrier signal 35. UO (i.e., the nominal gate signal without dead time inserted). Signal 38 is shown as G UO The original (nominal) lower device gate signal G which is the logical inversion of signal 37 LO These raw gate signals may also be generated by methods other than using a PWM carrier signal (eg, by direct digital computation).

[0090] In order to avoid the shoot-through phenomenon that may occur using the original gate signals 37 and 38, a conventional dead time insertion has been performed as follows. By introducing a time delay (e.g., a fixed dead time delay t D) to obtain waveform 40. The fixed time delay represents the insertion of a dead time long enough to avoid the simultaneous activation of both the upper and lower switching devices that may be caused by noise or propagation delay differences (usually lasting a few microseconds) between the upper and lower gate signals. The upper switching device gate signal (G UDI ) 41 with inserted dead time is obtained through the AND gate (i.e., forming a logical AND) of the original gate signal 37 and the delayed gate signal 40. Signal 42 shows the time-delayed version of the lower gate signal 38 using the same fixed delay t D . The lower switching device gate signal (G LDI ) 43 with inserted dead time is generated by the logical AND of the original lower device gate signal 38 and the delayed signal 42. In the prior art, the upper and lower gate signals 41 and 43 (G UDI and G LDI ) with inserted dead time have been used to drive the phase leg switching devices under all conditions (i.e., inserting dead time 44 in each switching event), where each rising edge of the conducting switching device has been delayed, while each falling edge of the turning-off switching device has not been changed.

[0091] The original nominal PWM switching signal (before dead time insertion) is operated by the phase voltage v to provide a target current i aimed at achieving the following:

[0092]

[0093] where L is the phase inductance. The unit of integration is volt-seconds. Dead time insertion generates lost or extra volt-seconds (depending on the current direction), and the lost or extra volt-seconds cause current distortion. Various techniques have been adopted to try to compensate the signals generating the PWM to account for the missing or extra volt-seconds introduced by dead time insertion, thereby reducing the load current distortion. However, this also requires additional hardware functions and the compensation is not completely effective.

[0094] In co-owned U.S. Patent Application Serial No. 14 / 601300, dead time can be inserted in a way that does not change the volt-seconds of the switching device actively carrying the output current, so as to reduce the distortion caused by dead time insertion. More specifically, the substantially sinusoidal current i in a specific phase leg has a positive direction when flowing from the phase leg connection point into the motor phase winding, and a negative direction when flowing from the winding to the connection point. During the positive phase current, commutation occurs between the active upper switching device and the passive lower switching device. In other words, even though the two switching devices are alternately activated, only the active upper device conducts, while the active lower device does not carry current even when it conducts due to the opposite current direction. Similarly, when the phase current is negative, commutation occurs between the passive upper device and the active lower device.

[0095] When the detected current direction is positive, the upper gate signal has an on-time and an off-time, each on-time and off-time being shifted relative to the nominal gate signal by up to a predetermined offset (e.g., equal to the dead time t D ). Since they are shifted equally, there is no deviation in the total volt-seconds transferred by the active upper switching device. The lower gate signal is generated with an increased dead time, which is generated by delaying its on-time relative to the corresponding off-time of the upper gate signal and advancing its off-time relative to the corresponding on-time of the upper gate signal. Since the lower switching device is passive, the distortion introduced by the dead time insertion is reduced.

[0096] When the detected current direction is negative, the lower gate signal has an on-time and an off-time, each on-time and off-time being shifted relative to the nominal gate signal by a predetermined offset (e.g., equal to the dead time t D ). Since they are shifted equally, there is no deviation in the total volt-seconds transferred by the active lower switching device. The upper gate signal is generated with an increased dead time, which is generated by delaying its on-time relative to the corresponding off-time of the lower gate signal and advancing its off-time relative to the corresponding on-time of the lower gate signal. Since the upper switching device is passive in this case, the distortion introduced by the dead time insertion is reduced.

[0097] Figure 3 Shown is the signal waveform of a method according to U.S. Patent Application Serial No. 14 / 601300 for generating a pre-compensated gate signal with inserted dead time. In this method, the PWM carrier signal is compared with an offset duty cycle signal instead of with the nominal value of the variable duty cycle obtained conventionally. Thus, current feedback is used to determine the nominal target value of the duty cycle signal 36 in a known manner. The “+Δ” or “positive offset” duty cycle signal 50 is obtained by adding a predetermined offset to the duty cycle signal 36. The “−Δ” or “negative offset” duty cycle signal 51 is obtained by subtracting the predetermined offset from the duty cycle signal 36. The PWM carrier signal 35 has a predetermined slope. Given the slope and the difference between the positive and negative offset duty cycles (equal to twice the predetermined offset), the dead time window 54 is defined as the time interval equal to the required dead time t D . The dead time window 54 is centered on the nominal switching transition time without dead time insertion.

[0098] Based on the comparison using the positive and negative offset duty cycles, when the current direction is positive or negative, a separate pair of gate signals with inserted dead time is obtained for use as shown below. Comparing the positive offset duty cycle with the PWM carrier generates the upper original positive offset gate signal G shown as waveform 55 UO+To generate the corresponding gate signal for the lower switching device, the upper gate signal is inverted to provide a signal shown as waveform 56. Gate signal G UO+ and is a pre - compensation signal that provides a basis for forming a gate signal with an inserted dead - time when the current direction is positive.

[0099] The PWM carrier is compared with a negative - offset duty cycle to generate an upper original negative - offset gate signal G as shown in waveform 57. UO- To generate the corresponding gate signal for the lower switching device, the upper gate signal is inverted to provide a signal as shown in waveform 58. Gate signal G UO- and is a pre - compensation signal that provides a basis for forming a gate signal with an inserted dead - time when the current direction is negative.

[0100] The pre - compensation signal is modified using a delay and AND - gate process to introduce a dead - time interval. Thus, the upper original positive - offset gate signal G UO+ is delayed by the dead - time t D to generate a delayed signal as shown in waveform 59. Waveform 59 and the non - delayed waveform 55 pass through an AND - gate to generate an upper positive - offset gate signal G with an inserted dead - time as shown in waveform 60. UO+DI For the lower gate signal, the inverted waveform is delayed to generate waveform 61 for an AND - operation with waveform 56, to generate a lower positive - offset gate signal with an inserted dead - time as shown in waveform 62. The positive - offset duty cycle corresponds to a positive load current, such that when the load current is positive, waveforms 60 and 62 (corresponding to G UO+DI and ) are selected as the gate drive signals G U and G L .

[0101] For a negative load current, a negative - offset duty cycle is used to generate the gate drive signals. Thus, the upper original negative - offset gate signal G UO- is delayed, and then the delayed and non - delayed signals pass through an AND - gate to generate an upper negative - offset gate signal G with an inserted dead - time as shown in waveform 63. UO-DI The inverted waveform is then delayed and the delayed and non - delayed signals pass through an AND - gate to generate a lower negative - offset gate signal with an inserted dead - time as shown in waveform 64.

[0102] Figure 4 shows the circuit for generating as Figure 3The logic circuit 65 of the gate signal shown. The logic circuit 65 may include the dedicated electronic circuit components shown, or may be implemented using a programmable controller such as a microcontroller. The PWM duty cycle command (e.g., generated using a conventional PWM control method) is increased by a predetermined offset in the adder 66. The magnitude of the offset corresponds to half of the desired dead time interval and also depends on the slope of the PWM carrier signal. More specifically, the difference between the positive offset duty cycle and the negative offset duty cycle (i.e., twice the magnitude of the predetermined offset) divided by the slope should be equal to the desired dead time interval t D .

[0103] The positive offset duty cycle from the adder 66 is connected to the non-inverting input terminal of the comparator 67. The PWM carrier signal is connected to the inverting input terminal of the comparator 67. The comparator 67 outputs the original upper gate drive signal G UO+ to the first input terminal of the AND gate 70. In a similar manner, the negative offset duty cycle formed by subtracting the predetermined offset from the command duty cycle by the adder 68 is connected to the non-inverting input terminal of the comparator 69. The comparator 69 outputs the original upper gate drive signal G UO- to the first input terminal of the AND gate 77 by comparing the negative offset duty cycle with the PWM carrier signal received at its inverting input terminal.

[0104] The output of the comparator 67 is delayed by the dead time interval t D in the delay module 71 to provide a second input to the AND gate 70. The output of the AND gate 70 corresponds to the signal G UO+DI and the output terminal is connected to the first input terminal of the multiplexer 72. When a high logic level (binary "1") signal exists at the selection input terminal (SEL) of the multiplexer 72, this input is a selection input through the multiplexer 72.

[0105] The output of the comparator 67 is inverted by the inverter 73 to provide the original pre-compensated lower gate drive signal connected to one input terminal of the AND gate 74. The output of the inverter 73 is delayed by the dead time interval t D in the delay module 75 to be provided to the second input terminal of the AND gate 74. The output of the AND gate 74 corresponds to the signal and the output terminal is connected to the first input terminal of the multiplexer 76. When a high logic level (binary "1") signal exists at the selection input terminal (SEL) of the multiplexer 76, this input is a selection input through the multiplexer 76.

[0106] The output of the comparator 69 is delayed by the dead time interval t D in the delay module 78 to provide a second input to the AND gate 77. The output of the AND gate 77 corresponds to the signal G UO-DIand the output terminal is connected to the second input terminal of the multiplexer 72. When a low logic level (binary "0") signal exists at the selection input terminal (SEL) of the multiplexer 72, this input is the zero-selection input through the multiplexer 72.

[0107] The output of the comparator 69 is inverted by the inverter 79 to provide the original pre-compensated lower gate drive signal connected to one input terminal of the AND gate 80. The output of the inverter 79 is delayed by a dead time interval t in the delay module 81 D to be provided to the second input terminal of the AND gate 80. The output of the AND gate 80 corresponds to this signal and the output terminal is connected to the second input terminal of the multiplexer 76. When a low logic level (binary "0") signal exists at the selection input terminal (SEL) of the multiplexer 76, this input is the zero-selection input through the multiplexer 76.

[0108] The comparison module 82 compares the detected value of the instantaneous current flowing in the corresponding phase leg with zero to determine whether the current is in the positive or negative direction from the phase leg to the load. When the direction is positive, the module 82 provides a high logic level to the SEL input terminals of the multiplexers 72 and 76. Otherwise, the negative current causes the module 82 to provide a low logic level to the SEL input terminals of the multiplexers 72 and 76. Therefore, the gate signal pair with appropriate inserted dead time is applied to the input terminals of the amplifiers 84 and 86 in the driver 83, and the phase leg switching devices 85 and 87 operate with the required dead time, while reducing current distortion. Due to noise and other fluctuations, it is easy to make mistakes in determining the current direction when the current amplitude is close to zero. To avoid shoot-through in this case, both the upper and lower gate signals are continuously inserted with dead time. Since the nominal gate signals are not used in an unmodified form, there is still some distortion.

[0109] As disclosed in the commonly assigned U.S. Patent Application Serial No. 14 / 601282, when the current amplitude is far enough from zero, the nominal gate signal can be used for one of the switches. FIG. 5 shows the phase current 88 of any one phase winding, which varies at a frequency corresponding to the motor speed. This frequency is generally lower than the PWM switching frequency. When the phase current is greater than the positive threshold T Pos there is a high current region 89, while when the phase current is less than the negative threshold T Neg there is a low current region 90. When the phase current is positive enough (i.e., in the region 89 at T PosDuring the above (period), the switching device conversion for this phase leg reliably occurs, for example, between the active upper switching device and the passive lower switching device. To detect the state where the phase current is sufficiently far from zero (to avoid noise-induced errors when selecting an appropriate gate signal), an additional comparator as shown in FIG. 6 is required. Thus, the current sensor 91 has an output terminal connected to the inverting input terminal of the comparator 93 and the inverting input terminal of the comparator 94. The positive threshold T POS is connected to the non-inverting input terminal of the comparator 93, and the negative threshold T NEG is connected to the non-inverting input terminal of the comparator 94.

[0110] The present invention eliminates the need for the above-mentioned "uncertain" band between the positive and negative thresholds, while allowing (especially during the time when a large current is flowing) the use of the nominal (unmodified) gate signal of the active phase switch to avoid distortion. Since the uncertain band is not used, the associated comparator is no longer required. Figure 7 A preferred embodiment is shown. Offset duty cycles 95 and 96 are obtained by adding a fixed offset (denoted as δ) to and subtracting it from the duty cycle signal 35, and the offset values are compared with the PWM carrier when generating the gate drive signal. Thus, based on comparing the duty cycle 36 with the PWM carrier 35, the original (nominal) upper and lower gate drive signals G UO and G LO are obtained in a conventional manner. The PWM carrier 35 provides edges 97 and 98 for the original signal. To generate the signal with inserted dead time, the PWM carrier signal 35 is compared with the offset duty cycle as follows. To generate the lower gate drive signal with inserted dead time, the PWM carrier 35 is compared with the positive offset duty cycle 95 (i.e., the commanded duty cycle + δ), and the comparison result is inverted. Thus, the lower gate drive signal with inserted dead time is obtained as the inverted upper gate drive signal obtained from the positive offset duty cycle 95 As Figure 7 shown, the signal has edges 99 and 101 that occur simultaneously with the intersection points of the PWM carrier 35 and the positive offset duty cycle 95. To generate the upper gate drive signal with inserted dead time, the negative offset duty cycle 96 is used. Edges 100 and 102 are shown for this signal, and this signal is also denoted as G UO- since it is generated using a negative offset. Thus, by applying an offset to the duty cycle, a change in the transition time of the gate drive signal providing the dead time interval is obtained.

[0111] Unlike the embodiment where the duty cycle offset Δ is half of the dead time t D and 4, in the present invention, the magnitude of each offset corresponds to the full dead time (i.e., δ = t Figure 3 ), and D)。In other words, based on the slope of the PWM carrier signal, the change in the signal amplitude of the PWM carrier signal 35 between the original PWM duty cycle 36 and the positive offset duty cycle 95 corresponds to a time period equal to the required dead time t D is the same for the negative offset duty cycle 96. Therefore, signals G UO 、G LO 、 and G UO- are all the signals required to adjust the gate signals to provide the required performance.

[0112] Input (IN) signals G UO 、G LO 、 and G UO- into the respective multiplexers (MUX) 105 and 106 in Figure 8 so as to select (SEL) the original or dead time inserted signal according to whether the current sensor of the phase leg detects a positive or negative direction of the current from the corresponding phase leg connection point to the load.

Claims

1. A power converter, comprising: A phase leg including an upper switching device and a lower switching device, wherein a connection point between the upper switching device and the lower switching device is configured to be connected to a load; A current sensor for the phase leg, the current sensor being configured to detect a positive or negative direction of a current from the connection point to the load; And A gate driver connected to the phase leg, the gate driver activating the upper switching device according to an upper gate signal and activating the lower switching device according to a lower gate signal; And A controller that compares a PWM carrier signal with a commanded duty cycle signal to generate a nominal upper timing signal and a nominal lower timing signal, wherein when the controller detects a positive direction of the current, it performs the following operations: Generating a positive offset duty cycle that is a predetermined positive offset larger than the commanded duty cycle; Comparing the PWM carrier signal with the positive offset duty cycle signal to generate a positive offset timing signal; Generating the upper gate signal according to the nominal upper timing signal; And Generating the lower gate signal according to a logical inversion of the positive offset timing signal; And wherein when the controller detects a negative direction of the current, it performs the following operations: Generating a negative offset duty cycle that is a predetermined negative offset smaller than the commanded duty cycle; Comparing the PWM carrier signal with the negative offset duty cycle signal to generate a negative offset timing signal; Generating the upper gate signal according to the negative offset timing signal; And Generating the lower gate signal according to the nominal lower timing signal.

2. The power converter according to claim 1, wherein the PWM carrier signal has a predetermined slope, and wherein the predetermined positive offset divided by the predetermined slope is equal to a predetermined dead time t D , and wherein the predetermined negative offset divided by the predetermined slope is equal to the predetermined dead time t D .

3. The power converter according to claim 2, wherein the PWM carrier signal includes a triangular wave.

4. The power converter according to claim 1, wherein the load includes an electric traction motor of a road vehicle, and wherein the commanded duty cycle corresponds to a required torque from the electric traction motor.

5. A power conversion method, comprising: Generating a PWM upper gate signal and a PWM lower gate signal for driving a phase leg; Detecting a current direction from the phase leg; When the direction is positive, delaying a rising edge of the lower gate signal and advancing a falling edge of the lower gate signal and using the unmodified upper gate signal; And When the direction is negative, delaying a rising edge of the upper gate signal and advancing a falling edge of the upper gate signal and using the unmodified lower gate signal.

6. The method according to claim 5, wherein the steps of advancing and delaying the edges of the lower gate signal include: Comparing a PWM carrier signal with a commanded duty cycle signal to generate a nominal upper timing signal and a nominal lower timing signal; Generating a positive offset duty cycle that is a predetermined positive offset larger than the commanded duty cycle; Comparing the PWM carrier signal with the positive offset duty cycle signal to generate a positive offset timing signal; Generating the upper gate signal according to the nominal upper timing signal; And Generating the lower gate signal according to a logical inversion of the positive offset timing signal.

7. The method according to claim 6, wherein the step of advancing and delaying the edge of the upper gate signal comprises: generating a negative offset duty cycle that is a predetermined negative offset smaller than the duty cycle of the command; comparing the PWM carrier signal with the negative offset duty cycle signal to generate a negative offset timing signal; generating the lower gate signal according to the nominal lower timing signal; and generating the upper gate signal according to the negative offset timing signal.

8. The method according to claim 7, wherein the PWM carrier signal has a predetermined slope, and wherein the predetermined positive offset divided by the predetermined slope is equal to a predetermined dead time t D , and wherein the predetermined negative offset divided by the predetermined slope is equal to the predetermined dead time t D .

9. An electric drive for a transport vehicle, comprising: a multiphase electric traction motor; a DC link configured to receive a DC supply voltage; a plurality of phase legs connected between the DC link and the multiphase electric traction motor, wherein each phase leg comprises: a corresponding upper switching device and a corresponding lower switching device, wherein a connection point between the upper switching device and the lower switching device is connected to the multiphase electric traction motor; a current sensor for the phase leg, the current sensor being configured to detect a positive or negative direction of a current from the connection point to the multiphase electric traction motor; and a gate driver connected to the phase leg, the gate driver activating the upper switching device according to an upper gate signal and activating the lower switching device according to a lower gate signal; and a controller that compares a PWM carrier signal with a commanded duty cycle signal to generate a corresponding nominal upper timing signal and a corresponding nominal lower timing signal, wherein when the controller detects a positive direction of a corresponding current, it performs the following operations: generating a corresponding positive offset duty cycle that is a predetermined positive offset larger than the duty cycle of the command; comparing the PWM carrier signal with the corresponding positive offset duty cycle signal to generate a corresponding positive offset timing signal; generating the corresponding upper gate signal according to the corresponding nominal upper timing signal; and generating the corresponding lower gate signal according to a logical inversion of the corresponding positive offset timing signal; and wherein when the controller detects a negative direction of a corresponding current, it performs the following operations: generating a corresponding negative offset duty cycle that is a predetermined negative offset smaller than the duty cycle of the command; comparing the PWM carrier signal with the corresponding negative offset duty cycle signal to generate a corresponding negative offset timing signal; generating the corresponding upper gate signal according to the corresponding negative offset timing signal; and generating the corresponding lower gate signal according to the corresponding nominal lower timing signal.

10. The electric drive according to claim 9, wherein the PWM carrier signal has a predetermined slope, and wherein the predetermined positive offset divided by the predetermined slope is equal to a predetermined dead time t D , and wherein the predetermined negative offset divided by the predetermined slope is equal to the predetermined dead time t D .

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