Metal Oxide Film and Method for Forming the Same

Abstract

Provided is a metal oxide film that includes a crystalline part and has high stability of physical properties. The size of the crystalline part is less than or equal to 10 nm, and thus, when the measurement region is greater than or equal to [specific value 1] and less than or equal to [specific value 2], circumferential spots are observed in the nanobeam electron diffraction pattern of the cross-section of the metal oxide film.

Description

[0001] This application is a divisional application of a patent application with the application number "201380058422.8", the invention title "Metal Oxide Film and Method for Forming Metal Oxide Film", and the filing date "October 30, 2013". Technical Field

[0002] One aspect of the present invention relates to, for example, a semiconductor device, a display device, a light-emitting device, a driving method thereof, or a manufacturing method thereof. One aspect of the present invention particularly relates to a metal oxide film and a method for forming a metal oxide film. Further, one aspect of the present invention relates to a semiconductor device including a metal oxide film.

[0003] Note that in this specification, semiconductor devices and the like refer to all devices that can function by utilizing semiconductor characteristics. For example, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. Background Art

[0004] Techniques for forming transistors using semiconductor thin films formed on substrates having insulating surfaces have attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also referred to as display devices). As semiconductor films applicable to transistors, silicon-based semiconductor materials are widely known; in addition, as other materials, metal oxides (oxide semiconductors) that exhibit semiconductor characteristics have attracted attention.

[0005] For example, Patent Document 1 discloses a technique for manufacturing a transistor using an amorphous oxide containing In, Zn, Ga, Sn, etc. as an oxide semiconductor.

[0006] [References]

[0007] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-165529 Summary of the Invention

[0009] One object of one aspect of the present invention is to provide a metal oxide film including a crystal part.

[0010] Another object of one aspect of the present invention is to provide a metal oxide film having high physical property stability.

[0011] Another object of one aspect of the present invention is to provide a highly reliable semiconductor device including the above metal oxide film.

[0012] Another object of one aspect of the present invention is to provide a novel semiconductor device. Note that the description of these objects does not preclude the existence of other objects. One aspect of the present invention does not necessarily achieve all of the above objects. Objects other than these can be apparent from the description in the specification, drawings, claims, etc., and can be extracted from the said description.

[0013] One aspect of the disclosed invention is a metal oxide film that includes minute crystal portions, where the periodicity of atomic arrangement is not observable macroscopically, or the long-range order of atomic arrangement is not observable macroscopically. The metal oxide film of one aspect of the present invention includes a region that shows a halo pattern indicating an amorphous state in a selected area electron diffraction pattern in a plane. On the other hand, in a nano-beam electron diffraction pattern of a cross section, a halo pattern is not observable, but spots without directionality are observable, and these spots are different from the spots having the regularity of crystal portions showing a specific plane orientation. Specifically, one aspect of the present invention is, for example, a metal oxide film having the following structure.

[0014] One aspect of the present invention is a metal oxide film that includes a region where a plurality of spots are observed to be circularly distributed in a nano-beam electron diffraction pattern of a cross section.

[0015] Another aspect of the present invention is a metal oxide film that includes a region where a plurality of spots are observed to be circularly distributed in a nano-beam electron diffraction pattern of a cross section and a halo pattern is observed in a selected area electron diffraction pattern in a plane.

[0016] In the above, the measurement region of the selected area electron diffraction is preferably greater than or equal to

[0017] In the above, the measurement region of the nano-beam electron diffraction is preferably greater than or equal to and less than or equal to Note that by irradiating an electron beam with a beam diameter converged to a nano-beam electron diffraction pattern with a measurement region greater than or equal to and less than or equal to can be obtained.

[0018] In the above, the nano-beam electron diffraction pattern is preferably a nano-beam electron diffraction pattern of a cross section of a sample thinned to be greater than 10 nm and less than or equal to 50 nm.

[0019] In the above, the metal oxide film preferably includes crystal portions, and the size of the crystal portions is preferably less than or equal to 10 nm. Alternatively, the size of the crystal portions is preferably greater than or equal to 1 nm and less than or equal to 10 nm.

[0020] One aspect of the present invention is a metal oxide film including a crystalline portion, and the crystalline portion includes a region having the following characteristics: in nano-beam electron diffraction of a measurement region having a size greater than or equal to and less than or equal to , a plurality of spots distributed in a circular pattern are observed in a cross-section of the metal oxide film thinned to a thickness greater than 10 nm and less than or equal to 50 nm, and spots having a regularity showing a crystalline portion with a specific plane orientation are observed in a cross-section of the metal oxide film thinned to a thickness less than or equal to 10 nm.

[0021] Any one of the above metal oxide films preferably contains at least indium, gallium, or zinc.

[0022] Another aspect of the present invention is a method for forming a metal oxide film, and the metal oxide film includes a region in which a plurality of spots distributed in a circular pattern are observed in a nano-beam electron diffraction pattern of a cross-section. The metal oxide film is formed by a sputtering method using an oxide target in an atmosphere at room temperature and containing oxygen.

[0023] In the method for forming the above metal oxide film, the partial pressure of oxygen in the atmosphere is preferably greater than or equal to 33%.

[0024] One aspect of the present invention can provide a metal oxide film including a crystalline portion.

[0025] Furthermore, one aspect of the present invention can provide a metal oxide film with high stability of physical properties. Moreover, by using the metal oxide film in a semiconductor device, the semiconductor device can have high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1A is a cross-sectional TEM image of a metal oxide film according to one aspect of the present invention, Figures 1B to 1D is its nano-beam electron diffraction pattern;

[0027] Figure 2A is a plan-view TEM image of a metal oxide film according to one aspect of the present invention, Figure 2B is its selected-area electron diffraction pattern;

[0028] Figures 3A to 3C is a conceptual diagram of an electron diffraction intensity distribution;

[0029] Figure 4 is a nano-beam electron diffraction pattern of a quartz glass substrate;

[0030] Figure 5A and Figure 5B are cross-sectional TEM images of a metal oxide film according to one aspect of the present invention;

[0031] Figure 6Shows the results of X-ray diffraction analysis of a metal oxide film according to one embodiment of the present invention;

[0032] Figure 7 Is the nanobeam electron diffraction pattern of a metal oxide film according to one embodiment of the present invention;

[0033] Figure 8 Is the nanobeam electron diffraction pattern of a metal oxide film according to one embodiment of the present invention;

[0034] Figures 9A to 9C Shows an example of the structure of a transistor in one embodiment;

[0035] Figures 10A to 10D Shows an example of the formation method of a transistor in one embodiment;

[0036] Figures 11A to 11C Shows an example of the structure of a transistor in one embodiment;

[0037] Figures 12A to 12C Shows the structure of a display panel in one embodiment;

[0038] Figure 13 Is a block diagram of an electronic device in one embodiment;

[0039] Figures 14A to 14D Is an external view of an electronic device in one embodiment;

[0040] Figure 15A Is a cross-sectional TEM image of a metal oxide film according to one embodiment of the present invention, Figures 15B to 15E Is its nanobeam electron diffraction pattern;

[0041] Figure 16 Is a conceptual diagram showing a method of thinning a sample by ion milling;

[0042] Figures 17A to 17D Is the nanobeam electron diffraction pattern of a metal oxide film according to one embodiment of the present invention;

[0043] Figure 18A And Figure 18B Shows the SIMS analysis results of a metal oxide film in a comparative example and one embodiment;

[0044] Figures 19A to 19D Shows the results of X-ray diffraction analysis of a sample prepared by a liquid phase method;

[0045] Figures 20A to 20C Is a cross-sectional TEM image of a sample in a comparative example;

[0046] Figures 21A to 21C Is the nanobeam electron diffraction pattern of a sample in a comparative example, Figure 21DThe nano-beam electron diffraction pattern of the metal oxide film according to one embodiment of the present invention;

[0047] Figure 22 Showing the crystal structure of the oxide semiconductor layer used for calculation;

[0048] Figures 23A to 23D Showing the calculation results of the effect of hydrogen addition on the crystal state;

[0049] Figures 24A to 24D Showing the measurement results of the bond energy in the metal oxide film according to one embodiment of the present invention and the samples in the comparative examples by XPS. Detailed Description of the Invention

[0050] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the following description, and it is easily understood by those skilled in the art that its embodiments and viewpoints can be changed into various forms. Therefore, the present invention should not be construed as being limited only to the contents of the embodiments shown below.

[0051] Embodiment 1

[0052] In this embodiment, with reference to Figures 1A to 1D , Figure 2A and Figure 2B , Figures 3A to 3C , Figure 4 , Figure 5A and Figure 5B , Figure 6 , Figure 7 , Figures 15A to 15E , Figure 16 , Figures 17A to 17D , Figure 18A and Figure 18B , Figures 19A to 19D , Figures 20A to 20C , and Figures 21A to 21D , a metal oxide film according to one embodiment of the present invention will be described.

[0053] <Crystal part in the metal oxide film>

[0054] The metal oxide film of this embodiment includes minute crystal parts, in which the periodicity of atomic arrangement cannot be observed macroscopically, or the long-range order of atomic arrangement cannot be observed macroscopically. Therefore, when the measurement area is larger (wider) than the crystal parts included in the above metal oxide film, it may not be possible to observe spots showing the regularity of the crystal state by electron diffraction.

[0055] <<Cross-sectional TEM image and nano-beam electron diffraction pattern>>

[0056] Figure 1Ais a cross-sectional transmission electron microscope (TEM) image of the metal oxide film of the present embodiment. Figure 1B , Figure 1C and Figure 1D are electron diffraction patterns observed at points 1, 2, and 3 in Figure 1A by nano-beam electron diffraction, respectively.

[0057] As an example of the metal oxide film, a 50-nm-thick In-Ga-Zn-based oxide film was formed on a quartz glass substrate. The metal oxide film was formed under the following conditions: using an oxide target with an atomic ratio of In, Ga, and Zn of 1:1:1; using an oxygen atmosphere (flow rate of 45 sccm); a pressure of 0.4 Pa; a DC power supply of 0.5 kW; and a substrate temperature of room temperature. Then, the formed metal oxide film was thinned to approximately 50 nm (e.g., 40 nm ± 10 nm), and the cross-sectional TEM image and nano-beam electron diffraction pattern were observed.

[0058] The cross-sectional TEM image of the metal oxide film was observed using a transmission electron microscope (“H-9000NAR” manufactured by Hitacti High-Technologies Corporation) at an acceleration voltage of 300 kV and a magnification of 2,000,000 times. The nano-beam electron diffraction was performed using a transmission electron microscope (“HF-2000” manufactured by Hitachi High-Technologies Corporation) at an acceleration voltage of 200 kV and a beam diameter of approximately . Note that the measurement area of the nano-beam electron diffraction is greater than or equal to and less than or equal to

[0059] As Figure 1B shown, in the nano-beam electron diffraction of the metal oxide film of the present embodiment, circular spots (light points) were observed. This means that in the case of the metal oxide film of the present embodiment, a plurality of spots distributed in a circular shape were observed. Moreover, it can be said that a plurality of concentric circles were formed by the plurality of spots distributed in a circular shape.

[0060] Furthermore, in Figure 1C showing the central portion of the metal oxide film in the thickness direction and in Figure 1D showing the vicinity of the interface with the quartz glass substrate, a plurality of spots distributed in a circular shape were similarly observed as in Figure 1B . In Figure 1C , the radius of the first circle (distance from the main spot to the periphery) was in the range of 3.88 / nm to 4.93 / nm, or when converted to the planar spacing, in the range of 0.203 nm to 0.257 nm.

[0061] In addition to showing the halo pattern of the amorphous state, multiple spots are observed in the Figures 1B to 1D shown nano-beam electron diffraction pattern. This confirms that the metal oxide film of the present embodiment contains a crystalline part. However, in the Figures 1B to 1D shown nano-beam electron diffraction pattern, spots are observed that do not have the regularity of showing a crystalline part with a specific plane orientation and do not have a directionality. Thus, it can be considered that the metal oxide film of the present embodiment contains multiple crystalline parts with irregular surface orientations and different sizes from each other.

[0062] Figure 5A and Figure 5B are Figure 1A partial enlarged views of the cross-sectional TEM image of Figure 5A It is a cross-sectional TEM image of the vicinity of point 1 (the surface of the metal oxide) in Figure 1A observed at an observation magnification of 8,000,000 times. Figure 5B It is a cross-sectional TEM image of the vicinity of point 2 (the central part in the thickness direction of the metal oxide film) in Figure 1A observed at an observation magnification of 8,000,000 times.

[0063] In the Figure 5A and Figure 5B shown cross-sectional TEM images of the metal oxide film of the present embodiment, the crystal structure cannot be clearly observed.

[0064] <<Planar TEM Image and Selected Area Electron Diffraction Pattern>>

[0065] Figure 2A is the planar TEM image of the metal oxide film of the present embodiment. Figure 2B It shows the electron diffraction pattern of the region surrounded by the circle in Figure 2A observed by selected area electron diffraction.

[0066] As an example of the metal oxide film, a 50-nm-thick In-Ga-Zn-based oxide film is formed on a quartz glass substrate. The metal oxide film is formed under the following conditions: using an oxide target with an atomic ratio of In, Ga, and Zn of 1:1:1; using an oxygen atmosphere (flow rate of 45 sccm); pressure of 0.4 Pa; DC power supply of 0.5 kW; and substrate temperature of room temperature. Then, the formed metal oxide film is thinned to approximately 50 nm (for example, 40 nm ± 10 nm), and the planar TEM image and selected area electron diffraction pattern are observed.

[0067] Obtained using a transmission electron microscope (“H-9000NAR” manufactured by Hitachi High-Technologies Corporation) at an acceleration voltage of 300 kV Figure 2A and Figure 2B the images shown. To obtain the images in Figure 2A , the plane of the metal oxide film was observed at an observation magnification of 500,000 times. Figure 2B Shows the diffraction results of the region in the circle in Figure 2A obtained by selected area electron diffraction. Figure 2B The pattern in was obtained by electron diffraction with a selected area of

[0068] As shown in Figure 2B , in the case of the metal oxide film of the present embodiment, in the electron diffraction pattern observed by selected area electron diffraction where the measurement area is wider than that of nano-beam electron diffraction, multiple spots observed by nano-beam electron diffraction are not observed, but a halo pattern is observed. Therefore, the metal oxide film of the present embodiment can be regarded as a metal oxide film containing microcrystalline portions, where the periodicity of atomic arrangement is not observed macroscopically (for example, when the measurement area is greater than or equal to ), or long-range order of atomic arrangement is not observed macroscopically.

[0069] <<Conceptual diagram of electron diffraction intensity distribution>>

[0070] Figures 3A to 3C Conceptually shows Figures 1B to 1D and Figure 2A and Figure 2B the diffraction intensity distributions in the electron diffraction patterns in Figure 3A is Figures 1B to 1D a conceptual diagram of the diffraction intensity distribution in the nano-beam electron diffraction pattern in Figure 3B is Figure 2B a conceptual diagram of the diffraction intensity distribution in the selected area electron diffraction pattern in Figure 3C is a conceptual diagram of the diffraction intensity distribution in the electron diffraction pattern of an ideal polycrystalline structure.

[0071] In Figures 3A to 3C , the vertical axis represents the electron diffraction intensity (in arbitrary units) and the horizontal axis represents the distance from the main spot.

[0072] In Figure 3CIn the ideal polycrystalline structure shown, peaks are observed at a specific distance from the main spot based on the plane spacing (d value) of the plane oriented by the crystal part. In this case, in the electron diffraction pattern, a ring with a small line width is clearly observed at a specific distance from the main spot.

[0073] On the other hand, as Figures 1B to 1D shown, the line width of the circumferential region formed by a plurality of spots observed in the nanobeam electron diffraction pattern of the metal oxide film of the present embodiment is relatively large. Thus, as Figure 3A shown, its electron beam diffraction intensity is discretely distributed and includes a plurality of regions (peak regions) where peaks are distributed. Note that a few spots are observed between the plurality of circumferential regions in the nanobeam electron diffraction pattern. This means that, as Figure 3A shown, diffraction peaks exist between two peak regions.

[0074] On the other hand, as Figure 3B shown, the electron beam diffraction intensity distribution in the selected area electron diffraction pattern of the metal oxide film of the present embodiment is continuous. Because Figure 3B it can be approximated to the result obtained by observing the Figure 3A shown electron beam diffraction intensity distribution in a wide range, it can be considered that Figure 3A the peak regions in are integrated and a continuous intensity distribution is obtained.

[0075] Figures 3A to 3C It is shown that the metal oxide film of the present embodiment includes a plurality of crystal parts, whose surface orientations are irregular and whose sizes are different from each other, and the crystal parts are so small that spots are not observed in the selected area electron diffraction pattern.

[0076] In the metal oxide film in which a plurality of spots are observed in the nanobeam electron diffraction pattern as Figures 1B to 1D shown, it is thinned to about 50 nm. Further, since the diameter of the electron beam converges to so the measurement area is greater than or equal to 5 nm and less than or equal to 10 nm. Thus, it can be considered that the size of the crystal part included in the metal oxide film of the present embodiment is at least less than or equal to 50 nm, for example, less than or equal to 10 nm or less than or equal to 5 nm.

[0077] <<Nanobeam Electron Diffraction Pattern of Ultrathin Sample>>

[0078] When the size of the crystal part in the metal oxide film included in this embodiment is less than or equal to 10 nm or less than or equal to 5 nm, the measurement region in the depth direction is larger than the size of the crystal part in the sample where the metal oxide film is thinned to about 50 nm; thus, multiple crystal parts are sometimes observed in the measurement region. Therefore, a metal oxide film thinned to less than or equal to 10 nm is formed, and its cross-section is observed by nano-beam electron diffraction.

[0079] The manufacturing method of the sample is shown below. A 50-nm-thick In-Ga-Zn-based oxide film is formed on a quartz glass substrate. This film is formed under the following conditions: using an oxide target with an atomic ratio of In, Ga, and Zn of 1:1:1; using an oxygen atmosphere (flow rate of 45 sccm); pressure of 0.4 Pa; DC power supply of 0.5 kW; and substrate temperature at room temperature. After forming the metal oxide film, the first heat treatment is performed at 450 °C for 1 hour in a nitrogen atmosphere, and the second heat treatment is performed at 450 °C for 1 hour in an atmosphere containing nitrogen and oxygen.

[0080] The metal oxide film after the second heat treatment is further thinned by the ion milling method using Ar ions. First, the quartz glass substrate on which the metal oxide film is formed is attached to a virtual substrate for strengthening. Then, the film is thinned to about 50 μm by cutting and grinding. After that, as Figure 16 shown, argon ions are irradiated at an oblique angle (about 3°) to the metal oxide film 204 provided on the quartz glass substrate 200 and the virtual substrate 202 to perform ion milling, thereby forming a region 210a thinned to about 50 nm (40 nm ± 10 nm), and a region 210b thinned to less than or equal to 10 nm, for example, 5 nm to 10 nm. Then, the cross-sections of the respective regions are observed.

[0081] Figure 15A is a cross-section TEM image of the sample thinned to about 50 nm corresponding to region 210a. Figures 15B to 15E Shows the electron diffraction pattern observed by nano-beam electron diffraction of the cross-section as Figure 15A shown. Figure 15B Shows the electron diffraction pattern observed using an electron beam whose beam diameter is converged to . Figure 15C Shows the electron diffraction pattern observed using an electron beam whose beam diameter is converged to . Figure 15D Shows the electron diffraction pattern observed using an electron beam whose beam diameter is converged to . Figure 15E Shows the electron diffraction pattern observed using an electron beam whose beam diameter is converged to .

[0082] As Figure 15B shown, similar to Figures 1B to 1D , multiple spots (light points) distributed in a circular pattern were also observed in the metal oxide film after performing heat treatment. Further, as Figures 15C to 15E shown, when the diameter of the electron beam was increased to observe a wider measurement area, the multiple spots gradually became blurred.

[0083] Figures 17A to 17D shows nanobeam electron diffraction patterns at four given points in a sample thinned to less than or equal to 10 nm corresponding to region 210b. The nanobeam electron diffraction patterns were observed using an electron beam whose beam diameter was converged to .

[0084] In Figure 17A and Figure 17B , spots having a regularity showing crystal parts oriented in a specific plane were observed. This means that the metal oxide film of the present embodiment indeed contains crystal parts. On the other hand, in Figure 17C and Figure 17D , multiple spots (light points) distributed in a circular pattern were observed.

[0085] As described above, the size of the crystal parts contained in the metal oxide film of the present embodiment is minute, at least less than or equal to 50 nm, for example, less than or equal to 10 nm or less than or equal to 5 nm. Therefore, in the case where the sample is thinned to less than or equal to 10 nm and the diameter of the electron beam is converged to so that the measurement area is less than, for example, the size of one crystal part, spots having a regularity showing crystal parts oriented in a specific plane can be observed according to the measurement area. In the case where multiple crystal parts are included in the observation area, the electron beam passing through the crystal parts further irradiates other crystal parts located in the depth direction, which can result in the observation of multiple nanobeam electron diffraction patterns.

[0086] <<Nanobeam Electron Diffraction Pattern of Quartz Substrate>>

[0087] Figure 4 shows the nanobeam electron diffraction pattern of a quartz glass substrate. The measurement conditions are the same as those for the oxide semiconductor film shown in Figures 1B to 1D .

[0088] As Figure 4 shown, in the case of a quartz glass substrate having an amorphous structure, a halo pattern in which specific spots were not obtained by diffraction and whose brightness gradually changed from the main spot was observed. Therefore, even when electron diffraction is performed on a minute area, circular spots as observed in the metal oxide film of the present embodiment cannot be observed in a film having an amorphous structure. Thus, it was confirmed that in Figures 1B to 1DThe circular spots observed are characteristic of the metal oxide film of the present embodiment.

[0089] <<Electron diffraction pattern after continuous irradiation with a nano-beam>>

[0090] Figure 8 Shows the electron diffraction pattern observed one minute after irradiating point 2 in Figure 1A with an electron beam whose beam diameter is converged to approximately .

[0091] Similar to the electron diffraction pattern shown in Figure 1C , a plurality of spots distributed in a circular pattern are observed in the electron diffraction pattern shown in Figure 8 , and there is not much difference between the electron diffraction patterns in Figure 1C and Figure 8 . This means that the crystal part confirmed by Figure 1C is formed when the metal oxide film of the present embodiment is formed, and is not formed by the irradiation of the converged electron beam.

[0092] <<Analysis by X-ray diffraction>>

[0093] Samples of the metal oxide film of the present embodiment formed on a quartz glass substrate used in Figures 1A to 1D and Figure 2A and Figure 2B are analyzed by X-ray diffraction (XRD). Figure 6 Shows the XRD spectrum measured by the out-of-plane method.

[0094] In Figure 6 , the vertical axis represents the X-ray diffraction intensity (arbitrary unit) and the horizontal axis represents the diffraction angle 2θ (degrees). Note that this XRD spectrum is measured using an X-ray diffractometer D8 ADVANCE manufactured by Bruker AXS.

[0095] As Figure 6 shows, the peak corresponding to quartz appears at approximately 2θ = 20° to 23°; however, no peak corresponding to the crystal part contained in the metal oxide film is confirmed.

[0096] In Figure 6 , the results show that the crystal part contained in the metal oxide film of the present embodiment is minute.

[0097] Based on the above results, it can be considered that the metal oxide film of the present embodiment is a film in which crystal parts with irregular surface orientations are aggregated.

[0098] In addition, it can be considered that the size of the crystal part included in the metal oxide film of the present embodiment is, for example, less than or equal to 10 nm or less than or equal to 5 nm. The metal oxide film of the present embodiment includes, for example, crystal parts (nanocrystals (nc)) having a size greater than or equal to 1 nm and less than or equal to 10 nm.

[0099] <Method for forming a metal oxide film>

[0100] A method for forming the metal oxide film of the present embodiment will be described below. As described above, the metal oxide film of the present embodiment is formed by a sputtering method in an atmosphere containing oxygen at room temperature. By using an atmosphere containing oxygen, oxygen vacancies in the metal oxide film can be reduced, and a film including crystal parts can be formed.

[0101] <<Reduction of oxygen vacancies>>

[0102] The reduction of oxygen vacancies in the metal oxide film of the present embodiment allows the formation of a film having stable physical properties. In particular, when a semiconductor device is formed using an oxide semiconductor film as the metal oxide film of the present embodiment, oxygen vacancies in the oxide semiconductor film cause the generation of carriers; as a result, the electrical characteristics of the semiconductor device change. Therefore, a semiconductor device formed using an oxide semiconductor film in which oxygen vacancies are reduced can have high reliability.

[0103] Note that it is preferable to increase the oxygen partial pressure in the deposition atmosphere because oxygen vacancies in the metal oxide film of the present embodiment can be further reduced. For example, the oxygen partial pressure in the deposition atmosphere is preferably greater than or equal to 33%.

[0104] Figure 7 The nanobeam electron diffraction pattern of the metal oxide film of the present embodiment formed at an oxygen partial pressure of 33% is shown. Except for using a mixed atmosphere of argon and oxygen (the flow rates of Ar and O2 are 30 sccm and 15 sccm, respectively) as the deposition atmosphere, Figure 7 the metal oxide film of the present embodiment shown in Figures 1A to 1D is formed under conditions similar to those of the metal oxide film shown in Figures 1B to 1D Nanobeam electron diffraction is performed in a manner similar to that described for

[0105] In the metal oxide film of the present embodiment formed at an oxygen partial pressure of 33%, spots arranged circumferentially are also observed in the Figure 7 shown nanobeam electron diffraction pattern. This confirms the formation of a metal oxide film including crystal parts.

[0106] <<Deposition by sputtering method>>

[0107] The oxide target that can be used to form the metal oxide film of the present embodiment is not limited to In-Ga-Zn-based oxides; for example, In-M-Zn-based oxides (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf) can be used.

[0108] The metal oxide film of the present embodiment including a crystal part is preferably formed using a sputtering target including a polycrystalline oxide including a plurality of crystal grains. The reason is as follows. When the sputtering target includes a plurality of crystal grains and has an interface where the crystal grains may crack due to weak bonding between the plurality of crystal grains, when ions collide with the sputtering target, the crystal grains crack along the interface, and thus plate-like sputtering particles can sometimes be obtained. The obtained plate-like sputtering particles are deposited on the substrate; thereby, a metal oxide film including a nanocrystal region can sometimes be formed. Note that the above mechanism for forming the metal oxide film of the present embodiment is an investigation.

[0109] The metal oxide film of the above present embodiment includes a plurality of crystal parts, having irregular surface orientations and different sizes from each other, and the crystal parts are minute, so spots cannot be observed in the selected area electron diffraction pattern.

[0110] Furthermore, the metal oxide film of the present embodiment includes a region having a crystal part and has stable physical properties. Therefore, by using the metal oxide film of the present embodiment in a semiconductor device, the semiconductor device can have high reliability.

[0111] (Comparative Example)

[0112] In this comparative example, the crystallinity of the metal oxide film formed by the liquid phase method will be described with reference to the drawings.

[0113] Hereinafter, the method for forming the metal oxide film of this comparative example will be described.

[0114] First, In2O3 (5 wt%), Ga2O3 (3 wt%), ZnO (5 wt%) and a coating agent are mixed so that the mixture contains In, Ga, and Zn in a composition ratio of 1:1:1, and the mixture is coated on a glass substrate by a spin coating method. The conditions of the spin coating method are as follows: using a spinner; and gradually changing the rotation rate from 900 rpm to 2000 rpm.

[0115] Then, a first heat treatment is performed at 150 °C for two minutes using a hot plate in an atmospheric atmosphere.

[0116] Next, a second heat treatment is performed at 450 °C for one hour in an atmospheric atmosphere. The bonding state of the metal oxide film (formed by the liquid phase method) of this comparative example that has been subjected to the second heat treatment is analyzed by X-ray photoelectron spectroscopy (XPS), and Figure 7The bonding state of the metal oxide film of the present embodiment (formed by sputtering) formed under the same conditions as the metal oxide film shown in Figures 24A to 24D shows the analysis results.

[0117] XPS analysis was performed using Quantera SXM manufactured by Physical Electronics, Inc. as the analysis equipment. Figures 24A to 24D shows the 3d(5 / 2) orbitals of In corresponding to each metal oxide film (refer to Figure 24A ), the 3d orbitals of Ga (refer to Figure 24B ), the 3p orbitals of Zn (refer to Figure 24C ), and the spectra in the region of the 1s orbitals of O (refer to Figure 24D ). Figures 24A to 24D The solid line in Figures 24A to 24D corresponds to the analysis results of the In-Ga-Zn oxide film of this comparative example formed by the liquid phase method.

[0118] In Figures 24A to 24D , although there are slight differences between the binding energies, the metal oxide film of this comparative example formed by the liquid phase method and the metal oxide film of the present embodiment formed by sputtering have substantially the same spectral shape. Therefore, the metal oxide film of this comparative example formed by the liquid phase method was determined to be an In-Ga-Zn oxide film.

[0119] Next, the samples of the comparative example formed were analyzed by XRD. Figures 19A to 19D shows the analysis results using the out-of-plane method.

[0120] In the XRD analysis, samples of In-Ga-Zn oxide films that were subjected to a second heat treatment at 350 °C, 450 °C, or 550 °C for one hour in an air atmosphere after the first heat treatment were used.

[0121] In Figures 19A to 19D , the vertical axis represents the X-ray diffraction intensity (arbitrary unit), and the horizontal axis represents the diffraction angle 2θ (degrees). XRD measurements were performed using an X-ray diffractometer D8 ADVANCE manufactured by Bruker AXS.

[0122] Figure 19A shows the measurement results of the samples of this comparative example formed by the liquid phase method. The XRD pattern of the sample without heat treatment is the pattern indicated by "as-depo". Note that Figures 19B to 19DShows the measurement results of indium oxide films, gallium oxide films, and zinc oxide films formed by a liquid phase method and heat-treated at 350 °C, 450 °C, and 550 °C for one hour in an atmospheric atmosphere.

[0123] As Figures 19A to 19D shown, peaks corresponding to the In2O3 crystal peaks were confirmed in the XRD pattern of the indium oxide film after the heat treatment. In addition, peaks corresponding to the ZnO crystal peaks were confirmed in the XRD pattern of the zinc oxide film after the heat treatment. On the other hand, in the samples of this comparative example that were heat-treated at any of the temperatures, unlike the indium oxide film and the zinc oxide film, no crystal peaks were confirmed.

[0124] Then, the film density of each sample heat-treated at 450 °C for one hour in an atmospheric atmosphere was measured using X-ray reflectometry (XRR).

[0125] Note that XRR is a measurement method for measuring the density of a deposited thin film, in which X-rays are incident on the measurement sample to measure changes in the critical angle and amplitude waveform of the incident X-rays, and theoretical analysis is performed using the above critical angle and amplitude waveform.

[0126] Table 1 shows the measured film density.

[0127] [Table 1]

[0128]

[0129] As shown in Table 1, the film formed by the liquid phase method has a very low density compared to the theoretical value calculated based on its single crystal structure. Note that since the film formed by the liquid phase method has a large roughness, it is not easy to measure the film density with high accuracy.

[0130] Next, SIMS was used to measure the concentration of impurities contained in the metal oxide film of this comparative example and the metal oxide film of this embodiment.

[0131] Figure 18A Shows the hydrogen ( 1 H) concentration distribution in the metal oxide film of the comparative example and the metal oxide film of this embodiment. Figure 18B Shows the carbon ( 12 C) concentration distribution in the metal oxide film of the comparative example and the metal oxide film of this embodiment. In Figure 18A and Figure 18B , the horizontal axis represents the depth (nm), and the vertical axis represents the concentration of hydrogen or oxygen (atoms / cm 3 ).

[0132] Samples formed by the liquid phase method under conditions similar to the above conditions were used as Figure 18A andFigure 18B Metal oxide films of comparative examples. Note that before spin coating, the material was filtered using a filter membrane (0.2 μm). In addition, a second heat treatment was performed at 450 °C, 500 °C, or 550 °C for one hour in an atmospheric atmosphere. Other conditions were the same as those for the above metal oxide films formed by the liquid phase method. Samples formed by sputtering under the same conditions as the metal oxide films shown in Figure 7 were used for the metal oxide films of this embodiment.

[0133] As Figure 18A and Figure 18B shown, compared with the metal oxide films of this embodiment, a large amount of hydrogen and carbon uniformly exist in the metal oxide films of the comparative examples.

[0134] Figure 18B As shown in

[0135] the carbon concentration of the metal oxide films of this embodiment shown in 22 (atoms / cm 3 ) gradually decreases from the surface to the inside of the film. This indicates that the carbon in the metal oxide films of this embodiment mainly comes from surface contamination. 21 (atoms / cm 3 ) or higher density of hydrogen, and up to 4 × 10

[0136] Next, in Figures 20A to 20C a cross-sectional TEM image of the sample of this comparative example that was subjected to a second heat treatment at 450 °C for one hour in an atmospheric atmosphere is shown. This cross-section was observed using a transmission electron microscope ("H-9000NAR" manufactured by Hitachi High-Technologies Corporation) at an acceleration voltage of 300 kV. Figure 20A is a cross-sectional image at a magnification of 500,000. Figure 20B is a cross-sectional image at a magnification of 2,000,000. Figure 20C is a cross-sectional observation image at a magnification of 8,000,000.

[0137] As Figure 20A and Figure 20B shown, most of the sample of this comparative example formed by the liquid phase method is occupied by amorphous regions. In addition, a gray-scale gradient (change in brightness) due to the difference in film density can be seen.

[0138] In Figure 20CIn region a in the cross-sectional TEM image, the brightness is high, which means that region a has a low film density. In Figure 20C In region b in the cross-sectional TEM image, the brightness is low, which means that region b has a high density.

[0139] Observation by nano-beam electron diffraction Figure 20C Regions a and b in Figures 21A to 21C Show the nano-beam electron diffraction pattern.

[0140] Using a transmission electron microscope ("HF-2000" manufactured by Hitachi High-Technologies Corporation) with an acceleration voltage of 200 kV and a beam diameter of approximately This nano-beam electron diffraction was performed. Figure 21A Show Figure 20C The nano-beam electron diffraction pattern of region a in Figure 21B And Figure 21C Show Figure 20C The nano-beam electron diffraction patterns of two different parts (denoted as b1 and b2) in region b in

[0141] Figure 21D Show the nano-beam electron diffraction pattern of the metal oxide film of one embodiment of the present invention, which was formed and observed under the same conditions as the Figure 7 Shown metal oxide film.

[0142] As Figures 21A to 21C Shown, in each region of the metal oxide film of this comparative example formed by the liquid phase method, a pattern different from the Figure 21D Circular spots (light spots) observed in the metal oxide film of one embodiment of the present invention shown.

[0143] Figure 21A The nano-beam electron diffraction pattern of the region a shown is similar to the halo pattern presenting an amorphous state. The existence of a region with such low crystallinity may be due to the low film density and high impurity concentration.

[0144] As Figure 21B And Figure 21C Shown, in the nano-beam electron diffraction pattern of region b, spots (denoted as 1 to 3 in Figure 21B And Figure 21C Shown) with regularity presenting crystal parts oriented in a specific plane are observed. The analysis results of the diffraction patterns of these spots are shown in Table 2 below.

[0145] [Table 2]

[0146]

[0147] According to Table 2, from Figure 21B or Figure 21C The measured d values estimated from the spots in are almost the same as the theoretical d values of multiple plane orientations in InGaZnO4, which means that the In-Ga-Zn oxide film of this comparative example formed by the liquid phase method contains crystal regions derived from InZnGaO4.

[0148] Therefore, although impurities are present, regions containing a periodic atomic arrangement derived from InZnGaO4 and regions with extremely low crystallinity and close to the amorphous state coexist in the InZnGaO4 film formed by the liquid phase method.

[0149] Next, the effect of impurities such as hydrogen and carbon on the crystallinity of the metal oxide film of the comparative example was evaluated by calculation.

[0150] In the following calculation, the effect of hydrogen on the crystallization of the metal oxide film was investigated by first-principles calculation. In particular, the energy difference between the amorphous state and the crystal state was measured in the case where InGaZnO4 does not contain hydrogen and in the case where InGaZnO4 contains 6.67 atomic percent of hydrogen. 8.54×10 22 atoms / cm 3 The atomic density of the In-Ga-Zn-O crystal, Figure 18A and Figure 18B The SIMS analysis results shown indicate that the hydrogen concentration is the same as that of the metal oxide film of this comparative example. Note that an In-Ga-Zn oxide film with an atomic ratio of In, Ga, and Zn of 1:1:1 was used as an example of the metal oxide film in this calculation.

[0151] Figure 22 The lattice structure of the In-Ga-Zn-O crystal containing 112 atoms in this calculation is shown.

[0152] Regarding the calculation, a structure was formed without adding hydrogen atoms to the Figure 22 shown structure, and a structure with eight hydrogen atoms added to the Figure 22 shown structure, and the structure was optimized. Then, the energy was calculated. In addition, an amorphous structure was formed from the optimized structure through the following steps.

[0153] (1) Molecular dynamics calculation using the NVT ensemble at 3000K.

[0154] (2) Molecular dynamics calculation using the NVT ensemble at 2 psec and 1000K.

[0155] (3) Optimization of the structure.

[0156] Note that three structures are obtained through the above calculations (1) of 5 psec, 5.5 psec, or 6 psec, and calculations (2) and optimization (3) are performed to form three amorphous structures of the three structures. Then, the average energy is obtained. In this calculation, the first-principles calculation software "Vienna Ab initio Simulation Package" (VASP) is used. Table 3 shows the calculation conditions.

[0157] [Table 3]

[0158]

[0159] Figures 23A to 23D Shows a part of each structure obtained by the calculation. Table 4 shows the calculation results of the energy difference. Figure 23A Shows a structure in which no H atoms (0 atomic percentage) are added to the single-crystal In-Ga-Zn oxide film. Figure 23B Shows a structure in which eight H atoms (6.67 atomic percentage) are added to the single-crystal In-Ga-Zn oxide film. Figure 23C Shows a structure in which no H atoms (0 atomic percentage) are added to the amorphous In-Ga-Zn oxide film. Figure 23D Shows a structure in which eight H atoms (6.67 atomic percentage) are added to the amorphous In-Ga-Zn oxide film.

[0160] [Table 4]

[0161]

[0162] According to Table 4, when the In-Ga-Zn oxide film crystallizes, its energy is greatly reduced. Further, when H atoms are added to the film, the energy reduction due to crystallization is stabilized. Therefore, it can be considered that in the metal oxide film of this comparative example formed by the liquid phase method, in addition to the pattern including spots with a periodic atomic arrangement, a nano-beam electron diffraction pattern similar to the halo pattern is observed, which is caused by the destabilization of the crystal structure by hydrogen.

[0163] As described above, when the metal oxide film contains hydrogen as an impurity, the stability of the crystal is reduced. These calculation results are consistent with the following results: when compared with the metal oxide film of this embodiment, the concentrations of impurities such as hydrogen and carbon in the metal oxide film of the comparative example showing a nano-beam electron diffraction pattern similar to the halo pattern are high.

[0164] This embodiment can be implemented by appropriately combining with the embodiments described in this specification.

[0165] Embodiment 2

[0166] In the present embodiment, a structural example of a transistor including a metal oxide film (oxide semiconductor film) that was described in Embodiment 1 and exhibits semiconductor characteristics will be described with reference to the drawings.

[0167] <Structural example of transistor>

[0168] Figure 9A It is a cross-sectional schematic view of a transistor 100 shown below. This transistor 100 is a bottom-gate transistor.

[0169] The transistor 100 includes a gate electrode 102 provided on a substrate 101, an insulating layer 103 provided on the substrate 101 and the gate electrode 102, an oxide semiconductor layer 104 provided on the insulating layer 103 and overlapping with the gate electrode 102, and a pair of electrodes 105a and 105b in contact with the top surface of the oxide semiconductor layer 104. Further, an insulating layer 106 is provided so as to cover the insulating layer 103, the oxide semiconductor layer 104, and the pair of electrodes 105a and 105b, and an insulating layer 107 is provided on the insulating layer 106.

[0170] The oxide semiconductor film of one aspect of the present invention can be applied to the oxide semiconductor layer 104 in the transistor 100.

[0171] <<Substrate 101>>

[0172] There are no particular limitations on the properties of the material of the substrate 101 as long as the material has at least sufficient thermal resistance to withstand the heat treatment performed later. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or a yttria-stabilized zirconia (YSZ) substrate can be used as the substrate 101. Alternatively, a single-crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate made of silicon germanium, or an SOI substrate can be used as the substrate 101. Furthermore, any of the above substrates provided with semiconductor elements can be used as the substrate 101.

[0173] Furthermore, a flexible substrate such as a plastic substrate can be used as the substrate 101, and the transistor 100 can be directly provided on the flexible substrate. Alternatively, a release layer can be provided between the substrate 101 and the transistor 100. This release layer can be used when forming a part or all of the transistor on the release layer and peeling the transistor from the substrate 101 and transferring it to another substrate. Thus, the transistor 100 can be transferred to a substrate with low thermal resistance or a flexible substrate.

[0174] <<Gate electrode 102>>

[0175] The gate electrode 102 can be formed using a metal selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten; an alloy containing any one of the above metals as a component; or an alloy combining any one of the above metals; etc. Further, one or more metals selected from manganese and zirconium can be used. Moreover, the gate electrode 102 can have a single-layer structure or a stacked structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a double-layer structure with a titanium film stacked on an aluminum film, a double-layer structure with a titanium film stacked on a titanium nitride film, a double-layer structure with a tungsten film stacked on a titanium nitride film, a double-layer structure with a tungsten film stacked on a tantalum nitride film or a tungsten nitride film, a three-layer structure with a titanium film, an aluminum film, and a titanium film stacked in sequence, etc. can be cited. Alternatively, an alloy film containing aluminum and one or more metals selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium; or a nitride film of the alloy film can be used.

[0176] The gate electrode 102 can also be formed using a transparent conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide added with silicon oxide. And, it can have a stacked structure formed using the above transparent conductive material and the above metal.

[0177] Further, an In-Ga-Zn-based oxynitride semiconductor film, an In-Sn-based oxynitride semiconductor film, an In-Ga-based oxynitride semiconductor film, an In-Zn-based oxynitride semiconductor film, an Sn-based oxynitride semiconductor film, an In-based oxynitride semiconductor film, or a film of a metal nitride (such as InN or ZnN), etc. can be provided between the gate electrode 102 and the insulating layer 103. Each of these films has a work function higher than or equal to 5 eV, or higher than or equal to 5.5 eV, which is higher than the electron affinity of the oxide semiconductor. Therefore, the threshold voltage of a transistor including an oxide semiconductor can drift in the positive direction, and a so-called normally-off switching element can be obtained. For example, an In-Ga-Zn-based oxynitride semiconductor film having at least a higher nitrogen concentration than the oxide semiconductor layer 104, specifically, an In-Ga-Zn-based oxynitride semiconductor film having a nitrogen concentration of 7 atomic percent or higher is used.

[0178] <<Insulating layer 103>>

[0179] The insulating layer 103 is used as a gate insulating film. The insulating layer 103 in contact with the bottom surface of the oxide semiconductor layer 104 is preferably an amorphous film.

[0180] The insulating layer 103 can have, for example, a single-layer structure or a stacked structure using one or more of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga-Zn-based metal oxide, and silicon nitride.

[0181] The insulating layer 103 is formed of a high-k material such as hafnium silicate (HfSiO x ), hafnium silicate with nitrogen added (HfSi x O y N z ), hafnium aluminate with nitrogen added (HfAl x O y N z ), hafnium oxide or yttrium oxide, which can reduce the gate leakage current of the transistor.

[0182] <>

[0183] A pair of electrodes 105a and 105b are used as the source electrode and the drain electrode of the transistor.

[0184] A pair of electrodes 105a and 105b can be formed with a single-layer structure or a stacked structure using any one of metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, or an alloy containing any one of these metals as the conductive material. For example, a single-layer structure of an aluminum film containing silicon, a double-layer structure with a titanium film stacked on an aluminum film, a double-layer structure with a titanium film stacked on a tungsten film, a double-layer structure with a copper film stacked on a copper-magnesium-aluminum alloy film, a three-layer structure with a titanium film or a titanium nitride film, an aluminum film or a copper film, and a titanium film or a titanium nitride film stacked in sequence, a three-layer structure with a molybdenum film or a molybdenum nitride film, an aluminum film or a copper film, and a molybdenum film or a molybdenum nitride film stacked in sequence, etc. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide can also be used.

[0185] <<Insulating layers 106 and 107>>

[0186] The insulating layer 106 is preferably formed of an oxide insulating film containing oxygen in a higher proportion than the stoichiometric composition. This oxide insulating film releases oxygen when heated. For example, when this oxide insulating film is heated at a temperature equal to or higher than the heating treatment temperature in the manufacturing process of the transistor, in the thermal desorption spectroscopy (TDS) analysis, the oxygen release amount converted into oxygen atoms is greater than or equal to 1.0×10 18 atoms / cm 3 , preferably greater than or equal to 3.0×10 20 atoms / cm 3 .

[0187] As the insulating layer 106, a silicon oxide film or an oxynitride film can be formed.

[0188] Note that the insulating layer 106 is also used as a film to mitigate damage to the oxide semiconductor layer 104 when forming the insulating layer 107 later.

[0189] An oxygen-permeable oxide film can be provided between the insulating layer 106 and the oxide semiconductor layer 104.

[0190] As an oxide film that transmits oxygen, a silicon oxide film, a silicon oxynitride film, or the like can be formed. Note that in this specification, the "silicon oxynitride film" refers to a film that contains oxygen in a higher proportion than nitrogen, and the "silicon nitride oxide film" refers to a film that contains nitrogen in a higher proportion than oxygen.

[0191] The insulating layer 107 can be formed of an insulating film that has a blocking effect on oxygen, hydrogen, water, and the like. By disposing the insulating layer 107 on the insulating layer 106, outward diffusion of oxygen from the oxide semiconductor layer 104 and entry of hydrogen, water, or the like from the outside into the oxide semiconductor layer 104 can be prevented. Examples of such an insulating film include a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, a gallium oxynitride film, a yttrium oxide film, a yttrium oxynitride film, a hafnium oxide film, and a hafnium oxynitride film.

[0192] <Example of a method for manufacturing a transistor>

[0193] Next, an example of a method for manufacturing the transistor 100 shown Figures 9A to 9C will be described.

[0194] First, as Figure 10A shown, a gate electrode 102 is formed on a substrate 101, and an insulating layer 103 is formed on the gate electrode 102.

[0195] Here, a glass substrate is used as the substrate 101.

[0196] <<Formation of the gate electrode>>

[0197] A method for forming the gate electrode 102 will be described below. First, a conductive film is formed by a sputtering method, a CVD method, an evaporation method, or the like, and then a resist mask is formed on the conductive film by a photolithography process using a first photomask. Next, a part of the conductive film is etched using the resist mask to form the gate electrode 102. After that, the resist mask is removed.

[0198] Note that the gate electrode 102 can also be formed by an electroplating method, a printing method, an inkjet method, or the like without using the above-described formation method.

[0199] <<Formation of the gate insulating layer>>

[0200] The insulating layer 103 is formed by a sputtering method, a CVD method, an evaporation method, or the like.

[0201] When the insulating layer 103 is formed of a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film, it is preferable to use a deposition gas containing silicon and an oxidation gas as source gases. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and fluorosilane. As the oxidation gas, for example, oxygen, ozone, nitrous oxide, and nitrogen dioxide can be cited.

[0202] When forming a silicon nitride film as the insulating layer 103, it is preferable to use a two-stage formation method. First, a first silicon nitride film with few defects is formed by plasma CVD method, using a mixed gas of silane, nitrogen, and ammonia as the source gas. Then, by switching the source gas to a mixed gas of silane and nitrogen, a second silicon nitride film with a low hydrogen concentration and capable of blocking hydrogen is formed. By this formation method, a silicon nitride film with few defects and having a hydrogen-blocking property can be formed as the insulating layer 103.

[0203] In addition, when forming a gallium oxide film as the insulating layer 103, the metal organic chemical vapor deposition (MOCVD) method can be used.

[0204] <<Formation of Oxide Semiconductor Layer>>

[0205] Next, as Figure 10B shown, an oxide semiconductor layer 104 is formed on the insulating layer 103.

[0206] The formation method of the oxide semiconductor layer 104 is described below. First, an oxide semiconductor film is formed using the method shown in Embodiment 1. Then, a resist mask is formed on the oxide semiconductor film by photolithography using a second photomask. Next, a part of the oxide semiconductor film is etched using this resist mask to form the oxide semiconductor layer 104. After that, the resist mask is removed.

[0207] Thereafter, a heat treatment may also be performed. In this case, the heat treatment is preferably performed in an oxygen-containing atmosphere.

[0208] <<Formation of a Pair of Electrodes>>

[0209] Next, as Figure 10C shown, a pair of electrodes 105a and 105b are formed.

[0210] The formation method of a pair of electrodes 105a and 105b is described below. First, a conductive film is formed by sputtering method, CVD method, evaporation method, etc. Then, a resist mask is formed on the conductive film by photolithography using a third photomask. Next, a part of the conductive film is etched using this resist mask to form a pair of electrodes 105a and 105b. After that, the resist mask is removed.

[0211] Note that, as Figure 10B shown, sometimes the upper part of the oxide semiconductor layer 104 is partially etched and thinned by the etching of the conductive film. Therefore, it is preferable to form the oxide semiconductor layer 104 thick.

[0212] <<Formation of Insulating Layer>>

[0213] Next, as Figure 10D shown, an insulating layer 106 is formed on the oxide semiconductor layer 104 and a pair of electrodes 105a and 105b, and then an insulating layer 107 is formed on the insulating layer 106.

[0214] When the insulating layer 106 is formed of a silicon oxide film or a silicon oxynitride film, it is preferable to use a deposition gas containing silicon and an oxidation gas as source gases. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and fluorosilane. As the oxidation gas, for example, oxygen, ozone, nitrous oxide, and nitrogen dioxide can be cited.

[0215] For example, the silicon oxide film or the silicon oxynitride film is formed under the following conditions: the substrate provided in the vacuum evacuation processing chamber of the plasma CVD device is maintained at a temperature of 180°C or higher and 260°C or lower, preferably 200°C or higher and 240°C or lower; the source gases are introduced into the processing chamber at a pressure of 100 Pa or higher and 250 Pa or lower, preferably 100 Pa or higher and 200 Pa or lower; and a high-frequency power of 0.17 W / cm 2 or higher and 0.5 W / cm 2 or lower, preferably 0.25 W / cm 2 or higher and 0.35 W / cm 2 or lower is supplied to the electrodes provided in the processing chamber.

[0216] By applying the high-frequency power, the decomposition efficiency of the source gases in the plasma increases, oxygen free radicals increase, and the oxidation of the source gases is promoted; therefore, the proportion of oxygen contained in the oxide insulating film is higher than the proportion of oxygen in the stoichiometric composition. However, the film prepared at the above substrate temperature releases a part of oxygen when heated in a subsequent process. Therefore, an oxide insulating film containing a proportion of oxygen higher than that in the stoichiometric composition and releasing a part of oxygen by heating can be formed.

[0217] Furthermore, when the oxide insulating film is provided between the oxide semiconductor layer 104 and the insulating layer 106, the oxide insulating film can be used as a protective film for the oxide semiconductor layer 104 in the process of forming the insulating layer 106. Therefore, the insulating layer 106 can be formed using a high-frequency power with a high power density while reducing damage to the oxide semiconductor layer 104.

[0218] For example, as the oxide insulating film, a silicon oxide film or a silicon oxynitride film can be formed under the following conditions: the substrate provided in the vacuum evacuation processing chamber of the plasma CVD device is maintained at a temperature of 180°C or higher and 400°C or lower, preferably 200°C or higher and 370°C or lower; the source gas is introduced into the processing chamber at a pressure of 20 Pa or higher and 250 Pa or lower, preferably 100 Pa or higher and 250 Pa or lower; and high-frequency power is supplied to the electrode provided in the processing chamber. Further, when the pressure in the processing chamber is 100 Pa or higher and 250 Pa or lower, the damage to the oxide semiconductor layer 104 can be reduced.

[0219] Preferably, a deposition gas containing silicon and an oxidation gas are used as the source gas for the oxide insulating film. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and fluorosilane. As the oxidation gas, for example, oxygen, ozone, nitrous oxide, and nitrogen dioxide can be cited.

[0220] The insulating layer 107 can be formed by a sputtering method or a CVD method.

[0221] In the case where the insulating layer 107 is formed of a silicon nitride film or a silicon oxynitride film, preferably, a deposition gas containing silicon, an oxidation gas, and a gas containing nitrogen are used as the source gas. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and fluorosilane. As the oxidation gas, for example, oxygen, ozone, nitrous oxide, and nitrogen dioxide can be cited. Examples of the gas containing nitrogen include nitrogen and ammonia.

[0222] Through the above process, the transistor 100 can be formed.

[0223] <Modification example of the transistor 100>

[0224] Hereinafter, a structural example of a transistor that is partially different from the transistor 100 will be described.

[0225] <<Modification example 1>>

[0226] Figure 9B It is a cross-sectional schematic view of the transistor 110 shown below. The transistor 110 is different from the transistor 100 in the structure of the oxide semiconductor layer. Note that hereinafter, the description of the constituent elements denoted by the same reference numerals having structures or functions similar to those of other structural examples is omitted.

[0227] In the oxide semiconductor layer 114 included in the transistor 110, the oxide semiconductor layer 114a and the oxide semiconductor layer 114b are stacked.

[0228] Because the boundary between the oxide semiconductor layer 114a and the oxide semiconductor layer 114b is sometimes unclear, Figure 9B this boundary in etc. is indicated by a dashed line.

[0229] The oxide semiconductor film of one embodiment of the present invention can be applied to one or both of the oxide semiconductor layers 114a and 114b.

[0230] Typical examples of materials that can be used for the oxide semiconductor layer 114a are In-Ga oxide, In-Zn oxide, and In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf). When using In-M-Zn oxide for the oxide semiconductor layer 114a, assuming that the total of In and M other than Zn and oxygen is 100 atomic percentages, the ratio of In and M is preferably: In is greater than or equal to 25 atomic percentages and M is less than 75 atomic percentages, and more preferably: In is greater than or equal to 34 atomic percentages and M is less than 66 atomic percentages. In addition, for example, a material having a bandgap of 2 eV or greater, preferably 2.5 eV or greater, and more preferably 3 eV or greater is used as the oxide semiconductor layer 114a.

[0231] For example: The oxide semiconductor layer 114b contains In or Ga, and typically contains In-Ga oxide, In-Zn oxide, or In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf). In addition, the energy level of the bottom of the conduction band of the oxide semiconductor layer 114b is closer to the vacuum energy level than that of the oxide semiconductor layer 114a. The difference between the energy level of the bottom of the conduction band of the oxide semiconductor layer 114b and the energy level of the bottom of the conduction band of the oxide semiconductor layer 114a is preferably 0.05 eV or greater, 0.07 eV or greater, 0.1 eV or greater, or 0.15 eV or greater, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less.

[0232] When, for example, using In-M-Zn oxide as the oxide semiconductor layer 114b, the atomic percentage between In and M is preferably: the atomic percentage of In is less than 50 atomic percentages, and the atomic percentage of M is greater than or equal to 50 atomic percentages, and more preferably: the atomic percentage of In is less than 25 atomic percentages, and the atomic percentage of M is greater than or equal to 75 atomic percentages, where the total of In and M other than Zn and oxygen is assumed to be 100 atomic percentages.

[0233] For example, an In-Ga-Zn oxide with an atomic ratio of In, Ga, and Zn of 1:1:1 or 3:1:2 can be used for the oxide semiconductor layer 114a. Further, an In-Ga-Zn oxide with an atomic ratio of In, Ga, and Zn of 1:3:2, 1:6:4, or 1:9:6 can be used for the oxide semiconductor layer 114b. Note that the atomic ratio of the oxide semiconductor layers 114a and 114b may be different from the atomic ratio of the target material used, and there may be a difference of ±20%.

[0234] When an oxide containing a large amount of Ga used as a stabilizer is used for the oxide semiconductor layer 114b provided on the oxide semiconductor layer 114a, oxygen can be prevented from being released from the oxide semiconductor layers 114a and 114b.

[0235] Note that it is not limited to the above composition and materials, and materials with an appropriate composition can be used according to the required semiconductor characteristics and electrical characteristics of the transistor (e.g., field-effect mobility and threshold voltage). Further, in order to obtain the required semiconductor characteristics of the transistor, it is preferable to appropriately set the carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, and density, etc. of the oxide semiconductor layers 114a and 114b.

[0236] Although a structure in which two oxide semiconductor layers are stacked is described as an example of the oxide semiconductor layer 114 above, a structure in which three or more oxide semiconductor layers are stacked can also be used.

[0237] <<Modification Example 2>>

[0238] Figure 9C is a cross-sectional schematic view of the transistor 120 shown below. The transistor 120 is different from the transistors 100 and 110 in the structure of the oxide semiconductor layer.

[0239] In the oxide semiconductor layer 124 included in the transistor 120, the oxide semiconductor layer 124a, the oxide semiconductor layer 124b, and the oxide semiconductor layer 124c are stacked in sequence.

[0240] The oxide semiconductor layers 124a and 124b are stacked on the insulating layer 103. The oxide semiconductor layer 124c is provided in contact with the top surface of the oxide semiconductor layer 124b and the top and side surfaces of the pair of electrodes 105a and 105b.

[0241] The oxide semiconductor film of one aspect of the present invention can be applied to at least one of the oxide semiconductor layers 124a, 124b, and 124c.

[0242] For example, the oxide semiconductor layer 124b may have a structure similar to that of the oxide semiconductor layer 114a shown in Modification Example 1. Further, for example, each of the oxide semiconductor layers 124a and 124c may have a structure similar to that of the oxide semiconductor layer 114b shown in Modification Example 1.

[0243] For example, when oxides containing a large amount of Ga used as a stabilizer are used for the oxide semiconductor layer 124a and the oxide semiconductor layer 124c, oxygen can be prevented from being released from the oxide semiconductor layer 124a, the oxide semiconductor layer 124b, and the oxide semiconductor layer 124c.

[0244] In the case where the channel is mainly formed in the oxide semiconductor layer 124b, for example, oxides containing a large amount of In can be used for the oxide semiconductor layer 124b, and a pair of electrodes 105a and 105b are provided in contact with the oxide semiconductor layer 124b; thereby, the on-state current of the transistor 120 can be increased.

[0245] <Other structural examples of the transistor>

[0246] The following describes a structural example of a top-gate transistor of an oxide semiconductor film to which one mode of the present invention can be applied.

[0247] <<Structural example>

[0248] Figure 11A It is a cross-sectional schematic view of the top-gate transistor 150 shown below.

[0249] The transistor 150 includes: an oxide semiconductor layer 104 provided on a substrate 101 provided with an insulating layer 151; a pair of electrodes 105a and 105b in contact with the top surface of the oxide semiconductor layer 104; an insulating layer 103 provided on the oxide semiconductor layer 104 and the pair of electrodes 105a and 105b; and a gate electrode 102 provided on the insulating layer 103 and overlapping the oxide semiconductor layer 104. Further, an insulating layer 152 is provided so as to cover the insulating layer 103 and the gate electrode 102.

[0250] An oxide semiconductor film of one mode of the present invention can be applied to the oxide semiconductor layer 104 in the transistor 150.

[0251] The insulating layer 151 has a function of suppressing the diffusion of impurities from the substrate 101 to the oxide semiconductor layer 104. For example, a structure similar to that of the insulating layer 107 can be used. Note that the insulating layer 151 may not be provided.

[0252] The insulating layer 152 can be formed in a manner similar to the insulating layer 107 using an insulating film having a barrier effect against oxygen, hydrogen, water, etc. Note that the insulating layer 107 may not be provided.

[0253] <<Modification Example>>

[0254] Hereinafter, a structural example of a transistor that is partially different from the transistor 150 will be described.

[0255] Figure 11B It is a cross-sectional schematic view of the transistor 160 shown below. The structure of the oxide semiconductor layer in the transistor 160 is different from that of the transistor 150.

[0256] In the oxide semiconductor layer 164 included in the transistor 160, an oxide semiconductor layer 164a, an oxide semiconductor layer 164b, and an oxide semiconductor layer 164c are sequentially stacked.

[0257] The oxide semiconductor film of one aspect of the present invention can be applied to at least one of the oxide semiconductor layer 164a, the oxide semiconductor layer 164b, and the oxide semiconductor layer 164c.

[0258] For example, the oxide semiconductor layer 164b may have a structure similar to the oxide semiconductor layer 114a shown in Modification Example 1. Further, for example, the oxide semiconductor layers 164a and 164c may each have a structure similar to the oxide semiconductor layer 114b shown in Modification Example 1.

[0259] Oxides containing a large amount of Ga used as a stabilizer are used for the oxide semiconductor layer 164a and the oxide semiconductor layer 164c; thus, oxygen can be prevented from being released from the oxide semiconductor layer 164a, the oxide semiconductor layer 164b, and the oxide semiconductor layer 164c.

[0260] The oxide semiconductor layer 164 can be formed by the following method: obtaining the oxide semiconductor layer 164c and the oxide semiconductor layer 164b by etching and exposing the oxide semiconductor film that will become the oxide semiconductor layer 164a; and processing the oxide semiconductor film into the oxide semiconductor layer 164a by a dry etching method. In this case, reaction products of the oxide semiconductor film sometimes adhere to the sides of the oxide semiconductor layers 164b and 164c to form sidewall protection layers (also called rabbit ears). Note that the reaction products adhere by a sputtering phenomenon or during dry etching.

[0261] Figure 11C It is a cross-sectional schematic view of the transistor 161 in which the sidewall protection layer 164d is formed on the side of the oxide semiconductor layer 164 in the above-described manner. Note that other components of the transistor 161 are the same as those of the transistor 160.

[0262] The sidewall protective layer 164d mainly contains the same material as the oxide semiconductor layer 164a. Sometimes, the sidewall protective layer 164d contains components (e.g., silicon) of the layer (here, the insulating layer 151) provided under the oxide semiconductor layer 164a.

[0263] As Figure 11C shown, by adopting a structure in which the side surface of the oxide semiconductor layer 164b is covered with the sidewall protective layer 164d so as not to come into contact with the pair of electrodes 105a and 105b, especially when the channel is mainly formed in the oxide semiconductor layer 164b, the unintentional leakage current of the transistor in the off state can be reduced; thus, a transistor with good off-state characteristics can be manufactured. Further, when a material containing a large amount of Ga used as a stabilizer is used for the sidewall protective layer 164d, oxygen can be effectively prevented from being released from the side surface of the oxide semiconductor layer 164b; therefore, a transistor with excellent stability of electrical characteristics can be manufactured.

[0264] This embodiment can be implemented by appropriately combining with the embodiments described in this specification.

[0265] Embodiment 3

[0266] In this embodiment, the structure of a display panel according to one aspect of the present invention will be described with reference to Figures 12A to 12C FIG.

[0267] Figure 12A is a top view of a display panel according to one aspect of the present invention. Figure 12B FIG. shows a pixel circuit that can be used in a pixel when a liquid crystal element is used in a display panel according to one aspect of the present invention. Figure 12C FIG. shows a pixel circuit that can be used in a pixel when an organic EL element is used in a display panel according to one aspect of the present invention.

[0268] The transistor in the pixel portion can be formed according to Embodiment 2. Further, the transistor can be easily formed into an n-channel transistor, and thus, a part of the drive circuit formed by using the n-channel transistor can be formed on the same substrate as the transistor in the pixel portion. In this way, by using the transistor described in Embodiment 2 for the pixel portion or the drive circuit, a display device with high reliability can be provided.

[0269] Figure 12AAn example of a block diagram showing an active matrix display device is shown. A pixel section 501, a first scan line drive circuit 502, a second scan line drive circuit 503, and a signal line drive circuit 504 are provided on a substrate 500 in the display device. In the pixel section 501, a plurality of signal lines extending from the signal line drive circuit 504 are arranged, and a plurality of scan lines extending from the first scan line drive circuit 502 and the second scan line drive circuit 503 are arranged. Note that pixels including display elements in the region where the scan lines and the signal lines cross each other are arranged in a matrix shape. The substrate 500 of the display device is connected to a timing control circuit (also referred to as a controller or a control IC) through a connection section such as a flexible printed circuit (FPC).

[0270] In Figure 12A , the first scan line drive circuit 502, the second scan line drive circuit 503, and the signal line drive circuit 504 are formed on the same substrate 500 as the pixel section 501. Accordingly, the number of components provided outside such as drive circuits can be reduced, and the cost can be lowered. Further, in the case where the drive circuits are provided outside the substrate 500, it is necessary to extend the wirings and the number of connections of the wirings increases; however, when the drive circuits are provided on the substrate 500, the number of connections of the wirings can be reduced. Therefore, improvement in reliability or yield can be achieved.

[0271] <Liquid crystal panel>

[0272] Figure 12B An example of the circuit structure of a pixel is shown. Here, a pixel circuit applicable to a pixel of a VA liquid crystal display panel is shown.

[0273] This pixel circuit can be applied to a structure in which one pixel includes a plurality of pixel electrode layers. The plurality of pixel electrode layers are connected to different transistors, and each transistor can be driven by a different gate signal. Thereby, signals applied to each pixel electrode layer in a multi-domain pixel can be independently controlled.

[0274] The gate wiring 512 of the transistor 516 and the gate wiring 513 of the transistor 517 are separated so that different gate signals can be supplied. In contrast, the source electrode or the drain electrode 514 used as a data line is common to the transistors 516 and 517. The transistors described in Embodiment 2 can be appropriately used as the transistors 516 and 517. Therefore, a liquid crystal display panel with high reliability can be provided.

[0275] The shapes of the first pixel electrode layer electrically connected to the transistor 516 and the second pixel electrode layer electrically connected to the transistor 517 will be described. The first pixel electrode layer and the second pixel electrode layer are separated by a gap. The first pixel electrode layer has a V shape, and the second pixel electrode layer is provided so as to surround the first pixel electrode layer.

[0276] The gate electrode of transistor 516 is connected to gate wiring 512, and the gate electrode of transistor 517 is connected to gate wiring 513. When different gate signals are supplied to gate wiring 512 and gate wiring 513, the operating timings of transistor 516 and transistor 517 can be changed. Thus, the alignment of liquid crystal can be controlled.

[0277] Furthermore, the storage capacitor can be formed using capacitor wiring 510, a gate insulating film serving as a dielectric, and a capacitor electrode electrically connected to the first pixel electrode layer or the second pixel electrode layer.

[0278] This multi-domain pixel includes a first liquid crystal element 518 and a second liquid crystal element 519. The first liquid crystal element 518 includes a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. The second liquid crystal element 519 includes a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween.

[0279] Note that the pixel circuit of the present invention is not limited to Figure 12B the structure shown. For example, a switch, resistor, capacitor, transistor, sensor, or logic circuit, etc. can be added to Figure 12B the pixel shown.

[0280] <Organic EL panel>

[0281] Figure 12C Another example of the circuit structure of the pixel portion is shown. Here, the pixel structure of a display panel using an organic EL element is shown.

[0282] In an organic EL element, by applying a voltage to the light-emitting element, electrons from one of a pair of electrodes and holes from the other of the pair of electrodes can be injected into a layer containing a light-emitting organic compound; thus, a current flows. The electrons and holes recombine, and thus, the light-emitting organic compound is excited. The light-emitting organic compound returns from the excited state to the ground state and emits light. Due to this mechanism, this light-emitting element is called a current-excited light-emitting element.

[0283] Figure 12C An example of an applicable pixel circuit is shown. Here, one pixel includes two n-channel transistors. Note that a metal oxide film of one aspect of the present invention can be used for the channel formation region of the n-channel transistor. Furthermore, this pixel circuit can employ digital time gray scale driving.

[0284] The structure of the applicable pixel circuit and the operation of the pixel using digital time gray scale driving will be described.

[0285] The pixel 520 includes a switching transistor 521, a driving transistor 522, a light-emitting element 524, and a capacitor 523. The gate electrode layer of the switching transistor 521 is connected to the scanning line 526, one of the first electrodes (either the source electrode layer or the drain electrode layer) of the switching transistor 521 is connected to the signal line 525, and the second electrode (the other of the source electrode layer and the drain electrode layer) of the switching transistor 521 is connected to the gate electrode layer of the driving transistor 522. The gate electrode layer of the driving transistor 522 is connected to the power supply line 527 through the capacitor 523, the first electrode of the driving transistor 522 is connected to the power supply line 527, and the second electrode of the driving transistor 522 is connected to the first electrode (pixel electrode) of the light-emitting element 524. The second electrode of the light-emitting element 524 corresponds to the common electrode 528. The common electrode 528 is electrically connected to a common potential line provided on the same substrate.

[0286] As the switching transistor 521 and the driving transistor 522, the transistors described in Embodiment 2 can be appropriately used. Thereby, an organic EL display panel with high reliability can be provided.

[0287] The potential of the second electrode (common electrode 528) of the light-emitting element 524 is set to a low power supply potential. Note that the low power supply potential is lower than the high power supply potential supplied to the power supply line 527. For example, the low power supply potential can be GND or 0V, etc. The high power supply potential and the low power supply potential are set to be higher than or equal to the forward threshold voltage of the light-emitting element 524, and this potential difference is applied to the light-emitting element 524, thereby supplying current to the light-emitting element 524 and causing light emission. The forward voltage of the light-emitting element 524 is the voltage at which the desired luminance can be obtained, and is at least higher than the forward threshold voltage.

[0288] Note that by using the gate capacitance of the driving transistor 522 instead of the capacitor 523, the capacitor 523 can be omitted. The gate capacitance of the driving transistor 522 can be formed between the channel formation region and the gate electrode layer.

[0289] Next, the signal input to the driving transistor 522 will be described. In the case of the voltage input voltage driving method, a video signal that surely turns on or off the driving transistor 522 is input to the driving transistor 522. In order to make the transistor 522 operate in the linear region, a voltage higher than the power supply line 527 is applied to the gate electrode layer of the driving transistor 522. Note that a voltage higher than or equal to the sum of the power supply line voltage and the threshold voltage Vth of the driving transistor 522 is applied to the signal line 525.

[0290] In the case of performing analog gradation driving, a voltage greater than or equal to the sum of the forward voltage of the light-emitting element 524 and the threshold voltage Vth of the driving transistor 522 is applied to the gate electrode layer of the driving transistor 522. By inputting a video signal that causes the driving transistor 522 to operate in the saturation region, current is supplied to the light-emitting element 524. In order to cause the driving transistor 522 to operate in the saturation region, the potential of the power supply line 527 is set to be higher than the gate potential of the driving transistor 522. When using an analog video signal, current can be supplied to the light-emitting element 524 according to the video signal, and analog gradation driving is performed.

[0291] Note that the structure of the pixel circuit of the present invention is not limited to Figure 12C the structure shown. For example, a switch, resistor, capacitor, sensor, transistor, or logic circuit, etc. can be added to Figure 12C the pixel circuit shown.

[0292] Embodiment 4

[0293] In this embodiment, with reference to Figure 13 and Figures 14A to 14D the structures of a semiconductor device and an electronic device including a metal oxide film according to one aspect of the present invention will be described.

[0294] Figure 13 is a block diagram of an electronic device including a semiconductor device incorporating a metal oxide film according to one aspect of the present invention.

[0295] Figures 14A to 14D is an external view of an electronic device including a semiconductor device incorporating a metal oxide film according to one aspect of the present invention.

[0296] Figure 13 The electronic device shown includes an RF circuit 901, an analog baseband circuit 902, a digital baseband circuit 903, a battery 904, a power supply circuit 905, an application processor 906, a flash memory 910, a display controller 911, a storage circuit 912, a display 913, a touch sensor 919, an audio circuit 917, and a keyboard 918, etc.

[0297] The application processor 906 includes a CPU 907, a DSP 908, and an interface (IF) 909. In addition, the storage circuit 912 may include an SRAM or a DRAM.

[0298] By applying the transistor described in Embodiment 2 to the storage circuit 912, an electronic device with high reliability for writing and reading data can be provided.

[0299] By applying the transistor described in Embodiment 2 to registers and the like included in the CPU 907 or DSP 908, an electronic device with high reliability for writing and reading data can be provided.

[0300] Note that when the off-state leakage current of the transistor described in Embodiment 2 is extremely low, the storage circuit 912 can store data for a long time and can have a sufficiently low power consumption. Further, during the execution of power gating, the CPU 907 or DSP 908 can store the state before power gating in registers and the like.

[0301] Further, the display 913 includes a display unit 914, a source driver 915, and a gate driver 916.

[0302] The display unit 914 includes a plurality of pixels arranged in a matrix. The pixel includes a pixel circuit, and the pixel circuit is electrically connected to the gate driver 916.

[0303] The transistor described in Embodiment 2 can be appropriately used in the pixel circuit or the gate driver 916. Thereby, a display with high reliability can be provided.

[0304] Examples of the electronic device are a television device (also referred to as a television or a television receiver), a display of a computer or the like, a photographing device such as a digital camera or a digital video camera, a digital photo frame, a mobile phone (also referred to as a mobile telephone or a mobile phone device), a portable game machine, a portable information terminal, a sound reproduction device, and a large game machine such as a pachinko machine.

[0305] Figure 14A A portable information terminal is shown, which includes a main body 1001, a housing 1002, a display unit 1003a and a display unit 1003b, etc. The display unit 1003b includes a touch panel. By touching the keyboard button 1004 displayed on the display unit 1003b, a screen operation can be performed and text can be input. Of course, the display unit 1003a can be used as a touch panel. A liquid crystal panel or an organic light-emitting panel is manufactured by using the transistor described in Embodiment 2 as a switching element, and is applied to the display unit 1003a or 1003b, thereby a portable information terminal with high reliability can be provided.

[0306] In Figure 14A The portable information terminal shown may have functions of displaying various kinds of data (for example, still images, moving images, and text images), functions of displaying a calendar, a date, or a time on the display unit, functions of operating or editing the data displayed on the display unit, and functions of controlling processing through various software (programs). Further, an external connection terminal (such as a headphone terminal or a USB terminal) or a recording medium insertion portion or the like can be provided on the back surface or side surface of the housing.

[0307] In Figure 14A the portable information terminal shown, data can be wirelessly transmitted and received. Through wireless communication, desired book data and the like can be purchased and downloaded from an e-book server.

[0308] Figure 14B A portable music player is shown, which includes a display unit 1023 in a main body 1021, a fixing unit 1022 for wearing the portable music player on the ear, a speaker, operation buttons 1024, an external memory slot 1025, and the like. A liquid crystal panel or an organic light emitting panel is manufactured by using the transistor described in Embodiment 2 as a switching element, and it is applied to the display unit 1023, whereby a portable music player with high reliability can be provided.

[0309] Furthermore, when Figure 14B the portable music player shown has an antenna, a microphone function, or a wireless communication function and is used together with a mobile phone, the user can make a hands-free call wirelessly while driving or the like.

[0310] Figure 14C A mobile phone is shown, which includes two housings, a housing 1030 and a housing 1031. The housing 1031 includes a display panel 1032, a speaker 1033, a microphone 1034, a pointing device 1036, a camera lens 1037, and an external connection terminal 1038, and the like. The housing 1030 is provided with a solar cell 1040 for charging the mobile phone; an external memory slot 1041; and the like. In addition, an antenna is mounted in the housing 1031. By applying the transistor described in Embodiment 2 to the display panel 1032, a mobile phone with high reliability can be provided.

[0311] Furthermore, the display panel 1032 includes a touch panel. In Figure 14C a plurality of operation keys 1035 for displaying an image are shown by dotted lines. In addition, a booster circuit for increasing the voltage output from the solar cell 1040 to a value required for each circuit is also included.

[0312] For example, when the thickness of the metal oxide film of the transistor described in Embodiment 2 is greater than or equal to 2 μm and less than or equal to 50 μm, a power transistor used for a power supply circuit such as a booster circuit can be formed.

[0313] In the display panel 1032, the display direction is appropriately changed according to the usage mode. Furthermore, since the mobile phone is provided with the camera lens 1037 on the same surface as the display panel 1032, it can be used as a videophone. The speaker 1033 and the microphone 1034 can be used not only for voice calls but also for video calls, recording, and playing sounds, etc. In addition, asFigure 14C The housings 1030 and 1031 in the unfolded state shown in FIG. can be overlapped with each other by sliding. Therefore, miniaturization of the mobile phone can be achieved, which is convenient for carrying.

[0314] The external connection terminal 1038 can be connected to an AC adapter and various cables such as a USB cable; thus, charging and data communication with a personal computer or the like can be performed. In addition, by inserting a recording medium into the external memory slot 1041, a large amount of data can be stored and transferred.

[0315] Furthermore, in addition to the above functions, an infrared communication function or a television reception function or the like can be provided.

[0316] Figure 14D An example of a television device is shown. In the television device 1050, a display unit 1053 is installed in a housing 1051. An image can be displayed on the display unit 1053. In addition, a CPU is installed in a base 1055 for supporting the housing 1051. By applying the transistors described in Embodiment 2 to the display unit 1053 and the CPU, the television device 1050 can have high reliability.

[0317] The television device 1050 can be operated by an operation switch of the housing 1051 or a separately provided remote control unit. Further, the remote control unit can be provided with a display unit for displaying data output from the remote control unit.

[0318] Note that the television device 1050 is provided with a receiver and a modem or the like. By using the receiver, the television device 1050 can receive general TV broadcasts. In addition, when the television device 1050 is connected to a communication network in a wired or wireless manner via the modem, one-way (from the sender to the receiver) or two-way (between the sender and the receiver or between the receivers) information communication can be performed.

[0319] Furthermore, the television device 1050 is provided with an external connection terminal 1054, a storage medium recording / playback unit 1052, and an external memory slot. The external connection terminal 1054 can be connected to various cables such as a USB cable; thus, data communication with a personal computer or the like can be performed. By inserting a disc storage medium into the storage medium recording / playback unit 1052, the data stored in the storage medium can be read and data can be written to the storage medium. In addition, images, videos, etc. stored as data in the external memory 1056 inserted into the external memory slot can be displayed on the display unit 1053.

[0320] Further, in the case where the off-state leakage current of the transistor described in Embodiment 2 is extremely small, when this transistor is applied to the external memory 1056 or the CPU, the television device 1050 can have high reliability and sufficiently low power consumption.

[0321] Symbol Description

[0322] 100, 110, 120, 150, 160, 161, 516, 517: Transistor; 101, 500: Substrate; 102: Gate electrode; 103, 106, 107, 151, 152: Insulating layer; 104, 114, 114a, 114b, 124, 124a - 124c, 164, 164a - 164c: Oxide semiconductor layer; 105a, 105b: Electrode; 200: Quartz glass substrate; 202: Virtual substrate; 204: Metal oxide film; 210a, 210b: Region; 501: Pixel portion; 502, 503: Scan line drive circuit; 504: Signal line drive circuit; 510: Capacitor wiring; 512, 513: Gate wiring; 514: Drain electrode; 518, 519: Liquid crystal element; 520: Pixel; 521: Switching transistor; 522: Driving transistor; 523: Capacitor; 524: Light emitting element; 525: Signal line; 526: Scan line; 527: Power supply line; 528: Common electrode; 901: RF circuit; 902: Analog baseband circuit; 903: Digital baseband circuit; 904: Battery; 905: Power supply circuit; 906: Application processor; 907: CPU; 908: DSP; 910: Flash memory; 911: Display controller; 912: Storage circuit; 913: Display; 914, 1003a, 1003b, 1023, 1053: Display unit; 915: Source driver; 916: Gate driver; 917: Audio circuit; 918: Keyboard; 919: Touch sensor; 1001, 1021: Main body; 1002, 1030, 1031, 1051: Housing; 1004: Keyboard button; 1022: Fixing portion; 1024: Operation button; 1025, 1041: External memory slot; 1032: Display panel; 1033: Speaker; 1034: Microphone; 1035: Operation key; 1036: Pointing device; 1037: Camera lens; 1038, 1054: External connection terminal; 1040: Solar cell; 1050: Television device; 1052: Storage medium recording / reproducing unit; 1055: Stand; 1056: External memory; 164d: Sidewall protective layer

[0323] This application claims priority from Japanese Patent Application No. 2012-245992, filed on Nov. 8, 2012, Japanese Patent Application No. 2013-016242, filed on Jan. 30, 2013, and Japanese Patent Application No. 2013-056768, filed on Mar. 19, 2013, the entire contents of which are incorporated herein by reference.

Claims

1. A transistor, characterized in that, it includes a gate electrode, a gate insulating film on the gate electrode, and an oxide semiconductor layer on the gate insulating film, the channel formation region of the oxide semiconductor layer includes a region where, through a nano-beam electron diffraction pattern, it is observed that instead of having a plurality of spots showing the regularity of crystal parts with a specific plane orientation, the spots are circularly distributed, the channel formation region has a plurality of nanocrystals, the surface orientations of the plurality of nanocrystals are irregular, the respective sizes of the plurality of nanocrystals are less than or equal to 10 nm, the gate insulating film has silicon oxide.

2. A transistor, characterized in that, it includes an oxide semiconductor layer, a gate insulating film on the oxide semiconductor layer, and a gate electrode on the gate insulating film, the channel formation region of the oxide semiconductor layer includes a region where, through a nano-beam electron diffraction pattern, it is observed that instead of having a plurality of spots showing the regularity of crystal parts with a specific plane orientation, the spots are circularly distributed, the channel formation region has a plurality of nanocrystals, the surface orientations of the plurality of nanocrystals are irregular, the respective sizes of the plurality of nanocrystals are less than or equal to 10 nm, the gate insulating film has silicon oxide.

3. A transistor, characterized in that, it includes a gate electrode, a gate insulating film on the gate electrode, and an oxide semiconductor layer on the gate insulating film, The carbon concentration of the oxide semiconductor layer is less than 4×10 21 atoms / cm 3 , the channel formation region of the oxide semiconductor layer includes a region where, through a nano-beam electron diffraction pattern, it is observed that instead of having a plurality of spots showing the regularity of crystal parts with a specific plane orientation, the spots are circularly distributed, the channel formation region has a plurality of nanocrystals, the surface orientations of the plurality of nanocrystals are irregular, the respective sizes of the plurality of nanocrystals are less than or equal to 10 nm, the gate insulating film has silicon oxide, as the oxide semiconductor layer, a target material with an atomic ratio of In:Ga:Zn = 1:1:1 is used.

4. A transistor, characterized in that, it includes a gate electrode, a gate insulating film on the gate electrode, and an oxide semiconductor layer on the gate insulating film, The hydrogen concentration in the oxide semiconductor layer is less than 1×10 22 atoms / cm 3 , the channel formation region of the oxide semiconductor layer includes a region where, through a nano-beam electron diffraction pattern, it is observed that instead of having a plurality of spots showing the regularity of crystal parts with a specific plane orientation, the spots are circularly distributed, the channel formation region has a plurality of nanocrystals, the surface orientations of the plurality of nanocrystals are irregular, the respective sizes of the plurality of nanocrystals are less than or equal to 10 nm, the gate insulating film has silicon oxide, as the oxide semiconductor layer, a target material with an atomic ratio of In:Ga:Zn = 1:1:1 is used.

5. A transistor, characterized in that, it includes a gate electrode, a gate insulating film on the gate electrode, and an oxide semiconductor layer on the gate insulating film, The carbon concentration of the oxide semiconductor layer is less than 4×10 21 atoms / cm 3 , The hydrogen concentration in the oxide semiconductor layer is less than 1×10 22 atoms / cm 3 , the channel formation region of the oxide semiconductor layer includes a region where, through a nano-beam electron diffraction pattern, it is observed that instead of having a plurality of spots showing the regularity of crystal parts with a specific plane orientation, the spots are circularly distributed, The channel formation region has a plurality of nanocrystals, the surface orientations of the plurality of nanocrystals are irregular, the respective sizes of the plurality of nanocrystals are less than or equal to 10 nm, the gate insulating film has silicon oxide, As the oxide semiconductor layer, a target having an atomic ratio of In:Ga:Zn = 1:1:1 is used.

6. A transistor, characterized in that it includes an oxide semiconductor layer, a gate insulating film on the oxide semiconductor layer, and a gate electrode on the gate insulating film, The carbon concentration of the oxide semiconductor layer is less than 4×10 21 atoms / cm 3 , the channel formation region of the oxide semiconductor layer includes a region where, through a nano-beam electron diffraction pattern, it is observed that instead of having a plurality of spots showing the regularity of crystal parts with a specific plane orientation, the spots are circularly distributed, the channel formation region has a plurality of nanocrystals, the surface orientations of the plurality of nanocrystals are irregular, the respective sizes of the plurality of nanocrystals are less than or equal to 10 nm, the gate insulating film has silicon oxide, As the oxide semiconductor layer, a target having an atomic ratio of In:Ga:Zn = 1:1:1 is used.

7. A transistor, characterized in that it includes an oxide semiconductor layer, a gate insulating film on the oxide semiconductor layer, and a gate electrode on the gate insulating film, The hydrogen concentration in the oxide semiconductor layer is less than 1×10 22 atoms / cm 3 , the channel formation region of the oxide semiconductor layer includes a region where, through a nano-beam electron diffraction pattern, it is observed that instead of having a plurality of spots showing the regularity of crystal parts with a specific plane orientation, the spots are circularly distributed, the channel formation region has a plurality of nanocrystals, the surface orientations of the plurality of nanocrystals are irregular, the respective sizes of the plurality of nanocrystals are less than or equal to 10 nm, the gate insulating film has silicon oxide, As the oxide semiconductor layer, a target having an atomic ratio of In:Ga:Zn = 1:1:1 is used.

8. A transistor, characterized in that it includes an oxide semiconductor layer, a gate insulating film on the oxide semiconductor layer, and a gate electrode on the gate insulating film, The carbon concentration of the oxide semiconductor layer is less than 4×10 21 atoms / cm 3 , The hydrogen concentration in the oxide semiconductor layer is less than 1×10 22 atoms / cm 3 , the channel formation region of the oxide semiconductor layer includes a region where, through a nano-beam electron diffraction pattern, it is observed that instead of having a plurality of spots showing the regularity of crystal parts with a specific plane orientation, the spots are circularly distributed, the channel formation region has a plurality of nanocrystals, the surface orientations of the plurality of nanocrystals are irregular, the respective sizes of the plurality of nanocrystals are less than or equal to 10 nm, the gate insulating film has silicon oxide, As the oxide semiconductor layer, a target having an atomic ratio of In:Ga:Zn = 1:1:1 is used.

9. The transistor according to any one of claims 1-8, characterized in that The nanobeam electron diffraction pattern is observed with an electron beam having a diameter of 1 nm for the illumination beam. ​ 10. The transistor according to any one of claims 1-8, characterized in that the oxide semiconductor layer has a region where no peak caused by the plurality of nanocrystals is observed by XRD measurement.

11. The transistor according to any one of claims 1-8, characterized in that the oxide semiconductor layer has a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer.

12. The transistor according to any one of claims 1-8, characterized in that the respective sizes of the plurality of nanocrystals are greater than or equal to 1 nm and less than or equal to 10 nm.

13. The transistor according to any one of claims 1-8, characterized in that the gate electrode comprises aluminum, chromium, copper, tantalum, titanium, molybdenum or tungsten.

14. The transistor according to any one of claims 1-8, characterized in that it has a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, the source electrode and the drain electrode comprise aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum or tungsten.

15. The transistor according to claim 14, characterized in that the side surface of the oxide semiconductor layer has a region in contact with the source electrode or the drain electrode.

16. A display device, characterized in that it has a first wiring, a second wiring, a third wiring, a first transistor, a second transistor and a light-emitting element, the first wiring is electrically connected to one of the source electrode or the drain electrode of the first transistor, the second wiring is electrically connected to the gate electrode of the first transistor, the other of the source electrode or the drain electrode of the first transistor is electrically connected to the gate electrode of the second transistor, one of the source electrode or the drain electrode of the second transistor is electrically connected to the light-emitting element, the other of the source electrode or the drain electrode of the second transistor is electrically connected to the third wiring, the second transistor comprises an oxide semiconductor layer, a gate insulating film on the oxide semiconductor layer, and a gate electrode of the second transistor on the gate insulating film, the channel formation region of the oxide semiconductor layer comprises a region where, through a nano-beam electron diffraction pattern, a plurality of spots observed are not regularly arranged spots showing a crystal part with a specific plane orientation but are circularly distributed, the channel formation region has a plurality of nanocrystals, the surface orientations of the plurality of nanocrystals are irregular, the respective sizes of the plurality of nanocrystals are less than or equal to 10 nm, as the oxide semiconductor layer, a target with an atomic ratio of In:Ga:Zn = 1:1:1 is used.

17. A display device, characterized in that it has a first wiring, a second wiring, a third wiring, a first transistor, a second transistor and a light-emitting element, the first wiring is electrically connected to one of the source electrode or the drain electrode of the first transistor, the second wiring is electrically connected to the gate electrode of the first transistor, the other of the source electrode or the drain electrode of the first transistor is electrically connected to the gate electrode of the second transistor, one of the source electrode or the drain electrode of the second transistor is electrically connected to the light-emitting element, the other of the source electrode or the drain electrode of the second transistor is electrically connected to the third wiring, the second transistor comprises an oxide semiconductor layer, a gate insulating film on the oxide semiconductor layer, and a gate electrode of the second transistor on the gate insulating film, The carbon concentration of the oxide semiconductor layer is less than 4×10 21 atoms / cm 3 , The channel formation region of the oxide semiconductor layer includes a region in which, as observed by a nano-beam electron diffraction pattern, instead of having a plurality of spots showing the regularity of crystal portions with a specific plane orientation, a plurality of spots are circularly distributed. The channel formation region has a plurality of nanocrystals. The surface orientations of the plurality of nanocrystals are irregular. The respective sizes of the plurality of nanocrystals are less than or equal to 10 nm. As the oxide semiconductor layer, a target having an atomic ratio of In:Ga:Zn = 1:1:1 is used.

18. A display device, characterized in that it includes a first wiring, a second wiring, a third wiring, a first transistor, a second transistor, and a light-emitting element. The first wiring is electrically connected to one of the source electrode or the drain electrode of the first transistor. The second wiring is electrically connected to the gate electrode of the first transistor. The other of the source electrode or the drain electrode of the first transistor is electrically connected to the gate electrode of the second transistor. One of the source electrode or the drain electrode of the second transistor is electrically connected to the light-emitting element. The other of the source electrode or the drain electrode of the second transistor is electrically connected to the third wiring. The second transistor includes an oxide semiconductor layer, a gate insulating film on the oxide semiconductor layer, and a gate electrode of the second transistor on the gate insulating film. The hydrogen concentration in the oxide semiconductor layer is less than 1×10 22 atoms / cm 3 , The channel formation region of the oxide semiconductor layer includes a region in which, as observed by a nano-beam electron diffraction pattern, instead of having a plurality of spots showing the regularity of crystal portions with a specific plane orientation, a plurality of spots are circularly distributed. The channel formation region has a plurality of nanocrystals. The surface orientations of the plurality of nanocrystals are irregular. The respective sizes of the plurality of nanocrystals are less than or equal to 10 nm. As the oxide semiconductor layer, a target having an atomic ratio of In:Ga:Zn = 1:1:1 is used.

19. A display device, characterized in that it includes a first wiring, a second wiring, a third wiring, a first transistor, a second transistor, and a light-emitting element. The first wiring is electrically connected to one of the source electrode or the drain electrode of the first transistor. The second wiring is electrically connected to the gate electrode of the first transistor. The other of the source electrode or the drain electrode of the first transistor is electrically connected to the gate electrode of the second transistor. One of the source electrode or the drain electrode of the second transistor is electrically connected to the light-emitting element. The other of the source electrode or the drain electrode of the second transistor is electrically connected to the third wiring. The second transistor includes an oxide semiconductor layer, a gate insulating film on the oxide semiconductor layer, and a gate electrode of the second transistor on the gate insulating film. The carbon concentration of the oxide semiconductor layer is less than 4×10 21 atoms / cm 3 , The hydrogen concentration in the oxide semiconductor layer is less than 1×10 22 atoms / cm 3 , The channel formation region of the oxide semiconductor layer includes a region in which, as observed by a nano-beam electron diffraction pattern, instead of having a plurality of spots showing the regularity of crystal portions with a specific plane orientation, a plurality of spots are circularly distributed. The channel formation region has a plurality of nanocrystals. The surface orientations of the plurality of nanocrystals are irregular. The respective sizes of the plurality of nanocrystals are less than or equal to 10 nm. As the oxide semiconductor layer, a target material with an atomic ratio of In:Ga:Zn = 1:1:1 is used.

20. A display device, characterized in that it includes a first wiring, a second wiring, a third wiring, a first transistor, a second transistor, a light-emitting element, a scan line driving circuit, and a signal line driving circuit, the first wiring is electrically connected to the signal line driving circuit, the first wiring is electrically connected to one of the source electrode or the drain electrode of the first transistor, the second wiring is electrically connected to the scan line driving circuit, the second wiring is electrically connected to the gate electrode of the first transistor, the other of the source electrode or the drain electrode of the first transistor is electrically connected to the gate electrode of the second transistor, one of the source electrode or the drain electrode of the second transistor is electrically connected to the light-emitting element, the other of the source electrode or the drain electrode of the second transistor is electrically connected to the third wiring, the third wiring has a function as a power supply line, the second transistor includes an oxide semiconductor layer, a gate insulating film on the oxide semiconductor layer, and the gate electrode of the second transistor on the gate insulating film, the channel formation region of the oxide semiconductor layer includes a region where, as observed through a nano-beam electron diffraction pattern, instead of having a plurality of spots showing the regularity of a crystal part with a specific plane orientation, a plurality of spots are circularly distributed, the channel formation region has a plurality of nanocrystals, the surface orientations of the plurality of nanocrystals are irregular, the respective sizes of the plurality of nanocrystals are less than or equal to 10 nm, As the oxide semiconductor layer, a target material with an atomic ratio of In:Ga:Zn = 1:1:1 is used.

21. A display device, characterized in that it includes a first wiring, a second wiring, a third wiring, a first transistor, a second transistor, a light-emitting element, a scan line driving circuit, and a signal line driving circuit, the first wiring is electrically connected to the signal line driving circuit, the first wiring is electrically connected to one of the source electrode or the drain electrode of the first transistor, the second wiring is electrically connected to the scan line driving circuit, the second wiring is electrically connected to the gate electrode of the first transistor, the other of the source electrode or the drain electrode of the first transistor is electrically connected to the gate electrode of the second transistor, one of the source electrode or the drain electrode of the second transistor is electrically connected to the light-emitting element, the other of the source electrode or the drain electrode of the second transistor is electrically connected to the third wiring, the third wiring has a function as a power supply line, the second transistor includes an oxide semiconductor layer, a gate insulating film on the oxide semiconductor layer, and the gate electrode of the second transistor on the gate insulating film, The carbon concentration of the oxide semiconductor layer is less than 4×10 21 atoms / cm 3 , the channel formation region of the oxide semiconductor layer includes a region where, as observed through a nano-beam electron diffraction pattern, instead of having a plurality of spots showing the regularity of a crystal part with a specific plane orientation, a plurality of spots are circularly distributed, the channel formation region has a plurality of nanocrystals, the surface orientations of the plurality of nanocrystals are irregular, the respective sizes of the plurality of nanocrystals are less than or equal to 10 nm, As the oxide semiconductor layer, a target having an atomic ratio of In:Ga:Zn = 1:1:1 is used.

22. A display device, characterized in that it includes a first wiring, a second wiring, a third wiring, a first transistor, a second transistor, a light-emitting element, a scan line driving circuit, and a signal line driving circuit, the first wiring is electrically connected to the signal line driving circuit, the first wiring is electrically connected to one of the source electrode or the drain electrode of the first transistor, the second wiring is electrically connected to the scan line driving circuit, the second wiring is electrically connected to the gate electrode of the first transistor, the other of the source electrode or the drain electrode of the first transistor is electrically connected to the gate electrode of the second transistor, one of the source electrode or the drain electrode of the second transistor is electrically connected to the light-emitting element, the other of the source electrode or the drain electrode of the second transistor is electrically connected to the third wiring, the third wiring has a function as a power supply line, the second transistor includes an oxide semiconductor layer, a gate insulating film on the oxide semiconductor layer, and the gate electrode of the second transistor on the gate insulating film, The hydrogen concentration in the oxide semiconductor layer is less than 1×10 22 atoms / cm 3 , the channel formation region of the oxide semiconductor layer includes a region where, through a nano-beam electron diffraction pattern, instead of having a plurality of spots showing the regularity of a crystal part with a specific plane orientation, a plurality of spots are circularly distributed, the channel formation region has a plurality of nanocrystals, the surface orientations of the plurality of nanocrystals are irregular, the respective sizes of the plurality of nanocrystals are less than or equal to 10 nm, As the oxide semiconductor layer, a target having an atomic ratio of In:Ga:Zn = 1:1:1 is used.

23. A display device, characterized in that it includes a first wiring, a second wiring, a third wiring, a first transistor, a second transistor, a light-emitting element, a scan line driving circuit, and a signal line driving circuit, the first wiring is electrically connected to the signal line driving circuit, the first wiring is electrically connected to one of the source electrode or the drain electrode of the first transistor, the second wiring is electrically connected to the scan line driving circuit, the second wiring is electrically connected to the gate electrode of the first transistor, the other of the source electrode or the drain electrode of the first transistor is electrically connected to the gate electrode of the second transistor, one of the source electrode or the drain electrode of the second transistor is electrically connected to the light-emitting element, the other of the source electrode or the drain electrode of the second transistor is electrically connected to the third wiring, the third wiring has a function as a power supply line, the second transistor includes an oxide semiconductor layer, a gate insulating film on the oxide semiconductor layer, and the gate electrode of the second transistor on the gate insulating film, The carbon concentration of the oxide semiconductor layer is less than 4×10 21 atoms / cm 3 , The hydrogen concentration in the oxide semiconductor layer is less than 1×10 22 atoms / cm 3 , the channel formation region of the oxide semiconductor layer includes a region where, through a nano-beam electron diffraction pattern, instead of having a plurality of spots showing the regularity of a crystal part with a specific plane orientation, a plurality of spots are circularly distributed, the channel formation region has a plurality of nanocrystals, the surface orientations of the plurality of nanocrystals are irregular, the respective sizes of the plurality of nanocrystals are less than or equal to 10 nm, As the oxide semiconductor layer, a target having an atomic ratio of In:Ga:Zn = 1:1:1 is used.

24. A display device, characterized in that it includes a signal line, a scan line, a power supply line, a first transistor, a second transistor, and a light-emitting element, the signal line is electrically connected to one of the source electrode or the drain electrode of the first transistor, the scan line is electrically connected to the gate electrode of the first transistor, the other of the source electrode or the drain electrode of the first transistor is electrically connected to the gate electrode of the second transistor, one of the source electrode or the drain electrode of the second transistor is electrically connected to the light-emitting element, the other of the source electrode or the drain electrode of the second transistor is electrically connected to the power supply line, the second transistor includes an oxide semiconductor layer, a gate insulating film on the oxide semiconductor layer, and a gate electrode of the second transistor on the gate insulating film, the channel formation region of the oxide semiconductor layer includes a region in which, as observed by a nano-beam electron diffraction pattern, instead of having a plurality of spots showing the regularity of a crystal part with a specific plane orientation, a plurality of spots are circularly distributed, the channel formation region has a plurality of nanocrystals, the surface orientations of the plurality of nanocrystals are irregular, the respective sizes of the plurality of nanocrystals are less than or equal to 10 nm, As the oxide semiconductor layer, a target having an atomic ratio of In:Ga:Zn = 1:1:1 is used.

25. A display device, characterized in that it includes a signal line, a scan line, a power supply line, a first transistor, a second transistor, and a light-emitting element, the signal line is electrically connected to one of the source electrode or the drain electrode of the first transistor, the scan line is electrically connected to the gate electrode of the first transistor, the other of the source electrode or the drain electrode of the first transistor is electrically connected to the gate electrode of the second transistor, one of the source electrode or the drain electrode of the second transistor is electrically connected to the light-emitting element, the other of the source electrode or the drain electrode of the second transistor is electrically connected to the power supply line, the second transistor includes an oxide semiconductor layer, a gate insulating film on the oxide semiconductor layer, and a gate electrode of the second transistor on the gate insulating film, The carbon concentration of the oxide semiconductor layer is less than 4×10 21 atoms / cm 3 , the channel formation region of the oxide semiconductor layer includes a region in which, as observed by a nano-beam electron diffraction pattern, instead of having a plurality of spots showing the regularity of a crystal part with a specific plane orientation, a plurality of spots are circularly distributed, the channel formation region has a plurality of nanocrystals, the surface orientations of the plurality of nanocrystals are irregular, the respective sizes of the plurality of nanocrystals are less than or equal to 10 nm, As the oxide semiconductor layer, a target having an atomic ratio of In:Ga:Zn = 1:1:1 is used.

26. A display device, characterized in that it includes a signal line, a scan line, a power supply line, a first transistor, a second transistor, and a light-emitting element, the signal line is electrically connected to one of the source electrode or the drain electrode of the first transistor, the scan line is electrically connected to the gate electrode of the first transistor, The other of the source electrode or the drain electrode of the first transistor is electrically connected to the gate electrode of the second transistor, One of the source electrode or the drain electrode of the second transistor is electrically connected to the light-emitting element, The other of the source electrode or the drain electrode of the second transistor is electrically connected to the power supply line, The second transistor includes an oxide semiconductor layer, a gate insulating film on the oxide semiconductor layer, and a gate electrode of the second transistor on the gate insulating film, The hydrogen concentration in the oxide semiconductor layer is less than 1×10 22 atoms / cm 3 , The channel formation region of the oxide semiconductor layer includes a region where, as observed by a nano-beam electron diffraction pattern, instead of having a plurality of spots showing the regularity of a crystal part with a specific plane orientation, a plurality of spots are circularly distributed, The channel formation region has a plurality of nanocrystals, The surface orientations of the plurality of nanocrystals are irregular, The respective sizes of the plurality of nanocrystals are less than or equal to 10 nm, As the oxide semiconductor layer, a target having an atomic ratio of In:Ga:Zn = 1:1:1 is used.

27. A display device, characterized in that, It has a signal line, a scanning line, a power supply line, a first transistor, a second transistor, and a light-emitting element, The signal line is electrically connected to one of the source electrode or the drain electrode of the first transistor, The scanning line is electrically connected to the gate electrode of the first transistor, The other of the source electrode or the drain electrode of the first transistor is electrically connected to the gate electrode of the second transistor, One of the source electrode or the drain electrode of the second transistor is electrically connected to the light-emitting element, The other of the source electrode or the drain electrode of the second transistor is electrically connected to the power supply line, The second transistor includes an oxide semiconductor layer, a gate insulating film on the oxide semiconductor layer, and a gate electrode of the second transistor on the gate insulating film, The carbon concentration of the oxide semiconductor layer is less than 4×10 21 atoms / cm 3 , The hydrogen concentration in the oxide semiconductor layer is less than 1×10 22 atoms / cm 3 , The channel formation region of the oxide semiconductor layer includes a region where, as observed by a nano-beam electron diffraction pattern, instead of having a plurality of spots showing the regularity of a crystal part with a specific plane orientation, a plurality of spots are circularly distributed, The channel formation region has a plurality of nanocrystals, The surface orientations of the plurality of nanocrystals are irregular, The respective sizes of the plurality of nanocrystals are less than or equal to 10 nm, As the oxide semiconductor layer, a target having an atomic ratio of In:Ga:Zn = 1:1:1 is used.

28. The display device according to any one of claims 16-27, characterized in that, The gate electrode of the second transistor includes aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten.

29. The display device according to any one of claims 16-27, characterized in that, Each of the source electrode and the drain electrode of the second transistor includes aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten.

30. The display device according to claim 29, characterized in that, The side surface of the oxide semiconductor layer has a region in contact with the source electrode or the drain electrode of the second transistor.

31. The display device according to any one of claims 16-27, characterized in that, The respective sizes of the plurality of nanocrystals are greater than or equal to 1 nm and less than or equal to 10 nm.

32. The display device according to any one of claims 16-27, characterized in that The oxide semiconductor layer has a region where no peak caused by the plurality of nanocrystals is observed when measured by XRD.

33. The display device according to any one of claims 16-27, characterized in that The nanobeam electron diffraction pattern is observed by an electron beam with a diameter of 1 nm of the irradiation light beam .

34. The display device according to any one of claims 16-27, characterized in that The oxide semiconductor layer has a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer.

35. The display device according to any one of claims 16-27, characterized in that The gate insulating film has silicon oxide.

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