Stacked package heat transfer system and method

Abstract

Systems and methods are provided for improving thermal distribution and heat removal efficiency in PoP semiconductor packages. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a second semiconductor package in a stack. A gap is formed between an upper surface of the first semiconductor package and a lower surface of the second semiconductor package. Additionally, a void is formed between each PoP semiconductor package disposed on an organic substrate. A curable fluid material, such as a mold compound, can flow in the void space between the PoP semiconductor packages and into the gap between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package.

Description

Technical Field

[0001] This disclosure relates to semiconductor manufacturing and heat transfer within package-on-package semiconductor packages. Background Technology

[0002] Stacked package (PoP) is an integrated circuit packaging technology in which multiple ball grid array (BGA) packages are vertically arranged. PoP packaging advantageously reduces the board area occupied by a single semiconductor package. PoP packaging also minimizes the path length between components that frequently interoperate. Minimizing path length can provide faster signal propagation, reduce noise, and reduce channel crosstalk. In assembly, PoP packaging allows individual components to be tested before stacking rather than after stacking (e.g., chip stacking), and rework is reduced because only known good parts are used in PoP packaging.

[0003] In a typical PoP (PoP) integrated circuit, memory packages are stacked with logic packages (such as System-on-a-Chip (SoC)). Typically, these stacked packages are physically and electrically coupled together through reflow. Since most semiconductor packages generate heat during operation, the heat generated by the semiconductor packages in the stack must be dissipated within a relatively small area. Reduced heat transfer within the PoP package leads to the formation of hot spots within the stack, ultimately causing premature failure of the PoP package. Attached Figure Description

[0004] The features and advantages of various embodiments of the claimed subject matter will become apparent from the following detailed description and with reference to the accompanying drawings, in which similar reference numerals indicate similar parts, and wherein:

[0005] Figure 1 This is a cross-sectional front view of an illustrative stacked package (PoP) semiconductor package according to at least one embodiment described herein, wherein a first semiconductor package and a second semiconductor package are stacked, a gap is formed between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package, and wherein a curable, flowable material, such as a molding compound, flows into the gap to thermally couple the first semiconductor package to the second semiconductor package.

[0006] Figure 2A This is a cross-sectional front view of an illustrative strip comprising a plurality of PoP semiconductor packages separated by a gap space according to at least one embodiment described herein, each of the plurality of PoP semiconductor packages including a corresponding one of a plurality of first semiconductor packages stacked with a corresponding one of a plurality of second semiconductor packages to form a gap therebetween.

[0007] Figure 2BAccording to at least one embodiment described herein Figure 2A The cross-sectional front view of the indicator portion of the semiconductor strip shown more clearly illustrates the cured molding compound present in the gap space between adjacent PoP semiconductor packages and in the gap between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package, which physically and thermally couples each of the plurality of first semiconductor packages to a corresponding one of the plurality of second semiconductor packages.

[0008] Figure 2C It is according to at least one embodiment described herein, such as Figure 2A and Figure 2B A cross-sectional front view of a singulated PoP semiconductor package shown.

[0009] Figure 3 This is a high-level logic flowchart illustrating an illustrative method for manufacturing a PoP semiconductor package with enhanced thermal performance according to at least one embodiment described herein; and

[0010] Figure 4 This is a high-level logic flowchart illustrating an illustrative method for manufacturing multiple PoP semiconductor packages with enhanced thermal performance according to at least one embodiment described herein.

[0011] Although the following detailed implementation is carried out with reference to illustrative embodiments, many alternatives, modifications and variations will be apparent to those skilled in the art. Detailed Implementation

[0012] The systems and methods disclosed herein provide a stacked package (PoP) construction using a material such as molding compound disposed in the gap between the lower surface of an upper semiconductor package and the upper surface of a lower semiconductor package. Such a construction allows for the advantageous use of materials with relatively high thermal conductivity compared to conventional molding compounds. Filling the gap between the upper and lower semiconductor packages provides a thermally efficient stack, which both promotes a more uniform heat distribution across the upper and lower packages and facilitates more efficient heat removal from the bottommost semiconductor package in the stack. Furthermore, using a free-flowing material to fill the gap between the semiconductor packages allows for the use of smaller gaps (e.g., 20 micrometers (μm) to 60 μm) between the upper and lower semiconductor packages. Therefore, the systems and methods described herein offer significant advantages over capillary underfill systems, which require larger gaps between non-monolithic PoP package strips or arrays and tend to detrimentally deposit underfill material in a memory bump field disposed around the periphery of the memory package rather than between the semiconductor packages forming the stack.

[0013] The systems and methods described herein use overmolding or exposed die molding processes to fill the gap between a first (i.e., lower) semiconductor package and a second (i.e., memory or upper) semiconductor package after memory attachment. The second semiconductor package can be attached to the first semiconductor package using strip-level mass reflow or thermoforming bonding. In embodiments, the upper semiconductor package can be smaller in size (i.e., having a smaller surface area than the lower semiconductor package) to provide additional safety margin during individualization or sawing processes. The strip can be molded such that the top of the second semiconductor package remains visible, thereby minimizing the z-height of the resulting PoP package. The top of the memory can be marked, and the PoP package contained within the strip can be individualized.

[0014] Typically, the systems and methods described herein provide greater thermal conductivity in the z-direction than PoP packages with a gap between the upper and lower semiconductor packages. The systems and methods described herein also provide more uniform thermal diffusion across the PoP package. Furthermore, the systems and methods described herein advantageously provide PoP packages with a lower overall z-height than overmolded PoP packages. Moreover, due to the excellent flowability of the molding compound and its ability to flow into a narrower space than in capillary underfill processes, the systems and methods described herein advantageously allow for greater PoP package density on strips.

[0015] A semiconductor stacked packaging system is provided. The system may include: a first package having a top surface and a bottom surface, wherein at least a portion of the top surface of the first package includes an exposed die; and a second package having a top surface and a bottom surface; the second package being communicatively coupled to the first package; wherein a gap exists between the bottom surface of the second package and the top surface of the first package; and wherein the gap is filled with a hardened, flowable material to thermally couple the top surface of the first package to the bottom surface of the second package.

[0016] A method for manufacturing a semiconductor stacked package is provided. The method may include: communicatively coupling a first package and a second package to provide a gap between a lower surface of the second package and an upper surface of the first package, wherein the first package includes an exposed die forming at least a portion of the upper surface of the first package; and allowing material to flow in the gap between the lower surface of the second package and the upper surface of the first package to thermally couple the upper surface of the first package to the lower surface of the second package.

[0017] A method for manufacturing a semiconductor stacked package (PoP) is provided. The method may include: forming a plurality of stacked package semiconductors on a strip by communicatively coupling each of a plurality of first packages to a corresponding one of a plurality of second packages to provide a gap between the lower surface of each of the plurality of second packages and the corresponding one of the plurality of first packages, each of the plurality of PoP semiconductors being separated from adjacent PoP semiconductors by lateral gaps, wherein each of the plurality of first packages includes an exposed die forming at least a portion of the upper surface of the respective package; allowing material to flow in the lateral gaps between each of the plurality of PoP semiconductors and in the gaps between the lower surfaces of each of the plurality of second packages and the upper surfaces of each of the plurality of first packages to thermally couple the upper surface of each of the plurality of first packages to the lower surface of the corresponding one of the plurality of second packages; and individualizing the plurality of PoP semiconductors to provide a plurality of individualized PoP semiconductors.

[0018] An electronic device is provided comprising at least one stacked package (PoP) semiconductor package. The device may include: at least one thermally enhanced semiconductor stacked package system comprising: a first package having a top surface and a bottom surface, wherein at least a portion of the top surface of the first package includes an exposed die; and a second package having a top surface and a bottom surface; the second package being communicatively coupled to the first package; wherein a gap exists between the bottom surface of the second package and the top surface of the first package; and wherein the gap is filled with a hardened, flowable material to thermally couple the top surface of the first package to the bottom surface of the second package.

[0019] A semiconductor stacked package (PoP) manufacturing system with enhanced thermal performance. The system may include: a module for communicatively coupling a first package and a second package to provide a gap between a lower surface of the second package and an upper surface of the first package, wherein the first package includes an exposed die forming at least a portion of the upper surface of the first package; and a module for allowing material to flow in the gap between the lower surface of the second package and the upper surface of the first package to thermally couple the upper surface of the first package to the lower surface of the second package.

[0020] A semiconductor stacked package (PoP) strip manufacturing system is provided. The system may include: a module for communicatively coupling each of a plurality of first packages to a corresponding one of a plurality of second packages to provide a gap between the lower surface of each of the plurality of second packages and the corresponding one of the plurality of first packages; a module for forming a plurality of stacked package semiconductors on the strip, each of the plurality of PoP semiconductors being separated from adjacent PoP semiconductors by lateral gaps, wherein each of the plurality of first packages includes an exposed die forming at least a portion of the upper surface of the corresponding package; a module for allowing material to flow in the lateral gaps between each of the plurality of PoP semiconductors and in the gaps between the lower surfaces of each of the plurality of second packages and the upper surfaces of each of the plurality of first packages to thermally couple the upper surface of each of the plurality of first packages to the lower surface of the corresponding one of the plurality of second packages; and a module for individualizing the plurality of PoP semiconductors to provide a plurality of individualized PoP semiconductors.

[0021] As used herein, when used in association with one or more elements, the terms “top,” “bottom,” “lowest,” and “highest” are intended to convey a relative rather than an absolute physical configuration. Thus, when the device is inverted, an element described as the “topmost element” or “top element” in the device may alternatively form the “bottommost element” or “bottom element” in the device. Similarly, when the device is inverted, an element described as the “bottommost element” or “bottom element” in the device may alternatively form the “topmost element” or “top element” in the device.

[0022] As used herein, the term "logically related" when used with reference to multiple objects, systems, or elements is intended to convey the existence of a relationship between the objects, systems, or elements such that access to one object, system, or element reveals other objects, systems, or elements that are "logically related" to or to the accessed object, system, or element. An exemplary "logical relationship" exists between relational databases, where access to an element in a first database can provide information and / or data from one or more elements in multiple additional databases, each with an identified relationship to the accessed element. In another example, if "A" is logically related to "B," then accessing "A" will reveal or otherwise extract information and / or data from "B," and vice versa.

[0023] Figure 1This is a cross-sectional front view of an illustrative stacked package (PoP) semiconductor package 100 according to at least one embodiment described herein, wherein a first semiconductor package 110 and a second semiconductor package 150 are stacked, forming a gap or void between the upper surface 132 of the first semiconductor package 110 and the lower surface 162 of the second semiconductor package 150, and wherein molding compound 102 is allowed to flow into the gap to thermally couple the first semiconductor package 110 to the second semiconductor package 150. The disclosed PoP package, including the non-overmolded second semiconductor package 150, advantageously reduces the overall z-height 104 of the PoP package 100, thereby facilitating a thinner electronic device housing. Additionally, the PoP package as described herein advantageously reduces the required board area, thereby facilitating a smaller electronic device housing.

[0024] The first semiconductor package 110 may include a stacked die semiconductor package, which includes any number of stacked semiconductor dies 120A-120n (collectively referred to as "semiconductor dies 120"). Figure 1 As shown, the first semiconductor package 110 includes a first semiconductor die 120A and a second semiconductor die 120B. In some embodiments, the first semiconductor package 110 may include a stacked die-semiconductor package in which the top or uppermost semiconductor die 120n is at least partially exposed (i.e., a bare die-semiconductor package). In some embodiments, the first semiconductor package 110 may include an overmolded stacked die-semiconductor package. The first semiconductor package 110 includes a substrate 112 having any number of layers, the layers including one or more conductive traces 114, on which semiconductor dies 120 are physically mounted, and at least some of the semiconductor dies 120 are communicatively and electrically coupled to the one or more conductive traces 114.

[0025] The second semiconductor package 150 may also include a stacked die semiconductor package, which includes any number of stacked semiconductor dies 160A-160n (collectively referred to as "semiconductor die 160"). Figure 1 As shown, the second semiconductor package 150 includes a first semiconductor die 160A stacked with a second semiconductor die 160B. A plurality of conductors 164 (bond wires, solder bumps, etc.) connect the first semiconductor die 160A to conductive pads 154 disposed on a substrate 152 of the second semiconductor package 150. Similarly, a plurality of conductors 166 (bond wires, solder bumps, etc.) communicatively couple the second semiconductor die 160B to the conductive pads 154 disposed on the substrate 152 of the second semiconductor package 150. In an embodiment, the second semiconductor package 150 may be partially or completely encapsulated in a molding compound 180. Although not explicitly stated... Figure 1In one embodiment, the second semiconductor package 150 may include an exposed die semiconductor package, wherein the second semiconductor die 160B forms at least a portion of the upper surface of the second semiconductor package 150.

[0026] The first semiconductor package 110 and the second semiconductor package 150 use multiple conductive structures to be electrically and communicatively coupled. For example... Figure 1 As shown, a plurality of solder balls 144 may be disposed on a plurality of corresponding pads 142 disposed in, on, or around the first semiconductor package substrate 112, and a plurality of solder balls 156 may be disposed on a plurality of corresponding conductive pads 154 disposed in, on, or around the second semiconductor package substrate 152. In an embodiment, reflow or a similar process may be used to conductively couple the first semiconductor package 110 to the second semiconductor package 150 via the solder balls 144 and 156. After coupling the first semiconductor package 110 to the second semiconductor package 150, a gap exists between the upper surface 132 of the first semiconductor package 110 and the lower surface 162 of the second semiconductor package 150.

[0027] In the unfilled state, the gas-filled gap between the first semiconductor package 110 and the second semiconductor package 150 restricts heat transfer from the first semiconductor package 110 to the second semiconductor package 150. Allowing molding compound 102 to flow into the gap such that, upon curing, the molding compound 102, thermally coupling the first semiconductor package 110 to the second semiconductor package 150, advantageously improves the heat distribution across the upper surface 132 of the first semiconductor package 110 and advantageously increases heat transfer from the first semiconductor package 110 to the second semiconductor package 150. In an embodiment, the molding compound 102 may have a higher thermal conductivity than the molding compound 180 used to encapsulate the second semiconductor package 150 to further enhance heat transfer from the first semiconductor package 110 and heat distribution across the upper surface 132 of the first semiconductor package 110.

[0028] The first semiconductor package 110 may include any number and / or combination of semiconductor dies 120A-120n. In embodiments, the semiconductor die 120 forming the first semiconductor package 110 may include: a system-in-package (SiP); a system-on-a-chip (SoC); an application-specific integrated circuit (ASIC); a reduced instruction set computer (RISC); a digital signal processor (DSP); a programmable gate array (PGA); or any other device, a collection of devices and / or systems capable of executing machine-readable instructions and accessing one or more storage devices. The first semiconductor package 110 may have any physical size, shape, or configuration.

[0029] like Figure 1As shown, in one embodiment, a bare die molding process can be used to manufacture the first semiconductor package 110, wherein the semiconductor die 120 is surrounded by molding compound 140. In such an embodiment, the uppermost semiconductor die 120n remains at least partially exposed after the molding compound 140 has cured, thereby forming a portion of the upper surface 132 of the first semiconductor package 110.

[0030] The second semiconductor package 150 may include any number and / or combination of semiconductor dies 160A-160n. In embodiments, the semiconductor dies 160 forming the second semiconductor package 150 may include, but are not limited to: low-power double data rate (LPDDR1, LPDDR2, LPDDR3, LPDDR4) random access memory; low-power standard data rate (LPSDR) random access memory; 3D NAND; universal flash memory (UFS); embedded multimedia controller (e.MMC); or combinations thereof. The second semiconductor package 150 may have any physical size, shape, or configuration. In some embodiments, the second semiconductor package 150 may occupy a smaller physical area than the first semiconductor package 110. For example, the surface area of ​​the lower surface 162 of the second semiconductor package 150 may be smaller than the surface area of ​​the upper surface 132 of the first semiconductor package 110. The first semiconductor package 110 and the second semiconductor package 150 may be physically, communicatively, and electrically coupled using a combination of mass reflow or thermocompression. Exemplary mass reflow techniques include, but are not limited to: forced convection; infrared radiation; vapor phase; laser; hot rod; or any combination thereof.

[0031] The molding compound 102 disposed in the gap between the first semiconductor package 110 and the second semiconductor package 150 may comprise any material or combination of materials. In embodiments, the molding compound may comprise at least one of the following: one or more elastomers, one or more thermoplastics, one or more thermosetting plastics, one or more silicone molding compounds, or combinations thereof. Exemplary elastomers include, but are not limited to: silicone resins, polyurethanes, chloroprene, butyl, polybutadiene, chloroprene rubber, natural rubber, or isoprene, and other synthetic rubbers or compounds. The molding compound 102 may be a composite material comprising a combination of epoxy resin, phenolic curing agent, silica, catalyst, pigment, and release agent. In some embodiments, the molding compound 102 may comprise one or more materials capable of increasing thermal conductivity (k, watts per meter Kelvin, W / (m·K)). In some embodiments, the molding compound 102 may have a higher thermal conductivity than the molding compound 180 used to encapsulate the second semiconductor package 150.

[0032] Figure 2A It includes a plurality of PoP semiconductor packages 1001-100 according to at least one embodiment described herein. nA cross-sectional front view of illustrative strip 200A (collectively referred to as "PoP semiconductor package 100"), each of the plurality of PoP semiconductor packages including a plurality of first semiconductor packages 1101-110. n One of the corresponding ones (collectively referred to as "first semiconductor package 110"), which is associated with a plurality of second semiconductor packages 1501-150 n A corresponding stack in (collectively referred to as "second semiconductor package 150"). Figure 2B According to at least one embodiment described herein Figure 2A The cross-sectional front view of the indicator portion of the semiconductor strip shown more clearly illustrates the cured molding compound 220 present in the gap or space between each of the first semiconductor package 110 and the second semiconductor package 150, which physically and thermally couples each of the plurality of first semiconductor packages 110 to a corresponding one of the plurality of second semiconductor packages 150. Figure 2C It is according to at least one embodiment described herein, such as Figure 2A and Figure 2B The image shows a cross-sectional front view of the individualized PoP semiconductor package 100.

[0033] In an embodiment, the first semiconductor package 110 may be disposed on all or a portion of the panel, or on all or a portion of the panel 230 that provides a substrate 112 for each PoP semiconductor package 100. Figure 2A-2C As shown, liquid or fluid molding compound 220 (flowing between molding compounds 220) is introduced into the space between semiconductor packages 100 on the strip and flows around and between the semiconductor packages, and flows into the gap between the first semiconductor package 110 and the second semiconductor package 150. In one embodiment, the molding compound 220 may cover or overmold the second semiconductor package 150. In other embodiments, the molding compound 220 may be disposed substantially flush with the upper surface of the second semiconductor package 150, leaving the upper surface of the second semiconductor package 150 to form at least a portion of the completed PoP semiconductor package 100. Allowing the upper surface of the second semiconductor package 150 to remain exposed advantageously provides guide lines for sawing or individualizing the PoP semiconductor package 100.

[0034] In embodiments, the molding compound 220 may be selected in part based on the flowability and / or surface tension of the uncured fluid molding compound 220. This allows the fluid molding compound to permeate the gap between the first semiconductor package 110 and the second semiconductor package 150 and fill the void spaces between each PoP semiconductor package 100 on the strip. After curing, the molding compound 220 protectively encapsulates the periphery of the PoP semiconductor package 100 and helps to physically couple the first semiconductor package 110 to the second semiconductor package 150. In embodiments, after the molding compound 220 is disposed between the first semiconductor package 110 and the second semiconductor package 150 and between the PoP semiconductor packages 100 on the strip 230, the PoP semiconductor packages 100 may be individualized, for example, along the dicing line 210.

[0035] Figure 3 This is a high-level logic flowchart of an illustrative method 300 for manufacturing a PoP semiconductor package 100 with enhanced thermal performance according to at least one embodiment described herein. The PoP semiconductor package 100 includes a first semiconductor package 110 and a stacked second semiconductor package 150, having a gap of approximately 20 nanometers to 60 nanometers separating an upper surface 132 of the first semiconductor package 110 from a lower surface 162 of the second semiconductor package 150. The first semiconductor package 110 may include an exposed die semiconductor package. Molding plastic 102 flows into the gap between the first semiconductor package 110 and the second semiconductor package 150. The cured molding plastic 102 distributes heat generated by hot spots on the upper surface 132 of the first semiconductor package 110 across the xy plane formed by the upper surface of the first semiconductor package 110. The cured molding plastic further facilitates the transfer of heat generated by the first semiconductor package 110 to the second semiconductor package 150 and then to the environment surrounding the PoP semiconductor package 100. Method 300 begins at 302.

[0036] At 304, the first semiconductor package 110 is electrically and communicatively coupled to the second semiconductor package 150. In some embodiments, the first semiconductor package 110 and the second semiconductor package 150 may be electrically coupled using solder balls and a reflow process. In one embodiment, the first semiconductor package 110 may include a system-on-a-chip (SoC) with a die stack, wherein the uppermost die 120B remains exposed (i.e., a bare die package). In another embodiment, the second semiconductor package 150 may include a memory package having a die stack enclosed in a molding compound 180. After coupling the first semiconductor package 110 to the second semiconductor package 150, a gap of approximately 20 nanometers (nm) to approximately 60 nm is created between the upper surface 132 of the first semiconductor package 110 and the lower surface 162 of the second semiconductor package 150.

[0037] At 306, fluid material such as uncured molding compound 102 flows into the gap formed by the upper surface 132 of the first semiconductor package 110 and the lower surface 162 of the second semiconductor package 150. The cured molding compound 102 advantageously physically couples the first semiconductor package 110 to the second semiconductor package 150, thereby improving the physical integrity of the PoP semiconductor package 100. The cured molding compound 102 also advantageously improves the heat distribution across the upper surface 132 of the first semiconductor package 110. The cured molding compound 102 also improves the transfer of heat generated by the first semiconductor package 110 to the second semiconductor package 150. Method 300 ends at 308.

[0038] Figure 4 This is a high-level logic flowchart of an illustrative method 400 for manufacturing multiple PoP semiconductor packages 100A-100n with enhanced thermal performance, according to at least one embodiment described herein. Each of the multiple PoP semiconductor packages 100 includes a first semiconductor package 110 and a stacked second semiconductor package 150, having a gap separating the upper surface 132 of the first semiconductor package 110 from the lower surface 162 of the second semiconductor package 150 by approximately 20 nanometers to 60 nanometers. In embodiments, the multiple PoP semiconductor packages 100 can be fabricated on a substrate such as an organic substrate 230. The use of a fluid material such as an uncured molding compound 220 allows each PoP semiconductor package 100 to be placed close to adjacent PoP semiconductor packages, as the fluid molding compound is able to permeate the relatively small void spaces or gaps between the PoP semiconductor packages and the gap between the first semiconductor package 110 and the second semiconductor package 150 in each PoP semiconductor package 100. After curing the molding compound 220, the multiple PoP semiconductor packages 100 can be individualized. Method 400 begins at 402.

[0039] At location 404, a plurality of PoP semiconductor packages 100A-100n are formed on substrate 230. Substrate 230 may include an organic substrate having multiple conductive layers and dielectric layers. Each of the plurality of PoP semiconductor packages 100 is separated from the adjacent PoP semiconductor package by a void space or gap.

[0040] At 406, each PoP semiconductor package 100 is formed by communicatively and electrically coupling a first semiconductor package 110 to a second semiconductor package 150. In some embodiments, the first semiconductor package 110 and the second semiconductor package 150 may be electrically coupled using solder balls and a reflow process. In one embodiment, the first semiconductor package 110 may include a system-on-a-chip (SoC) with a die stack, wherein the uppermost die 120B remains exposed (i.e., a bare die package). In another embodiment, the second semiconductor package 150 may include a memory package having a die stack enclosed in a molding compound 180. After coupling the first semiconductor package 110 to the second semiconductor package 150, a gap of approximately 20 nanometers (nm) to approximately 60 nm is created between the upper surface 132 of the first semiconductor package 110 and the lower surface 162 of the second semiconductor package 150.

[0041] At 408, fluid material, such as uncured molding compound 220, flows into the void space between each PoP semiconductor package 100 and into the gap formed by the upper surface 132 of the first semiconductor package 110 and the lower surface 162 of the second semiconductor package 150 in each of the plurality of PoP semiconductor packages 100.

[0042] In one embodiment, the upper surface of the cured molding compound 220 may be flush with the upper surface of the second semiconductor package 150, such that the upper surface of the second semiconductor package 150 forms part of the upper surface of the PoP semiconductor package 100. In other embodiments, the upper surface of the cured molding compound 220 may cover the upper surface of the second semiconductor package 150, thereby sealing the PoP semiconductor package 100.

[0043] The cured molding compound 102 advantageously physically couples the first semiconductor package 110 to the second semiconductor package 150, thereby improving the physical integrity of the PoP semiconductor package 100. The cured molding compound 102 also advantageously improves the heat distribution across the upper surface 132 of the entire first semiconductor package 110. The cured molding compound 102 further improves the transfer of heat generated by the first semiconductor package 110 to the second semiconductor package 150. Method 300 ends at 308.

[0044] At 410, a plurality of PoP semiconductor packages 100A-100n disposed across the surface of the substrate 230 strip are separated, for example, by sawing or similar cutting equipment, to provide a plurality of individual PoP semiconductor packages 100. In an embodiment, with the second semiconductor package 150 remaining exposed (i.e., with the upper surface of the cured molding compound 220 at or below the level of the upper surface of the second semiconductor package 150), the second semiconductor package 150 provides guidance for individualizing the PoP semiconductor package 100. Method 400 ends at 412.

[0045] Although Figure 3 and 4 Various operations according to one or more embodiments are illustrated, but it should be understood that not all are included. Figure 3 and 4 The operations shown are necessary for other embodiments. In fact, other embodiments of this disclosure are fully contemplated herein. Figure 3 and 4 The operations shown and / or other operations described herein may be combined in ways not specifically shown in any of the accompanying drawings, but still fully comply with this disclosure. Therefore, claims relating to features and / or operations not precisely shown in a single drawing are considered to be within the scope and content of this disclosure.

[0046] As used in this application and claims, a list of items connected by the term "and / or" can represent any combination of the listed items. For example, the phrase "A, B and / or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C. As used in this application and claims, a list of items connected by the term "at least one" can represent any combination of the listed items. For example, the phrase "at least one of A, B or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C.

[0047] As used in any embodiment herein, the terms “system” or “module” can refer to, for example, software, firmware, and / or circuitry configured to perform any of the foregoing operations. Software can be embodied as software packages, code, instructions, instruction sets, and / or data recorded on a non-transitory computer-readable storage medium. Firmware can be embodied as hard-coded (e.g., non-volatile) code, instructions, or instruction sets and / or data in a memory device. As used in any embodiment herein, “circuitry” can include, for example, hardwired circuitry, either alone or in any combination, programmable circuitry such as a computer processor including one or more separate instruction processing cores, state machine circuitry, and / or firmware storing instructions or future computing paradigms executed by the programmable circuitry, including, for example, massively parallel, analog, or quantum computing, hardware embodiments of accelerators such as neural network processors, and the non-silicon implementations described above. The circuitry can be embodied collectively or individually as part of a larger system, such as an integrated circuit (IC), a system-on-a-chip (SoC), a desktop computer, a laptop computer, a tablet computer, a server, a smartphone, etc.

[0048] Any operation described herein can be implemented in a system comprising one or more media (e.g., non-transitory storage media) wherein instructions, individually or in combination, are stored, which, when executed by one or more processors, perform the method. Here, the processor may include, for example, a server CPU, a mobile device CPU, and / or other programmable circuitry. Moreover, it is intended that the operations described herein can be distributed across multiple physical devices, such as processing architectures located in more than one different physical location. The storage medium may include any type of physical medium, such as any type of disk including hard disks, floppy disks, optical disks, optical disc read-only memory (CD-ROM), rewritable optical discs (CD-RW), and magneto-optical disks; semiconductor devices such as read-only memory (ROM), random access memory (RAM) (such as dynamic and static RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, solid-state drives (SSDs), embedded multimedia cards (eMMC), secure digital input / output (SDIO) cards, magnetic cards, or optical cards; or any type of medium suitable for storing electronic instructions. Other embodiments may be implemented as software executed by a programmable control device.

[0049] Therefore, this disclosure relates to systems and methods for improving heat distribution and heat removal efficiency in a PoP semiconductor package. The PoP semiconductor package includes a first semiconductor package physically, communicatively, and electrically coupled to a stack of second semiconductor packages. The first semiconductor package may include a die stack in which the uppermost die remains exposed (i.e., the first semiconductor package may be a bare die package). The second semiconductor package may include a die stack in which all dies are encapsulated in molding compound. A gap is formed between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package. Additionally, a void is formed between each PoP semiconductor package disposed on an organic substrate. Fluid-uncured molding compound can flow in the void space between the PoP semiconductor packages and into the gap between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package. The substrate containing multiple PoP semiconductor packages can be individualized to provide multiple individual PoP semiconductor packages. The presence of cured molding compound in the gap between the first and second semiconductor packages advantageously and beneficially distributes heat across the entire upper surface of the first semiconductor package and enhances thermal flow from the first semiconductor package to the second semiconductor package.

[0050] The following examples relate to further embodiments. Examples of this disclosure may include subject matter such as at least one device, method, at least one machine-readable medium for storing instructions (which, when executed, cause a machine to perform operations based on the method), and modules for performing operations based on a method and / or system for improving and enhancing lateral heat distribution across the entire upper surface of a first semiconductor package in a PoP semiconductor package, and improving and enhancing heat flow from the first semiconductor package to a second semiconductor package within the PoP semiconductor package.

[0051] According to Example 1, a semiconductor stacked packaging system with enhanced thermal performance is provided. The system may include: a first package having a top surface and a bottom surface, wherein at least a portion of the top surface of the first package includes an exposed die; and a second package having a top surface and a bottom surface; the second package being communicatively coupled to the first package; wherein a gap exists between the bottom surface of the second package and the top surface of the first package; and wherein the gap is filled with a hardened, flowable material to thermally couple the top surface of the first package to the bottom surface of the second package.

[0052] Example 2 may include elements of Example 1, wherein at least one first semiconductor package includes a die stack, and wherein at least a portion of the top surface of the first package may include the uppermost exposed die in the die stack.

[0053] Example 3 may include elements of Example 2, wherein at least one first semiconductor package includes a system-on-a-chip (SoC).

[0054] Example 4 may include elements of Example 3, wherein the second package includes one or more memory dies encapsulated in a molding compound having a first thermal conductivity.

[0055] Example 5 may include the elements of Example 4, wherein the hardened flowable material comprises a non-conductive material having a second thermal conductivity greater than the first thermal conductivity.

[0056] Example 6 may include elements of Example 1, wherein, in operation, the thermal output of the first package exceeds the thermal output of the second package.

[0057] Example 7 may include elements of Example 1, wherein the top surface of the first package includes a surface having a first area, and the bottom surface of the second package includes a surface having a second area, the second area being smaller than the first area.

[0058] According to Example 8, a method for manufacturing a semiconductor stacked package with enhanced thermal performance is provided. The method may include: communicatively coupling a first package and a second package to provide a gap between a lower surface of the second package and an upper surface of the first package, wherein the first package includes an exposed die forming at least a portion of the upper surface of the first package; and allowing material to flow in the gap between the lower surface of the second package and the upper surface of the first package to thermally couple the upper surface of the first package to the lower surface of the second package.

[0059] Example 9 may include elements of Example 8, wherein communicatively coupling the first package and the second package to provide a gap between the lower surface of the second package and the upper surface of the first package may include: communicatively coupling the first package and the second package to provide a gap between the lower surface of the second package and the upper surface of the first package; wherein the first package includes a die stack; and wherein the exposed die forming at least a portion of the upper surface of the first package includes the uppermost die in the die stack.

[0060] Example 10 may include elements of Example 9, wherein communicatively coupling the first package and the second package to provide a gap between the lower surface of the second package and the upper surface of the first package may include: communicatively coupling the first package and the second package to provide a gap between the lower surface of the second package and the upper surface of the first package; wherein the first package includes a system-on-a-chip (SoC).

[0061] Example 11 may include elements of Example 10, wherein communicatively coupling the first package and the second package to provide a gap between the lower surface of the second package and the upper surface of the first package may include: communicatively coupling the first package and the second package to provide a gap between the lower surface of the second package and the upper surface of the first package; wherein the second package includes one or more memory dies encapsulated in a molding compound having a first thermal conductivity.

[0062] Example 12 may include elements of Example 8, wherein causing material to flow in the gap between the lower surface of the second package and the upper surface of the first package may include: causing material to flow in the gap between the lower surface of the second package and the upper surface of the first package, wherein the material comprises a non-conductive material having a second thermal conductivity greater than the first thermal conductivity.

[0063] Example 13 may include elements of Example 8, wherein communicatively coupling the first package and the second package to provide a gap between the lower surface of the second package and the upper surface of the first package may include: communicatively coupling the first package and the second package to provide a gap between the lower surface of the second package and the upper surface of the first package; wherein the top surface of the first package includes a surface having a first area, and the bottom surface of the second package includes a surface having a second area, the second area being smaller than the first area.

[0064] According to Example 14, a method for manufacturing a semiconductor stacked package with enhanced thermal performance is provided, which may include: forming a plurality of stacked package semiconductors on a strip by communicatively coupling each of a plurality of first packages to a corresponding one of a plurality of second packages to provide a gap between the lower surface of each of the plurality of second packages and the corresponding one of the plurality of first packages, each of the plurality of PoP semiconductors being separated from an adjacent PoP semiconductor by a lateral gap, wherein each of the plurality of first packages includes an exposed die forming at least a portion of the upper surface of the respective package; allowing material to flow in the lateral gaps between each of the plurality of PoP semiconductors and in the gaps between the lower surfaces of each of the plurality of second packages and the upper surfaces of each of the plurality of first packages to thermally couple the upper surfaces of each of the plurality of first packages to the lower surface of the corresponding one of the plurality of second packages; and individualizing the plurality of PoP semiconductors to provide a plurality of individualized PoP semiconductors.

[0065] Example 15 may include elements of Example 14, wherein communicatively coupling each of a plurality of first packages to a corresponding one of a plurality of second packages to provide a gap between the lower surface of each of the plurality of second packages and the corresponding one of the plurality of first packages may include: communicatively coupling each of the plurality of first packages to a corresponding one of the plurality of second packages to provide a gap between the lower surface of each of the plurality of second packages and the corresponding one of the plurality of first packages; wherein each of the plurality of first packages includes a die stack; and wherein the exposed die forming at least a portion of the upper surface of each of the plurality of first packages includes the uppermost die in the die stack.

[0066] Example 16 may include elements of Example 15, wherein communicatively coupling each of a plurality of first packages to a corresponding one of a plurality of second packages to provide a gap between the lower surface of each of the plurality of second packages and the corresponding one of the plurality of first packages may include: communicatively coupling each of a plurality of first packages to a corresponding one of a plurality of second packages to provide a gap between the lower surface of each of the plurality of second packages and the corresponding one of the plurality of first packages; wherein each of the plurality of first packages includes a system-on-a-chip (SoC).

[0067] Example 17 may include elements of Example 16, wherein communicatively coupling each of a plurality of first packages to a corresponding one of a plurality of second packages to provide a gap between the lower surface of each of the plurality of second packages and the corresponding one of the plurality of first packages may include: communicatively coupling each of a plurality of first packages to a corresponding one of a plurality of second packages to provide a gap between the lower surface of each of the plurality of second packages and the corresponding one of the plurality of first packages; wherein each of the plurality of second packages includes one or more memory dies encapsulated in a molding compound having a first thermal conductivity.

[0068] Example 18 may include elements of Example 14, wherein flowing material in the gap between the lower surface of each of the plurality of second packages and the upper surface of each of the plurality of first packages to thermally couple the upper surface of each of the plurality of first packages to the lower surface of a corresponding one of the plurality of second packages comprises: flowing material in the gap between the lower surface of each of the plurality of second packages and the upper surface of each of the plurality of first packages to thermally couple the upper surface of each of the plurality of first packages to the lower surface of a corresponding one of the plurality of second packages; wherein the material comprises a non-conductive material having a second thermal conductivity greater than the first thermal conductivity.

[0069] Example 19 may include elements of Example 14, wherein communicatively coupling each of a plurality of first packages to a corresponding one of a plurality of second packages to provide a gap between the lower surface of each of the plurality of second packages and the corresponding one of the plurality of first packages may include: wherein communicatively coupling each of the plurality of first packages to a corresponding one of the plurality of second packages to provide a gap between the lower surface of each of the plurality of second packages and the corresponding one of the plurality of first packages; wherein each of the upper surfaces of the plurality of first packages includes a surface having a first area, and each of the lower surfaces of the plurality of second packages includes a surface having a second area, the second area being smaller than the first area.

[0070] According to Example 20, an electronic device is provided. The device may include: at least one semiconductor stacked package system with enhanced thermal performance, comprising: a first package having a top surface and a bottom surface, wherein at least a portion of the top surface of the first package includes an exposed die; and a second package having a top surface and a bottom surface; the second package being communicatively coupled to the first package; wherein a gap exists between the bottom surface of the second package and the top surface of the first package; and wherein the gap is filled with a hardened, flowable material to thermally couple the top surface of the first package to the bottom surface of the second package.

[0071] Example 21 may include elements of Example 20, wherein at least one first package includes a die stack, and wherein at least a portion of the top surface of the first package includes the uppermost exposed die in the die stack.

[0072] Example 22 may include elements of Example 20, wherein at least one first package includes a system-on-a-chip (SoC).

[0073] Example 23 may include elements of Example 22, wherein the second package may include one or more memory dies encapsulated in a molding compound having a first thermal conductivity.

[0074] Example 24 may include elements of Example 23, wherein the hardened flowable material comprises a non-conductive material having a second thermal conductivity greater than the first thermal conductivity.

[0075] Example 25 may include elements of Example 20, wherein, in operation, the thermal output of the first package exceeds the thermal output of the second package.

[0076] Example 26 may include elements of Example 20, wherein the top surface of the first package includes a surface having a first area, and the bottom surface of the second package includes a surface having a second area, the second area being smaller than the first area.

[0077] Example 27 may include elements of Example 20, wherein the electronic device includes a portable electronic device selected from the group consisting of: smartphones, wearable processor-based devices, handheld processor-based devices, and portable gaming systems.

[0078] According to Example 28, a semiconductor stacked package manufacturing system with enhanced thermal performance is provided. The system may include: a module for communicatively coupling a first package and a second package to provide a gap between a lower surface of the second package and an upper surface of the first package, wherein the first package includes an exposed die forming at least a portion of the upper surface of the first package; and a module for allowing material to flow in the gap between the lower surface of the second package and the upper surface of the first package to thermally couple the upper surface of the first package to the lower surface of the second package.

[0079] Example 29 may include elements of Example 28, wherein the module for communicatively coupling the first package and the second package to provide a gap between the lower surface of the second package and the upper surface of the first package may include: a module for communicatively coupling the first package and the second package to provide a gap between the lower surface of the second package and the upper surface of the first package; wherein the first package includes a die stack; and wherein the exposed die forming at least a portion of the upper surface of the first package includes the uppermost die in the die stack.

[0080] Example 30 may include elements of Example 29, wherein the module for communicatively coupling the first package and the second package to provide a gap between the lower surface of the second package and the upper surface of the first package may include: a module for communicatively coupling the first package and the second package to provide a gap between the lower surface of the second package and the upper surface of the first package; wherein the first package includes a system-on-a-chip (SoC).

[0081] Example 31 may include elements of Example 30, wherein the module for communicatively coupling the first package and the second package to provide a gap between the lower surface of the second package and the upper surface of the first package may include: a module for communicatively coupling the first package and the second package to provide a gap between the lower surface of the second package and the upper surface of the first package; wherein the second package includes one or more memory dies encapsulated in a molding compound having a first thermal conductivity.

[0082] Example 32 may include elements of Example 28, wherein the module for allowing material to flow in the gap between the lower surface of the second package and the upper surface of the first package may include: a module for allowing material to flow in the gap between the lower surface of the second package and the upper surface of the first package, wherein the material comprises a non-conductive material having a second thermal conductivity greater than the first thermal conductivity.

[0083] Example 33 may include elements of Example 28, wherein communicatively coupling the first package and the second package to provide a gap between the lower surface of the second package and the upper surface of the first package includes: a module for communicatively coupling the first package and the second package to provide a gap between the lower surface of the second package and the upper surface of the first package; wherein the top surface of the first package includes a surface having a first area, and the bottom surface of the second package includes a surface having a second area, the second area being smaller than the first area.

[0084] According to Example 34, a semiconductor stacked package manufacturing system with enhanced thermal performance is provided. The system may include: a module for communicatively coupling each of a plurality of first packages to a corresponding one of a plurality of second packages to provide a gap between the lower surface of each of the plurality of second packages and the corresponding one of the plurality of first packages; a module for forming a plurality of stacked package semiconductors on a strip, each of the plurality of PoP semiconductors being separated from an adjacent PoP semiconductor by a lateral gap, wherein each of the plurality of first packages includes an exposed die forming at least a portion of the upper surface of the corresponding package; a module for allowing material to flow in the lateral gaps between each of the plurality of PoP semiconductors and in the gaps between the lower surfaces of each of the plurality of second packages and the upper surfaces of each of the plurality of first packages to thermally couple the upper surface of each of the plurality of first packages to the lower surface of the corresponding one of the plurality of second packages; and a module for individualizing the plurality of PoP semiconductors to provide a plurality of individualized PoP semiconductors.

[0085] Example 35 may include elements of Example 34, wherein the module for communicatively coupling each of the plurality of first packages to a corresponding one of the plurality of second packages to provide a gap between the lower surface of each of the plurality of second packages and the corresponding one of the plurality of first packages may include: a module for communicatively coupling each of the plurality of first packages to a corresponding one of the plurality of second packages to provide a gap between the lower surface of each of the plurality of second packages and the corresponding one of the plurality of first packages; wherein each of the plurality of first packages includes a die stack; and wherein the exposed die forming at least a portion of the upper surface of each of the plurality of first packages includes the uppermost die in the die stack.

[0086] Example 36 may include elements of Example 35, wherein the module for communicatively coupling each of the plurality of first packages to a corresponding one of the plurality of second packages to provide a gap between the lower surface of each of the plurality of second packages and the corresponding one of the plurality of first packages may include: a module for communicatively coupling each of the plurality of first packages to a corresponding one of the plurality of second packages to provide a gap between the lower surface of each of the plurality of second packages and the corresponding one of the plurality of first packages; wherein each of the plurality of first packages includes a system-on-a-chip (SoC).

[0087] Example 37 may include elements of Example 36, wherein the module for communicatively coupling each of the plurality of first packages to a corresponding one of the plurality of second packages to provide a gap between the lower surface of each of the plurality of second packages and the corresponding one of the plurality of first packages may include: a module for communicatively coupling each of the plurality of first packages to a corresponding one of the plurality of second packages to provide a gap between the lower surface of each of the plurality of second packages and the corresponding one of the plurality of first packages; wherein each of the plurality of second packages includes one or more memory dies encapsulated in a molding compound having a first thermal conductivity.

[0088] Example 38 may include elements of Example 34, wherein the module for allowing material to flow in the gap between the lower surface of each of the plurality of second packages and the upper surface of each of the plurality of first packages to thermally couple the upper surface of each of the plurality of first packages to the lower surface of a corresponding one of the plurality of second packages may include: a module for allowing material to flow in the gap between the lower surface of each of the plurality of second packages and the upper surface of each of the plurality of first packages to thermally couple the upper surface of each of the plurality of first packages to the lower surface of a corresponding one of the plurality of second packages; wherein the material comprises a non-conductive material having a second thermal conductivity greater than the first thermal conductivity.

[0089] Example 39 may include elements of Example 34, wherein the module for communicatively coupling each of the plurality of first packages to a corresponding one of the plurality of second packages to provide a gap between the lower surface of each of the plurality of second packages and the corresponding one of the plurality of first packages may include: a module for communicatively coupling each of the plurality of first packages to a corresponding one of the plurality of second packages to provide a gap between the lower surface of each of the plurality of second packages and the corresponding one of the plurality of first packages; wherein each of the upper surfaces of the plurality of first packages includes a surface having a first area, and each of the lower surfaces of the plurality of second packages includes a surface having a second area, the second area being smaller than the first area.

[0090] The terms and expressions used herein are descriptive rather than restrictive, and their use is not intended to exclude any equivalents of the features shown and described (or parts thereof), and it is recognized that various modifications may be made within the scope of the claims. Therefore, the claims are intended to cover all such equivalents.

Claims

1. A stacked package (PoP) semiconductor package, comprising: A first semiconductor package having a top surface and a bottom surface; A first solder ball disposed on the top surface of the first semiconductor package; A second semiconductor package having a top surface and a bottom surface, the second semiconductor package being communicatively coupled to the first semiconductor package, and the second semiconductor package comprising one or more dies encapsulated in a molding compound having a first thermal conductivity; and A second solder ball is disposed on the bottom surface of the second semiconductor package, wherein the second solder ball is in contact with the first solder ball. Wherein, after the first semiconductor package is communicatively coupled to the second semiconductor package, a gap is formed between the bottom surface of the second semiconductor package and the top surface of the first semiconductor package; The gap is filled with a curable fluid material, which cures to thermally couple the top surface of the first semiconductor package to the bottom surface of the second semiconductor package using the cured material. The cured material has a second thermal conductivity greater than the first thermal conductivity. The curable fluid material extends at least partially along the sidewall of the first semiconductor package, and the cured material forms a peripheral wall extending at least partially around the periphery of the first semiconductor package. The curable fluid material contacts the first solder ball and the second solder ball within the gap.

2. The stacked semiconductor package according to claim 1, wherein, The first semiconductor package includes a die stack, and wherein at least a portion of the top surface of the first semiconductor package includes the uppermost exposed die included in the die stack.

3. The stacked semiconductor package according to claim 1, wherein, The first semiconductor package includes a system-on-a-chip (SoC).

4. The stacked semiconductor package according to claim 1, wherein, The one or more dies of the second semiconductor package include one or more memory dies encapsulated in the molding compound having the first thermal conductivity.

5. The stacked semiconductor package according to claim 1, wherein, The cured material includes non-conductive materials.

6. The stacked semiconductor package according to claim 1, wherein, During operation, the heat output of the first semiconductor package exceeds that of the second semiconductor package.

7. The stacked semiconductor package according to claim 1, wherein, The top surface of the first semiconductor package includes a surface having a first area, and the bottom surface of the second semiconductor package includes a surface having a second area, the second area being smaller than the first area.

8. A method for manufacturing a stacked package (PoP) semiconductor package, comprising: A first solder ball of a first semiconductor package and a second solder ball of a second semiconductor package are communicatively coupled such that a gap is formed between a lower surface of the second semiconductor package and an upper surface of the first semiconductor package, wherein the first semiconductor package includes an exposed die forming at least a portion of the upper surface of the first semiconductor package, and wherein the second semiconductor package includes one or more dies encapsulated in a molding compound having a first thermal conductivity. A curable fluid material is allowed to flow in the gap between the lower surface of the second semiconductor package and the upper surface of the first semiconductor package, and in contact with the first and second solder balls within the gap, to form a cured material. This cured material thermally couples the upper surface of the first semiconductor package to the lower surface of the second semiconductor package, and the cured material has a second thermal conductivity greater than the first thermal conductivity. The curable fluid material is allowed to flow at least partially along the side of the first semiconductor package, such that the cured material forms a peripheral wall extending at least partially around the periphery of the first semiconductor package.

9. The method for manufacturing a stacked semiconductor package according to claim 8, in, The first semiconductor package includes a die stack; and The exposed die forming at least a portion of the upper surface of the first semiconductor package includes the uppermost die in the die stack.

10. The method for manufacturing a stacked semiconductor package according to claim 8, wherein, The first semiconductor package includes a system-on-a-chip (SoC).

11. The method for manufacturing a stacked semiconductor package according to claim 8, wherein, The one or more dies of the second semiconductor package include one or more memory dies encapsulated in the molding compound having the first thermal conductivity.

12. The method for manufacturing a stacked semiconductor package according to claim 8, wherein, The cured material includes non-conductive materials.

13. The method for manufacturing a stacked semiconductor package according to claim 8, wherein, The upper surface of the first semiconductor package includes a surface having a first area, and the lower surface of the second semiconductor package includes a surface having a second area, the second area being smaller than the first area.

14. A method for manufacturing a stacked package (PoP) semiconductor package strip, comprising: A plurality of stacked semiconductor packages are formed on a strip by communicatively coupling each of a plurality of first solder balls of a plurality of first semiconductor packages to a corresponding one of a plurality of second solder balls of a plurality of second semiconductor packages such that a gap is formed between the lower surface of each of the plurality of second semiconductor packages and the upper surface of the corresponding one of the plurality of first semiconductor packages, each of the plurality of stacked semiconductor packages being separated from one or more adjacent stacked semiconductor packages by a gap space, wherein each of the plurality of first semiconductor packages includes an exposed die forming at least a portion of the upper surface of the corresponding first semiconductor package, and wherein each of the plurality of second semiconductor packages includes one or more dies encapsulated in a molding compound having a first thermal conductivity; A curable fluid material is allowed to flow in the gaps between each of the plurality of stacked semiconductor packages, and in the gaps between the lower surface of each of the plurality of second semiconductor packages and the upper surface of each of the plurality of first semiconductor packages, and in contact with the first and second solder balls within the gaps, to form a cured material that thermally couples the upper surface of each of the plurality of first semiconductor packages to the lower surface of a corresponding one of the plurality of second semiconductor packages, and the cured material has a second thermal conductivity greater than the first thermal conductivity; and The plurality of stacked packaged semiconductor packages are individualized to provide a plurality of individualized stacked packaged semiconductor packages.

15. The method for manufacturing a stacked semiconductor package strip according to claim 14, in, Each of the plurality of first semiconductor packages includes a die stack; and The exposed die forming at least a portion of the upper surface of each of the plurality of first semiconductor packages includes the uppermost die in the die stack.

16. The method for manufacturing a stacked semiconductor package strip according to claim 14, wherein, Each of the plurality of first semiconductor packages includes a system-on-a-chip (SoC).

17. The method for manufacturing a stacked semiconductor package strip according to claim 14, wherein, Each of the plurality of second semiconductor packages includes one or more dies comprising one or more memory dies encapsulated in the molding compound having the first thermal conductivity.

18. The method for manufacturing a stacked semiconductor package strip according to claim 14, wherein, The cured material includes non-conductive materials.

19. The method for manufacturing a stacked semiconductor package strip according to claim 14, wherein, Each of the upper surfaces of the plurality of first semiconductor packages includes a surface having a first area, and each of the lower surfaces of the plurality of second semiconductor packages includes a surface having a second area, the second area being smaller than the first area.

20. An electronic device comprising at least one stacked package (PoP) semiconductor package, comprising: At least one semiconductor stacked package (PoP) system with enhanced thermal performance, comprising: A first semiconductor package having an upper surface and a lower surface, wherein at least a portion of the upper surface of the first semiconductor package includes an exposed die; A first solder ball disposed on the upper surface of the first semiconductor package; A second semiconductor package having an upper surface and a lower surface, the second semiconductor package being communicatively coupled to the first semiconductor package, and the second semiconductor package comprising one or more dies encapsulated in a molding compound having a first thermal conductivity; and A second solder ball is disposed on the lower surface of the second semiconductor package, wherein the second solder ball is in contact with the first solder ball. Wherein, there is a gap between the lower surface of the second semiconductor package and the upper surface of the first semiconductor package; The gap is filled with a curable fluid material, which is cured to thermally couple at least a portion of the upper surface of the first semiconductor package to at least a portion of the lower surface of the second semiconductor package using the cured material. The cured material has a second thermal conductivity greater than the first thermal conductivity. The curable fluid material extends at least partially along the sidewall of the first semiconductor package, and the cured material forms a peripheral wall extending at least partially around the periphery of the first semiconductor package. The curable fluid material contacts the first solder ball and the second solder ball within the gap.

21. The electronic device according to claim 20, wherein, The first semiconductor package includes a die stack, and wherein at least a portion of the upper surface of the first semiconductor package includes the uppermost exposed die in the die stack.

22. The electronic device according to claim 20, wherein, The first semiconductor package includes a system-on-a-chip (SoC).

23. The electronic device according to claim 20, wherein, The one or more dies of the second semiconductor package include one or more memory dies encapsulated in the molding compound having the first thermal conductivity.

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